Image decompression method and system based on FPGA

Abstract

The invention provides an image decompression method and system based on an FPGA (Field Programmable Gate Array). The method comprises the following steps: acquiring a to-be-decompressed data packet; wherein the data packet to be decompressed comprises a plurality of sub-packets consisting of row marks, table indexes, segment length information and coded data. And segmenting the to-be-decompressed data packet based on the row mark and the segment length information to obtain a plurality of segments of coded data corresponding to the plurality of sub-packets. And decoding the plurality of segments of coded data in parallel until all pixel values corresponding to the coded data in the data packet to be decompressed are obtained. And sorting the pixel values based on the pixel coordinate sequence, and obtaining and caching positive sequence pixel values. According to the decompression method provided by the invention, the characteristics of the image data are utilized, parallel decoding is realized on the premise of not increasing any boundary information, and the decoding efficiency is further improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an image decompression method and system based on FPGA. Background Art

[0002] With the development of technology, the demand for high-speed and high-precision machine vision inspections has placed increasingly higher demands on the resolution and frame rate of industrial cameras, thus requiring higher data bandwidth for image transmission. Using compressed data to transmit images is a common method to achieve higher data transmission bandwidth.

[0003] Image compression is the process of representing the original pixel matrix with fewer bits, either losslessly or losslessly. Raw data contains spatial redundancy (manifested as information correlation between adjacent pixels in an image), temporal redundancy (manifested as correlation between different frames in an image sequence), and spectral redundancy (manifested as correlation between different color planes or spectral bands). The fundamental principle of image compression is to design algorithms to reduce image data redundancy.

[0004] To further improve compression efficiency and reduce storage space or transmission bandwidth, a variable length encoding (VLE) method has been proposed in the prior art for compressing data. In this encoding method, different symbols are represented by bit sequences of different lengths. Compared to fixed-length encoding, variable length encoding can more effectively represent high-frequency symbols, thereby improving compression efficiency. Common variable length encoding methods include Huffman coding, run-length coding, arithmetic coding, and dictionary coding.

[0005] During variable-length code decoding, the code length information of the preceding symbol needs to be calculated before parsing the succeeding symbol. This creates a dependency between the preceding and succeeding symbols, which limits the implementation of variable-length code parallel decoding.

[0006] Chinese Patent Publication No. CN118100955A discloses a preprocessing method for parallel decompression of compressed data, as well as a parallel decompression device, chip circuit, decompression system, and computing equipment. This patent sets a number of storage spaces corresponding to the degree of parallelism, for storing compressed data of equal bit length, and then performs parallel decompression on the compressed data in each storage space. The parallel decoding method in this patent is based on setting the degree of parallelism and storage space equal, and does not involve a method for decoding variable-length coded data, which is different from the technical problem solved by this patent.

[0007] Chinese Patent Publication No. CN102244518A discloses a system and method for hardware-implemented parallel decompression. This patent uses a field-programmable logic device (FPGA) to implement Gzip decompression. Through a hardware architecture (data merging and shifting units), a large number of variable-length bit operations are performed, enabling parallel decoding operations. This completes a Huffman decoding algorithm within a single cycle, resulting in more efficient Lz77 decoding. The variable-length data operations in this patent are caused by the hardware architecture and are controllable, differing from the technical problems and technical approaches addressed by this solution.

[0008] Chinese patent publication number CN118074726A discloses an FPGA-based Huffman parallel decompression and storage device. This application appropriately increases or decreases the number of combined delimiters based on different resource and performance requirements to achieve a balance between decompression bandwidth and hardware storage resources. This method, which finds delimiting points in the encoded data stream, can truncate the data stream at the boundary point, enabling independent parallel decoding. This device can extract multiple codewords within a single clock cycle while only adding a small amount of hardware overhead. This patent utilizes delimiters to achieve parallel decoding, which differs from the technical approach of this solution.

[0009] Chinese Patent Publication No. CN 118118035 A proposes an FPGA-based implementation of the Huffman decompression algorithm. This patent uses a lookup table (RAM) to store the Huffman decoding table. This storage method can extract one or more codewords within a single clock cycle while adding only a small amount of hardware overhead. This patent addresses a different technical approach than this solution. Summary of the Invention

[0010] The present invention provides an FPGA-based image decompression method and system, which can solve at least one of the above technical problems.

[0011] To achieve the above objectives, the present invention proposes the following technical solutions: An image decompression method based on FPGA, comprising: Obtaining a data packet to be decompressed; wherein the data packet to be decompressed includes a plurality of sub-packets consisting of row marks, table indexes, segment length information, and encoded data; Based on the row mark and segment length information, the data packet to be decompressed is divided to obtain a plurality of segments of encoded data corresponding to a plurality of sub-packets; Decoding several segments of coded data in parallel until all pixel values ​​corresponding to the coded data in the data packet to be decompressed are obtained; Sort the pixel values ​​based on the pixel coordinate order, and obtain and cache the positive sequence pixel values.

[0012] Furthermore, the segmentation of the data packet to be decompressed includes: detecting row marks, and dividing the data packet to be decompressed into several sub-packets based on segment length information; based on the segment length information of the current sub-packet, segmentally reading the encoded data of the current sub-packet, obtaining several segments of the encoded data of the current sub-packet, and caching them in the FPGA buffer.

[0013] Furthermore, the parallel decoding of the plurality of segments of coded data includes: In the FPGA buffer, the encoded data is pre-read once from each segment of encoded data; within multiple clock cycles, the pre-read encoded data is decoded multiple times so that at least one codeword is obtained each time it is decoded; the number of bits of the decoded encoded data is counted, the next pre-read encoded data is refreshed, and the next pre-read encoded data is decoded multiple times; residual recovery is performed on each codeword to obtain the pixel value corresponding to each codeword.

[0014] Furthermore, it also includes: based on the known number of code words corresponding to each segment of coded data, real-time statistics are obtained on the number of code words, and the number of code words obtained is compared with the number of code words corresponding to each segment of coded data to determine whether the current segment of coded data has been decoded.

[0015] Furthermore, each decoding includes: within one clock cycle, intercepting a fixed number of bits of coded data from the pre-read coded data for decoding, selecting a corresponding decoding mapping relationship based on the table index corresponding to the current segment of coded data to obtain a codeword and the number of bits of the coded data corresponding to the codeword, counting the number of bits of the coded data decoded this time, and refreshing the undecoded position of the next clock cycle in real time.

[0016] Furthermore, refreshing the next pre-read coded data includes: if the number of bits of the coded data that has been decoded multiple times is not less than the output bit width of the FPGA buffer, then pre-reading new coded data from the FPGA buffer and splicing it with the remaining undecoded coded data of this pre-read as the next pre-read coded data.

[0017] Furthermore, the fixed number of bits is not less than the maximum number of bits of the encoded data corresponding to any single codeword.

[0018] Furthermore, the pre-reading of the encoded data once includes: pre-reading the encoded data of at least two FPGA buffer output bit widths.

[0019] Based on the same inventive concept, the present application also proposes an FPGA-based image decompression system, comprising: An acquisition module is used to acquire a data packet to be decompressed; wherein the data packet to be decompressed includes a plurality of sub-packets consisting of a row mark, a table index, a segment length information, and encoded data; The segmentation module is used to detect row marks and divide the data packet to be decompressed into several sub-packets based on the segment length information; based on the segment length information of the current sub-packet, it reads the encoded data of the current sub-packet in segments, obtains several segments of the encoded data of the current sub-packet, and caches them in the FPGA buffer; A decoding module, configured to decode several segments of coded data in parallel until all pixel values ​​corresponding to the coded data in the data packet to be decompressed are obtained; the decoding module includes at least two decoding submodules; The sorting module is used to sort the pixel values ​​based on the pixel coordinate order, obtain and cache the positive sequence pixel values.

[0020] Furthermore, the decoding submodule includes: The pre-reading unit pre-reads the encoded data from each segment of the encoded data in the FPGA buffer and outputs the pre-read encoded data to the data interception unit. Upon receiving feedback from the statistics unit that the number of bits of the decoded encoded data is not less than the output bit width of the FPGA buffer, the pre-reading unit refreshes the position of the next pre-read encoded data and pre-reads new encoded data from the FPGA buffer. The data interception unit intercepts a fixed number of bits of encoded data from the pre-read encoded data within one clock cycle and outputs the intercepted encoded data to the decoding unit; wherein the fixed number of bits is not less than the maximum number of bits of the encoded data corresponding to any single codeword; A decoding unit, based on the table index corresponding to the current segment of coded data, is used to select a corresponding decoding mapping relationship and decode the intercepted coded data to obtain a codeword and the number of bits of the coded data corresponding to the codeword within one clock cycle; The statistical unit counts the number of bits of the currently decoded coded data and refreshes the undecoded position of the next clock cycle in real time; counts the number of bits of the coded data that have been decoded multiple times and determines whether the number of bits of the coded data that have been decoded multiple times is not less than the output bit width of the FPGA buffer; based on the number of code words corresponding to each segment of the known coded data, counts the number of acquired code words in real time and compares the number of acquired code words with the number of code words corresponding to each segment of the coded data to determine whether the current segment of the coded data has been decoded; The residual recovery unit is used to perform residual recovery processing on each codeword to obtain the pixel value corresponding to each codeword.

[0021] The beneficial effects of the present invention are as follows: The decompression method proposed in this application utilizes the characteristics of image data and, without adding any boundary information, decomposes the data packet to be decompressed into segmented coded data based on row marks and segment length information. The length of the data to be coded corresponding to each segment of coded data is the same, so that in the subsequent parallel decompression process, synchronous analysis and synchronous decompression can be performed, further improving the decompression efficiency and thereby improving the parallel decompression efficiency.

[0022] The decompression method proposed in this application performs a pre-read operation on the segment coded data during the decoding process in order to obtain at least one codeword within one clock cycle, so as to achieve the continuity of decoding within each clock cycle and improve the decompression efficiency.

[0023] The decompression method proposed in this application is suitable for FPGA operation and can realize real-time decompression of compressed data; compared with software decompression methods, this method has a faster decompression speed and can better meet the needs of big data application scenarios.

[0024] Compared to software decompression methods, the decompression method proposed in this application is not limited by the number of CPUs and can meet the requirements of simultaneous decompression of multiple compressed data links. At the same time, it is not limited by the CPU main frequency and can meet the real-time decompression requirements of large-bandwidth compressed data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a flow chart of the FPGA-based image decompression method of the present invention; Figure 2 1 is a flow chart of a compression method according to an embodiment of the present invention; Figure 3 It is a schematic diagram of the decoding process in the decompression method of the present invention; Figure 4 It is a schematic diagram of pre-reading in the decompression method of the present invention; Figure 5 is a schematic diagram of an FPGA-based image decompression system in the present invention; Figure 6 It is a schematic diagram of a decoding submodule in the decompression system of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0027] like Figure 1 As shown, the present application proposes an FPGA-based image decompression method, comprising: Obtaining a data packet to be decompressed; wherein the data packet to be decompressed includes a plurality of sub-packets consisting of row marks, table indexes, segment length information, and encoded data; Based on the row mark and segment length information, the data packet to be decompressed is divided to obtain a plurality of segments of encoded data corresponding to a plurality of sub-packets; Decode several segments of coded data in parallel until all codewords corresponding to the coded data in the decompressed data packet are obtained; recover all codewords using residuals to obtain the pixel value corresponding to each codeword; Sort the pixel values ​​based on the pixel coordinate order, and obtain and cache the positive sequence pixel values.

[0028] Before further describing the decompression method of the present application, a compression method is briefly described. Figure 2 shown.

[0029] Acquire some image data.

[0030] Since the compressed data is image data, and considering the correlation between adjacent pixel information, which is generally manifested as a gradual change in grayscale values, the image data contains spatial redundancy. By encoding the grayscale differences between adjacent pixels instead of directly encoding the grayscale values ​​of each pixel, this reduces the spatial redundancy of the image data and achieves compression.

[0031] Perform residual calculation on each segment of image data to obtain residual data corresponding to the segment of image data.

[0032] In order to facilitate the compression processing of the image data, the arrival order of the image data is in lines. Therefore, the residual data is compressed in lines without adding additional delimiters to truncate the currently arriving image data.

[0033] The occurrence probabilities of different symbols in each row of residual data are counted to generate a corresponding coding table, so that residual data with different symbol distributions can select corresponding coding mapping relationships to achieve the minimum space compression rate.

[0034] In order to facilitate compression and decompression processing, each row of residual data is evenly divided into several segments. The number of segments can be adjusted according to the performance and configuration resources of the processors at the compression and decompression ends.

[0035] Each row of residual data is compressed using the same coding mapping relationship to obtain the coded data corresponding to the image data.

[0036] Before compression, the length of each segment of data to be encoded is the same. Due to the use of variable length encoding, the length of each segment of encoded data after encoding is different, so the length of each row of encoded data after compression is different.

[0037] Since the coding table used for each row changes, the (coding) table index used for the row data and the number of bits of each segment of coded data (i.e., segment length information) are recorded at the beginning of each row.

[0038] The data format of each row of compressed encoded data packets is: row mark, table index, segment length information, and encoded data (of the row).

[0039] After compression of a number of data to be encoded (residual data), a data packet to be decompressed can be obtained. The data packet to be decompressed includes a number of sub-packets consisting of row marks, table indexes, segment length information, and encoded data.

[0040] Based on the above compression method, this embodiment proposes an FPGA-based image decompression method. All operations described in this embodiment are implemented based on FPGA. The method is as follows: Obtain a data packet to be decompressed; wherein the data packet to be decompressed includes several sub-packets consisting of row marks, table indexes, segment length information, and encoded data.

[0041] Based on the row mark and segment length information, the data packet to be decompressed is divided to obtain several segments of encoded data corresponding to several sub-packets.

[0042] The row segmentation operation includes: detecting row marks, dividing the data packet to be decompressed into several sub-packets based on the segment length information; reading the encoded data of the current sub-packet in segments based on the segment length information of the current sub-packet, obtaining several segments of the encoded data of the current sub-packet, and caching them in the FPGA buffer.

[0043] The segment coded data obtained by the above-mentioned branching and segmenting operation is cached in the buffer of the FPGA.

[0044] The encoded data is divided into rows and segments as a preprocessing step for parallel decoding. By dividing the encoded data into rows and segments using row markers and segment length information, the variable-length encoded data can be segmented, providing the foundation for subsequent parallel decoding.

[0045] In addition, the design of row marking can also avoid and self-recover from erroneous sub-packets.

[0046] By detecting the line marker, obtaining any sub-packet and combining it with the segment length information, the length of the encoded data in the sub-packet can be verified, making it easy to determine whether the encoded data in the current sub-packet has experienced data loss or bit errors. If the erroneous sub-packet is decoded directly without intervention, it will lead to decoding confusion. With this verification, the erroneous sub-packet can be skipped until the next line marker is detected, and normal decoding can be resumed.

[0047] Several segments of coded data are decoded in parallel until all pixel values ​​corresponding to the coded data in the data packet to be decompressed are obtained.

[0048] In the FPGA buffer, the encoded data is pre-read once from each segment of encoded data; within multiple clock cycles, the pre-read encoded data is decoded multiple times so that at least one codeword is obtained each time it is decoded; the number of bits of the decoded encoded data is counted, the next pre-read encoded data is refreshed, and the next pre-read encoded data is decoded multiple times; residual recovery is performed on each codeword to obtain the pixel value corresponding to each codeword.

[0049] Pre-reading the encoded data once includes: pre-reading the encoded data of at least two FPGA buffer output bit widths.

[0050] Based on the known number of codewords corresponding to each segment of coded data, the number of codewords obtained is counted in real time, and the number of codewords obtained is compared with the number of codewords corresponding to each segment of coded data to determine whether the current segment of coded data is decoded.

[0051] Each decoding process involves extracting a fixed number of bits of encoded data from the pre-read encoded data within a clock cycle, decoding the data to obtain a codeword and the number of bits of the encoded data corresponding to the codeword, counting the number of bits of the decoded encoded data, and refreshing the undecoded position in the next clock cycle in real time. The fixed number of bits is no less than the maximum number of bits of the encoded data corresponding to any single codeword.

[0052] Among them, refreshing the encoding data for the next pre-read includes: if the number of bits of the encoding data that has been decoded multiple times is not less than the output bit width of the FPGA buffer, then pre-reading new encoding data from the FPGA buffer and splicing it with the remaining undecoded encoding data of this pre-read as the encoding data for the next pre-read.

[0053] The fixed number of bits is not less than the maximum number of bits of the encoded data corresponding to any single codeword.

[0054] Since variable-length coding is used to encode and map the encoded data, the length of each row and each segment of the encoded data is not the same. Therefore, when the encoded data with the same number of bits is intercepted for decoding, the length of the encoded data corresponding to at least one codeword obtained each time is decoded is not the same, so the number of decoding times of the pre-read encoded data each time is also different.

[0055] like Figure 3 As shown, taking the decoding process of any segment of encoded data as an example, the following is explained: The decoding process can be roughly divided into three parts: pre-reading operation, decoding operation, and residual recovery operation.

[0056] Pre-read operation: In the FPGA buffer, the encoded data is pre-read from each segment of encoded data, and the pre-read encoded data is output for decoding operation.

[0057] Generally, a pre-read operation is performed starting from the start position of each segment of coded data, and based on a subsequent decoding operation, a pre-read refresh operation is performed from the next non-pre-read position.

[0058] If the number of bits of the encoded data decoded multiple times is not less than the output bit width of the FPGA buffer, the next pre-read refresh operation is performed. The next pre-read refresh operation involves pre-reading new encoded data from the FPGA buffer and concatenating it with the remaining undecoded encoded data from the current pre-read operation to form the encoded data for the next pre-read operation.

[0059] In order to facilitate the next pre-read refresh operation, in this embodiment, pre-reading once is to pre-read the encoded data of at least two buffer output bit widths.

[0060] like Figure 4 As shown, this embodiment illustrates the above-mentioned pre-reading operation.

[0061] In the FPGA buffer, the encoded data is pre-read once from each segment of encoded data. Here, pre-reading once means pre-reading encoded data of two buffer output widths from the FPGA buffer. In this embodiment, the buffer output width is 64 bits. The pre-read encoded data outputted are the upper 64 bits of pre-read encoded data and the lower 64 bits of pre-read encoded data, respectively.

[0062] Preferably, pre-reading once may also be pre-reading encoded data of three or other numbers of buffer output bit widths from the FPGA buffer.

[0063] The pre-read coded data is decoded, and 16 bits of coded data are intercepted from the upper 64 bits of coded data for decoding, and at least one code word is obtained each time the coded data is decoded. Starting from the position of the undecoded coded data, 16 bits of coded data are re-intercepted for the next decoding.

[0064] If the number of bits of the encoded data that has been decoded multiple times is not less than the output bit width of the FPGA buffer, the new encoded data is pre-read from the buffer and spliced ​​with the remaining undecoded encoded data in this pre-read to form the encoded data for the next pre-read.

[0065] In this embodiment, the number of bits of the encoded data that has been decoded multiple times is not less than half the number of bits of the pre-read data read this time. That is, the 16-bit encoded data currently intercepted is the last 16 bits of the upper 64 bits of the pre-read encoded data, or the 16-bit encoded data currently intercepted contains both the upper 64 bits of the pre-read encoded data and the lower 64 bits of the pre-read encoded data.

[0066] Preferably, if the pre-reading is to pre-read three or more encoded data of the buffer output bit width from the FPGA buffer, then the next pre-read data refresh must ensure that the number of bits of the currently undecoded encoded data is at least not less than the output bit width of the FPGA buffer.

[0067] If the pre-reading is to pre-read the coded data of three buffer output bit widths from the FPGA buffer, then the judgment condition for refreshing the next pre-read data is that the number of bits of the decoded coded data counted multiple times can be one buffer output bit width or two buffer output bit widths.

[0068] Decoding operation: Within one clock cycle, a fixed number of bits of coded data is intercepted from the pre-read coded data for decoding. Based on the table index corresponding to the current segment of coded data, the corresponding decoding mapping relationship is selected to obtain a codeword and the number of bits of the coded data corresponding to the codeword. The number of bits of the decoded coded data is counted, and the undecoded position of the next clock cycle is refreshed in real time.

[0069] Generally, decoding starts from the starting position of each segment of coded data, and based on subsequent decoding operations, the undecoded position of the next clock cycle is refreshed.

[0070] The fixed number of bits is not less than the maximum number of bits of the coded data corresponding to any single codeword, so that by intercepting the coded data of the fixed number of bits at a time, at least one codeword can be parsed in each clock cycle.

[0071] Based on the compression method in this embodiment, each row of residual data is evenly divided into several segments, and the number of residual data in each segment is the same, that is, the number of codewords in each segment in the decompression method is the same.

[0072] Based on the known number of codewords corresponding to each segment of coded data, the system calculates the number of codewords obtained in real time and compares the number of codewords obtained with the number of codewords corresponding to each segment of coded data to determine whether the current segment of coded data has been decoded. If so, the system jumps to the next segment of coded data for decoding.

[0073] If all the coded data segments in the current row have been decoded, the row mark is re-detected, the next row of coded data is divided into rows and segments, and the above decoding operation is repeated for each segment of coded data in the row to obtain the codeword corresponding to the row.

[0074] Residual recovery operation: Residual recovery processes each codeword to obtain the pixel value corresponding to each codeword.

[0075] Sort the pixel values ​​based on the pixel coordinate order, and obtain and cache the positive sequence pixel values.

[0076] Principle of the method: This application utilizes the arrival characteristics of image data, truncates the image data in units of lines, and performs segmented processing on each line of image data, providing the necessary basic conditions for realizing parallel decoding. Several decoding channels can be carried out simultaneously, and then independent parallel decoding can be performed. Multiple codewords can be parsed out within one clock cycle, greatly improving the decoding efficiency.

[0077] like Figure 5 As shown, based on the same inventive concept, the present application also proposes an FPGA-based image decompression system for implementing the above-mentioned decompression method, comprising: An acquisition module is used to acquire a data packet to be decompressed; wherein the data packet to be decompressed includes a plurality of sub-packets consisting of a row mark, a table index, a segment length information, and encoded data; The segmentation module is used to detect row marks and divide the data packet to be decompressed into several sub-packets based on the segment length information; based on the segment length information of the current sub-packet, it reads the encoded data of the current sub-packet in segments, obtains several segments of the encoded data of the current sub-packet, and caches them in the FPGA buffer; A decoding module, configured to decode several segments of coded data in parallel until all pixel values ​​corresponding to the coded data in the data packet to be decompressed are obtained; the decoding module includes at least two decoding submodules; The sorting module is used to sort pixel values ​​based on the order of pixel coordinates, obtain and cache the positive sequence pixel values.

[0078] Among them, such as Figure 6 As shown, any decoding submodule includes: The pre-reading unit pre-reads the encoded data from each segment of the encoded data in the FPGA buffer and outputs the pre-read encoded data to the data interception unit. Upon receiving feedback from the statistics unit that the number of bits of the decoded encoded data is not less than the output bit width of the FPGA buffer, the pre-reading unit refreshes the position of the next pre-read encoded data and pre-reads new encoded data from the FPGA buffer. The data interception unit intercepts a fixed number of bits of encoded data from the pre-read encoded data within one clock cycle and outputs the intercepted encoded data to the decoding unit; wherein the fixed number of bits is not less than the maximum number of bits of the encoded data corresponding to any single codeword; A decoding unit, based on the table index corresponding to the current segment of coded data, is used to select a corresponding decoding mapping relationship and decode the intercepted coded data to obtain a codeword and the number of bits of the coded data corresponding to the codeword within one clock cycle; The statistical unit counts the number of bits of the currently decoded coded data and refreshes the undecoded position of the next clock cycle in real time; counts the number of bits of the coded data that have been decoded multiple times and determines whether the number of bits of the coded data that have been decoded multiple times is not less than the output bit width of the FPGA buffer; based on the number of code words corresponding to each segment of the known coded data, counts the number of acquired code words in real time and compares the number of acquired code words with the number of code words corresponding to each segment of the coded data to determine whether the current segment of the coded data has been decoded; The residual recovery unit is used to perform residual recovery processing on each codeword to obtain the pixel value corresponding to each codeword.

[0079] Based on the same inventive concept, the present application also proposes an electronic device, comprising: FPGA, used to implement the FPGA-based image decompression method as described above; FPGA peripheral circuits are used to support the operation of FPGA.

[0080] In addition, a buffer can be provided inside the FPGA to store data packets to be decompressed.

[0081] Based on the above electronic device, the electronic device further includes: a memory for storing positive sequence pixel values.

[0082] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An image decompression method based on FPGA, characterized in that: include: Obtain a data packet to be decompressed; wherein the data packet to be decompressed includes a plurality of sub-packets consisting of row marks, table indexes, segment length information, and encoded data; Based on the row mark and the segment length information, the data packet to be decompressed is divided to obtain a plurality of segments of encoded data corresponding to a plurality of sub-packets; Decoding several segments of coded data in parallel until all pixel values ​​corresponding to the coded data in the data packet to be decompressed are obtained; Based on the pixel coordinate order, the pixel values ​​are sorted, and the positive-sequence pixel values ​​are obtained and cached.

2. The FPGA-based image decompression method according to claim 1, characterized in that: The method for segmenting the data packet to be decompressed includes: detecting a row mark, and dividing the data packet to be decompressed into a plurality of sub-packets based on the segment length information; and reading the encoded data of the current sub-packet in segments based on the segment length information of the current sub-packet, obtaining a plurality of segments of the encoded data of the current sub-packet, and caching them in an FPGA buffer.

3. The FPGA-based image decompression method according to claim 2, characterized in that: The parallel decoding of the plurality of segments of coded data comprises: In the FPGA buffer, the coded data is pre-read once from each segment of coded data; within multiple clock cycles, the pre-read coded data is decoded multiple times so that at least one code word is obtained each time the decoding is performed; the number of bits of the coded data that have been decoded multiple times is counted, the next pre-read coded data is refreshed, and the next pre-read coded data is decoded multiple times; the residual recovery process is performed on each code word to obtain the pixel value corresponding to each code word.

4. The FPGA-based image decompression method according to claim 3, characterized in that: Also includes: Based on the known number of code words corresponding to each segment of coded data, the number of code words is obtained by real-time statistics, and the number of code words obtained is compared with the number of code words corresponding to each segment of coded data to determine whether the current segment of coded data has been decoded.

5. The FPGA-based image decompression method according to claim 3, characterized in that: Each decoding includes: within one clock cycle, intercepting a fixed number of bits of coded data from the pre-read coded data for decoding, selecting a corresponding decoding mapping relationship based on the table index corresponding to the current segment of coded data to obtain a codeword and the number of bits of the coded data corresponding to the codeword, counting the number of bits of the coded data decoded this time, and refreshing the undecoded position of the next clock cycle in real time.

6. The FPGA-based image decompression method according to claim 3, characterized in that: The refreshing of the next pre-read coded data includes: if the number of bits of the coded data that have been decoded multiple times is not less than the output bit width of the FPGA buffer, then pre-reading new coded data from the FPGA buffer and splicing it with the remaining undecoded coded data of this pre-reading as the next pre-read coded data.

7. The FPGA-based image decompression method according to claim 5, characterized in that: The fixed number of bits is not less than the maximum number of bits of the encoded data corresponding to any single codeword.

8. The FPGA-based image decompression method according to claim 3, characterized in that: The pre-reading of the encoded data once includes: pre-reading the encoded data of at least two FPGA buffer output bit widths.

9. An image decompression system based on FPGA, characterized in that: include: The acquisition module is used to acquire the data packet to be decompressed; wherein the data packet to be decompressed includes a plurality of sub-packets consisting of row marks, table indexes, segment length information, and encoded data; The segmentation module is used to detect the row mark and divide the data packet to be decompressed into several sub-packets based on the segment length information; based on the segment length information of the current sub-packet, the encoded data of the current sub-packet is read in segments, and several segments of the encoded data of the current sub-packet are obtained and cached in the FPGA buffer; A decoding module, used for decoding several segments of coded data in parallel until all pixel values ​​corresponding to the coded data in the data packet to be decompressed are obtained; the decoding module includes at least two decoding submodules; The sorting module is used to sort the pixel values ​​based on the pixel coordinate order, obtain and cache the positive sequence pixel values.

10. The FPGA-based image decompression system according to claim 9, characterized in that: The decoding submodule includes: The pre-reading unit pre-reads the coded data from each section of the coded data in the FPGA buffer, and outputs the pre-read coded data to the data interception unit; receives feedback from the statistical unit that the number of bits of the coded data that have been decoded multiple times is not less than the output bit width of the FPGA buffer, and is used to refresh the position of the coded data to be pre-read next time, and pre-read new coded data from the FPGA buffer; The data interception unit intercepts a fixed number of bits of coded data from the pre-read coded data within one clock cycle, and outputs the intercepted coded data to the decoding unit; wherein the fixed number of bits is not less than the maximum number of bits of the coded data corresponding to any single codeword; A decoding unit, based on the table index corresponding to the current segment of coded data, is used to select a corresponding decoding mapping relationship and decode the intercepted coded data to obtain a codeword and the number of bits of the coded data corresponding to the codeword within one clock cycle; The statistical unit counts the number of bits of the coded data decoded this time, and refreshes the undecoded position of the next clock cycle in real time; counts the number of bits of the coded data decoded multiple times, and determines whether the number of bits of the coded data decoded multiple times is not less than the output bit width of the FPGA buffer; based on the number of code words corresponding to each segment of the known coded data, counts the number of acquired code words in real time, and compares the number of acquired code words with the number of code words corresponding to each segment of the coded data to determine whether the current segment of the coded data has been decoded; The residual recovery unit is used to perform residual recovery processing on each codeword to obtain a pixel value corresponding to each codeword.

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