Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and a storage system, the semiconductor device comprises a stacking structure and a channel structure, the stacking structure comprises gate layers and insulating layers which are alternately stacked, and the channel structure penetrates through the stacking structure along the stacking direction of the stacking structure. The channel structure comprises a channel layer and a storage layer surrounding the channel layer, and the storage layer is located between the gate layer and the channel layer. Wherein the storage layer comprises a ferroelectric layer, and the channel layer comprises a metal oxide semiconductor. Because an interface layer is not generated between the metal oxide semiconductor and the ferroelectric layer, the formation of an oxide layer between the channel layer and the ferroelectric layer can be effectively reduced, the risk of breakdown of the oxide layer is reduced, the reliability of the device is further improved, and the application of the metal oxide semiconductor channel in the 3DNAND structure is realized.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and more specifically, to a semiconductor device and a method for manufacturing the same, and a storage system. Background Art

[0002] NAND memory devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limit. In order to further increase storage capacity and reduce the storage cost per bit, 3D NAND memory is proposed. In the 3D NAND memory structure, a stacked memory structure is realized by vertically stacking multiple layers of data storage units.

[0003] However, current research shows that the storage layer and channel layer of 3D NAND still have various reliability issues, which affect the performance of the device.

[0004] Application Contents

[0005] The purpose of the embodiments of the present application is to provide a semiconductor device and a method for manufacturing the same, and a storage system, aiming to effectively reduce the interaction between the channel layer and the storage layer and increase the reliability of the device.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, the semiconductor device comprising:

[0007] A stacked structure comprising alternately stacked gate layers and insulating layers;

[0008] a channel structure, which penetrates the stack structure along a stacking direction of the stack structure and comprises a channel layer and a storage layer surrounding the channel layer, wherein the storage layer is located between the gate layer and the channel layer;

[0009] Wherein, the storage layer includes a ferroelectric layer, and the channel layer includes a metal oxide semiconductor.

[0010] In some embodiments, the semiconductor device further comprises:

[0011] The common source layer is located at one side of the stack structure and connected to one end of the channel layer.

[0012] In some embodiments, the semiconductor device further comprises:

[0013] A control circuit is bonded to a side of the stack structure away from the common source layer.

[0014] In some embodiments, the channel structure further comprises:

[0015] The barrier layer surrounds the storage layer and is located between the gate layer and the storage layer.

[0016] In some embodiments, the ferroelectric layer includes a high-k dielectric material having a dielectric constant greater than 5.

[0017] In some embodiments, the high-k dielectric material includes hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, niobium oxide, tantalum oxide, tungsten oxide, molybdenum oxide, vanadium oxide, lanthanum oxide, and / or combinations thereof.

[0018] In some embodiments, the metal oxide semiconductor includes one or more of indium gallium zinc oxide, zinc oxide, indium tin oxide, titanium dioxide, molybdenum disulfide, and tungsten disulfide.

[0019] In some embodiments, the gate layer, a portion of the storage layer opposite to the gate layer, and a portion of the channel layer opposite to the gate layer constitute a storage unit.

[0020] In some embodiments, the material of the common source layer includes at least one of metal and indium tin oxide.

[0021] In some embodiments, the semiconductor device further comprises:

[0022] The bit line lead-out contact is located at a side of the stack structure away from the common source layer and is connected to the other end of the channel layer.

[0023] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising:

[0024] forming a stacked structure, the stacked structure comprising alternately stacked gate layers and insulating layers;

[0025] A channel structure is formed, wherein the channel structure penetrates the stack structure along the stacking direction of the stack structure and includes a channel layer and a storage layer surrounding the channel layer, wherein the storage layer is located between the gate layer and the channel layer, wherein the storage layer includes a ferroelectric layer, and the channel layer includes a metal oxide semiconductor.

[0026] In some embodiments, the step of forming a stacked structure includes:

[0027] providing a substrate;

[0028] Alternatingly stacking gate sacrificial layers and insulating layers on the substrate to form a stacked layer;

[0029] forming a channel hole penetrating the stacked layers along a stacking direction of the stacked layers;

[0030] forming a storage layer and a channel sacrificial layer in the channel hole in sequence;

[0031] The gate sacrificial layer is replaced by the gate layer to form the stacked structure.

[0032] In some embodiments, the step of forming the channel structure includes:

[0033] removing the substrate and a portion of the storage layer located in the substrate to expose the channel sacrificial layer;

[0034] The channel sacrificial layer is removed, and the channel layer is formed in the channel hole.

[0035] In some embodiments, the step of replacing the gate sacrificial layer with the gate layer includes:

[0036] forming a protection layer covering the stack layer, the storage layer and the channel sacrificial layer;

[0037] Removing the gate sacrificial layer to form a cavity;

[0038] The gate layer is filled in the cavity.

[0039] In some embodiments, before the step of removing the substrate and a portion of the storage layer located in the substrate, the method for preparing the semiconductor device further includes:

[0040] forming a bit line lead-out contact on the channel sacrificial layer, and forming a first bonding contact on a side of the stacked structure away from the substrate;

[0041] providing a control circuit, the control circuit comprising a circuit layer and a second bonding contact;

[0042] The first bonding contact is bonded to the second bonding contact, and the circuit layer is located on a side of the second bonding contact facing away from the first bonding contact.

[0043] In some embodiments, the method for preparing the semiconductor device further includes:

[0044] A common source layer is formed on a side of the stack structure away from the control circuit, and the common source layer is connected to an end of the channel layer away from the bit line lead-out contact;

[0045] A through contact is formed at the periphery of the stack structure, wherein the through contact connects the common source layer and the first bonding contact.

[0046] In a third aspect, the present application provides a storage system, the storage system comprising:

[0047] The semiconductor device in any of the above embodiments;

[0048] A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

[0049] The present application provides a semiconductor device and a preparation method thereof, and a storage system. The semiconductor device includes a stacking structure and a channel structure. The stacking structure includes alternately stacked gate layers and insulating layers, and the channel structure penetrates the stacking structure along the stacking direction of the stacking structure. The channel structure includes a channel layer and a storage layer surrounding the channel layer, and the storage layer is located between the gate layer and the channel layer. Among them, the storage layer includes a ferroelectric layer, and the channel layer includes a metal oxide semiconductor. Since the metal oxide semiconductor does not generate an interface layer with the ferroelectric layer, the formation of an oxide layer between the channel layer and the ferroelectric layer can be effectively reduced, the risk of oxide layer breakdown can be reduced, and the reliability of the device can be increased, thereby realizing the application of the metal oxide semiconductor channel in the 3D NAND structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0051] Figure 1 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application;

[0052] Figure 2 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application;

[0053] Figure 3 is a schematic flow chart of a method for preparing a semiconductor device provided in some embodiments of the present application;

[0054] Figure 4a-4m Some embodiments of the present application provide Figure 2 A schematic diagram of the structure of a semiconductor device during the preparation process;

[0055] Figure 5 is a schematic diagram of the structure of a memory provided by some embodiments of the present application;

[0056] Figure 6 It is a schematic diagram of the structure of the storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0058] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0059] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0060] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.

[0061] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0062] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application. The semiconductor device 100 may be a wafer or a three-dimensional memory, or a part of a three-dimensional memory. The three-dimensional memory may be applied to communication products, consumer electronic products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronic products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0063] The semiconductor device 100 includes a stacked structure 10 and a channel structure 20, wherein the stacked structure 10 includes alternately stacked gate layers 11 and insulating layers 12, and the channel structure 20 penetrates the stacked structure 10 along the stacking direction (Z) of the stacked structure 10. The channel structure 20 includes a channel layer 21 and a storage layer 22 surrounding the channel layer 21, and the storage layer 22 is located between the gate layer 11 and the channel layer 21. The storage layer 22 includes a ferroelectric layer, and the channel layer 21 includes a metal oxide semiconductor.

[0064] In some embodiments, the gate layer 11, the portion of the storage layer 22 opposite to the gate layer 11, and the portion of the channel layer 21 opposite to the gate layer 11 constitute a storage cell C, that is, the storage cell C includes the gate layer 11, the portion of the storage layer 22 opposite to the gate layer 11, and the portion of the channel layer 21 opposite to the gate layer 11. The information stored in the storage cell C depends on the polarization direction of the ferroelectric layer in the storage layer 22. The ferroelectric layer uses a polarization reversal or switching effect and stores digital bits "0" and "1" according to the direction of spontaneous polarization.

[0065] In some embodiments, the ferroelectric layer includes a high-k dielectric material having a dielectric constant greater than five.

[0066] The high-k dielectric material may include hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, niobium oxide, tantalum oxide, tungsten oxide, molybdenum oxide, vanadium oxide, lanthanum oxide, and / or combinations thereof.

[0067] In some embodiments, the metal oxide semiconductor includes one or more semiconductor materials such as indium gallium zinc oxide, zinc oxide, indium tin oxide, titanium dioxide, molybdenum disulfide, and tungsten disulfide.

[0068] In some embodiments, the material of the insulating layer 12 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The gate layer 11 may include a conductive layer, such as a metal such as tungsten, molybdenum, or polysilicon.

[0069] The gate layer 11 may also include a dielectric layer and a conductive layer (not shown in the figure), wherein the conductive layer may include a first conductive layer and a second conductive layer formed in sequence, and the first conductive layer is located between the dielectric layer and the second conductive layer. The material of the dielectric layer may include a high-K dielectric layer (such as aluminum oxide), the material of the first conductive layer may include titanium nitride, and the material of the second conductive layer may include tungsten.

[0070] The number of layers of the stacking structure 10 determines the number of storage units C it contains in the stacking direction (Z). For example, the number of layers of the stacking structure 10 can be 32 layers, 64 layers, 96 layers, 128 layers, etc., and the more layers the stacking structure 10 has, the higher the integration of the corresponding three-dimensional memory.

[0071] like Figure 1 As shown, the channel layer 21 may be a hollow cylinder having a first end 211 and a second end 212 along the stacking direction (Z). The storage layer 22 may surround the sidewall of the channel layer 21 without covering the first end 211 and the second end 212 of the channel layer 21 .

[0072] In some embodiments, the semiconductor device 100 may further include a common source layer 13 and a cover layer 14, wherein the common source layer 13 is located on one side of the stack structure 10 and is connected to the first end 211 of the channel layer 21. The material of the common source layer 13 includes at least one of a metal (such as tungsten, copper, aluminum, etc.) and indium tin oxide (ITO). The cover layer 14 is located on the side of the common source layer 13 away from the stack structure 10, and the cover layer 14 may be an insulating material such as silicon oxide.

[0073] The semiconductor device 100 may further include a bit line lead-out contact 15, which is located on a side of the stacked structure 10 away from the common source layer 13 and connected to the second end 212 of the channel layer 21. One channel layer 21 is connected to one bit line lead-out contact 15, and the bit line lead-out contact 15 is connected to a bit line (not shown in the figure).

[0074] The semiconductor device 100 may further include a control circuit 17, which is bonded to the side of the stacked structure 10 away from the common source layer 13. The common source layer 13 is connected to the first ends 211 of the plurality of channel layers 21, and is connected to the control circuit 17 via the through contacts 16. The bit line lead-out contacts 15 are connected to the control circuit 17 via the bit lines. The control circuit 17 may include various control structures formed by CMOS (complementary metal oxide semiconductor).

[0075] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures as those in the above embodiments, and the same structures are not described in detail. Only the structures different from those in the above embodiments are described in detail in this embodiment.

[0076] The semiconductor device 200 includes a stacked structure 10 and a channel structure 20a. The channel structure 20a includes not only a storage layer 22 and a channel layer 21, but also a barrier layer 23 surrounding the storage layer 22. The barrier layer 23 is located between the gate layer 11 and the storage layer 22, and can block the interaction between the ferroelectric layer and the gate layer 11, thereby improving the device performance. The material of the barrier layer 23 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials (e.g., HfO2, Al 2 O3 ), and / or any combination thereof.

[0077] The memory cell C′ includes a gate layer 11 , a portion of a barrier layer 23 opposite to the gate layer 11 , a portion of a memory layer 22 opposite to the gate layer 11 , and a portion of a channel layer 21 opposite to the gate layer 11 .

[0078] The semiconductor device provided in the embodiment of the present application includes a stacked structure 10 and a channel structure 20 / 20a, wherein the stacked structure 10 includes a gate layer 11 and an insulating layer 12 that are alternately stacked, and the channel structure 20 / 20a penetrates the stacked structure 10 along the stacking direction (Z) of the stacked structure 10. The channel structure 20 / 20a includes a channel layer 21 and a storage layer 22 surrounding the channel layer 21, and the storage layer 22 is located between the gate layer 11 and the channel layer 21. Among them, the storage layer 22 includes a ferroelectric layer, and the channel layer 21 includes a metal oxide semiconductor. Since the metal oxide semiconductor does not generate an interface layer with the ferroelectric layer, the formation of an oxide layer between the channel layer 21 and the ferroelectric layer can be effectively reduced, the risk of oxide layer breakdown can be reduced, and the reliability of the device can be increased, thereby realizing the application of the metal oxide semiconductor channel in the 3D NAND structure.

[0079] See also Figure 3 , Figure 3 is a schematic diagram of a method for preparing a semiconductor device provided in some embodiments of the present application. Figure 4a-4m , Figure 4a-4m Some embodiments of the present application provide Figure 2 The present embodiment takes the preparation of the semiconductor device 200 as an example to illustrate the preparation method of the semiconductor device 200. Figure 2 The method for preparing the semiconductor device 200 includes the following steps S1-S2.

[0080] Step S1: forming a stacked structure 10 , wherein the stacked structure 10 includes gate layers 11 and insulating layers 12 that are alternately stacked.

[0081] In some embodiments, step S1 may include: 1) Figure 4a As shown, a substrate 101 is provided, on which gate sacrificial layers 11a (eg, silicon nitride) and insulating layers 12 are alternately stacked to form a stacked layer 10a; 2) as Figure 4b As shown, a channel hole 201 penetrating the stacked layer 10a is formed along the stacking direction (Z) of the stacked layer 10a, and the channel hole 201 extends into the substrate 101; 3) as Figure 4c-4e As shown, a barrier layer 23, a storage layer 22 and a channel sacrificial layer 21a (eg, amorphous silicon) are sequentially formed in the channel hole 201; 4) as Figure 4f-4h As shown, the gate sacrificial layer 11 a is replaced by the gate layer 11 to form the stacked structure 10 . The replacement process of the gate layer 11 is generally performed at a high temperature.

[0082] Specifically, Figure 4f As shown, a protective layer 18 is first formed on the stacked structure 10, and the protective layer 18 covers the stacked structure 10, the storage layer 22 and the channel sacrificial layer 21a. Figure 4g As shown, the gate sacrificial layer 11a is then removed by etching to form a cavity 11b, as shown in FIG. Figure 4h As shown, the gate layer 11 is filled in the cavity 11b. The protection layer 18 can prevent the loss of the storage layer 22 and the channel sacrificial layer 21a during the etching process.

[0083] In some embodiments, after forming the stacked structure 10, the method for preparing the semiconductor device further includes: 1) Figure 4i As shown, a bit line lead-out contact 15 is formed on the channel sacrificial layer 21a, and a first bonding contact 102 is formed on the side of the stacked structure 10 away from the substrate 101, and the first bonding contact 102 is connected to the bit line lead-out contact 15; 2) as Figure 4j As shown, a control circuit 17 is provided, and the control circuit 17 includes a circuit layer 171 and a second bonding contact 172 connected to each other; 3) the first bonding contact 102 is bonded to the second bonding contact 172, and the circuit layer 171 is located on the side of the second bonding contact 172 away from the first bonding contact 102; 4) as Figure 4k As shown, the whole structure is then rotated 90° so that the substrate 101 (back side) is located at the top and the control circuit 17 (front side) is located at the bottom, so as to facilitate the removal of the substrate 101 in the subsequent process.

[0084] Step S2: forming a channel structure 20, wherein the channel structure 20 penetrates the stacked structure 10 along the stacking direction (Z) of the stacked structure 10, and comprises a channel layer 21 and a storage layer 22 surrounding the channel layer 21, wherein the storage layer 22 comprises a ferroelectric layer, and the channel layer 21 comprises a metal oxide semiconductor.

[0085] Specifically, Figure 4l As shown, the substrate 101 and a portion of the storage layer 22 located in the substrate 101 are removed to expose the channel sacrificial layer 21a. The insulating layer 12 where the stacked structure 10 contacts the substrate 101 can be used as a stop layer, and the substrate 101 and a portion of the storage layer 22 and the channel sacrificial layer 21a above the stop layer are removed. Since the end of the storage layer 22 surrounding the channel sacrificial layer 21a is removed, the channel sacrificial layer 21a is exposed.

[0086] like Figure 4m As shown, the channel sacrificial layer 21a is removed by an etching process, and the channel layer 21 is formed in the channel hole 201 by a deposition process. The channel layer 21 includes a metal oxide semiconductor, such as indium gallium zinc oxide (IGZO). IGZO has poor high temperature resistance, and amorphous IGZO will crystallize at 500-600°C, resulting in poor performance. Since the replacement process of the gate layer 11 is performed before the channel layer 21 is formed, the high temperature of the replacement process will not affect the metal oxide semiconductor, that is, it will not affect the performance of the channel layer 21.

[0087] The deposition method of the channel layer 21 may be, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, etc. A gap is formed in the channel layer 21, and both ends are sealed to form a hollow cylinder.

[0088] In some embodiments, a filling layer may also be formed inside the channel layer 21 .

[0089] In some embodiments, the channel layer 21 ( Figure 4m ), the method for preparing the semiconductor device may further include the following steps, referring to Figure 2 .

[0090] 1) A common source layer 13 is formed on a side of the stacked structure 10 away from the control circuit 17, and the common source layer 13 is connected to an end of the channel layer 21 away from the bit line lead contact 15. The channel layer 21 includes a first end 211 and a second end 212, the first end 211 is connected to the common source layer 13, and the second end 212 is connected to the bit line lead contact 15.

[0091] 2) A through contact 16 is formed at the periphery of the stack structure 10 , and the through contact 16 connects the common source layer 13 and the first bonding contact 102 , so that the common source layer 13 can be connected to the control circuit 17 through the through contact 16 .

[0092] 3) forming a cover layer 14 on a side of the common source layer 13 away from the stack structure 10 .

[0093] The embodiment of the present application provides a method for preparing a semiconductor device, based on the architecture of NAND and COMS bonding, first forming a channel sacrificial layer 21a on the front, and rotating the structure so that the back is facing up after bonding, so that the channel sacrificial layer 21a can be removed on the back and the channel layer 21 can be deposited, realizing the application of metal oxide semiconductor channels in 3D NAND structures, effectively avoiding the formation of an oxide layer between the channel layer and the ferroelectric layer, reducing the risk of oxide layer breakdown, and increasing reliability. Compared with the polysilicon channel formed by a long annealing crystallization process in conventional 3D NAND, the present application uses metal oxide semiconductors to replace polysilicon, omitting the long annealing crystallization process, and reducing the process cost to a certain extent.

[0094] See also Figure 5 , Figure 5 3 is a schematic diagram of a memory structure provided in some embodiments of the present application. The memory 300 may be a three-dimensional memory, such as a 3D NAND or 3D NOR memory.

[0095] The memory 300 includes a semiconductor device 301 and a peripheral circuit 302 . The control circuit 17 in the above embodiment may be a part of the peripheral circuit 302 or the entire peripheral circuit 302 .

[0096] The peripheral circuit 302 may include various control structures formed by CMOS (complementary metal oxide semiconductor) or other types of circuits. The peripheral circuit 302 is electrically connected to the semiconductor device 301 to transmit signals to the semiconductor device 301. The peripheral circuit 302 may be used for logical operations and to control and detect the switching state of each storage unit in the semiconductor device 301 through metal wiring to achieve data storage and reading.

[0097] Among them, the semiconductor device 301 includes: a stacking structure, including alternately stacked gate layers and insulating layers; a channel structure, which penetrates the stacking structure along the stacking direction of the stacking structure and includes a channel layer and a storage layer surrounding the channel layer, and the storage layer is located between the gate layer and the channel layer; wherein the storage layer includes a ferroelectric layer, and the channel layer includes a metal oxide semiconductor.

[0098] See also Figure 6 , Figure 6 4 is a schematic diagram of a storage system provided in some embodiments of the present application. The storage system 400 includes a semiconductor device 401 and a controller 402. The semiconductor device 401 may be a semiconductor device in any of the above embodiments. The controller 402 is electrically connected to the semiconductor device 401 and is used to control the semiconductor device 401 to store data. The semiconductor device 401 may perform an operation of storing data based on the control of the controller 402.

[0099] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0100] The semiconductor device 401 includes: a stacking structure, including alternately stacked gate layers and insulating layers; a channel structure, which penetrates the stacking structure along the stacking direction of the stacking structure and includes a channel layer and a storage layer surrounding the channel layer, and the storage layer is located between the gate layer and the channel layer; wherein the storage layer includes a ferroelectric layer, and the channel layer includes a metal oxide semiconductor.

[0101] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A stacked structure comprising alternately stacked gate layers and insulating layers; a channel structure, which penetrates the stack structure along a stacking direction of the stack structure and comprises a channel layer and a storage layer surrounding the channel layer, wherein the storage layer is located between the gate layer and the channel layer; Wherein, the storage layer includes a ferroelectric layer, and the channel layer includes a metal oxide semiconductor.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The common source layer is located at one side of the stack structure and connected to one end of the channel layer.

3. The semiconductor device according to claim 2, characterized in that The semiconductor device further comprises: A control circuit is bonded to a side of the stack structure away from the common source layer.

4. The semiconductor device according to claim 1, wherein: The channel structure further includes: The barrier layer surrounds the storage layer and is located between the gate layer and the storage layer.

5. The semiconductor device according to claim 1, wherein: The ferroelectric layer includes a high-k dielectric material having a dielectric constant greater than 5.

6. The semiconductor device according to claim 5, characterized in that The high-k dielectric material includes hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, niobium oxide, tantalum oxide, tungsten oxide, molybdenum oxide, vanadium oxide, lanthanum oxide, and / or combinations thereof.

7. The semiconductor device according to claim 1, wherein: The metal oxide semiconductor includes one or more of indium gallium zinc oxide, zinc oxide, indium tin oxide, titanium dioxide, molybdenum disulfide, and tungsten disulfide.

8. The semiconductor device according to claim 1, wherein: The gate layer, the portion of the storage layer opposite to the gate layer, and the portion of the channel layer opposite to the gate layer form a storage unit.

9. The semiconductor device according to claim 2, characterized in that The material of the common source layer includes at least one of metal and indium tin oxide.

10. The semiconductor device according to claim 2, wherein: The semiconductor device further comprises: The bit line lead-out contact is located at a side of the stack structure away from the common source layer and is connected to the other end of the channel layer.

11. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises: forming a stacked structure, the stacked structure comprising alternately stacked gate layers and insulating layers; A channel structure is formed, wherein the channel structure penetrates the stack structure along the stacking direction of the stack structure and includes a channel layer and a storage layer surrounding the channel layer, wherein the storage layer is located between the gate layer and the channel layer, wherein the storage layer includes a ferroelectric layer, and the channel layer includes a metal oxide semiconductor.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: The step of forming a stacked structure comprises: providing a substrate; Alternatingly stacking gate sacrificial layers and insulating layers on the substrate to form a stacked layer; forming a channel hole penetrating the stacked layers along a stacking direction of the stacked layers; forming a storage layer and a channel sacrificial layer in the channel hole in sequence; The gate sacrificial layer is replaced by the gate layer to form the stacked structure.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: The step of forming the channel structure comprises: removing the substrate and a portion of the storage layer located in the substrate to expose the channel sacrificial layer; The channel sacrificial layer is removed, and the channel layer is formed in the channel hole.

14. The method for preparing a semiconductor device according to claim 12, characterized in that: The step of replacing the gate sacrificial layer with the gate layer comprises: forming a protection layer covering the stack layer, the storage layer and the channel sacrificial layer; Removing the gate sacrificial layer to form a cavity; The gate layer is filled in the cavity.

15. The method for preparing a semiconductor device according to claim 13, characterized in that: Before the step of removing the substrate and a portion of the storage layer located in the substrate, the method for preparing the semiconductor device further includes: forming a bit line lead-out contact on the channel sacrificial layer, and forming a first bonding contact on a side of the stacked structure away from the substrate; providing a control circuit, the control circuit comprising a circuit layer and a second bonding contact; The first bonding contact is bonded to the second bonding contact, and the circuit layer is located on a side of the second bonding contact facing away from the first bonding contact.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: The method for preparing the semiconductor device further includes: A common source layer is formed on a side of the stack structure away from the control circuit, and the common source layer is connected to an end of the channel layer away from the bit line lead-out contact; A through contact is formed at the periphery of the stack structure, wherein the through contact connects the common source layer and the first bonding contact.

17. A storage system, characterized in that: The storage system comprises: The semiconductor device according to any one of claims 1 to 10; A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

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