Package including substrate and interconnect die configured for high density interconnection

Abstract

A package includes: a substrate (102) including a first surface and a second surface; a first integrated device (103) coupled to the first surface of the substrate; an interconnect die (110) coupled to the first surface of the substrate; a first encapsulation layer (104) coupled to the first surface of the substrate, where the first encapsulation layer encapsulates the first integrated device and the interconnect die; and a second integrated device (105) coupled to the second surface of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application serial number 17 / 741,986 filed in the U.S. Patent Office on May 11, 2022, the entire contents of which are incorporated herein by reference as if fully set forth in its entirety below and for all applicable purposes. Technical Field

[0003] Various features are directed to a package having a substrate and an integrated device. Background Art

[0004] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various electrical functions. There is a constant need to provide a package with better performance and to reduce the overall size of the package. Summary of the invention

[0005] Various features are directed to a package having a substrate and an integrated device.

[0006] An example provides a package, which includes: a substrate, the substrate including a first surface and a second surface; a first integrated device, the first integrated device coupled to the first surface of the substrate; a dummy die, the dummy die coupled to the first surface of the substrate; a first packaging layer, the first packaging layer coupled to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the dummy die; and a second integrated device, the second integrated device coupled to the second surface of the substrate.

[0007] Another example provides a device, which includes a package. The package includes: a substrate, the substrate including a first surface and a second surface; a first integrated device, the first integrated device coupled to the first surface of the substrate; a dummy die, the dummy die coupled to the first surface of the substrate; a first packaging layer, the first packaging layer coupled to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the dummy die; and a second integrated device, the second integrated device coupled to the second surface of the substrate.

[0008] Another example provides a method for manufacturing a package. The method provides a substrate, the substrate comprising a first surface and a second surface. The method couples a first integrated device to the first surface of the substrate. The method couples an interconnect die to the first surface of the substrate. The method couples a first packaging layer to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the interconnect die. The method couples a second integrated device to the second surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings, in which like reference characters designate corresponding features throughout.

[0010] Figure 1 An exemplary cross-sectional profile view of a package including a substrate and at least one interconnected die is illustrated.

[0011] Figure 2 An exemplary cross-sectional profile view of a package including a substrate and at least one interconnected die is illustrated.

[0012] FIG. 3A to FIG. 3B An exemplary process for fabricating an interconnect die is illustrated.

[0013] FIG. 4A to FIG. 4B An exemplary process for fabricating an interconnect die is illustrated.

[0014] Figure 5 An exemplary flow chart of a method for fabricating an interconnect die is illustrated.

[0015] FIG. 6A to FIG. 6C An exemplary process for manufacturing a package including a substrate and an interconnect die is illustrated.

[0016] Figure 7 An exemplary flow chart of a method for manufacturing a package including a substrate and an interconnect die is illustrated.

[0017] FIG. 8A to FIG. 8C An exemplary process for manufacturing a package including a substrate and an interconnect die is illustrated.

[0018] Fig. 9 An exemplary flow chart of a method for manufacturing a package including a substrate and an interconnect die is illustrated.

[0019] FIG. 10A to FIG. 10B An exemplary process for manufacturing a substrate is illustrated.

[0020] Fig.11 An exemplary flow chart of a method for manufacturing a substrate is illustrated.

[0021] Fig.12 Various electronic devices are illustrated that may integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION

[0022] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, those of ordinary skill in the art will appreciate that these aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid complicating these aspects with unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of the present disclosure.

[0023] The present disclosure describes a package, the package comprising: a substrate, the substrate comprising a first surface and a second surface; a first integrated device, the first integrated device coupled to the first surface of the substrate; an interconnection die, the interconnection die coupled to the first surface of the substrate; a first packaging layer, the first packaging layer coupled to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the interconnection die; and a second integrated device, the second integrated device coupled to the second surface of the substrate. As will be further described below, the package provides high density interconnects, which helps provide improved package performance while keeping the package small and thin.

[0024] Exemplary package including substrate and interconnect die

[0025] Figure 1 A cross-sectional cutaway view of a package 100 including a substrate and high density interconnects is illustrated. Package 100 is coupled to board 108 via a plurality of solder interconnects 115. Board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. Board 108 may include a printed circuit board (PCB).

[0026] Package 100 includes at least one interconnected die 101, substrate 102, integrated device 103, integrated device 105, integrated device 107, passive device 109a, passive device 109b, passive device 109c, packaging layer 104, packaging layer 106, and external metal layer 160. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 includes a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface).

[0027] The integrated device 103 (e.g., the first integrated device) is coupled to a first surface (e.g., the bottom surface) of the substrate 102 through a plurality of solder interconnects 130. The integrated device 103 may be coupled to the substrate 102 through a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 130. An underfill 132 may be present between the integrated device 103 and the substrate 102. The at least one interconnect die 101 may be coupled to the first surface of the substrate 102 through a plurality of solder interconnects 114. As will be further described below, the at least one interconnect die 101 may be configured to provide a high-density interconnect to the package 100. The encapsulation layer 104 may be coupled to the first surface of the substrate 102. The encapsulation layer 104 may encapsulate (e.g., partially or completely) the integrated device 103 and the at least one interconnect die 101. The encapsulation layer 104 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 104 may be a member for encapsulation. The encapsulation layer 104 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The integrated device 103 may include a front side and a back side. The front side of the integrated device 103 may face the substrate 102. The back side of the integrated device 103 may face the board 108. The back side of the integrated device 103 may be covered by the encapsulation layer 104. In some implementations, the back side (e.g., the back side surface) of the integrated device 103 may remain exposed (e.g., not covered by the encapsulation layer 104). Figure 2 An example of how the back side of the integrated device 103 may be exposed is illustrated and described in .

[0028] At least one interconnect die 101 includes a die substrate 110 and a plurality of die interconnects 112. The die substrate 110 may include silicon. The plurality of die interconnects 112 include a pad interconnect 112a (e.g., a pad), a via interconnect 112b (e.g., a via), and a pad interconnect 112c (e.g., a pad). The pad interconnect 112a is coupled to the via interconnect 112b. The via interconnect 112b is coupled to the pad interconnect 112c. The pad interconnect 112a is coupled to a solder interconnect 114a. The solder interconnect 114a is a part of the plurality of solder interconnects 114. The plurality of solder interconnects 114 are coupled to the plurality of die interconnects 112. The pad interconnect 112c is coupled to a solder interconnect 115a. The solder interconnect 115a is a part of the plurality of solder interconnects 115. At least one interconnect die 101 may be a dummy die. The interconnect die 101 may not have any transistors. At least one interconnect die 101 may not have active components. At least one interconnect die 101 may be a member for die interconnection.

[0029] The plurality of die interconnects 112 may have a pitch between adjacent die interconnects in the range of about 150 microns-270 microns. The packaging layer 104 may have a thickness (e.g., height) in the range of about 150 microns-300 microns. The plurality of solder interconnects 115 may have a diameter and / or thickness of about 100 microns. The total combined thickness (e.g., height) of the plurality of solder interconnects 114, the at least one interconnect die 101, and the plurality of solder interconnects 115 may be in the range of about 250 microns-400 microns. These dimensions are possible by using at least one interconnect die 101, which (i) helps provide a thinner package 100 that is still able to accommodate bottom-side integrated devices (e.g., having sufficient support height), and (ii) helps provide interconnects with low pitches (e.g., 150 microns-270 microns) in the packaging layer, and thus helps provide high-density wiring (e.g., high-density interconnects) in the packaging layer.

[0030] The integrated device 105 (e.g., the second integrated device) is coupled to the second surface (e.g., the top surface) of the substrate 102 through a plurality of solder interconnects 152. For example, the integrated device 105 may be coupled to the plurality of interconnects 122 of the substrate 102 through the plurality of solder interconnects 152. The integrated device 105 may be coupled to the substrate 102 through a plurality of pillar interconnects (not shown) and the plurality of solder interconnects 152. The integrated device 107 (e.g., the third integrated device) is coupled to the second surface of the substrate 102 through a plurality of solder interconnects 172. For example, the integrated device 107 may be coupled to the plurality of interconnects 122 of the substrate 102 through a plurality of solder interconnects 172. The integrated device 107 may be coupled to the substrate 102 through a plurality of pillar interconnects (not shown) and the plurality of solder interconnects 172. The passive device 109a is coupled to the second surface of the substrate 102 through a plurality of solder interconnects 190a. For example, the passive device 109a is coupled to the plurality of interconnects 122 of the substrate 102 through the plurality of solder interconnects 190a. The passive device 109b is coupled to the second surface of the substrate 102 through the plurality of solder interconnects 190b. For example, the passive device 109b is coupled to the plurality of interconnects 122 of the substrate 102 through the plurality of solder interconnects 190b. The passive device 109c is coupled to the second surface of the substrate 102 through the plurality of solder interconnects 190c. For example, the passive device 109c is coupled to the plurality of interconnects 122 of the substrate 102 through the plurality of solder interconnects 190c. The passive devices (e.g., 109a, 109b, 109c) may include capacitors and / or inductors.

[0031] The encapsulation layer 106 is coupled to the second surface (e.g., the top surface) of the substrate 102. The encapsulation layer 106 may encapsulate the integrated device 105, the integrated device 107, the passive device 109a, the passive device 109b, and the passive device 109c. The encapsulation layer 106 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 106 may be a member for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0032] The external metal layer 160 may be coupled to an outer surface of the encapsulation layer 106. The outer surface of the encapsulation layer 106 may include a top surface and a side surface. The external metal layer 160 may also be coupled to a side surface of the substrate 102 and a side surface of the encapsulation layer 104. The external metal layer 160 may be configured to be coupled to ground. The external metal layer 160 may be configured to serve as an electromagnetic interference (EMI) shield for the package 100. The external metal layer 160 may be configured to be coupled to one or more interconnects from the plurality of interconnects 122 of the substrate 102.

[0033] Figure 2 2 illustrates a cross-sectional view of a package 200 including a substrate and high density interconnects. Figure 1 The package 200 is similar to the package 100 and thus includes the same or similar components as the package 100. The package 200 includes at least one interconnect die 201 having the same Figure 1 The at least one interconnect die 101 has a different configuration.

[0034] The package 200 is coupled to the board 108 through a plurality of solder interconnects 115. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB).

[0035] Package 200 includes at least one interconnect die 201, substrate 102, integrated device 103, integrated device 105, integrated device 107, passive device 109a, passive device 109b, passive device 109c, packaging layer 104, packaging layer 106, and external metal layer 160. At least one interconnect die 201 is coupled to the first surface of substrate 102 through a plurality of solder interconnects 114.

[0036] At least one interconnect die 201 includes a die substrate 110 and a plurality of die interconnects 112. The die substrate 110 may include silicon. The plurality of die interconnects 112 include pad interconnects 112a (e.g., pads) and via interconnects 112b (e.g., vias). The pad interconnects 112a are coupled to the via interconnects 112b. The pad interconnects 112a are coupled to solder interconnects 114a. The solder interconnects 114a are part of the plurality of solder interconnects 114. The plurality of solder interconnects 114 are coupled to the plurality of die interconnects 112. The via interconnects 112b are coupled to solder interconnects 115a. The solder interconnects 115a are part of the plurality of solder interconnects 115. At least one interconnect die 101 may be a dummy die. Thus, one possible difference between at least one interconnect die 201 and at least one interconnect die 101 is that at least one interconnect die 201 does not include pad interconnect 112c. One advantage of not having pad interconnect 112c is that at least one interconnect die 201 can be thinner than at least one interconnect die 101, which can help reduce the overall thickness of the package. At least one interconnect die 201 can be a dummy die. The interconnect die 201 can not have any transistors. The at least one interconnect die 201 can not have active components. The at least one interconnect die 201 can be a member for die interconnection.

[0037] The plurality of die interconnects 112 of at least one interconnect die 201 may have a pitch between adjacent die interconnects in the range of about 150 microns-270 microns. The packaging layer 104 may have a thickness (e.g., height) in the range of about 150 microns-300 microns. The plurality of solder interconnects 115 may have a diameter and / or thickness of about 100 microns. The total combined thickness (e.g., height) of the plurality of solder interconnects 114, the at least one interconnect die 201, and the plurality of solder interconnects 115 may be in the range of about 250 microns-400 microns. By using at least one interconnect die 201, these dimensions are possible, which (i) helps provide a thinner package 200 that is still able to accommodate bottom-side integrated devices (e.g., having sufficient support height), and (ii) helps provide interconnects with low pitches (e.g., 150 microns-270 microns) in the packaging layer, and thus helps provide high-density wiring (e.g., high-density interconnects) in the packaging layer.

[0038] Another difference between package 200 and package 100 is that the back side of integrated device 103 of package 200 is exposed. Figure 2As shown, at least a portion of the back side of the integrated device 103 is not covered by the encapsulation layer 104. This may be because during the manufacturing process of the package 200, portions of the encapsulation layer 104, portions of the back side of the integrated device 103, and / or portions of the at least one interconnected die 201 may be removed during a grinding and / or polishing process of the bottom side of the package 200. However, it should be noted that in some specific implementations of the package 200, the back side of the integrated device 103 may be covered by the encapsulation layer 104.

[0039] The integrated device (e.g., 103, 105, 107) may include a die (e.g., a bare semiconductor die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, an integrated device based on gallium arsenide (GaAs), a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or a combination thereof. The integrated device (e.g., 103, 105, 107) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may be a core particle. The core particles can be manufactured using a process that provides better yields than manufacturing processes for other types of integrated devices, which can reduce the overall cost of manufacturing the core particles. Different core particles can have different sizes and / or shapes. Different core particles can be configured to provide different functions. Different core particles can have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several core particles can be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Relative to using a single chip to perform all the functions of a package, using several core particles that perform several functions can reduce the overall cost of the package.

[0040] The package (e.g., 100, 200) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 100, 200) may be configured to provide wireless fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 300) may be configured to support a global system for mobile communications (GSM), a universal mobile telecommunications system (UMTS), and / or long term evolution (LTE). The package (e.g., 100, 200) may be configured to send and receive signals having different frequencies and / or communication protocols.

[0041] Having described various interconnect dies, processes for fabricating the interconnect dies will now be described below.

[0042] Exemplary Process for Fabricating Interconnect Dies

[0043] In some implementations, fabricating an interconnect die includes several processes. FIG. 3A to FIG. 3B An exemplary process for providing or manufacturing an interconnect die is illustrated. In some implementations, an FIG. 3A to FIG. 3B The interconnect die 101 may be provided or manufactured using a process. FIG. 3A to FIG. 3B The process of manufacturing any interconnect die (e.g., 201) described in this disclosure.

[0044] It should be noted that FIG. 3A to FIG. 3B The process of the present invention may combine one or more stages to simplify and / or clarify the process for providing or manufacturing the interconnect die. In some implementations, the order of the processes may be changed or improved. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of the present disclosure.

[0045] like Figure 3A As shown, stage 1 illustrates a state after providing a die substrate 110. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface.

[0046] Stage 2 illustrates a state after forming a plurality of cavities 302 in the die substrate 110. For example, the plurality of cavities 302 may be formed through the first surface of the die substrate 110. The plurality of cavities 302 may include trenches. The plurality of cavities 302 may extend partially through the thickness of the die substrate 110. The plurality of cavities 302 may be formed using a laser ablation process and / or an etching process.

[0047] Stage 3 illustrates after forming a metal layer 305 in the plurality of cavities 302 and / or on the first surface of the die substrate 110. The metal layer 305 may include copper. The metal layer 305 may be formed using a plating process.

[0048] Stage 4 illustrates a state after portions of metal layer 305 are removed. For example, portions of metal layer 305 coupled to the first surface of die substrate 110 may be removed, leaving metal layer 305 in the plurality of cavities 302. A polishing process may be used to remove portions of metal layer 305. The remaining metal from metal layer 305 in the plurality of cavities 302 may define a plurality of interconnects 112 b, such as Figure 1 and Figure 2 Described in .

[0049] like Figure 3B As shown, stage 5 illustrates a state after forming a metal layer 307 on the first surface of the die substrate 110. The metal layer 307 may be formed using a plating process. The metal layer 307 may be coupled to the metal layer 305. The metal layer 307 may define a plurality of interconnects 112a, such as Figure 1 and Figure 2 Metal layer 307 may represent a front-side interconnect that interconnects the die.

[0050] Stage 6 illustrates a state after thinning the die substrate 110. For example, a portion of the die substrate 110 may be removed, leaving at least the die substrate 110a, so that the bottom side of the metal layer 305 is exposed. In some implementations, a portion of the die substrate 110 may be removed, leaving at least the die substrate 110a and the die substrate 110b. When the die substrate 110b is present, the bottom side of the metal layer 305 is not exposed. A grinding process may be used to remove the portion of the die substrate 110. In some implementations, stage 6 may illustrate an implementation of an interconnect die including an interconnect, and no additional interconnects are formed in, on, or below the die substrate 110. If no additional interconnects are formed, singulation may be performed in a manner similar to that described below at stage 8. As will be further described below, the interconnect die shown in stage 6 may be used to couple to a substrate.

[0051] Stage 7 illustrates a state after forming a metal layer 309 on the second surface of the die substrate 110. The metal layer 309 may be formed using a plating process. The metal layer 309 may be coupled to the metal layer 305. The metal layer 309 may define a plurality of interconnects 112c, such as Figure 1 and Figure 2 Metal layer 309 may represent a backside interconnect of the interconnect die.

[0052] Stage 8 illustrates a state after singulation to form a number of interconnected dies. A mechanical process may be used to singulate the die substrate 110 into a number of interconnected dies (eg, 101). A saw may be used to singulate the die substrate 110.

[0053] Exemplary Process for Fabricating Interconnect Dies

[0054] In some implementations, fabricating an interconnect die includes several processes. FIG. 4A to FIG. 4B An exemplary process for providing or manufacturing an interconnect die is illustrated. In some implementations, an FIG. 4A to FIG. 4B The interconnect die 101 may be provided or manufactured using a process. FIG. 4A to FIG. 4B The process of manufacturing any interconnect die (e.g., 201) described in this disclosure.

[0055] It should be noted that FIG. 4A to FIG. 4B The process of the present invention may combine one or more stages to simplify and / or clarify the process for providing or manufacturing the interconnect die. In some implementations, the order of the processes may be changed or improved. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of the present disclosure.

[0056] like Figure 4A As shown, stage 1 illustrates a state after providing a die substrate 110. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface.

[0057] Stage 2 illustrates a state after forming a plurality of cavities 402 in the die substrate 110. For example, the plurality of cavities 402 may be formed through the first surface of the die substrate 110. The plurality of cavities 402 may include trenches. The plurality of cavities 402 may extend partially through the thickness of the die substrate 110. The plurality of cavities 402 may be formed using a laser ablation process and / or an etching process.

[0058] Stage 3 illustrates a state after forming a metal layer 405 in the plurality of cavities 402 and / or on the first surface of the die substrate 110. The metal layer 405 may include copper. The metal layer 405 may be formed using a filling process, wherein the plurality of cavities 402 may be filled with a conductive paste.

[0059] Stage 4 illustrates a state after portions of metal layer 405 are removed. For example, portions of metal layer 405 coupled to the first surface of die substrate 110 may be removed, leaving metal layer 405 in the plurality of cavities 402. A polishing process may be used to remove portions of metal layer 405. The remaining metal from metal layer 405 in the plurality of cavities 402 may define a plurality of interconnects 112 b, such as Figure 1 and Figure 2 Described in .

[0060] like Figure 4BAs shown, stage 5 illustrates a state after forming a metal layer 407 on the first surface of the die substrate 110. The metal layer 407 may be formed using a plating process. The metal layer 407 may be coupled to the metal layer 405. The metal layer 407 may define a plurality of interconnects 112a, such as Figure 1 and Figure 2 Metal layer 407 may represent a front-side interconnect that interconnects the die.

[0061] Stage 6 illustrates a state after thinning the die substrate 110. For example, a portion of the die substrate 110 may be removed, leaving at least the die substrate 110a, so that the bottom side of the metal layer 405 is exposed. In some implementations, a portion of the die substrate 110 may be removed, leaving at least the die substrate 110a and the die substrate 110b. When the die substrate 110b is present, the bottom side of the metal layer 405 is not exposed. A grinding process may be used to remove the portion of the die substrate 110. In some implementations, stage 6 may illustrate an implementation of an interconnect die including an interconnect, and no additional interconnects are formed in, on, or below the die substrate 110. If no additional interconnects are formed, singulation may be performed in a manner similar to that described below at stage 8. As will be further described below, the interconnect die shown in stage 6 may be used to couple to a substrate.

[0062] Stage 7 illustrates a state after forming a metal layer 409 on the second surface of the die substrate 110. The metal layer 409 may be formed using a plating process. The metal layer 409 may be coupled to the metal layer 405. The metal layer 409 may define a plurality of interconnects 112c, such as Figure 1 and Figure 2 Metal layer 409 may represent a backside interconnect of the interconnect die.

[0063] Stage 8 illustrates a state after singulation to form a number of interconnected dies. A mechanical process may be used to singulate the die substrate 110 into a number of interconnected dies (eg, 101). A saw may be used to singulate the die substrate 110.

[0064] Exemplary flow chart of a method for manufacturing an interconnect die

[0065] In some implementations, fabricating an interconnect die includes several processes. Figure 5 An exemplary flow chart of a method 500 for providing or manufacturing an interconnect die is illustrated. In some implementations, the method may be used Figure 5 The method 500 is used to provide or manufacture the interconnect die 101 described in the present disclosure. However, the method 500 may be used to provide or manufacture any interconnect die (eg, 201) described in the present disclosure.

[0066] It should be noted that Figure 5The method 500 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an interconnect die. In some implementations, the order of the processes may be changed or modified.

[0067] The method provides (at 505) a die substrate (e.g., 110). The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface. Figure 3A Stage 1 of the present invention illustrates and describes an example of providing a die substrate. Figure 4A Stage 1 of the present invention illustrates and describes an example of providing a die substrate.

[0068] The method forms (at 510) a plurality of cavities (e.g., 302, 402) in the die substrate 110. For example, the plurality of cavities (e.g., 302, 402) may be formed through a first surface of the die substrate 110. The plurality of cavities (e.g., 302, 402) may include trenches. The plurality of cavities (e.g., 302, 402) may extend partially through a thickness of the die substrate 110. The plurality of cavities (e.g., 302, 402) may be formed using a laser ablation process and / or an etching process. Figure 3A Stage 2 of FIG. 1 illustrates and describes an example of forming a cavity in a die substrate. Figure 4A Stage 2 of FIG. 1 illustrates and describes an example of forming a cavity in a die substrate.

[0069] The method forms (at 515) a conductive material in the plurality of cavities (e.g., 302, 402) of the die substrate 110. The conductive material may include a metal layer (e.g., 305, 405). The conductive material may be formed on a surface of the die substrate 110. The conductive material may include copper. The conductive material may be formed using a plating process. The conductive material may be formed using a filling process. Figure 3A Stage 3 of the present invention illustrates and describes an example of forming a conductive material in a die substrate. Figure 4A Stage 3 of exemplifies and describes an example of forming a conductive material in the die substrate. In some implementations, forming the conductive material may include removing portions of the conductive material. A polishing process may be used to remove the portions of the conductive material. Removing the portions of the conductive material may include removing portions of the conductive material coupled to the first surface of the die substrate 110 and leaving the conductive material in the plurality of cavities (e.g., 302, 402) of the die substrate 110. Figure 3A Stage 4 of the present invention illustrates and describes an example of removing portions of the conductive material in the die substrate. Figure 4AStage 4 of the present invention illustrates and describes an example of removing portions of the conductive material in the die substrate.

[0070] The method forms (at 520) a plurality of front side interconnects. The front side interconnects may be coupled to the top side of the die substrate 110. The plurality of front side interconnects may be defined by a patterned metal layer (e.g., 307, 407) on the top surface of the die substrate 110. The metal layers (e.g., 307, 407) may be formed using a plating process. Metal layer 307 may be coupled to metal layer 305. Metal layer 407 may be coupled to metal layer 405. Metal layer 407 may define a plurality of interconnects 112b, such as Figure 1 and Figure 2 . Metal layer 407 may represent a front-side interconnect of an interconnect die. Multiple interconnects 112a may represent the multiple front-side interconnects of an interconnect die. Figure 3B Stage 5 of exemplifies and describes an example of forming a front-side interconnect. Figure 4B Stage 5 of exemplifies and describes an example of forming a front-side interconnect.

[0071] The method thins (at 525) the die substrate (e.g., 110). Different implementations may thin the die substrate 110 in different ways. For example, some implementations may thin the die substrate 110 so that the bottom side of the metal layer (e.g., 305, 405) is exposed. Some implementations may thin the die substrate 110 without exposing the bottom side of the metal layer (e.g., 305, 405). A grinding process may be used to remove portions of the die substrate 110. Figure 3B Stage 6 of the present invention illustrates and describes an example of thinning the die substrate. Figure 4B Stage 6 of the present invention illustrates and describes an example of thinning the die substrate.

[0072] The method optionally forms (at 530) a plurality of backside interconnects. The backside interconnects may be coupled to the bottom side of the die substrate 110. The plurality of backside interconnects may be defined by a patterned metal layer (e.g., 309, 409) on the top surface of the die substrate 110. The metal layer (e.g., 309, 409) may be formed using a plating process. Metal layer 309 may be coupled to metal layer 305. Metal layer 409 may be coupled to metal layer 405. Metal layer 409 may define a plurality of interconnects 112c, such as Figure 1 and Figure 2 . Metal layer 409 may represent a backside interconnect of an interconnect die. Multiple interconnects 112c may represent the multiple backside interconnects of an interconnect die. Figure 3B Stage 7 of FIG. 1 illustrates and describes an example of forming a backside interconnect. Figure 4B Stage 7 of FIG. 1 illustrates and describes an example of forming a backside interconnect.

[0073] The method singulates (at 535) the die substrate 110 to form a number of interconnected dies (eg, 101, 201). A mechanical process may be used to singulate the die substrate 110 into the number of interconnected dies (eg, 101). A saw may be used to singulate the die substrate 110. Figure 3B Stage 8 of the present invention illustrates and describes an example of singulation. Figure 4B Stage 8 of the present invention illustrates and describes an example of singulation.

[0074] Exemplary process for making a package including a substrate and an interconnect die

[0075] In some implementations, manufacturing a package includes several processes. FIG. 6A to FIG. 6C An exemplary process for providing or manufacturing a package is illustrated. In some implementations, a FIG. 6A to FIG. 6C The package 100 can be provided or manufactured using a process. FIG. 6A to FIG. 6C 200 ) described in the present disclosure.

[0076] It should be noted that FIG. 6A to FIG. 6C The process of one or more stages may be combined to simplify and / or illustrate the process for providing or manufacturing a package. In some implementations, the order of each process may be changed or improved. In some implementations, one or more of these processes may be replaced or substituted without departing from the scope of the present disclosure.

[0077] like Fig. 6A As shown, stage 1 illustrates a state after providing a substrate 102. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 102 may be formed using a dielectric layer 120, e.g., a bottom surface, and a second surface (e.g., a top surface). FIG. 10A to FIG. 10B In some implementations, a core substrate (eg, a substrate including a core layer) is provided.

[0078] Stage 2 illustrates a state after coupling the integrated device 103 to the first surface (e.g., bottom surface) of the substrate 102. The integrated device 103 may be coupled to the substrate 102 via a plurality of solder interconnects 130. A solder reflow process may be used to couple the integrated device 103 to the substrate 102. In some implementations, the integrated device 103 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and the plurality of solder interconnects 130. Stage 2 also illustrates a state after coupling at least one interconnect die 101 to the first surface of the substrate 102. The at least one interconnect die 101 may be coupled to the substrate 102 via a plurality of solder interconnects 114. A solder reflow process may be used to couple the at least one interconnect die 101 to the substrate 102. Stage 2 also illustrates an underfill 132 provided and / or formed between the first integrated device 105 and the substrate 102.

[0079] Stage 3 illustrates a state after providing and coupling the encapsulation layer 104 to the substrate 102. The encapsulation layer 104 may encapsulate the integrated device 103 and the at least one interconnected die 101. The encapsulation layer 104 may be coupled to the first surface of the substrate 102. The encapsulation layer 104 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 104 may be a member for encapsulation. The encapsulation layer 104 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0080] Stage 4 illustrates a state after portions of the encapsulation layer 104 are removed. A grinding process and / or a polishing process may be used to remove portions of the encapsulation layer 104. In some implementations, portions of at least one interconnect die 101 and / or portions of the backside of the integrated device 103 may also be removed.

[0081] like Figure 6B As shown, stage 5 illustrates a state after the integrated device 105, the integrated device 107, and the plurality of passive devices 109 (e.g., 109a, 109b, 109c) are coupled to the second surface (e.g., top surface) of the substrate 102. The integrated device 105 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 152. The integrated device 107 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 172. The plurality of passive devices 109 (e.g., 109a, 109b, 109c) may be coupled to the substrate 102 via a corresponding plurality of solder interconnects (e.g., 190a, 190b, 190c). A solder reflow process may be used to couple the integrated devices and / or passive devices to the substrate 102.

[0082] Stage 6 illustrates a state after the encapsulation layer 106 is provided to and coupled to the substrate 102. The encapsulation layer 106 may encapsulate the integrated devices (e.g., 105, 107) and the passive devices (e.g., 109a, 109b, 109c). The encapsulation layer 106 may be coupled to the second surface of the substrate 102. The encapsulation layer 106 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 106 may be a member for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0083] like Figure 6C As shown, stage 7 illustrates a state after the plurality of solder interconnects 115 are coupled to the at least one interconnect die 101. The plurality of solder interconnects 115 may be coupled to the at least one interconnect die 101 using a solder reflow process.

[0084] Stage 8 illustrates a state after forming an outer metal layer 160 on the outer surface of the encapsulation layer 106. The outer metal layer 160 may be formed using a sputtering process. The outer metal layer 160 may be formed on the top surface of the encapsulation layer 106, the side surface of the encapsulation layer 106, the side surface of the substrate 102, and / or the side surface of the encapsulation layer 104. Stage 8 may illustrate the package 100. The package 100 may be manufactured one at a time, or may be manufactured together as part of one or more wafers and then singulated into individual packages.

[0085] Exemplary flow chart of a method for manufacturing a package including a substrate and an interconnect die

[0086] In some implementations, manufacturing a package includes several processes. Figure 7 An exemplary flow chart of a method 700 for providing or manufacturing a package is illustrated. In some implementations, Figure 7 The method 700 may be used to provide or manufacture the package 100 described in the present disclosure. However, the method 700 may be used to provide or manufacture any package (eg, 200) described in the present disclosure.

[0087] It should be noted that Figure 7 The method 700 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0088] The method provides (at 705) a substrate (e.g., 102). The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 102 may be fabricated using a dielectric layer such as FIG. 10A to FIG. 10B In some implementations, a core substrate (eg, a substrate including a core layer) is provided. Fig. 6A Stage 1 of the present invention illustrates and describes an example of providing a substrate.

[0089] The method couples (at 710) an integrated device (e.g., 103) and at least one interconnect die (e.g., 101) to a first surface (e.g., bottom surface) of a substrate 102. The integrated device 103 may be coupled to the substrate 102 via a plurality of solder interconnects 130. A solder reflow process may be used to couple the integrated device 103 to the substrate 102. The at least one interconnect die 101 may be coupled to the substrate 102 via a plurality of solder interconnects 114. A solder reflow process may be used to couple the at least one interconnect die 101 to the substrate 102. Fig. 6A Stage 2 of FIG. 1 illustrates and describes an example of coupling an integrated device and interconnect die to a substrate.

[0090] The method forms (at 715) an encapsulation layer (e.g., 104) coupled to a substrate (e.g., 102). Encapsulation layer 104 (e.g., a first encapsulation layer) may encapsulate integrated device 103 and at least one interconnected die 101. Encapsulation layer 104 may be coupled to a first surface of substrate 102. Encapsulation layer 104 may include a molding, a resin, and / or an epoxy. Encapsulation layer 104 may be a component for encapsulation. Encapsulation layer 104 may be provided using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, forming the encapsulation layer may include removing portions of encapsulation layer 104. A grinding process and / or a polishing process may be used to remove portions of encapsulation layer 104. In some implementations, portions of at least one interconnected die 101 and / or portions of the back side of integrated device 103 may also be removed. Fig. 6A Stages 3 and 4 of the present invention illustrate and describe examples of providing an encapsulation layer and removing portions of the encapsulation layer.

[0091] The method couples (at 720) integrated devices (e.g., 105, 107) and passive devices (e.g., 109a, 109b, 109c) to a second surface (e.g., top surface) of the substrate 102. The integrated device 105 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 152. The integrated device 107 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 172. A plurality of passive devices 109 (e.g., 109a, 109b, 109c) may be coupled to the substrate 102 via a corresponding plurality of solder interconnects (e.g., 190a, 190b, 190c). A solder reflow process may be used to couple the integrated devices and / or passive devices to the substrate 102. Figure 6B Stage 5 of exemplifies and describes an example of coupling integrated devices and passive devices to a substrate.

[0092] The method forms (at 725) an encapsulation layer (e.g., 106). The encapsulation layer is coupled to the substrate 102. The encapsulation layer 106 (e.g., a second encapsulation layer) may encapsulate integrated devices (e.g., 105, 107) and passive devices (e.g., 109a, 109b, 109c). The encapsulation layer 106 may be coupled to the second surface of the substrate 102. The encapsulation layer 106 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 106 may be a member for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Figure 6B Stage 6 of illustrates and describes an example of providing an encapsulation layer.

[0093] The method couples (at 730) a plurality of solder interconnects (eg, 115) to the at least one interconnect die 101. The plurality of solder interconnects 115 may be coupled to the at least one interconnect die 101 using a solder reflow process. Figure 6C Stage 7 of the present invention illustrates and describes an example of coupling a solder interconnect to a substrate.

[0094] The method forms (at 735) an external metal layer (e.g., 160) on an outer surface of the encapsulation layer 106. A sputtering process may be used to form the external metal layer 160. The external metal layer 160 may be formed on a top surface of the encapsulation layer 106, a side surface of the encapsulation layer 106, a side surface of the substrate 102, and / or a side surface of the encapsulation layer 104. The external metal layer 160 may be coupled to an interconnect from the plurality of interconnects 122 of the substrate 102. The external metal layer 160 may be configured to function as an electromagnetic interference (EMI) shield for the package 100. Figure 6C Stage 8 of the present invention illustrates and describes an example of forming an outer metal layer.

[0095] In some implementations, several packages are manufactured simultaneously. In such cases, the method can singulate the packages (eg, 100, 200).

[0096] Exemplary process for making a package including a substrate and an interconnect die

[0097] In some implementations, manufacturing a package includes several processes. FIG. 8A to FIG. 8C An exemplary process for providing or manufacturing a package is illustrated. In some implementations, a FIG. 8A to FIG. 8C The package 200 can be provided or manufactured using a process. FIG. 8A to FIG. 8C The process of manufacturing any package (e.g., 100) described in this disclosure.

[0098] It should be noted that FIG. 8A to FIG. 8CThe process of one or more stages may be combined to simplify and / or illustrate the process for providing or manufacturing a package. In some implementations, the order of each process may be changed or improved. In some implementations, one or more of these processes may be replaced or substituted without departing from the scope of the present disclosure.

[0099] like Fig. 8A As shown, stage 1 illustrates a state after providing a substrate 102. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 102 may be formed using a dielectric layer 120, e.g., a bottom surface, and a second surface (e.g., a top surface). FIG. 10A to FIG. 10B In some implementations, a core substrate (eg, a substrate including a core layer) is provided.

[0100] Stage 2 illustrates a state after the integrated device 105, the integrated device 107, and the plurality of passive devices 109 (e.g., 109a, 109b, 109c) are coupled to the second surface (e.g., top surface) of the substrate 102. The integrated device 105 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 152. The integrated device 107 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 172. The plurality of passive devices 109 (e.g., 109a, 109b, 109c) may be coupled to the substrate 102 via a corresponding plurality of solder interconnects (e.g., 190a, 190b, 190c). A solder reflow process may be used to couple the integrated devices and / or the passive devices to the substrate 102.

[0101] Stage 3 illustrates a state after the encapsulation layer 106 is provided to and coupled to the substrate 102. The encapsulation layer 106 (e.g., a second encapsulation layer) may encapsulate integrated devices (e.g., 105, 107) and passive devices (e.g., 109a, 109b, 109c). The encapsulation layer 106 may be coupled to the second surface of the substrate 102. The encapsulation layer 106 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 106 may be a member for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0102] like Figure 8BAs shown, stage 4 illustrates a state after the integrated device 103 is coupled to the first surface (e.g., bottom surface) of the substrate 102. The integrated device 103 may be coupled to the substrate 102 via a plurality of solder interconnects 130. The integrated device 103 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and the plurality of solder interconnects 130. A solder reflow process may be used to couple the integrated device 103 to the substrate 102. Stage 2 also illustrates a state after at least one interconnect die 201 is coupled to the first surface of the substrate 102. The at least one interconnect die 201 may be coupled to the substrate 102 via a plurality of solder interconnects 114. A solder reflow process may be used to couple the at least one interconnect die 201 to the substrate 102. Stage 2 also illustrates an underfill 132 provided and / or formed between the first integrated device 105 and the substrate 102.

[0103] Stage 5 illustrates a state after providing and coupling an encapsulation layer 104 (e.g., a first encapsulation layer) to the substrate 102. The encapsulation layer 104 may encapsulate the integrated device 103 and the at least one interconnected die 201. The encapsulation layer 104 may be coupled to the first surface of the substrate 102. The encapsulation layer 104 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 104 may be a member for encapsulation. The encapsulation layer 104 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0104] Stage 6 illustrates a state after portions of encapsulation layer 104 are removed. A grinding process and / or a polishing process may be used to remove portions of encapsulation layer 104. Portions of at least one interconnect die 201 and / or portions of the back side of integrated device 103 may also be removed. Removing portions of interconnect die 201 may remove portions of die substrate 110, which may expose interconnects in die substrate 110.

[0105] like Figure 8C As shown, stage 7 illustrates a state after the plurality of solder interconnects 115 are coupled to the at least one interconnect die 201. The plurality of solder interconnects 115 may be coupled to the at least one interconnect die 201 using a solder reflow process.

[0106] Stage 8 illustrates a state after forming an outer metal layer 160 on the outer surface of the encapsulation layer 106. The outer metal layer 160 may be formed using a sputtering process. The outer metal layer 160 may be formed on the top surface of the encapsulation layer 106, the side surface of the encapsulation layer 106, the side surface of the substrate 102, and / or the side surface of the encapsulation layer 104. Stage 8 may illustrate a package 200. The packages 200 may be manufactured one at a time, or may be manufactured together as part of one or more wafers and then singulated into individual packages.

[0107] Exemplary flow chart of a method for manufacturing a package including a substrate and an interconnect die

[0108] In some implementations, manufacturing a package includes several processes. Fig. 9 An exemplary flow chart of a method 900 for providing or manufacturing a package is illustrated. In some implementations, a Fig. 9 The method 900 is used to provide or manufacture the package 200 described in the present disclosure. However, the method 900 may be used to provide or manufacture any package (eg, 100) described in the present disclosure.

[0109] It should be noted that Fig. 9 The method 900 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0110] The method provides (at 905) a substrate (e.g., 102). The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 102 may be fabricated using a dielectric layer such as FIG. 10A to FIG. 10B In some implementations, a core substrate (eg, a substrate including a core layer) is provided. Fig. 8A Stage 1 of the present invention illustrates and describes an example of providing a substrate.

[0111] The method couples (at 910) integrated devices (e.g., 105, 107) and passive devices (e.g., 109a, 109b, 109c) to a second surface (e.g., top surface) of the substrate 102. The integrated device 105 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 152. The integrated device 107 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 172. A plurality of passive devices 109 (e.g., 109a, 109b, 109c) may be coupled to the substrate 102 via a corresponding plurality of solder interconnects (e.g., 190a, 190b, 190c). A solder reflow process may be used to couple the integrated devices and / or passive devices to the substrate 102. Fig. 8A Phase 2 of FIG. 1 illustrates and describes an example of coupling integrated devices and passive devices to a substrate.

[0112] The method forms (at 915) an encapsulation layer (e.g., 106). The encapsulation layer is coupled to the substrate 102. The encapsulation layer 106 (e.g., a second encapsulation layer) may encapsulate integrated devices (e.g., 105, 107) and passive devices (e.g., 109a, 109b, 109c). The encapsulation layer 106 may be coupled to the second surface of the substrate 102. The encapsulation layer 106 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 106 may be a member for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Fig. 8A Stage 3 of exemplifies and describes an example of providing an encapsulation layer.

[0113] The method couples (at 920) an integrated device (e.g., 103) and at least one interconnect die (e.g., 101) to a first surface (e.g., bottom surface) of a substrate 102. The integrated device 103 may be coupled to the substrate 102 via a plurality of solder interconnects 130. The integrated device 103 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and the plurality of solder interconnects 130. A solder reflow process may be used to couple the integrated device 103 to the substrate 102. The at least one interconnect die 101 may be coupled to the substrate 102 via a plurality of solder interconnects 114. A solder reflow process may be used to couple the at least one interconnect die 101 to the substrate 102. Figure 8B Stage 4 of exemplifies and describes an example of coupling an integrated device and interconnect die to a substrate.

[0114] The method forms (at 925) an encapsulation layer (e.g., 104) coupled to a substrate (e.g., 102). The encapsulation layer 104 (e.g., a first encapsulation layer) may encapsulate the integrated device 103 and the at least one interconnected die 101. The encapsulation layer 104 may be coupled to a first surface of the substrate 102. The encapsulation layer 104 may include a molding, a resin, and / or an epoxy. The encapsulation layer 104 may be a component for encapsulation. The encapsulation layer 104 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, forming the encapsulation layer may include removing portions of the encapsulation layer 104. A grinding process and / or a polishing process may be used to remove portions of the encapsulation layer 104. In some implementations, portions of the at least one interconnected die 101 and / or portions of the back side of the integrated device 103 may also be removed. Figure 8B Stages 5 and 6 of illustrate and describe examples of providing an encapsulation layer and removing portions of the encapsulation layer.

[0115] The method couples (at 930) a plurality of solder interconnects (eg, 115) to the at least one interconnect die 101. The plurality of solder interconnects 115 may be coupled to the at least one interconnect die 101 using a solder reflow process. Figure 8CStage 7 of the present invention illustrates and describes an example of coupling a solder interconnect to a substrate.

[0116] The method forms (at 735) an outer metal layer (e.g., 160) on an outer surface of the encapsulation layer 106. A sputtering process may be used to form the outer metal layer 160. The outer metal layer 160 may be formed on a top surface of the encapsulation layer 106, a side surface of the encapsulation layer 106, a side surface of the substrate 102, and / or a side surface of the encapsulation layer 104. Figure 8C Stage 8 of exemplifies and describes an example of forming an outer metal layer.

[0117] In some implementations, several packages are manufactured simultaneously. In such cases, the method can singulate the packages (eg, 100, 200).

[0118] Exemplary Process for Making a Substrate

[0119] In some implementations, manufacturing a substrate includes several processes. FIG. 10A to FIG. 10B An exemplary process for providing or manufacturing a substrate is illustrated. In some implementations, a substrate may be used. FIG. 10A to FIG. 10B The substrate 102 may be provided or manufactured using a process. FIG. 10A to FIG. 10B The process can be used to manufacture any substrate described in this disclosure.

[0120] It should be noted that FIG. 10A to FIG. 10B The process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing the substrate. In some specific implementations, the order of each process can be changed or improved. In some specific implementations, one or more processes in these processes can be replaced or substituted without departing from the scope of the present disclosure.

[0121] like Fig. 10A As shown in , stage 1 illustrates a state after providing a carrier 1000. A seed layer 1001 and an interconnect 1002 may be located above the carrier 1000. The interconnect 1002 may be located above the seed layer 1001. The interconnect 1002 may be formed using a plating process and an etching process. In some implementations, the carrier 1000 may be provided with the seed layer 1001 and a metal layer that is patterned to form the interconnect 1002. The interconnect 1002 may represent at least some of the interconnects from the plurality of interconnects 142.

[0122] Stage 2 illustrates a state after a dielectric layer 1020 is formed on the carrier 1000, the seed layer 1001, and the interconnect 1002. The dielectric layer 1020 may be formed using a deposition process and / or a lamination process. The dielectric layer 1020 may include a prepreg and / or a polyimide. The dielectric layer 1020 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0123] Stage 3 illustrates a state after a plurality of cavities 1010 are formed in the dielectric layer 1020. The plurality of cavities 1010 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0124] Stage 4 illustrates a state after forming interconnects 1012 in and on dielectric layer 1020 (including in and on multiple cavities 1010). For example, vias, pads, and / or traces may be formed. The interconnects may be formed using a plating process.

[0125] Stage 5 illustrates a state after dielectric layer 1022 is formed on dielectric layer 1020 and interconnect 1012. Dielectric layer 1022 may be formed using a deposition process and / or a lamination process. Dielectric layer 1022 may include prepreg and / or polyimide. Dielectric layer 1022 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0126] like Fig. 10B As shown, stage 6 illustrates a state after a plurality of cavities 1030 are formed in the dielectric layer 1022. The plurality of cavities 1030 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0127] Stage 7 illustrates a state after forming interconnects 1014 in and on dielectric layer 1022 (including in and on multiple cavities 1030). For example, vias, pads, and / or traces may be formed. The interconnects may be formed using a plating process.

[0128] Stage 8 illustrates a state after carrier 1000 is decoupled (e.g., separated, removed, ground away) from at least one dielectric layer 140 and seed layer 1001, portions of seed layer 1001 are removed (e.g., etched away), leaving substrate 102 including at least one dielectric layer 120 and a plurality of interconnects 122. At least one dielectric layer 120 may represent dielectric layer 1020 and / or dielectric layer 1022. A plurality of interconnects 122 may represent interconnects 1002, 1012, and / or 1014.

[0129] Different implementations may use different processes to form metal layers and / or interconnects. In some implementations, the metal layers may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0130] Exemplary Flowchart of a Method for Manufacturing a Substrate

[0131] In some implementations, manufacturing a substrate includes several processes. Fig.11An exemplary flow chart of a method 1100 for providing or manufacturing a substrate is illustrated. In some implementations, Fig.11 The method 1100 can be used to provide or manufacture a substrate of the present disclosure. For example, Fig.11 The method 1100 is used to manufacture the substrate 102.

[0132] It should be noted that Fig.11 The method 1100 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0133] The method provides (at 1105) a carrier (e.g., 1000). Different implementations may use different materials for the carrier 1000. The carrier 1000 may include a seed layer (e.g., 1001). The seed layer 1001 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or a carrier tape. Fig. 10A Stage 1 of the present invention illustrates and describes an example of a provided carrier having a seed layer.

[0134] The method forms (at 1110) interconnects on the carrier 1000 and the seed layer 1001 and patterns them. The metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer is located above the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 142). Fig. 10A Stage 1 of FIG. 1 illustrates and describes an example of forming and patterning interconnects on a seed layer and a carrier.

[0135] The method forms (at 1115) a dielectric layer 1020 on the seed layer 1001, the carrier 1000, and the interconnect 1002. The dielectric layer 1020 may be formed using a deposition process and / or a lamination process. The dielectric layer 1020 may include a prepreg and / or a polyimide. The dielectric layer 1020 may include a photoimageable dielectric. Forming the dielectric layer 1020 may also include forming a plurality of cavities (e.g., 1010) in the dielectric layer 1020. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Fig. 10A Stages 2 to 3 of exemplify and describe an example of forming a dielectric layer and forming a cavity in the dielectric layer.

[0136] The method forms (at 1120) an interconnect in and on the dielectric layer. For example, the interconnect 1012 may be formed in and on the dielectric layer 1020. The interconnect may be formed using a plating process. Forming the interconnect may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity of the dielectric layer. Fig. 10A Stage 4 of the present invention illustrates and describes an example of forming interconnects in and on a dielectric layer.

[0137] The method forms (at 1125) a dielectric layer 1022 on the dielectric layer 1020 and the interconnect 1012. The dielectric layer 1022 may be formed using a deposition process and / or a lamination process. The dielectric layer 1022 may include a prepreg and / or a polyimide. The dielectric layer 1022 may include a photoimageable dielectric. Forming the dielectric layer 1022 may also include forming a plurality of cavities (e.g., 1030) in the dielectric layer 1022. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Fig. 10A Stage 5 to Fig. 10B Stage 6 of exemplifies and describes an example of forming a dielectric layer and forming a cavity in the dielectric layer.

[0138] The method forms (at 1130) an interconnect in and on the dielectric layer. For example, the interconnect 1014 may be formed in and on the dielectric layer 1022. The interconnect may be formed using a plating process. Forming the interconnect may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity of the dielectric layer. Forming the interconnect may include forming a pillar-shaped interconnect. Fig. 10B Stage 7 of exemplifies and describes an example of forming interconnects in and on a dielectric layer, including forming pillar-shaped interconnects.

[0139] The method (at 1135) decouples the carrier (e.g., 1000) from the seed layer (e.g., 1001). The carrier 1000 may be separated and / or ground away. The method (at 1135) may also remove portions of the seed layer (e.g., 1001). An etching process may be used to remove portions of the seed layer 1001. Fig. 10B Stage 8 of exemplifies and describes an example of decoupling the carrier and removing the seed layer.

[0140] Different implementations may use different processes to form the metal layer. In some implementations, the metal layer may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0141] Exemplary Electronic Devices

[0142] Fig.12 Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC) are illustrated. For example, a mobile phone device 1202, a laptop computer device 1204, a fixed location terminal device 1206, a wearable device 1208, or a motor vehicle 1210 may include a device 1200 as described herein. For example, the device 1200 may be any of the devices and / or integrated circuit (IC) packages described herein. Fig.12 The illustrated devices 1202, 1204, 1206, and 1208 and vehicle 1210 are merely exemplary. Other electronic devices may also feature device 1200, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication systems (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0143] Figure 1 to Figure 2 , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4B , Figure 5 , FIG. 6A to FIG. 6C , Figure 7 , FIG. 8A to FIG. 8C , Fig. 9 , FIG. 10A to FIG. 10B as well as Figure 11 to Figure 12 One or more of the components, processes, features, and / or functions illustrated in the disclosure may be rearranged and / or combined into a single component, process, feature, or function, or may be implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the disclosure. It should also be noted that Figure 1 to Figure 2 , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4B , Figure 5 , FIG. 6A to FIG. 6C , Figure 7 , FIG. 8A to FIG. 8C , Fig. 9 , FIG. 10A to FIG. 10Bas well as Figure 11 to Figure 12 and its corresponding description in this disclosure are not limited to die and / or IC. In some specific implementations, Figure 1 to Figure 2 , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4B , Figure 5 , FIG. 6A to FIG. 6C , Figure 7 , FIG. 8A to FIG. 8C , Fig. 9 , FIG. 10A to FIG. 10B as well as Figure 11 to Figure 12 The invention and its corresponding description may be used to manufacture, create, provide and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink and / or an interposer.

[0144] It should be noted that the drawings in the present disclosure may represent actual representations and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size and / or shape of various parts and / or components in the drawings may be exemplary. In some implementations, various components and / or parts in the drawings may be optional.

[0145] The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages or modes of operation discussed. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other, even if they are not in direct physical contact with each other. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are coupled together directly or indirectly so that an electric current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have an electric current flowing between the two objects. The use of the terms "first", "second", "third" and "fourth" (and / or anything above the fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component or a fourth component. For example, the component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The terms "encapsulate", "encapsulate" and / or any derivatives refer to an object that may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. The component located at the top may be located above the component at the bottom. The top component may be considered as the bottom component, and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component may be located above (e.g., above) a first surface of the second component, and the third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. It should also be noted that the term "above" as used in the context of a component being located on another component in the present application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is above (e.g., on a surface of) the second component; and / or (3) the first component is in (e.g., embedded in) the second component. A first component that is "in" a second component may be partially in the second component or completely in the second component. A value of about X to XX may refer to a value between X and XX, inclusive. The values ​​between X and XX may be discrete or continuous. As used in the present disclosure, the term "about 'value X'" or "approximately value X" means within 10 percent of 'value X'.For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0146] In some implementations, an interconnect is an element or component in a device or package that allows or facilitates electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a column, a metallization layer, a redistribution layer, and / or an under-bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path to a signal (e.g., a data signal), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or procedures to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and / or a plating process may be used to form an interconnect.

[0147] It should also be noted that the various disclosures contained herein may be described as processes depicted as job diagrams, flow charts, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a process, many operations in an operation may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0148] Further examples are described below to facilitate understanding of the present disclosure.

[0149] Aspect 1: A package, comprising: a substrate, the substrate comprising a first surface and a second surface; a first integrated device, the first integrated device coupled to the first surface of the substrate; an interconnect die, the interconnect die coupled to the first surface of the substrate; a first packaging layer, the first packaging layer coupled to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the interconnect die; and a second integrated device, the second integrated device coupled to the second surface of the substrate.

[0150] Aspect 2: The package of aspect 1, wherein the interconnect die comprises: a die substrate; and a plurality of die interconnects.

[0151] Aspect 3: The package of aspect 2, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of about 150 microns - 270 microns.

[0152] Aspect 4: The package of aspects 1 to 3, wherein the interconnect die has a thickness in the range of approximately 100 microns to 200 microns.

[0153] Aspect 5: The package of aspects 2 to 4, wherein the plurality of die interconnects include via die interconnects and pad die interconnects.

[0154] Aspect 6: The package of aspects 2 to 5, wherein the die substrate comprises glass and / or silicon.

[0155] Aspect 7: The package according to aspects 1 to 6, further comprising a second encapsulation layer coupled to the second surface of the substrate.

[0156] Aspect 8: The package of aspect 7, further comprising an external metal layer coupled to the second packaging layer.

[0157] Aspect 9: The package of aspects 1 to 8, wherein the first integrated device comprises a first die and the second integrated device comprises a second die.

[0158] Aspect 10: The package according to aspects 1 to 9, wherein the interconnect die is located to the side of the first integrated device.

[0159] Aspect 11: The package of aspects 1 to 10, wherein the first integrated device comprises a first die and the second integrated device comprises a second die.

[0160] Aspect 12: A device, comprising a package. The package comprises a substrate, the substrate comprising a first surface and a second surface; a first integrated device, the first integrated device coupled to the first surface of the substrate; an interconnect die, the interconnect die coupled to the first surface of the substrate; a first packaging layer, the first packaging layer coupled to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the interconnect die; and a second integrated device, the second integrated device coupled to the second surface of the substrate.

[0161] Aspect 13: The apparatus of aspect 12, wherein the interconnect die comprises: a die substrate; and a plurality of die interconnects.

[0162] Aspect 14: The apparatus of aspect 13, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 microns - 270 microns.

[0163] Aspect 15: The apparatus of aspects 12 to 14, wherein the interconnect die has a thickness in the range of approximately 100 microns - 200 microns.

[0164] Aspect 16: The apparatus of aspects 13 to 15, wherein the plurality of die interconnects include via die interconnects and pad die interconnects.

[0165] Aspect 17: The apparatus of aspects 13 to 16, wherein the die substrate comprises glass and / or silicon.

[0166] Aspect 18: The apparatus of any of aspects 12 to 17, further comprising a second encapsulation layer coupled to the second surface of the substrate.

[0167] Aspect 19: The apparatus of aspect 18, further comprising an external metal layer coupled to the second encapsulation layer.

[0168] Aspect 20: The apparatus of aspects 12 to 19, wherein the first integrated device comprises a first core-die and the second integrated device comprises a second core-die.

[0169] Aspect 21: The apparatus of any of aspects 12 to 20, wherein the interconnect die is located to the side of the first integrated device.

[0170] Aspect 22: The apparatus of aspects 12 to 21, wherein the first integrated device comprises a first core-die and the second integrated device comprises a second core-die.

[0171] Aspect 23: A device according to Aspects 12 to 22, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0172] Aspect 24: A method for manufacturing a package. The method provides a substrate, the substrate comprising a first surface and a second surface. The method couples a first integrated device to the first surface of the substrate. The method couples an interconnect die to the first surface of the substrate. The method couples a first packaging layer to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the interconnect die. The method couples a second integrated device to the second surface of the substrate.

[0173] Aspect 25: The method of aspect 24, wherein the interconnect die comprises: a die substrate; and a plurality of die interconnects.

[0174] Aspect 26: The method of aspect 25, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 microns - 270 microns.

[0175] Aspect 27: The method of aspects 24 to 26, wherein the interconnect die has a thickness in the range of approximately 100 microns to 200 microns.

[0176] Aspect 28: The method of aspects 25 to 27, wherein the plurality of die interconnects include via die interconnects and pad die interconnects.

[0177] Aspect 29: The method of aspects 25 to 28, wherein the die substrate comprises glass and / or silicon.

[0178] Aspect 30: The method of aspects 24 to 29, further comprising coupling a second encapsulation layer to the second surface of the substrate.

[0179] The various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be interpreted as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative, rather than limiting the scope of the appended claims. Thus, the present teachings can be easily applied to other types of devices, and many replacements, modifications and variations will be apparent to those skilled in the art.

Claims

1. A package, comprising: a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnect die coupled to the first surface of the substrate; a first packaging layer coupled to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the interconnect die; and A second integrated device is coupled to the second surface of the substrate.

2. The package of claim 1 , wherein the interconnect die comprises: die substrate; and Multiple die interconnects. 3 . The package of claim 2 , wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 microns-270 microns. 4 . The package of claim 2 , wherein the interconnect die has a thickness in the range of approximately 100 microns-200 microns. 5 . The package of claim 2 , wherein the plurality of die interconnects include via die interconnects and pad die interconnects. The package of claim 2 , wherein the die substrate comprises glass and / or silicon. 7 . The package of claim 1 , further comprising a second encapsulation layer coupled to the second surface of the substrate. 8 . The package of claim 7 , further comprising an external metal layer coupled to the second packaging layer. 9 . The package of claim 1 , wherein the first integrated device comprises a first die and the second integrated device comprises a second die.

10. The package of claim 1, wherein the interconnect die is located to the side of the first integrated device. 11 . The package of claim 1 , wherein the first integrated device comprises a first die and the second integrated device comprises a second die.

12. A device, comprising: A package, the package comprising: a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnect die coupled to the first surface of the substrate; a first packaging layer coupled to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the interconnect die; and A second integrated device is coupled to the second surface of the substrate.

13. The apparatus of claim 12, wherein the interconnect die comprises: die substrate; and Multiple die interconnects. 14 . The apparatus of claim 13 , wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 microns-270 microns.

15. The apparatus of claim 13, wherein the interconnect die has a thickness in the range of approximately 100 microns - 200 microns.

16. The apparatus of claim 13, wherein the plurality of die interconnects comprises via die interconnects and pad die interconnects.

17. The apparatus of claim 13, wherein the die substrate comprises glass and / or silicon.

18. The apparatus of claim 12, further comprising a second encapsulation layer coupled to the second surface of the substrate.

19. The apparatus of claim 18, further comprising an external metal layer coupled to the second encapsulation layer.

20. The apparatus of claim 12, wherein the first integrated device comprises a first chiplet and the second integrated device comprises a second chiplet.

21. The apparatus of claim 12, wherein the interconnect die is located to the side of the first integrated device.

22. The apparatus of claim 12, wherein the first integrated device comprises a first chiplet and the second integrated device comprises a second chiplet.

23. The device of claim 12, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

24. A method for manufacturing a package, the method comprising: providing a substrate including a first surface and a second surface; coupling a first integrated device to the first surface of the substrate; coupling an interconnect die to the first surface of the substrate; coupling a first packaging layer to the first surface of the substrate, wherein the first packaging layer encapsulates the first integrated device and the interconnect die; as well as A second integrated device is coupled to the second surface of the substrate.

25. The method of claim 24, wherein the interconnect die comprises: die substrate; and Multiple die interconnects.

26. The method of claim 25, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of about 150 microns - 270 microns.

27. The method of claim 25, wherein the interconnect die has a thickness in the range of approximately 100 microns - 200 microns.

28. The method of claim 25, wherein the plurality of die interconnects include via die interconnects and pad die interconnects.

29. The method of claim 25, wherein the die substrate comprises glass and / or silicon.

30. The method of claim 24, further comprising coupling a second encapsulation layer to the second surface of the substrate.

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