Comparator circuit with speed control element
By introducing a speed control element into the comparator, adjusting the swing of the clock signal using a variable voltage source and transistor, the collision between noise and speed in traditional comparators under high PVT conditions is solved, and the noise reduction and maintaining high speed is achieved. effect.
Patent Information
- Application Number
- CN202380039821.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-05-16
- Filing Date
- 2023-05-11
- Publication Date
- 2024-12-10
AI Technical Summary
In advanced node processes, traditional comparators have significant changes in speed and noise due to process, voltage and temperature (PVT) diffusion, and lack of speed control mechanisms, resulting in noise and decision speed correlation, making it difficult to operate at the optimal operating point.
The speed control element, including variable voltage source and transistor, is adopted to dynamically adjust the speed of the comparator by controlling the swing of the clock signal, reducing the noise level, and ensuring that the speed requirements are met under high PVT conditions.
Through the speed control element, the noise level of the comparator is reduced, the noise integral in the amplification stage is reduced, the decision accuracy and stability of the comparator are improved, the conflict between speed and noise is avoided, and the slow PVT condition is satisfied. Low noise and high speed requirements.
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Figure CN119111036A_ABST
Abstract
Description
[0001] This application claims priority under 35 USC 120 to U.S. patent application serial number 17 / 745,756, filed on May 16, 2022, entitled “Comparator Circuit with Speed Control Element,” the entire contents of which are incorporated herein by reference. field
[0002] The present disclosure relates generally to a clocked comparator circuit and, more particularly, to an improved clocked comparator circuit having a speed control element. background
[0003] Clocked comparators are components used in a variety of applications such as analog-to-digital converters (ADCs), serializers / deserializers (SERDES), and high-speed communication circuits. The reliability, sensitivity, and accuracy of a comparator's decision depend heavily on thermal noise, which is also generated by the comparator itself. The noise and decision speed of a comparator are related, so that improving the performance of a comparator, for example by reducing the noise level (e.g., by spending more time on integration), will slow down the comparator operation. Comparators are generally measured by speed and accuracy (noise). In advanced node processes, the variation between speed and noise is more significant due to process, voltage, and temperature (PVT) diffusion. However, conventional comparators have no mechanism to control their speed.
[0004] This proposal aims to balance these two parameters according to each process. This allows the comparator to be operated at the optimal operating point by dynamically controlling the speed. Overview
[0005] The embodiments disclosed herein solve the above-mentioned technical problems and may also provide other technical solutions. In some example embodiments, a speed control element may be provided for a comparator circuit. The speed control element may include a variable voltage source and one or more transistors. Using the voltage supplied by the variable voltage source, one or more transistors may control the swing of the clock signal to provide a swing-controlled clock signal to the amplification portion of the comparator circuit. The swing-controlled clock therein may be used to control the speed of the comparator circuit (e.g., the amplification stage) based on the noise level in the circuit. The swing-controlled clock may also be used to align the output common voltage of the amplifier-based comparator circuit with the switch voltage of a downstream logic unit (e.g., an inverter) connected to the comparator circuit.
[0006] In an example embodiment, a speed control element for a comparator circuit may include: a variable voltage source, one or more transistors, the variable voltage source configured to supply a variable voltage to the one or more transistors; the one or more transistors configured to: receive a clock signal; control a swing of the clock signal based on the variable voltage supplied by the variable voltage source to generate a swing-controlled clock signal; and provide the swing-controlled clock signal to control the speed of an amplification stage of the comparator circuit.
[0007] In another embodiment, the comparator circuit may include a speed control element, which includes: a variable voltage source, one or more transistors, the variable voltage source is configured to supply a variable voltage to the one or more transistors; the one or more transistors are configured to: receive a clock signal; control the swing of the clock signal based on the variable voltage supplied by the variable voltage source to generate a swing-controlled clock signal; and provide the swing-controlled clock signal to control the speed of the amplification stage of the comparator circuit.
[0008] In yet another embodiment, a method for controlling the speed of a comparator circuit may include: supplying a variable voltage to one or more transistors of a speed control element of the comparator circuit from a variable voltage source; receiving a clock signal from one or more transistors; controlling a swing of the clock signal based on the variable voltage supplied by the variable voltage source to generate a swing-controlled clock signal by the one or more transistors; and providing the swing-controlled clock signal to control the speed of an amplification stage of the comparator circuit by the one or more transistors. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description of the present disclosure briefly summarized above may be obtained by reference to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure and are therefore not to be considered as limiting the scope of the present disclosure, as the present disclosure may allow for other equally effective embodiments.
[0010] Figure 1 is a schematic circuit diagram of a StrongARM comparator with an additional speed control element according to an example embodiment.
[0011] Figure 2 is a schematic circuit diagram of an amplifier-based comparator with an additional speed control element according to an example embodiment.
[0012] Figure 3 is a diagram showing a method according to an example embodiment Figure 1 Diagram of the StrongARM comparator's stages of operation.
[0013] Figure 4is a graph showing a comparison between an output of an original comparator and an output of a proposed comparator according to an example embodiment.
[0014] Figure 5 is a graph showing a comparison between a differential output of an original comparator and a differential output of a proposed comparator according to an example embodiment.
[0015] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. Detailed Description
[0016] Embodiments disclosed herein generally relate to improved comparator designs. More specifically, embodiments disclosed herein generally relate to an improved comparator design that utilizes a speed control element to help reduce noise of the comparator.
[0017] There have been some attempts to reduce comparator noise. For example, conventional systems attempt to reduce the noise of the comparator by controlling the capacitance of internal nodes (e.g., by adding capacitors). However, adding such capacitors adds constant parasitic capacitance, which affects the overall PVT variation. Another attempt to reduce comparator noise is by changing the input common mode. However, this approach usually requires adjustments to the previous stages.
[0018] In order to understand the noise mechanism and its effect on the operation of the comparator, a comparator is described below. As an example, the StrongARM comparator will be described below. As those skilled in the art will recognize, this architecture is exemplary and is not meant to limit the type of comparator that can utilize the speed control element.
[0019] Figure 1 is a schematic circuit diagram of a StrongARM comparator 100 (“comparator 100 ”) with an additional speed control element 101 according to an example embodiment.
[0020] As shown, the comparator 100 may include a plurality of switches S1-S4 (which may be formed using transistors in some embodiments) and a plurality of transistors M0-M6. The transistors M0-M6 may include a clocked differential pair M1 and M2, a first cross-coupled pair M3 and M4, and a second first cross-coupled pair M5 and M6. The comparator 100 may also include a node P and a node Q. In operation, the comparator 100 may go through several stages.
[0021] The first phase may be referred to as a reset phase. During the reset phase, the clock (clk) signal is low (e.g., the state of the clk signal is at logic level "0"). Therefore, during the reset phase, M0 is turned off because the swing-controlled clk signal is also low and controls the gate terminal of M0. During this phase (clk is low), S1-S4 are turned on because they are PMOS devices, while M0 is an NMOS device. Turning off M0 and turning on S1-S4 will cause the internal nodes (P, Q, Out p and Out n ) is charged to V dd A logic level of "1".
[0022] The second stage can be referred to as the amplification stage. In the amplification stage, the clk signal and the "swing controlled clk" are high (logic level "1"). Therefore, in the amplification stage, M0 can be turned on, pulling its drain to ground, thereby turning on the input pair M1-M2. When the current in each of the input pair M1-M2 depends on its gate voltage (input signal, vin p andvin n ), current starts to flow from nodes P and Q through the input pair M1-M2. Since the input signal vin p andvin n It is a differential signal and is not necessarily equal, so the current flowing through M1 and M2 is different, and the differential input signal vin is generated at nodes P and Q. p andvin n This discharge (or amplification) process continues until P and Q reach V dd -V t The "on" voltage (such as Figure 3 , as shown in ph2.a), and turns on transistors M3 and M4, which discharge Out accordingly. p and Out n (Depending on the differential input signal) ( Figure 3 , ph2.b). The result of this stage is to amplify the input signal vin at the output node p andvin n , generating the amplified signal Out p and Out n .
[0023] When Out p or Out n reaches the “on” voltage (V dd -V t The third phase begins when the voltage level of the cross-coupled transistors M5 / M6 is turned on. Once one of them is turned on, the associated output network pulls up and enables the positive feedback of the back-to-back inverters (e.g., M3-M6) (e.g., Figure 3, as shown in ph3). For example, a back-to-back inverter can convert the output (Out p 、Out n ) is charged to V dd and V ss .
[0024] The stage that is usually most sensitive to noise is the amplification stage. The amplification stage may be particularly sensitive to noise because during the amplification stage, a voltage difference is generated between nodes P and Q, thereby generating the Out of comparator 100. p and Out n Noise generated by this process or any other source during the amplification phase can cause the output of the phase to flip, resulting in comparator erroneous decisions. In addition, because the noise is integrated during the amplification phase, slowing down this phase using the speed control element 101 will reduce the input referred noise of the comparator 100. The speed control element 101 can reduce the noise to the desired noise level for amplification during the amplification phase by controlling the speed.
[0025] Due to the correlation between the speed and noise of the comparator 100, the speed control element 101 can be used to slow down the comparator in noisy PVT and still meet the speed requirement. The speed limit is stronger in slow PVT, where the noise may be lower, so no slowing down is needed.
[0026] The speed control element 101 can be configured to control the speed of the comparator 100 by limiting the current flowing through M0. As shown, the speed control element 101 can include a transistor M7, a transistor M8, and a variable voltage source 102. The speed control element 101 can limit the current through M0 by changing the voltage level of the clock signal applied to the gate of M0. To this end, the speed control element 101 can use the transistor M7, the transistor M8, and the variable voltage source 102 to control the supply of the driver of M0 (i.e., the gate voltage of M0). In other words, the swing is determined by the supply voltage (V DD ) and the external DC voltage V of the variable voltage source 102 DC In addition to controlling speed, by reducing the gate voltage swing of M0, M0 can operate more in the saturation region, so the gain is increased and the common mode rejection ratio (CMRR) can be improved.
[0027] As shown, a portion of the speed control element 101 is highlighted in circle 105. The circled portion 105 of the speed control element 101 indicates that the gate signals for S1-S4 are of the same polarity as M0, but have a constant supply because the original (ie, non-swing controlled) clock signal is used for S1-S4.
[0028] Figure 2is a schematic circuit diagram of an amplifier-based comparator 200 (“comparator 200 ”) having a speed control element 201 according to an example embodiment.
[0029] As shown, the comparator 200 may include a plurality of switches S10-S11 (which may be formed using transistors in some embodiments) and a plurality of transistors M10-M14. The transistors M10-M14 may include a clocked differential pair M11 and M12 and a cross-coupled pair M13 and M14. The comparator 200 may also be followed by an inverter 202 and an inverter 204. The inverter 202 and the inverter 204 or any other logic unit may be used to turn the signal toward rail-to-rail, which may be implemented after one or several logic unit stages.
[0030] For comparator 200, it may be desirable to align the output common voltage of comparator 200 to the switching point of the next (or downstream) logic unit, such as an inverter (202 and 204 in the illustrated embodiment, but other logic units are possible). For example, if these voltages are not aligned, the output of the logic unit may not change independently of the comparator decision. In order to align the output common voltage to the switching point of the next logic unit, in addition to the purpose of noise reduction, comparator 200 may also use a speed control element 201.
[0031] The speed control element 201 may include a transistor M15, a transistor M16, and a variable voltage source 206. The speed control element 201 may limit the current through M10 by changing the voltage level of the clock signal applied to the gate of M10. In addition, the speed control element 201 may be configured to align the output common voltage to the next logic unit by changing the voltage swing of M10. For example, controlling the voltage swing of the gate of M10 using the speed control element 201 may be used to align the output common voltage to the next logic unit ( Figure 2 The switching points of inverters 202 and 204 are coordinated.
[0032] As shown, a portion of the speed control element 201 is highlighted in circle 205. The circled portion of the speed control element 201 highlights that the gate signal for S10-S11 has the same polarity as M0, but has a constant supply because the original (ie, non-swing controlled) clock signal is used for S10-S11.
[0033] Figure 3 300 is a diagram illustrating the operation phases of a comparator (eg, a StrongARM comparator without a speed control element 101) according to an example embodiment. As shown, the diagram 300 shows the output terminal Out p (reference numeral "302"), output terminal Out n(reference numeral "304"), node P (reference numeral "306") and node Q (reference numeral "308") are at output voltages that vary with time during different phases. First, following the output terminal Out n , comparator 100 at Out n The output voltage at Out remains stable in the first phase until it starts to decrease in the second phase. n The output voltage at the output continues to decrease until it reaches zero in the third stage. p Output p The output voltage at also follows a similar drop from the first stage to the second stage, but due to the amplification effect, in the second stage, Out n and Out p As a result, during the third phase, an output drops to zero (Output n ) and one output rises to Vdd (Out p ).
[0034] Figure 4 4 is a graph 400 showing a comparison between the output of a comparator (e.g., a StrongARM comparator) according to an example embodiment and a comparator having a speed control element (e.g., comparator 100 having a speed control element 101). As can be shown, a significant differential voltage is generated earlier in the conventional comparator than in the presently disclosed comparator because in the present comparator, the integration operation is slowed down using the speed control element.
[0035] For example, as shown, graph 400 illustrates the Outp of a comparator without a speed control element (e.g., “outporig” corresponds to reference numeral 402 ), the Outn of a comparator without a speed control element (e.g., “outn orig” corresponds to reference numeral 404 ), the Outp of a comparator with a speed control element (e.g., “Outp proposed” corresponds to reference numeral 406 ), and the Outn of a comparator with a speed control element (e.g., “Outn proposed” corresponds to reference numeral 408 ).
[0036] Figure 55 is a diagram 500 showing a comparison between the differential output of a conventional StrongARM comparator and the differential output of a comparator with a speed control element (e.g., comparator 100 with speed control element 101) according to an example embodiment. For example, reference numeral 502 may correspond to the differential output of a conventional StrongARM comparator; reference numeral 504 may correspond to the differential output of a comparator with a speed control element. As shown, by including speed control element 101, the amplification stage (e.g., stage two) may be extended beyond what was originally possible.
[0037] Those skilled in the art will appreciate that the foregoing embodiments are exemplary and non-restrictive. After reading the specification and studying the drawings, all arrangements, enhancements, equivalents and improvements thereto will be apparent to those skilled in the art and are included in the true spirit and scope of this disclosure. Therefore, the appended claims are intended to include all such modifications, arrangements and equivalents that fall within the true spirit and scope of these teachings.
Claims
1. A speed control element for a comparator circuit, the speed control element comprising: a variable voltage source configured to supply a variable voltage to the one or more transistors; The one or more transistors are configured to: receiving a clock signal; controlling a swing of the clock signal to generate a swing-controlled clock signal based on the variable voltage supplied by the variable voltage source; and The swing controlled clock signal is provided to control the speed of an amplification stage of the comparator circuit.
2. The speed control element of the comparator circuit according to claim 1, wherein: During a reset phase of the comparator circuit, the one or more transistors are configured to provide a swing-controlled clock logic to turn off another transistor of the comparator circuit.
3. The speed control element of the comparator circuit according to claim 1, wherein: During the amplification phase of the comparator circuit, the one or more transistors are configured to provide a swing-controlled clock logic to turn on another transistor of the comparator circuit.
4. The speed control element of the comparator circuit according to claim 1, wherein: The one or more transistors are configured to provide the swing controlled clock signal to another transistor of the comparator circuit based on a predetermined noise level for the amplification.
5. The speed control element of the comparator circuit according to claim 1, wherein: The one or more transistors are configured to provide the swing-controlled clock signal to another transistor of the comparator circuit based on an alignment of an output common voltage of the comparator circuit with a switch point of a downstream logic unit connected to the comparator circuit.
6. The speed control element of the comparator circuit according to claim 5, wherein: At least one of the downstream logic cells includes an inverter.
7. The speed control element of the comparator circuit according to claim 1, wherein: The variable voltage source includes a DC voltage source.
8. A comparator circuit comprising: A speed control element comprising: a variable voltage source configured to supply a variable voltage to the one or more transistors; The one or more transistors are configured to: receiving a clock signal; controlling a swing of the clock signal to generate a swing-controlled clock signal based on the variable voltage supplied by the variable voltage source; and The swing controlled clock signal is provided to control the speed of an amplification stage of the comparator circuit.
9. The comparator circuit according to claim 8, wherein: During a reset phase of the comparator circuit, the one or more transistors are configured to provide a swing-controlled clock logic to turn off another transistor of the comparator circuit.
10. The comparator circuit according to claim 8, wherein: During the amplification phase of the comparator circuit, the one or more transistors are configured to provide a swing-controlled clock logic to turn on another transistor of the comparator circuit.
11. The comparator circuit according to claim 8, wherein: The one or more transistors are configured to provide the swing controlled clock signal to another transistor of the comparator circuit based on a predetermined noise level for the amplification.
12. The comparator circuit according to claim 8, wherein: The one or more transistors are configured to provide the swing-controlled clock signal to another transistor of the comparator circuit based on an alignment of an output common voltage of the comparator circuit with a switch point of a downstream logic unit connected to the comparator circuit.
13. The comparator circuit according to claim 12, wherein: At least one of the downstream logic cells includes an inverter.
14. The comparator circuit according to claim 8, wherein: The variable voltage source includes a DC voltage source.
15. A method of controlling the speed of a comparator circuit, the method comprising: supplying a variable voltage from a variable voltage source of a speed control element of a comparator circuit to one or more transistors of the speed control element; receiving a clock signal by the one or more transistors; controlling, by the one or more transistors, a swing of the clock signal based on the variable voltage supplied by the variable voltage source to generate a swing-controlled clock signal; and The swing controlled clock signal is provided by the one or more transistors to control the speed of an amplification stage of the comparator circuit.
16. The method according to claim 15, wherein: Providing the swing-controlled clock includes: During a reset phase of the comparator circuit, swing-controlled clock logic is provided by the one or more transistors to turn off another transistor of the comparator circuit.
17. The method according to claim 15, wherein: Providing the swing-controlled clock includes: During the amplification phase of the comparator circuit, swing-controlled clock logic is provided by the one or more transistors to turn off another transistor of the comparator circuit.
18. The method according to claim 15, wherein: Providing the swing-controlled clock includes: The swing-controlled clock signal is provided by the one or more transistors to another transistor of the comparator circuit based on a predetermined noise level for the amplification.
19. The method according to claim 15, wherein: Providing the swing-controlled clock includes: The swing-controlled clock signal is provided by the one or more transistors to another transistor of the comparator circuit based on alignment of an output common voltage of the comparator circuit with a switch point of a downstream logic unit connected to the comparator circuit.
20. The method according to claim 15, wherein: The variable voltage source includes a DC voltage source.