Power-on sequence detection device and method, chip and electronic equipment

Abstract

The invention relates to a power-on sequence detection device and method, a chip and electronic equipment, and belongs to the field of electronic circuits. The power-on sequence detection device is used for detecting the power-on sequence of N voltage domains in a chip, N is an integer greater than or equal to 2, and the power-on sequence detection device comprises power-on sequence detection units, each power-on sequence detection unit is used for connecting two voltage domains so as to detect the power-on sequence of the two voltage domains connected with the power-on sequence detection unit; wherein the detection result of each power-on sequence detection unit is used for determining the power-on sequence of the N voltage domains. The power-on sequence detection unit is used for connecting the two voltage domains to detect the power-on sequence of the two voltage domains connected with the power-on sequence detection unit, so that the power-on sequence of the N voltage domains can be quickly and accurately determined according to the detection result of each power-on sequence detection unit.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuits, and specifically relates to a power-on sequence detection device, method, chip and electronic equipment. Background Art

[0002] In chip power design, many power networks (including voltage domain Power) are designed for considerations such as power consumption. When the chip is powered on, each power network will be powered on one by one for considerations such as current peak. Since some digital states in the chip are determined by the power-on timing of the voltage domain, for example, after Power1 is powered on, some input states under the Power2 power network must be controlled through the logic of Power1. This requires that Power1 must be powered on before Power2. Therefore, during the power-on process, it is necessary to understand whether the power-on order of the power networks inside the chip is consistent with expectations. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a power-on sequence detection device, method, chip and electronic device to quickly and accurately detect the power-on sequence of N voltage domains.

[0004] The embodiment of the present application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a power-on sequence detection device for detecting the power-on sequence of N voltage domains in a chip, where N is an integer greater than or equal to 2, and the power-on sequence detection device comprises: a power-on sequence detection unit, each of the power-on sequence detection units being used to connect two voltage domains to detect the power-on sequence of the two voltage domains to which it is connected; wherein the detection result of each of the power-on sequence detection units is used to determine the power-on sequence of the N voltage domains.

[0006] In the above embodiment, the power-on sequence detection unit is used to connect two voltage domains to detect the power-on sequence of the two voltage domains connected thereto, so that the power-on sequence of N voltage domains can be quickly and accurately determined according to the detection result of each power-on sequence detection unit.

[0007] In combination with a possible implementation manner of the first aspect, the power-on sequence detection unit includes: a storage unit, the storage unit comprising two inverters connected end to end, the power supply end of each inverter is connected to a voltage domain, wherein the power-on sequence of the two voltage domains to which it is connected is determined according to the output value of the storage unit.

[0008] In the above embodiment, since the storage unit includes two inverters connected end to end, and the power-on sequences of the two voltage domains connected to the inverters are different, the values ​​stored therein are also different. Therefore, the output value of the storage unit can be used to quickly determine the power-on sequence of the two voltage domains connected to it.

[0009] In combination with a possible implementation manner of the embodiment of the first aspect, the power-on sequence detection unit includes: a latch device, and two power supply terminals of the latch device are respectively connected to two voltage domains.

[0010] In the above embodiment, since the power-on sequences of the two voltage domains connected to the latch device are different, the values ​​stored therein are also different. Therefore, the latch device can be used to detect the power-on sequence of the two voltage domains connected to it.

[0011] In combination with a possible implementation manner of the embodiment of the first aspect, the latch device includes: a first inverter and a second inverter, wherein a power supply terminal of the first inverter is connected to one of the two voltage domains; a power supply terminal of the second inverter is connected to one of the two voltage domains, an output terminal of the second inverter is connected to an input terminal of the first inverter, and an input terminal of the second inverter is connected to an output terminal of the first inverter; wherein the first inverter and the second inverter both include a PMOS tube and an NMOS tube connected in series, and a gate of the PMOS tube is connected to a gate of the NMOS tube.

[0012] In the above embodiment, the latch device includes: a first inverter and a second inverter, and the two inverters are connected end to end, so that the power-on sequence of the two voltage domains connected to the inverters is different, and the stored values ​​are also different. Therefore, the latch device using the above structure can quickly determine the power-on sequence of the two voltage domains connected to itself.

[0013] In combination with a possible implementation manner of the embodiment of the first aspect, the latch device includes: a first NOR gate and a second NOR gate, wherein the power supply terminal of the first NOR gate is connected to one of the two voltage domains; the power supply terminal of the second NOR gate is connected to the other of the two voltage domains, the first input terminal of the second NOR gate is connected to the output terminal of the first NOR gate, and the output terminal of the second NOR gate is connected to the first input terminal of the first NOR gate; wherein the second input terminal of the first NOR gate and the second input terminal of the second NOR gate are used to receive a target level signal.

[0014] In the above embodiment, the latch device of the above structure is used to connect two voltage domains. The power-on sequence of the two voltage domains is different, and the stored values ​​are also different. Therefore, the latch device of the above structure can quickly determine the power-on sequence of the two voltage domains to which it is connected.

[0015] In combination with a possible implementation manner of the first aspect, the power-on sequence detection device also includes: a judgment unit, connected to each of the power-on sequence detection units, and the judgment unit is used to determine the power-on sequence of the N voltage domains based on the detection results of each of the power-on sequence detection units.

[0016] In the above embodiment, a judgment unit is further added to connect each power-on sequence detection unit, so as to determine the power-on sequence of the N voltage domains according to the detection result of each power-on sequence detection unit.

[0017] In a second aspect, an embodiment of the present application further provides a chip comprising: N voltage domains, where N is an integer greater than or equal to 2; and a power-on sequence detection device provided in the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment.

[0018] In combination with a possible implementation manner of the second aspect, if N is 2, the power-on sequence detection unit in the power-on sequence detection device is a storage unit, then the chip is a memory, and the power-on sequence of the two voltage domains connected to the storage unit is related to the initial value of the storage unit.

[0019] In the above embodiment, the initial value of the memory cell may be controlled by the power-on sequence of the two voltage domains to which the memory cell is connected.

[0020] In a third aspect, an embodiment of the present application further provides an electronic device, including: a chip as provided in the embodiment of the second aspect.

[0021] In a fourth aspect, an embodiment of the present application also provides a power-on sequence detection method, comprising: obtaining the detection result of each power-on sequence detection unit, wherein each power-on sequence detection unit is used to detect the power-on sequence of two voltage domains to which it is connected; according to the detection result of each power-on sequence detection unit, determining the power-on sequence of N voltage domains in the chip, where N is an integer greater than or equal to 2.

[0022] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The above and other purposes, features and advantages of the present application will be more clear as shown in the drawings.

[0024] Figure 1 A schematic diagram showing the principle of using a power-on sequence detection device to detect the power-on sequence of three voltage domains provided in an embodiment of the present application is shown.

[0025] Figure 2 A schematic diagram showing the principle of a first power-on sequence detection unit provided in an embodiment of the present application is shown.

[0026] Figure 3 A schematic diagram showing the principle of a second power-on sequence detection unit provided in an embodiment of the present application is shown.

[0027] Figure 4 A schematic diagram showing the principle of a third power-on sequence detection unit provided in an embodiment of the present application is shown.

[0028] Figure 5 A schematic diagram showing the principle of a fourth power-on sequence detection unit provided in an embodiment of the present application is shown.

[0029] Figure 6 A schematic diagram of the process principle of a power-on sequence detection method provided in an embodiment of the present application is shown.

[0030] Figure 7 A schematic diagram of the principle of a storage array provided in an embodiment of the present application is shown.

[0031] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0033] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0034] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0035] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0036] In order to understand whether the power-on sequence of the internal power supply network of the chip is consistent with expectations, it is necessary to detect the power-on sequence of the N voltage domains in the chip. Based on this, an embodiment of the present application provides a power-on sequence detection device for detecting the power-on sequence of N voltage domains in the chip, where N is an integer greater than or equal to 2.

[0037] The power-on sequence detection device includes: a power-on sequence detection unit, each of which is used to connect two voltage domains to detect the power-on sequence of the two voltage domains connected to itself. The principle diagram is as follows Figure 1 shown. Figure 1 The figure shows a case where three power-on sequence detection units are used to detect the power-on sequence of three voltage domains (Power). When the number of Power increases, the number of power-on sequence detection units required also needs to increase. For example, when the number of Power increases to 4, the number of power-on sequence detection units required needs to increase to 6. When the number of Power decreases, the number of power-on sequence detection units required also needs to decrease. For example, when the number of Power decreases to 1, the number of power-on sequence detection units required is only 1.

[0038] The detection result of each power-on sequence detection unit is used to determine the power-on sequence of the N voltage domains. Figure 1Taking the example shown as an example, three power-on sequence detection units are used to compare the power-on sequence between Power1, Power2, and Power3 respectively, and finally the power-on sequence of the three voltage domains can be obtained according to the Q values ​​output by the three power-on sequence detection units. That is, the first power-on sequence detection unit is used to detect the power-on sequence of Power2 and Power3, the second power-on sequence detection unit is used to detect the power-on sequence of Power1 and Power3, and the third power-on sequence detection unit is used to detect the power-on sequence of Power1 and Power2. The power-on sequence of Power1, Power2, and Power3 can be determined according to the detection results output by the Q end of each power-on sequence detection unit. For example, assuming that Q=1 of the first power-on sequence detection unit indicates that power2 is powered on before power3, Q=1 of the second power-on sequence detection unit indicates that power1 is powered on before power3, and Q=1 of the third power-on sequence detection unit indicates that power2 is powered on before power1.

[0039] In some implementations, the power-on sequence of the N voltage domains can be determined manually based on the detection results of each power-on sequence detection unit. In some possible implementations, the power-on sequence of the N voltage domains can also be determined automatically by a machine based on the detection results of the power-on sequence detection unit. In this implementation, the power-on sequence detection device also includes: a judgment unit connected to each power-on sequence detection unit, and the judgment unit is used to determine the power-on sequence of the N voltage domains based on the detection results of each of the power-on sequence detection units.

[0040] In one implementation, the judgment unit may include a comparator, which determines the power-on sequence of the N voltage domains by comparing the detection results of each power-on sequence detection unit. In some possible implementations, the judgment unit may also include a decoder, which uses the decoder to determine the power-on sequence of the N voltage domains based on the decoding results of the detection results of each power-on sequence detection unit (as the input of the decoder), that is, the output of the decoder is used to detect whether the input signal matches the predetermined code, so as to determine whether the power-on sequence of the voltage domains is consistent with the expected.

[0041] In some possible implementations, the judgment unit can also be implemented by a device such as a processor or a controller, and the processor or controller is used to determine the power-on sequence of the N voltage domains according to the detection results of each power-on sequence detection unit. In this implementation, the processor (or controller) can be an existing processor (controller) in the chip, and by reusing the existing devices in the chip, costs can be saved and the chip area can be reduced.

[0042] In one embodiment, the power-on sequence detection unit includes: a storage unit, the storage unit includes two inverters connected end to end, the power supply end of each inverter is connected to a voltage domain, wherein the power-on sequence of the two voltage domains connected to the storage unit is determined according to the output value of the storage unit. If the power-on sequence detection device also includes a judgment unit, the output end of each inverter can also be connected to the judgment unit. Its principle diagram is as follows Figure 2 As shown, Figure 2 The schematic diagram of a storage unit composed of 6 transistors, WL represents the word line, BL and BLB are a pair of bit lines, PU and PD, PU_X and PD_X form two inverters connected end to end, that is, the output of one inverter is connected to the input of another inverter, and vice versa. Among them, PU and PD form an inverter, and PU_X and PD_X form an inverter.

[0043] Since the two inverters are connected end to end to form a latch, when there is no external influence, Q and QB can store data very stably, and the two are complementary. For example, when Q=0, QB=1, and when Q=1, QB=0. When the latch is powered on, due to the influence of factors such as the process, Q and QB will become unknown states after power-on, that is, Q may be logic 0 or logic 1. The present application introduces a mechanism for connecting the PU tube and the PU_X tube to different voltage domains. If the power supply end of the PU tube is powered on first (VDD2 is powered on before VDD1), Q=1, otherwise Q=0.

[0044] like Figure 2 As shown, the PU tube is connected to VDD2, and the PU_X tube is connected to VDD1. In the example, VDD2 is powered on first, Q=1, and QB=0. By obtaining the value of Q and / or QB, the actual power-on sequence of VDD1 and VDD2 can be understood. In the figure, the WL word line, BL, BLB bit line, etc. are used to obtain the values ​​of Q and QB. In some possible implementations, the WL word line, BL, BLB bit line, PG tube and PG_X tube may not be required, and the data of Q and QB may be directly output. It can be understood that how to read the values ​​of Q and QB is not the focus of the present invention.

[0045] In some possible implementations, the power-on sequence detection unit includes: a latch device, two power supply terminals of the latch device are respectively connected to two voltage domains, and if the power-on sequence detection device also includes a judgment unit, the positive phase output terminal and / or the negative phase output terminal of the latch device are also connected to the judgment unit. Different voltage domains are connected through the latch device, and when the power-on sequence of the two voltage domains is different, the latch of the latch device is also different, and then the power-on sequence of the two voltage domains connected to itself can be determined according to the output value of the latch device.

[0046] In some implementations, the latch device may be a latch. In one implementation, the latch device includes: a first inverter and a second inverter, the power supply terminal of the first inverter is connected to one of the two voltage domains; the power supply terminal of the second inverter is connected to one of the two voltage domains, the output terminal of the second inverter is connected to the input terminal of the first inverter, and the input terminal of the second inverter is connected to the output terminal of the first inverter. If the power-on sequence detection device further includes a judgment unit, the output terminal of the second inverter may also be connected to the judgment unit, and the output terminal of the first inverter may also be connected to the judgment unit.

[0047] The first inverter and the second inverter both include a PMOS tube and an NMOS tube connected in series, and the gate of the PMOS tube is connected to the gate of the NMOS tube. The schematic diagram is as follows: Figure 3 As shown, the PU tube and the PD tube form an inverter, the PU_X tube and the PD_X tube form an inverter, and the PU tube and the PD tube, the PU_X tube and the PD_X tube form two inverters connected end to end, that is, the output of one inverter is connected to the input of another inverter, and vice versa. By obtaining the value of Q and / or QB, the actual power-on sequence of VDD1 and VDD2 can be understood.

[0048] In one implementation, the latch device includes: a first NOR gate and a second NOR gate, the power supply terminal of the first NOR gate is connected to one of the two voltage domains, the power supply terminal of the second NOR gate is connected to the other of the two voltage domains, the first input terminal of the second NOR gate is connected to the output terminal of the first NOR gate, the output terminal of the second NOR gate is connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate and the second input terminal of the second NOR gate are used to receive a target level signal (such as a low level "0"), and its schematic diagram is as follows Figure 4 If the power-on sequence detection device further includes a judgment unit, the output end of the first NOR gate can be connected to the judgment unit, and the output end of the second NOR gate can be connected to the judgment unit. Figure 4 In the example shown, NOR1 is powered on before NOR2, so Q=1, Q'=0. The power-on sequence of the two voltage domains to which they are connected can be determined by the values ​​of Q and Q'.

[0049] In another implementation manner, the power-on sequence detection unit can also be implemented by other logic devices, for example, it can be implemented by an AND gate + inverter, and its schematic diagram can be as follows: Figure 5As shown. The power-on sequence of VDD1 and VDD2 can be determined based on the values ​​of Q1, Q2, and Q3. Assuming that VDD1 is powered on before VDD2, the powered-on VDD1 = 1, and the unpowered VDD2 = 0, then the values ​​of Q1, Q2, and Q3 are 0, 0, and 1 respectively. When Q2 is powered on, the powered-on VDD2 = 1. At this time, the values ​​of Q1, Q2, and Q3 are 0, 1, and 0 respectively. Therefore, when the values ​​of Q1, Q2, and Q3 are 0, 0, and 1, and their values ​​jump from 0, 0, 1 to 0, 1, and 0, it can be confirmed that VDD1 is powered on before VDD2. Among them, the AND gate and the inverter have separate power supplies (which can be the first power supply) to power them to ensure that they can work normally.

[0050] The power-on sequence detection device shown in the present application is a very effective voltage sequence detection circuit, which occupies a small area and has strong anti-interference performance. Monte Carlo simulation shows that its detection efficiency and accuracy are extremely high, which can be considered to be 100%.

[0051] The present application also provides a power-on sequence detection method. Figure 6 The principle of the power-on sequence detection method provided in the embodiment of the present application is explained.

[0052] S1: Acquire a detection result of each power-on sequence detection unit, wherein each power-on sequence detection unit is used to detect a power-on sequence of two voltage domains connected to the unit.

[0053] The power-on sequence detection unit can be used to detect the power-on sequence of the two voltage domains to which it is connected.

[0054] In one implementation, the power-on sequence detection unit may include a storage unit or a latch device, wherein the latch device includes: a first inverter and a second inverter, or a first NOR gate and a second NOR gate. For details, please refer to the content of the same part above.

[0055] S2: Determine the power-on sequence of the N voltage domains in the chip according to the detection result of each power-on sequence detection unit.

[0056] According to the detection result of each power-on sequence detection unit, the power-on sequence of N voltage domains in the chip can be determined, where N is an integer greater than or equal to 2.

[0057] The power-on sequence detection method provided in the present application can be applied to chips. For example, the execution subject includes but is not limited to the judgment unit in the above-mentioned chip, and the judgment unit is used to obtain the detection result of each power-on sequence detection unit, and the power-on sequence of N voltage domains in the chip is determined according to the detection result of each power-on sequence detection unit.

[0058] The method provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned power-on sequence detection device embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference may be made to the corresponding contents in the aforementioned power-on sequence detection device embodiment.

[0059] The embodiment of the present application also provides a chip, which includes N voltage domains and a power-on sequence detection device as shown above. The chip provided in the embodiment of the present application can be various types of chips with multiple voltage domains (including at least 2 voltage domains), which can be processors, memories, network and communication chips, power management chips, and some artificial intelligence AI chips. Processors can be divided into mobile processors, such as Apple A series, Qualcomm Snapdragon series, Huawei Kirin series, etc., as well as desktop and server processors, such as Intel Core series, AMD Ryzen series, etc.

[0060] In one implementation, if N is 2, the power-on sequence detection unit in the power-on sequence detection device is a storage unit, the chip can be a memory, and the power-on sequence of the two voltage domains connected to the storage unit is related to the initial value of the storage unit. Figure 2 It can be seen that since the power-on sequence of the voltage domains connected to the PU tube and the PU_X tube is different, the value of Q is different. For example, if the power supply end of the PU tube is powered on first (VDD2 is powered on before VDD1), then Q = 1, otherwise, Q = 0. Therefore, the storage value of the memory can be configured by controlling the power-on sequence of the voltage domains. Figure 2 The storage cells shown are arranged in an array. By controlling the power-on sequence of the voltage domains connected to the PU tube and the PU_X tube, the Q value of an array can be finally obtained. Figure 7 As shown, Figure 7 In the example shown, only a 2*2 storage array is shown. It is understandable that the number of storage units can be larger, and a larger storage array can be obtained by adding more columns and / or more rows, such as an 8*8 storage array.

[0061] The chip provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned power-on sequence detection device embodiment. For the sake of brief description, for matters not mentioned in the chip embodiment, reference may be made to the corresponding contents in the aforementioned power-on sequence detection device embodiment.

[0062] The present application also provides an electronic device, which includes the above-mentioned chip. In one implementation mode, Figure 8 As shown, the electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230 and a processor 240. The above chip can be the memory 220 or the processor 240.

[0063] The transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses 230 or signal lines. Among them, the transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, wherein the computer program includes at least one software function module that can be stored in the memory 220 in the form of software or firmware (Firmware) or solidified in the operating system (Operating System, OS) of the electronic device 200. The processor 240 is used to execute the software function module or computer program stored in the memory 220. For example, the processor is used to execute the above-mentioned power-on sequence detection method.

[0064] Among them, the memory 220 can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0065] The processor 240 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. Alternatively, the processor 240 may also be any conventional processor, etc.

[0066] The electronic devices 200 include but are not limited to mobile devices, computing devices, household devices, medical devices, gaming devices, security devices, network and communication devices, vehicles, etc. Mobile devices include but are not limited to smart phones, tablets, and wearable devices. Computing devices include but are not limited to personal computers, servers, computing cards, etc. Household devices include but are not limited to smart TVs, refrigerators, washing machines, air conditioners, etc. Medical devices include but are not limited to ultrasonic devices, electrocardiogram machines, radiation devices, etc. Gaming devices include but are not limited to game consoles, game consoles, etc. Security devices include but are not limited to cameras, smart locks, access control systems, etc. Network and communication devices include but are not limited to routers, switches, firewalls, etc. Vehicles include but are not limited to various vehicles containing electronic control units.

[0067] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0068] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0069] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A power-on sequence detection device, used to detect the power-on sequence of N voltage domains in a chip, N is an integer greater than or equal to 2, characterized in that: The power-on sequence detection device comprises: A power-on sequence detection unit, each of which is used to connect two voltage domains to detect the power-on sequence of the two voltage domains connected to it; The detection result of each of the power-on sequence detection units is used to determine the power-on sequence of the N voltage domains.

2. The power-on sequence detection device according to claim 1, characterized in that: The power-on sequence detection unit comprises: A storage unit comprises two inverters connected end to end, wherein the power supply end of each inverter is connected to a voltage domain, wherein the power-on sequence of the two voltage domains connected to the storage unit is determined according to the output value of the storage unit.

3. The power-on sequence detection device according to claim 1, characterized in that: The power-on sequence detection unit comprises: A latch device, wherein two power supply terminals of the latch device are respectively connected to two voltage domains.

4. The power-on sequence detection device according to claim 3, characterized in that: The latch device comprises: A first inverter, wherein a power supply terminal of the first inverter is connected to one of the two voltage domains; A second inverter, wherein a power supply terminal of the second inverter is connected to one of the two voltage domains, an output terminal of the second inverter is connected to an input terminal of the first inverter, and an input terminal of the second inverter is connected to an output terminal of the first inverter; The first inverter and the second inverter both include a PMOS tube and an NMOS tube connected in series, and the gate of the PMOS tube is connected to the gate of the NMOS tube.

5. The power-on sequence detection device according to claim 3, characterized in that: The latch device comprises: A first NOR gate, wherein a power supply terminal of the first NOR gate is connected to one of the two voltage domains; a second NOR gate, wherein a power supply terminal of the second NOR gate is connected to the other voltage domain of the two voltage domains, a first input terminal of the second NOR gate is connected to the output terminal of the first NOR gate, and the output terminal of the second NOR gate is connected to the first input terminal of the first NOR gate; The second input terminal of the first NOR gate and the second input terminal of the second NOR gate are used to receive a target level signal.

6. The power-on sequence detection device according to any one of claims 1 to 5, characterized in that: The power-on sequence detection device also includes: A judgment unit is connected to each of the power-on sequence detection units, and is used to determine the power-on sequence of the N voltage domains according to the detection result of each of the power-on sequence detection units.

7. A chip, characterized in that: include: N voltage domains, where N is an integer greater than or equal to 2; And a power-on sequence detection device as described in any one of claims 1 to 6.

8. The chip according to claim 7, characterized in that: If N is 2, the power-on sequence detection unit in the power-on sequence detection device is a storage unit, the chip is a memory, and the power-on sequence of the two voltage domains connected to the storage unit is related to the initial value of the storage unit.

9. An electronic device, characterized in that: include: A chip as claimed in claim 7 or 8.

10. A power-on sequence detection method, characterized in that: include: Obtaining a detection result of each power-on sequence detection unit, wherein each power-on sequence detection unit is used to detect a power-on sequence of two voltage domains connected to the unit; According to the detection result of each power-on sequence detection unit, the power-on sequence of N voltage domains in the chip is determined, where N is an integer greater than or equal to 2.

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