Voltage-stabilized power supply and electronic equipment

Abstract

The invention provides a voltage-stabilized power supply and electronic equipment, the voltage-stabilized power supply comprises a driving tube, a first resistor, a second resistor, an error amplification unit, a first feedback unit and a second feedback unit, the error amplification unit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube and a second PMOS tube, a first wiring terminal is led out between the second resistor and the second end of the driving tube to serve as the output end of the voltage-stabilized power supply; the first end of the first feedback unit is connected between the second PMOS tube and the second NMOS tube, and the second end of the first feedback unit is connected to the grid electrode of the third NMOS tube; the first end of the second feedback unit is connected to the first wiring terminal, the second end of the second feedback unit is connected to the first PMOS transistor and the second PMOS transistor, the third end of the second feedback unit is connected to the control end of the first feedback unit, and the problem that the load current response speed of the off-chip capacitor-free stabilized voltage supply is poor can be solved.

Description

Technical Field

[0001] The present application relates to the field of power supplies, and in particular to a voltage-stabilized power supply and electronic equipment. Background Art

[0002] Low voltage dropout linear regulator LDO is one of the essential modules of power management chip, with the advantages of low cost, low input voltage, high output voltage and large driving capability. Traditional LDO relies on large external capacitors to achieve output voltage regulation and loop stability, and PCB usually requires external voltage regulator capacitors of hundreds of nf to uf. A complete power supply system may need to integrate more than ten voltage regulators, so LDO without external capacitors is increasingly valued and more conducive to system integration. When LDO without external capacitors is used to power the chip internally or externally, the external uf capacitor can be removed, which can effectively reduce the cost of peripheral devices and reduce the PCB area.

[0003] Therefore, those skilled in the art continue to pay attention to how to implement LDO without external capacitors. Summary of the invention

[0004] The purpose of the present application is to provide a voltage-stabilized power supply and an electronic device to at least partially improve the above-mentioned problems.

[0005] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, an embodiment of the present application provides a regulated power supply, the regulated power supply comprising a driving tube, a first resistor, a second resistor, an error amplifying unit, a first feedback unit and a second feedback unit, the error amplifying unit comprising a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube and a second PMOS tube;

[0007] The first end of the driving tube is connected to the first power supply, the second end of the driving tube is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is grounded, and a first wiring terminal is connected between the second resistor and the second end of the driving tube, and the first wiring terminal is the output end of the voltage-stabilized power supply;

[0008] The source of the first PMOS tube and the source of the second PMOS tube are both connected to the first power supply, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, the source of the first NMOS tube and the source of the second NMOS tube are both connected to the drain of the third NMOS tube, the source of the third NMOS tube is grounded, the gate of the first NMOS tube is used to access the reference voltage, the gate of the second NMOS tube is connected between the first resistor and the second resistor, a second wiring terminal is led out between the drain of the first PMOS tube and the drain of the first NMOS tube, and the second wiring terminal is connected to the third end of the driving tube;

[0009] The first end of the first feedback unit is connected between the drain of the second PMOS tube and the drain of the second NMOS tube, and the second end of the first feedback unit is connected to the gate of the third NMOS tube;

[0010] The first end of the second feedback unit is connected to the first terminal, the second end of the second feedback unit is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and the third end of the second feedback unit is connected to the control end of the first feedback unit.

[0011] Optionally, the first feedback unit includes a third PMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a first capacitor;

[0012] The gate of the third PMOS tube is connected to the gate of the fourth PMOS tube, and a third wiring terminal is connected between the source of the third PMOS tube and one end of the first capacitor, and the third wiring terminal serves as the first end of the first feedback unit;

[0013] The drain of the third PMOS tube is connected to the other end of the first capacitor, the drain of the fifth NMOS tube is connected to the drain of the third PMOS tube, the source of the fifth NMOS tube is grounded, and a fourth terminal is connected between the drain of the fifth NMOS tube and the drain of the third PMOS tube, and the fourth terminal is the second end of the first feedback unit;

[0014] The source of the fourth PMOS tube is connected to the first power supply, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube;

[0015] A fifth connecting terminal is led out from the connection between the gate of the fourth NMOS tube and the gate of the fifth NMOS tube, and the fifth connecting terminal is the control end of the first feedback unit.

[0016] Optionally, the second feedback unit includes: a fifth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a third resistor and a second capacitor;

[0017] The gate of the sixth NMOS tube is connected to the first end of the third resistor, the second end of the third resistor is connected to the gate of the seventh NMOS tube, the first end of the second capacitor serves as the first end of the second feedback unit, the second end of the second capacitor is connected between the gate of the sixth NMOS tube and the first end of the third resistor, a sixth terminal is drawn between the gate of the sixth NMOS tube and the first end of the third resistor, and the sixth terminal serves as the third end of the second feedback unit;

[0018] The source of the sixth NMOS tube is grounded, the drain of the sixth NMOS tube is connected to the drain of the fifth PMOS tube, the source of the fifth PMOS tube is connected to the first power supply, the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube, and the gate of the fifth PMOS tube serves as the second end of the second feedback unit;

[0019] The source node of the seventh NMOS tube, the drain of the seventh NMOS tube is used to connect to the second current source, and the drain of the seventh NMOS tube is connected between the gate of the seventh NMOS tube and the third resistor.

[0020] Optionally, the second feedback unit further includes an eighth NMOS tube, a first switch tube and a low power consumption logic unit;

[0021] The gate of the eighth NMOS tube is connected to the gate of the seventh NMOS tube, the source of the eighth NMOS tube is grounded, the drain of the eighth NMOS tube is connected to the first end of the first switch tube, the second end of the first switch tube is connected to the drain of the seventh NMOS tube, and the control end of the first switch tube is connected to the low power logic unit;

[0022] The low power consumption logic unit is used for sending a trigger instruction to the first switch tube to switch the first switch tube to a closed state when the regulated power supply switches to a low power consumption mode.

[0023] Optionally, the second feedback unit further includes a power-on logic unit, a second switch tube, a third switch tube and a third capacitor;

[0024] One end of the third capacitor is connected to the second end of the second capacitor, and the other end of the third capacitor is grounded;

[0025] The first end of the second switch tube is connected to the second end of the second capacitor, the second end of the second switch tube is connected to the first end of the third resistor, the first end of the third switch tube is connected to one end of the third capacitor, and the second end of the third switch tube is connected to the other end of the third capacitor;

[0026] The control end of the second switch tube and the control end of the third switch tube are connected to the power-on logic unit.

[0027] Optionally, the power-on logic unit is used to control the second switch tube to be in an open state and the third switch tube to be in a closed state when the regulated power supply is powered on; after the regulated power supply is powered on for a preset time length, the second switch tube is controlled to be in a closed state and the third switch tube is controlled to be in an open state.

[0028] Optionally, the error amplification unit also includes a fourth resistor and a fourth capacitor, one end of the fourth resistor is connected to the second end of the driving tube, the other end of the fourth resistor is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is connected to the third end of the driving tube.

[0029] Optionally, the fourth resistor is a variable resistor and / or the fourth capacitor is a variable capacitor.

[0030] In a second aspect, an embodiment of the present application provides an electronic device, comprising the above-mentioned voltage-stabilized power supply.

[0031] Optionally, the electronic device further comprises a post-stage load circuit, and the post-stage load circuit is connected to the output end of the regulated power supply.

[0032] Compared with the prior art, the embodiment of the present application provides a voltage-stabilized power supply and electronic equipment, the voltage-stabilized power supply includes a driving tube, a first resistor, a second resistor, an error amplifying unit, a first feedback unit and a second feedback unit, the error amplifying unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube and a second PMOS tube; the first end of the driving tube is connected to the first power supply, the second end of the driving tube is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is grounded, and a first wiring terminal is drawn between the second resistor and the second end of the driving tube, and the first wiring terminal is the output end of the voltage-stabilized power supply; the first end of the first feedback unit is connected between the drain of the second PMOS tube and the drain of the second NMOS tube, the second end of the first feedback unit is connected to the gate of the third NMOS tube; the first end of the second feedback unit is connected to the first wiring terminal, the second end of the second feedback unit is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and the third end of the second feedback unit is connected to the control end of the first feedback unit. The problem of poor load current response speed of the voltage-stabilized power supply without off-chip capacitor can be improved.

[0033] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of the structure of a voltage-stabilized power supply provided in an embodiment of the present application;

[0036] Figure 2 A schematic diagram of the structure of a first feedback unit provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of the structure of a second feedback unit provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of transient characteristics of an LDO load current and output voltage provided in an embodiment of the present application.

[0039] In the figure: 101 - error amplification unit; 102 - first feedback unit; 103 - second feedback unit; 1031 - low power consumption logic unit; 1032 - power-on logic unit. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0042] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0043] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0044] In the description of the present application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0045] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0046] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0047] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the voltage-stabilized power supply provided in the embodiment of the present application, which has a fast-response voltage-stabilized power supply circuit structure without external capacitors and bidirectional transient acceleration technology. Figure 1 As shown, the regulated power supply includes a driving tube MP0, a first resistor R1, a second resistor R2, an error amplifying unit 101, a first feedback unit 102 and a second feedback unit 103. The error amplifying unit 101 includes a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first PMOS tube MP1 and a second PMOS tube MP2.

[0048] The first end of the driving tube MP0 is connected to the first power supply (VCC), the second end of the driving tube MP0 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first resistor R1, the other end of the first resistor R1 is grounded, and a first wiring terminal is led out between the second resistor R2 and the second end of the driving tube MP0, and the first wiring terminal is the output end (Vout) of the voltage-stabilized power supply.

[0049] The source of the first PMOS tube MP1 and the source of the second PMOS tube MP2 are both connected to the first power supply, the drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN1, the drain of the second PMOS tube MP2 is connected to the drain of the second NMOS tube MN2, the source of the first NMOS tube MN1 and the source of the second NMOS tube MN2 are both connected to the drain of the third NMOS tube MN3, the source of the third NMOS tube MN3 is grounded, the gate of the first NMOS tube MN1 is used to access the reference voltage (VREF), the gate of the second NMOS tube MN2 is connected between the first resistor R1 and the second resistor R2 (at VFB in the figure), a second wiring terminal (at Va in the figure) is led out between the drain of the first PMOS tube MP1 and the drain of the first NMOS tube MN1, and the second wiring terminal is connected to the third end of the driving tube MP0.

[0050] Optionally, the driving tube MP0 is a PMOS tube, the first end of the driving tube MP0 is a source, the second end of the driving tube MP0 is a drain, and the third end of the driving tube MP0 is a gate.

[0051] The first end of the first feedback unit 102 is connected between the drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2 (at Vb in the figure), and the second end of the first feedback unit 102 (at Vc in the figure) is connected to the gate of the third NMOS transistor MN3.

[0052] A first end of the second feedback unit 103 is connected to the first connection terminal, a second end of the second feedback unit 103 is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 , and a third end of the second feedback unit 103 is connected to the control end of the first feedback unit 102 .

[0053] Optionally, the second feedback unit 103 is used to provide a driving signal to the gate of the first PMOS tube MP1, the gate of the second PMOS tube MP2, and the control end of the first feedback unit 102. It can be understood that the second feedback unit 103 is a current source for the gate of the first PMOS tube MP1, the gate of the second PMOS tube MP2, and the control end of the first feedback unit 102.

[0054] The second feedback unit 103 is further used to adjust the driving signal when the output voltage Vout at the output end changes, so as to change the working states of the first feedback unit 102 and the error amplification unit 101 , thereby responding to the change of the output voltage Vout.

[0055] The first feedback unit 102 is used to transfer the voltage change at Vb to Vc under the requirement of fast response of the output load in the medium and high frequency band, so as to adjust the current flowing through the third NMOS transistor MN3, and then adjust the current (Ibias1) flowing through the first NMOS transistor MN1, so as to change the pull-down capability of the gate voltage of the driving transistor MP0. The medium and high frequency band refers to 20-100MHZ.

[0056] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the first feedback unit provided in the embodiment of the present application. Figure 2 As shown, the first feedback unit 102 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a first capacitor Cf1.

[0057] The gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4. A third terminal is connected between the source of the third PMOS transistor MP3 and one end of the first capacitor Cf1. The third terminal is connected to Vb as the first end of the first feedback unit 102.

[0058] The drain of the third PMOS transistor MP3 is connected to the other end of the first capacitor Cf1, the drain of the fifth NMOS transistor MN5 is connected to the drain of the third PMOS transistor MP3, the source of the fifth NMOS transistor MN5 is grounded, and a fourth terminal is connected between the drain of the fifth NMOS transistor MN5 and the drain of the third PMOS transistor MP3. The fourth terminal is the second end of the first feedback unit 102 and is connected to the gate of the third NMOS transistor MN3.

[0059] The source of the fourth PMOS tube MP4 is connected to the first power source, the drain of the fourth PMOS tube MP4 is connected to the drain of the fourth NMOS tube MN4, and the gate of the fourth PMOS tube MP4 is connected to the drain of the fourth PMOS tube MP4.

[0060] A fifth terminal is connected between the gate of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5 . The fifth terminal is a control terminal of the first feedback unit 102 and is used to connect the third terminal of the second feedback unit 103 .

[0061] Please refer to Figure 3 , Figure 3 Schematic diagram of the structure of the second feedback unit provided in the embodiment of the present application. Figure 3 As shown, the second feedback unit 103 includes: a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a third resistor R3 and a second capacitor Cf2.

[0062] The gate of the sixth NMOS transistor MN6 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the gate of the seventh NMOS transistor MN7, the first end of the second capacitor Cf2 serves as the first end of the second feedback unit 103 and is connected to the first wiring terminal (Vout), the second end of the second capacitor Cf2 is connected between the gate of the sixth NMOS transistor MN6 and the first end of the third resistor R3, a sixth wiring terminal is led out between the gate of the sixth NMOS transistor MN6 and the first end of the third resistor R3, and the sixth wiring terminal serves as the third end of the second feedback unit 103 and is connected to the gate of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5.

[0063] The source of the sixth NMOS tube MN6 is grounded, the drain of the sixth NMOS tube MN6 is connected to the drain of the fifth PMOS tube MP5, the source of the fifth PMOS tube MP5 is connected to the first power supply, the gate of the fifth PMOS tube MP5 is connected to the drain of the fifth PMOS tube MP5, and the gate of the fifth PMOS tube MP5 serves as the second end of the second feedback unit 103, connected to the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2.

[0064] The source node of the seventh NMOS transistor MN7 and the drain of the seventh NMOS transistor MN7 are used to connect to the second current source (such as Ibias in the figure), and the drain of the seventh NMOS transistor MN7 is connected between the gate of the seventh NMOS transistor MN7 and the third resistor R3.

[0065] Please continue to refer to Figure 3 The second feedback unit 103 also includes an eighth NMOS tube MN8, a first switch tube Q1 and a low power consumption logic unit 1031.

[0066] The gate of the eighth NMOS transistor MN8 is connected to the gate of the seventh NMOS transistor MN7, the source of the eighth NMOS transistor MN8 is grounded, the drain of the eighth NMOS transistor MN8 is connected to the first end of the first switch transistor Q1, the second end of the first switch transistor Q1 is connected to the drain of the seventh NMOS transistor MN7, and the control end of the first switch transistor Q1 is connected to the low power logic unit 1031;

[0067] The low power consumption logic unit 1031 is used for sending a trigger instruction to the first switch tube Q1 to switch the first switch tube Q1 to a closed state when the regulated power supply is switched to the low power consumption mode.

[0068] It should be understood that the low power consumption logic unit 1031 can receive instructions from the host computer (MCU or CPU) to determine whether the regulated power supply is switched to the low power consumption mode.

[0069] Please continue to refer to Figure 3 The second feedback unit 103 further includes a power-on logic unit 1032 , a second switch tube Q2 , a third switch tube Q3 and a third capacitor Cf3 .

[0070] One end of the third capacitor Cf3 is connected to the second end of the second capacitor Cf2 , and the other end of the third capacitor Cf3 is grounded.

[0071] The first end of the second switch tube Q2 is connected to the second end of the second capacitor Cf2, the second end of the second switch tube Q2 is connected to the first end of the third resistor R3, the first end of the third switch tube Q3 is connected to one end of the third capacitor Cf3, and the second end of the third switch tube Q3 is connected to the other end of the third capacitor Cf3.

[0072] The control end of the second switch tube Q2 and the control end of the third switch tube Q3 are connected to the power-on logic unit 1032 .

[0073] The power-on logic unit 1032 is used to control the second switch tube Q2 to be in an open state and the third switch tube Q3 to be in a closed state when the regulated power supply is powered on. After the regulated power supply is powered on for a preset time length, the second switch tube Q2 is controlled to be in a closed state and the third switch tube Q3 is controlled to be in an open state.

[0074] In a possible implementation, the error amplification unit 101 also includes a fourth resistor R4 and a fourth capacitor Cf4, one end of the fourth resistor R4 is connected to the second end of the driving tube MP0, the other end of the fourth resistor R4 is connected to one end of the fourth capacitor Cf4, and the other end of the fourth capacitor Cf4 is connected to the third end of the driving tube MP0.

[0075] Optionally, the fourth resistor R4 is a variable resistor and / or the fourth capacitor Cf4 is a variable capacitor.

[0076] The Miller compensation circuit composed of the fourth resistor R4 and the fourth capacitor Cf4 realizes the stability of the entire regulated power supply (LDO loop). The regulated power supply in the present application is also referred to as LDO without external capacitors. The output pole (Va) of the error amplifier unit 101 of the LDO without external capacitors is the main pole, and the LDO output pole (Vout) is the secondary pole. When the LDO is unloaded, the distance between the LDO output pole and the main pole is the shortest, and the closed-loop stability is the worst. However, due to the introduction of Miller compensation, the output pole of the LDO without external capacitors is still the main pole. When the LDO is loaded, the distance between the LDO output pole and the output pole of the LDO without external capacitors is the farthest, and the closed-loop stability is the best at this time. Setting Miller compensation can easily make the loop stability greater than 70 degrees of phase margin.

[0077] Please refer to Figure 4 , Figure 4 A schematic diagram of transient characteristics of an LDO load current and output voltage provided in an embodiment of the present application. Figure 4 As shown in the figure, the biggest challenge facing the LDO without external capacitors is the lack of output voltage-stabilizing capacitors. The limited bandwidth makes the LDO unable to respond to sudden changes in load current in a timely manner. When the load current or power supply changes instantly, the LDO output voltage drop and overshoot voltage are abnormally obvious, which will have a great impact on the performance of the entire system.

[0078] The output load fast response of the medium and high frequency band of the voltage-stabilized power supply provided by the present application is realized by the dynamic bias current technology. Taking the output voltage Vout dropping caused by the increase of the load current as an example, the medium and high frequency change of Vout returns to the gate voltage of the second NMOS tube MN2 through the feedback network, and causes the Vb voltage to rise after being amplified by the first-level voltage amplifier (the second NMOS tube MN2). Vb is transmitted to Vc in advance through the feedforward capacitor (the first capacitor Cf1), causing the tail current I of the third NMOS tube MN3 of the entire error amplification unit 101 to increase. Since the reference voltage VREF voltage remains unchanged, and the gate voltage of the second NMOS tube MN2 drops, the current of the second NMOS tube MN2 is lower than the current of the first NMOS tube MN1. Combined with the increase of the tail current of the third NMOS tube MN3, the current flowing through the first NMOS tube MN1 is doubled, that is, the pull-down capability Ibias1 of the gate voltage of the driving tube MP0 is greatly enhanced, the driving tube MP0 is rapidly reduced, and the output driving capability of the driving tube MP0 is enhanced, and the output voltage Vout is pulled up to a normal value. It should be understood that the output voltage reverse jump process is also valid, which will not be elaborated here.

[0079] The dynamic bias current technology provided in the embodiment of the present application does not consume the static power consumption of the LDO. Only when the load consumes a large current, the bias current of the LDO itself increases, and only then changes the pull-down current of the gate voltage of the driving tube and the bandwidth of the entire LDO loop. This technology significantly improves the load current increase and the instantaneous drop of the output voltage Vout, and greatly reduces the voltage amplitude of the Vout transient undershoot.

[0080] The voltage-stabilized power supply provided in the present application also adopts a high-frequency bidirectional transient acceleration circuit. Specifically, when the output voltage Vout overshoots, the pull-up current Ibais2 of the gate voltage of the driving tube MP0 is enhanced, and the pull-down current Ibais1 of the gate voltage of the driving tube MP0 is reduced, so the gate voltage of the driving tube MP0 increases rapidly, so that the power supply of the driving tube MP0 to the load is reduced, and the output voltage quickly falls back to a normal value. When the output voltage Vout drops, the pull-up current Ibais2 of the gate voltage of the driving tube MP0 decreases, and the pull-down current Ibais1 of the gate voltage of the driving tube MP0 increases, so the gate voltage of the PMOS driving tube decreases rapidly, so that the PMOS driving tube provides more current to the load, and the output voltage rises rapidly to a normal value. Since the current signal transmission is faster than the voltage amplification, the high-frequency bidirectional transient acceleration technology has an obvious transient acceleration effect on the jitter of the output voltage. This technology does not rely on the voltage stabilizing effect of the output capacitor Cout, and does not require additional static power consumption.

[0081] The working principle of the pull-up current Ibias2 for increasing the gate voltage of the driving tube MP0 in the bidirectional transient acceleration technology is to dynamically adjust the gate voltage of the first PMOS tube MP1 and the second PMOS tube MP2 in the error amplifier unit 101 of the LDO by outputting the NMOS current mirror gate voltage Vbias after the high-pass RC filter composed of the third resistor and the second capacitor Cf2.

[0082] When the load is reduced and the output voltage Vout overshoots, the positive jitter of the output voltage Vout is transmitted in advance to the gate voltage Vbias of the sixth NMOS tube MN6 through the high-pass RC filter, causing the branch current of the sixth NMOS tube MN6 to increase, and the gate voltage of the first PMOS tube MP1 and the second PMOS tube MP2 is reduced through the PMOS current mirror, so that the gate voltage current of the first PMOS tube MP1 and the second PMOS tube MP2 is dynamically increased, that is, the pull-up current Ibias2 of the gate voltage of the driving tube MP0 is accelerated.

[0083] The working principle of the high-frequency dynamic pull-down current Ibias1 of the bidirectional transient acceleration technology to increase the gate voltage of the PMOS driver tube is as follows: When the load decreases and the output voltage Vout surges, the positive jitter of the output voltage Vout is simultaneously transmitted to the gate voltage Vbias of the fifth NMOS tube MN5 in advance through the feedback high-pass RC filter, and after amplification, the drain voltage of the fifth NMOS tube MN5 is reduced, thereby reducing the tail current (I) of the third NMOS tube MN3. Since the reference VREF voltage remains unchanged, and the gate voltage of the second NMOS tube MN2 increases with the output voltage Vout, the current divided by the second NMOS tube MN2 increases, combined with the reduction of the branch current of the third NMOS tube MN3, the final result is that the current flowing through the first NMOS tube MN1 is doubled, that is, the pull-down current Ibais1 of the gate voltage of the driver tube MP0 is reduced.

[0084] After the non-chip capacitor-stabilized power supply provided in the embodiment of the present application adopts high-frequency bidirectional transient acceleration technology, when the load current changes at high speed and causes the output voltage to drop or overshoot, under the common regulation in both directions, the pull-up and pull-down currents of the PMOS driver gate voltage are superimposed and increased, and the PMOS driver gate voltage responds more quickly, thereby achieving high-frequency and rapid response of the output voltage. The same is true for changes in the output in the opposite direction.

[0085] The embodiment of the present application provides a fast response voltage-stabilized power supply without external capacitors, and designs a set of transient acceleration loop enabling circuits to eliminate the disturbance caused by the bidirectional transient acceleration circuit to the LDO power-on process. When the LDO enable signal arrives, the output voltage Vout is extremely low, and is fed back to the gate voltage Vbias of the current mirror corresponding to the sixth NMOS tube MN6, the fourth NMOS tube MN4, and the fifth NMOS tube MN5 through the RC high-pass filter. Therefore, the Vbias voltage is also very low, so that the sixth NMOS tube MN6, the fourth NMOS tube MN4, and the fifth NMOS tube MN5 cannot be turned on normally, resulting in the third NMOS tube MN3 of the tail current source and the fifth PMOS official MP5 of the load tube current mirror in the error amplifier unit 101 not having the correct working point. After adding the enabling circuit, the transient acceleration loop is avoided from being turned on during the LDO power-on process. The specific principle is: after the LDO enable signal arrives, the power-on logic unit 1032 (also known as the power-on counting circuit) charges the fixed capacitor through a small current to achieve a fixed time delay of 50us to 100us. After ensuring that the LDO completes the power-on process, the power-on logic unit 1032 gives a bidirectional transient acceleration circuit enable signal TREN, so that the second switch tube Q2 is closed and the third switch tube Q3 is disconnected, enabling the feedback switch of the output RC high-pass filter, effectively eliminating the interference caused by the transient acceleration loop to the LDO main loop in the initial power-on period.

[0086] Another technology of the fast response voltage-stabilized power supply without external capacitors in the present application is to realize two working modes, normal mode and low power mode, through a set of loops. In low power mode, the load current capacity of LDO is reduced to one twentieth of that in normal working mode, and there is no need to design an additional set of low power loops, which eliminates the jitter generated by the output voltage when the two modes are switched. Since the output of LDO without external capacitors has no large capacitor voltage stabilization, if two loops are used for the two modes, the output voltage will generate large jitter at the moment of switching between the two modes due to the different gains of the two loops. The power consumption of the low power mode of LDO without external capacitors is reduced to one tenth of that of the normal mode. This function is realized by the difference of the width-to-length ratio of the seventh NMOS tube MN7 and the eighth NMOS tube MN8 of the IBIAS current mirror tube by a preset multiple, for example, a difference of nine times, and the width-to-length ratio of the seventh NMOS tube MN7 and the sixth NMOS tube MN6 is the same. The low power logic unit 1031 only needs to give the ECOEN signal when the low power mode is enabled, so that the first switch tube Q1 is closed and the series switch of the eighth NMOS tube MN8 is turned on, so that the power consumption of the error amplifier in the low power mode can be reduced by 90%.

[0087] In a possible embodiment, the fast response linear voltage regulator without external capacitors provided by the present application is adopted, and the full corner load jump speed is 100ns from full no-load to full load 20mA transient jump, and the LDO output voltage transient overshoot voltage is less than 200mV, and the undershoot voltage is less than 120mV. The load capacitance of the linear voltage regulator without external capacitors is the equivalent capacitance of the digital circuit load, and the on-chip voltage regulator capacitance is 100pf.

[0088] An embodiment of the present application also provides an electronic device, comprising the above-mentioned voltage-stabilized power supply.

[0089] Optionally, the electronic device further includes a post-stage load circuit, and the post-stage load circuit is connected to the output end of the voltage-stabilized power supply.

[0090] In summary, the embodiment of the present application provides a voltage-stabilized power supply and electronic equipment, the voltage-stabilized power supply includes a driving tube, a first resistor, a second resistor, an error amplifying unit, a first feedback unit and a second feedback unit, the error amplifying unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube and a second PMOS tube; the first end of the driving tube is connected to the first power supply, the second end of the driving tube is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is grounded, and a first terminal is drawn between the second resistor and the second end of the driving tube, and the first terminal is the output end of the voltage-stabilized power supply; the first end of the first feedback unit is connected between the drain of the second PMOS tube and the drain of the second NMOS tube, the second end of the first feedback unit is connected to the gate of the third NMOS tube; the first end of the second feedback unit is connected to the first terminal, the second end of the second feedback unit is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and the third end of the second feedback unit is connected to the control end of the first feedback unit. The problem of poor load current response speed of the voltage-stabilized power supply without off-chip capacitors can be improved.

[0091] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0092] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A voltage-stabilized power supply, characterized in that: The voltage-stabilized power supply includes a driving tube, a first resistor, a second resistor, an error amplifying unit, a first feedback unit and a second feedback unit, and the error amplifying unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube and a second PMOS tube; The first end of the driving tube is connected to the first power supply, the second end of the driving tube is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is grounded, and a first wiring terminal is connected between the second resistor and the second end of the driving tube, and the first wiring terminal is the output end of the voltage-stabilized power supply; The source of the first PMOS tube and the source of the second PMOS tube are both connected to the first power supply, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, the source of the first NMOS tube and the source of the second NMOS tube are both connected to the drain of the third NMOS tube, the source of the third NMOS tube is grounded, the gate of the first NMOS tube is used to access the reference voltage, the gate of the second NMOS tube is connected between the first resistor and the second resistor, a second wiring terminal is led out between the drain of the first PMOS tube and the drain of the first NMOS tube, and the second wiring terminal is connected to the third end of the driving tube; The first end of the first feedback unit is connected between the drain of the second PMOS tube and the drain of the second NMOS tube, and the second end of the first feedback unit is connected to the gate of the third NMOS tube; The first end of the second feedback unit is connected to the first terminal, the second end of the second feedback unit is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and the third end of the second feedback unit is connected to the control end of the first feedback unit.

2. The voltage-stabilized power supply according to claim 1, characterized in that: The first feedback unit includes a third PMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a first capacitor; The gate of the third PMOS tube is connected to the gate of the fourth PMOS tube, and a third wiring terminal is connected between the source of the third PMOS tube and one end of the first capacitor, and the third wiring terminal serves as the first end of the first feedback unit; The drain of the third PMOS tube is connected to the other end of the first capacitor, the drain of the fifth NMOS tube is connected to the drain of the third PMOS tube, the source of the fifth NMOS tube is grounded, and a fourth terminal is connected between the drain of the fifth NMOS tube and the drain of the third PMOS tube, and the fourth terminal is the second end of the first feedback unit; The source of the fourth PMOS tube is connected to the first power supply, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube; A fifth connecting terminal is led out from the connection between the gate of the fourth NMOS tube and the gate of the fifth NMOS tube, and the fifth connecting terminal is the control end of the first feedback unit.

3. The voltage-stabilized power supply according to claim 1, characterized in that: The second feedback unit includes: a fifth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a third resistor and a second capacitor; The gate of the sixth NMOS tube is connected to the first end of the third resistor, the second end of the third resistor is connected to the gate of the seventh NMOS tube, the first end of the second capacitor serves as the first end of the second feedback unit, the second end of the second capacitor is connected between the gate of the sixth NMOS tube and the first end of the third resistor, a sixth terminal is drawn between the gate of the sixth NMOS tube and the first end of the third resistor, and the sixth terminal serves as the third end of the second feedback unit; The source of the sixth NMOS tube is grounded, the drain of the sixth NMOS tube is connected to the drain of the fifth PMOS tube, the source of the fifth PMOS tube is connected to the first power supply, the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube, and the gate of the fifth PMOS tube serves as the second end of the second feedback unit; The source node of the seventh NMOS tube and the drain of the seventh NMOS tube are used to connect to the second current source, and the drain of the seventh NMOS tube is connected between the gate of the seventh NMOS tube and the third resistor.

4. The voltage-stabilized power supply according to claim 3, characterized in that: The second feedback unit also includes an eighth NMOS tube, a first switch tube and a low power consumption logic unit; The gate of the eighth NMOS tube is connected to the gate of the seventh NMOS tube, the source of the eighth NMOS tube is grounded, the drain of the eighth NMOS tube is connected to the first end of the first switch tube, the second end of the first switch tube is connected to the drain of the seventh NMOS tube, and the control end of the first switch tube is connected to the low power logic unit; The low power consumption logic unit is used for sending a trigger instruction to the first switch tube to switch the first switch tube to a closed state when the regulated power supply switches to a low power consumption mode.

5. The voltage-stabilized power supply according to claim 3, characterized in that: The second feedback unit further includes a power-on logic unit, a second switch tube, a third switch tube and a third capacitor; One end of the third capacitor is connected to the second end of the second capacitor, and the other end of the third capacitor is grounded; The first end of the second switch tube is connected to the second end of the second capacitor, the second end of the second switch tube is connected to the first end of the third resistor, the first end of the third switch tube is connected to one end of the third capacitor, and the second end of the third switch tube is connected to the other end of the third capacitor; The control end of the second switch tube and the control end of the third switch tube are connected to the power-on logic unit.

6. The voltage-stabilized power supply according to claim 5, characterized in that: The power-on logic unit is used to control the second switch tube to be in an open state and the third switch tube to be in a closed state when the regulated power supply is powered on; after the regulated power supply is powered on for a preset time length, the second switch tube is controlled to be in a closed state and the third switch tube is controlled to be in an open state.

7. The voltage-stabilized power supply according to claim 1, characterized in that: The error amplification unit also includes a fourth resistor and a fourth capacitor, one end of the fourth resistor is connected to the second end of the driving tube, the other end of the fourth resistor is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is connected to the third end of the driving tube.

8. The voltage-stabilized power supply according to claim 7, characterized in that: The fourth resistor is a variable resistor and / or the fourth capacitor is a variable capacitor.

9. An electronic device, characterized in that: A voltage-stabilized power supply comprising any one of claims 1 to 8.

10. The electronic device according to claim 9, characterized in that: The electronic device further comprises a post-stage load circuit, and the post-stage load circuit is connected to the output end of the voltage-stabilized power supply.

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