Control chip and control method

Abstract

The invention discloses a control chip and a control method, and the control chip supplies power to a power receiving device, and comprises a connection port, an encoder, a decoder and a control circuit. The connection port provides an output voltage to the powered device and receives a reply signal provided by the powered device. The control circuit obtains the voltage actually received by the powered device according to the reply signal, and adjusts the output voltage according to the voltage actually received by the powered device. In the setting mode, the control circuit obtains a protection point voltage value of the powered device according to the return signal and adjusts the output voltage according to the protection point voltage value so as to prevent the output voltage from being greater than the protection point voltage value.

Description

Technical Field

[0001] The present invention relates to a control chip, and more particularly to a control chip and a control method for providing an appropriate output voltage to an external chip according to an upper voltage limit of the external chip. Background Art

[0002] Generally speaking, a power supply chip provides an output voltage to an external chip according to the requirements of an external chip. However, when the external chip outputs an abnormal requirement and requires the power supply chip to provide an excessive output voltage, if the power supply chip complies with the requirements of the external chip, the external chip may be burned by the excessive output voltage. In addition, when the power supply chip supplies power to the external chip through a connecting line, the line resistance of the connecting line may affect the output voltage, so that the voltage actually received by the external chip is less than the voltage provided by the power supply chip. Summary of the invention

[0003] One embodiment of the present invention provides a control chip that supplies power to a power receiving device and includes a connection port, an encoder, a decoder, and a control circuit. The connection port includes a power pin and a communication pin. The power pin is used to provide an output voltage to the power receiving device. The communication pin is coupled to the power receiving device and, according to a communication protocol, provides an inquiry signal to the power receiving device and receives a response signal provided by the power receiving device. The encoder encodes an inquiry message to generate an inquiry signal. The decoder decodes the response signal to generate a decoding result. The control circuit provides inquiry information and operates in a compensation mode or a setting mode. In the compensation mode, the control circuit learns the voltage actually received by the power receiving device based on the decoding result, and adjusts the output voltage based on the voltage actually received by the power receiving device. In the setting mode, the control circuit learns a protection point voltage value of the power receiving device based on the decoding result, and adjusts the output voltage based on the protection point voltage value to prevent the output voltage from being greater than the protection point voltage value.

[0004] In another embodiment, the control chip includes a connection port, an encoder, a decoder and a control circuit. The connection port includes a power pin and a communication pin. The power pin is used to receive an output voltage from a power supply device. The communication pin is coupled to the power supply device, and according to a communication protocol, receives an inquiry signal from the power supply device and outputs a reply signal. The decoder decodes the inquiry signal to generate a decoding result. The control circuit performs a detection operation or a notification operation based on the decoding result. When the control circuit performs the detection operation, the control circuit detects the output voltage to generate a detection result. When the control circuit performs the notification operation, the control circuit provides a protection point voltage value. The encoder encodes the detection result or the protection point voltage value to generate a reply signal.

[0005] In another embodiment, the present invention provides a control method, including: providing an output voltage to a power receiving device; sending an inquiry signal to the power receiving device; receiving a reply signal provided by the power receiving device; and performing a compensation operation or a setting operation according to the reply signal. The compensation operation adjusts the output voltage so that the output voltage received by the power receiving device is equal to an initial value. The setting operation prevents the output voltage from being greater than a protection point voltage value.

[0006] In another embodiment, the present invention provides a control method, including: receiving an output voltage and setting the output voltage as a system voltage; receiving an inquiry signal; performing a detection operation or a notification operation according to the inquiry signal to generate a reply signal; and outputting the reply signal. The detection operation includes: detecting the system voltage to generate a detection result; and generating a reply signal according to the detection result. The notification operation includes: reading a protection point voltage value; and generating a reply signal according to the protection point voltage value.

[0007] The control method of the present invention can be implemented via the control chip of the present invention, which is hardware or firmware that can execute specific functions, or can be recorded in a storage medium in the form of a program and implemented in combination with specific hardware. When the program is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a control chip for implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the operating system of the present invention.

[0009] Figure 2A The figure is a flow chart of a control method for performing compensation operation on a control chip of the present invention.

[0010] Figure 2B The figure is a flow chart of a control method for setting operation of a control chip of the present invention.

[0011] Figure 2C It is a flow chart of a control method for a control chip of the present invention to perform compensation operation and setting operation.

[0012] Figure 3 FIG. 4 is another flow chart of the control method of the control chip of the present invention.

[0013] Figure 4 This is a possible embodiment of the control chip of the present invention.

[0014] Explanation of symbols

[0015] 100: Operating System

[0016] 110, 120, 400: control chip

[0017] VOUT: output voltage

[0018] VSYS: system voltage

[0019] 111, 112: Transmission interface

[0020] VBUS, D+, D-, CC: pins

[0021] S_QY, S_QY1, S_QY2: inquiry signal

[0022] S_AK, S_AK1, S_AK2: reply signal

[0023] 130: Connection line

[0024] 131: Power Path

[0025] 132: Communication path

[0026] S211-S215, S221-S223, S311-S313: Step 410: Connecting ports

[0027] 420: Encoder

[0028] 430: Decoder

[0029] 440: Control circuit

[0030] 450: Power circuit

[0031] 411: Power interface

[0032] 412: Communication interface

[0033] INF1, INF2: output information

[0034] S_D1, S_D2: decoding results DETAILED DESCRIPTION

[0035] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the following examples are specifically cited and described in detail with the accompanying drawings. The present invention specification provides different examples to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the example is for illustration purposes and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the examples are for the purpose of simplifying the description and do not mean the relevance between different examples.

[0036] Figure 1Schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 100 includes control chips 110 and 120. In this embodiment, the control chip 110 acts as a power supply device (SOURCE) to provide an output voltage VOUT. The control chip 120 receives the output voltage VOUT and uses the output voltage VOUT as a system voltage VSYS. In this example, the control chip 120 acts as a power receiving device (SINK).

[0037] The control chip 110 has a transmission interface 111. The transmission interface 111 is used to transmit the output voltage VOUT to the control chip 120. The control chip 120 has a transmission interface 112. The transmission interface 112 is used to receive the output voltage VOUT. The present invention does not limit the types of the transmission interfaces 111 and 112. As long as the transmission interface can transmit power, it can be used as the transmission interface 111 and 112. In one possible embodiment, the transmission interfaces 111 and 112 are universal serial bus (USB) connection ports. In this example, the power pin VBUS of the transmission interface 111 provides the output voltage VOUT, and the power pin VBUS of the transmission interface 112 receives the output voltage VOUT.

[0038] In other embodiments, the transmission interfaces 111 and 112 further include pins D+ and D- (or communication pins). The control chip 110 communicates with the control chip 120 through the pins D+ and D- of the transmission interface 111. For example, the control chip 110 may send an inquiry signal S_QY to the control chip 120 through the pins D+ and D-, and receive a response signal S_AK generated by the control chip 120 through the pins D+ and D-. In this example, the control chip 120 receives the inquiry signal S_QY from the control chip 110 through the pins D+ and D- of the transmission interface 112. The control chip 120 performs a corresponding action according to the inquiry signal S_QY, and generates a response signal S_AK according to the execution result. The control chip 120 outputs the response signal S_AK to the control chip 110 through the pins D+ and D-.

[0039] In another possible embodiment, the control chip 120 may send an inquiry signal S_QY to the control chip 110 through the pins D+ and D-, and receive the response signal S_AK generated by the control chip 110 through the pins D+ and D-. In this example, the control chip 110 receives the inquiry signal S_QY from the control chip 120 through the pins D+ and D- of the transmission interface 111. The control chip 110 performs a corresponding action according to the inquiry signal S_QY, and generates the response signal S_AK according to the execution result. The control chip 110 outputs the response signal S_AK to the control chip 120 through the pins D+ and D-. In other embodiments, the control chip 120 may request the control chip 110 to adjust the output voltage VOUT through the pins D+ and D- of the transmission interface 112. In this example, the control chip 110 adjusts the output voltage VOUT according to the request of the control chip 120.

[0040] In other embodiments, the control chip 110 communicates with the control chip 120 via the configuration channel pin CC of the transmission interface 111. In this example, the control chip 110 may send an inquiry signal S_QY to the control chip 120 via the pin CC (or communication pin) of the transmission interface 111, and receive a response signal S_AK from the control chip 120. In another possible embodiment, the control chip 120 sends the inquiry signal S_QY to the control chip 110 via the pin CC, and receives a response signal S_AK from the control chip 110.

[0041] In some embodiments, the operating system 100 further includes a connection line 130. The present invention does not limit the type of the connection line 130. In one possible embodiment, the connection line 130 is a USB connection line. The connection line 130 is coupled between the control chips 110 and 120 and has a power path 131. In this example, the power path 131 is coupled between the power pins VBUS of the transmission interfaces 111 and 112 to transmit the output voltage VOUT.

[0042] In other embodiments, the connection line 130 further includes a communication path 132. The communication path 132 is used to transmit the inquiry signal S_QY and the response signal S_AK. The communication path 132 may have a first path and a second path. The first path couples the pins D+ of the transmission interfaces 111 and 112. The second path couples the pins D- of the transmission interfaces 111 and 112. In another possible embodiment, the communication path 132 couples the pins CC of the transmission interfaces 111 and 112.

[0043] The present invention does not limit the sources of the inquiry signal S_QY and the response signal S_AK. In one possible embodiment, when the control chip 110 sends the inquiry signal S_QY, the control chip 120 generates the response signal S_AK to the control chip 110 according to the inquiry signal S_QY. In another possible embodiment, when the control chip 120 sends the inquiry signal S_QY, the control chip 110 generates the response signal S_AK to the control chip 120 according to the inquiry signal S_QY.

[0044] The control chip 120 uses the output voltage VOUT as its own system voltage VSYS and operates according to the system voltage VSYS. Figure 1 In the figure, the output voltage VOUT refers to the voltage provided by the control chip 110, and the system voltage VSYS refers to the voltage received by the control chip 120. Due to the influence of the length and material of the connection line 130, when the connection line 130 transmits the output voltage VOUT generated by the control chip 110 to the control chip 120, the voltage received by the control chip 120 (i.e., the system voltage VSYS) may be slightly lower than the voltage provided by the control chip 110 (i.e., the output voltage VOUT). For example, the output voltage VOUT provided by the control chip 110 may be 5V, and the system voltage VSYS received by the control chip 120 may be 4.96V.

[0045] In order to compensate for the voltage drop (IR Drop) caused by the connection line 130, when the control chip 120 is coupled to the control chip 110 through the connection line 130, the control chip 110 enters a compensation mode. In the compensation mode, the control chip 110 sends an inquiry signal S_QY through the communication path 132 of the connection line 130 to inquire about the voltage value of the system voltage VSYS actually received by the control chip 120. The control chip 120 detects the system voltage VSYS according to the inquiry signal S_QY to generate a detection result. The control chip 120 generates a response signal S_AK according to the detection result and outputs the response signal S_AK. The control chip 110 learns a difference between the system voltage VSYS and the output voltage VOUT according to the response signal S_AK. The control chip 110 adjusts the output voltage VOUT according to the difference, such as increasing the output voltage VOUT from 5V to 5.04V.

[0046] In a possible embodiment, after the control chip 120 is coupled to the control chip 110 through the connection line 130, the control chip 110 first sets the output voltage VOUT to an initial value, such as 5V, and then provides the output voltage VOUT to the control chip 120 through the power path 131. Then, the control chip 110 sends an inquiry signal S_QY to the control chip 120 to inquire about the voltage value of the system voltage VSYS. In some embodiments, after the control chip 110 sends the inquiry signal S_QY, if the control chip 110 does not receive the reply signal S_AK after a period of time, it means that the control chip 120 does not support the inquiry signal S_QY. Therefore, the control chip 110 may suspend the compensation operation.

[0047] In one possible embodiment, the inquiry signal S_QY and the received response signal S_AK comply with a specific communication protocol. The specific communication protocol may be a power delivery specification (PD) protocol or a universal fast charging specification (UFCS) protocol. In this example, the control chip 110 encodes an inquiry message according to the specific communication protocol to generate the inquiry signal S_QY. The control chip 120 decodes the inquiry signal S_QY using the same specific communication protocol. The control chip 120 encodes a response message based on the decoding result to generate the response signal S_AK. The control chip 110 decodes the response signal S_AK using the same specific communication protocol and acts according to the decoding result, such as adjusting the output voltage VOUT.

[0048] In other embodiments, the control chip 120 may request the control chip 110 to increase the output voltage VOUT through the communication path 132. Ideally, the control chip 120 requests the control chip 110 to increase or decrease the output voltage VOUT according to its own needs. However, when the control chip 120 operates abnormally, the control chip 120 may request an excessively large output voltage VOUT. When the control chip 110 provides an excessively large output voltage VOUT according to the control chip 120's request, the control chip 120 is likely to be burned. In other embodiments, even if the control chip 120 does not request an increase in the output voltage VOUT, the control chip 110 may mistakenly adjust the output voltage VOUT so that the output voltage VOUT exceeds the maximum voltage that the control chip 120 can withstand. Therefore, before entering the normal mode, the control chip 110 may first enter a setting mode. In the setting mode, the control chip 110 sends an inquiry signal S_QY to inquire about the voltage upper limit value of the control chip 120. Then, according to the reply of the control chip 120, the control chip 110 uses the voltage upper limit value of the control chip 120 as a first protection point voltage value. After entering the normal mode, the control chip 110 provides a suitable output voltage VOUT according to the first protection point voltage value. For example, when the voltage required by the control chip 120 is greater than the first protection point voltage value, the control chip 110 may ignore the request of the control chip 120.

[0049] In other embodiments, in the setting mode, the control chip 110 inquires a voltage lower limit value of the control chip 120 through the inquiry signal S_QY, and uses the voltage lower limit value of the control chip 120 as a second protection point voltage value. In this example, in the normal mode, when the voltage required by the control chip 120 is less than the second protection point voltage value, the control chip 110 may ignore the request of the control chip 120.

[0050] In some embodiments, after the connection line 130 is plugged in and out again, the control chip 110 obtains a new protection point voltage value through the inquiry signal S_QY, and replaces the previous protection point voltage value with the new protection point voltage value. Therefore, the control chip 110 can provide overvoltage protection or undervoltage protection for different control chips 120. In one possible embodiment, the control chip 110 stores the protection point voltage value in a volatile memory. In this case, when the control chip 110 is powered on again, the control chip 110 re-enters the setting mode to detect and record the voltage upper limit value of the control chip 120. Before the control chip 110 inquires about the voltage upper limit value of the control chip 120, the control chip 110 may first set the output voltage VOUT equal to an initial value, and then inquire about the control chip 120.

[0051] In one possible embodiment, after the control chip 110 and the control chip 120 are connected, the control chip 110 may first set the output voltage VOUT to be equal to an initial value, and provide the output voltage VOUT to the control chip 120. Then, the control chip 110 enters a compensation mode or a setting mode. In the compensation mode, the control chip 110 performs a compensation operation to compensate for the influence of the connection line 130 on the output voltage VOUT. After completing the compensation operation, the control chip 110 may enter a setting mode. In another possible embodiment, after completing the compensation operation, the control chip 110 may directly enter the normal mode. In the normal mode, the control chip 110 adjusts the output voltage VOUT according to the requirements of the control chip 120. In addition, when the control chip 110 enters the setting mode, the control chip 110 performs a setting operation to set the protection point voltage value of the control chip 120. After completing the setting operation, the control chip 110 may directly enter a normal mode or enter the compensation mode. For example, the control chip 110 may set the protection point voltage value without compensating for the influence of the connection line 130 on the output voltage VOUT.

[0052] Figure 2A 1 is a flow chart of a control method for performing compensation operation on the control chip 110 of the present invention. The compensation operation may be implemented by a program. When the program is loaded and executed by a machine, the machine becomes a control chip 110 for implementing the present invention. First, the control chip 110 sends a first inquiry signal to inquire about the voltage value of the system voltage VSYS of the control chip 120 (step S211). In a possible embodiment, the first inquiry signal complies with the USB PD protocol or the UFCS protocol.

[0053] Next, it is determined whether a first reply signal is received (step S212). When the control chip 110 receives the first reply signal, the control chip 110 adjusts the output voltage VOUT according to the first reply signal (step S213). In one possible embodiment, the control chip 110 decodes the first reply signal, and then learns the voltage value of the system voltage VSYS actually received by the control chip 120 based on the decoding result. In this example, the control chip 110 adjusts the output voltage VOUT, such as from 5V to 5.04V, based on the difference between the output voltage VOUT and the system voltage VSYS (such as 0.4V). In some embodiments, the communication protocol of the first reply signal is the same as the communication protocol of the first inquiry signal.

[0054] When the control chip 110 does not receive the first reply signal, the control chip 110 determines whether a preset time has been reached (step S214). When the waiting time of the control chip 110 reaches the preset time, it indicates that the compensation has failed (step S215). When the waiting time of the control chip 110 does not reach the preset time, it returns to step S212 and continues to wait for the first reply signal.

[0055] In other embodiments, before the control chip 110 sends the first inquiry signal, the control chip 110 first sets the output voltage VOUT to be equal to an initial value, and then provides the output voltage VOUT to the control chip 120. In this example, the control chip 110 may send a third inquiry signal to inquire about the voltage actually received by the control chip 120. The control chip 120 generates a third reply signal based on the voltage actually received. The control chip 110 decodes the third reply signal to determine whether the voltage actually received by the control chip 120 is equal to the initial value. When the voltage actually received by the control chip 120 is not equal to the initial value, the control chip 110 adjusts the output voltage until the voltage actually received by the control chip 120 is equal to the initial value.

[0056] Figure 2B Flow chart of the control method for setting operation of the control chip 110 of the present invention. The setting operation can be implemented by a program. When the program is loaded and executed by the machine, the machine becomes the control chip 110 for implementing the present invention. First, the control chip 110 sends a second inquiry signal to inquire about the voltage upper limit value of the control chip 120 (step S221). In a possible embodiment, the second inquiry signal complies with the USB PD protocol or the UFCS protocol.

[0057] Next, a second reply signal is received (step S222). In one possible embodiment, the control chip 110 decodes the second reply signal, and then obtains the voltage upper limit value of the control chip 120, that is, the maximum voltage value that the control chip 120 can withstand, according to the decoding result. The control chip 110 uses the voltage upper limit value of the control chip 120 as a protection point voltage value (step S223). In one possible embodiment, the control chip 110 stores the protection point voltage value in a volatile memory.

[0058] In some embodiments, after setting the highest protection point of the system of the control chip 120, the control chip 110 adjusts the output voltage VOUT according to the request of the control chip 120. In this example, the control chip 110 determines whether the voltage value requested by the control chip 120 is greater than the protection point voltage value. When the voltage value requested by the control chip 120 is greater than the protection point voltage value, the control chip 110 ignores the request issued by the control chip 120. At this time, the control chip 110 may maintain the output voltage VOUT. When the voltage value requested by the control chip 120 is not greater than the protection point voltage value, the control chip 110 adjusts the output voltage VOUT according to the request of the control chip 120.

[0059] In other embodiments, before the control chip 110 sends the second inquiry signal, the control chip 110 first sets the output voltage VOUT to be equal to an initial value, and then provides the output voltage VOUT to the control chip 120. In this example, the control chip 110 may send a third inquiry signal to inquire about the voltage actually received by the control chip 120. The control chip 120 generates a third reply signal based on the voltage actually received. The control chip 110 decodes the third reply signal to determine whether the voltage actually received by the control chip 120 is equal to the initial value. When the voltage actually received by the control chip 120 is not equal to the initial value, the control chip 110 adjusts the output voltage until the voltage actually received by the control chip 120 is equal to the initial value.

[0060] Figure 2C FIG. 1 is a flow chart of a control method for the control chip 110 of the present invention to perform compensation operation and setting operation. In one possible embodiment, the control chip 110 first performs the compensation operation and then performs the setting operation. In this example, the compensation operation includes Figure 2A Steps S211 to S215, the setting operation includes Figure 2B In another possible embodiment, the control chip 110 performs the setting operation first and then the compensation operation. In this example, steps S221 to S223 are performed earlier than step S211.

[0061] Figure 3 FIG. 1 is a flow chart of a control method of the control chip 120 of the present invention. Figure 3 The operation can be implemented by a program. When the program is loaded and executed by the machine, the machine becomes a control chip 120 for implementing the present invention. First, the control chip 120 receives an inquiry signal (step S311). In a possible embodiment, before receiving the inquiry signal, the control chip 120 first receives an output voltage and uses the output voltage as a system voltage.

[0062] Next, a specific operation is performed according to the inquiry signal (step S312). In one possible embodiment, the control chip 120 decodes the inquiry signal to learn the matters inquired by the inquiry signal. In this example, the control chip 120 performs different specific operations according to different inquiry signals. For example, when the inquiry signal inquires about the system voltage of the control chip 120, the control chip 120 performs a detection operation. The control chip 120 detects the system voltage to generate a detection result. In this example, the control chip 120 encodes the detection result to generate a reply signal. In another possible embodiment, when the inquiry signal inquires about the voltage upper limit value of the control chip 120, the control chip 120 performs a notification operation. In this example, the control chip 120 encodes a voltage upper limit value to generate a reply signal. In this example, the voltage upper limit value is stored in the control chip 120 in advance. The control chip 120 has a storage circuit (not shown) to store the voltage upper limit value. The control chip 210 reads the storage circuit and then generates a reply signal according to the read result.

[0063] Next, a reply signal is output (step S313). In one possible embodiment, the control chip 120 receives the inquiry signal according to a specific communication protocol, and outputs the reply signal using the specific communication protocol.

[0064] Figure 4 The control chip 400 is a possible embodiment of the control chip of the present invention. The control chip 400 includes a connection port 410, an encoder 420, a decoder 430 and a control circuit 440. The connection port 410 includes a power interface 411. The power interface 411 is used to transmit the output voltage VOUT or the system voltage VSYS. For example, when the control chip 400 is used as Figure 1 When the control chip 110 is used as the power interface 411, the power interface 411 is used to output the output voltage VOUT. Figure 1 When the control chip 120 is connected to the power supply interface 411, the power supply interface 411 is used to receive the output voltage VOUT. In this example, the output voltage entering the control chip 400 is called the system voltage VSYS.

[0065] In other embodiments, the connection port 410 further includes a communication interface 412. The communication interface 412 is used to transmit the inquiry signals S_QY1, S_QY2 and the response signals S_AK1, S_AK2. Figure 1 When the control chip 400 is used as the control chip 110, the communication interface 412 outputs the inquiry signal S_QY1 to a first external chip and receives the response signal S_AK1 from the first external chip. In this example, the inquiry signal S_QY1 and the response signal S_AK1 comply with a first communication protocol. In another possible embodiment, when the control chip 400 is used as the control chip 110, the communication interface 412 outputs the inquiry signal S_QY1 to a first external chip and receives the response signal S_AK1 from the first external chip. Figure 1When the control chip 120 is turned on, the communication interface 412 receives a query signal S_QY2 from a second external chip and outputs a response signal S_AK2 to the second external chip. In this example, the query signal S_QY2 and the response signal S_AK2 conform to a second communication protocol. The second communication protocol may be the same as or different from the first communication protocol.

[0066] The present invention does not limit the type of the connection port 410. As long as the connection port can transmit power and communication signals, it can be used as the connection port 410. In one possible embodiment, the connection port 410 is a USB connection port. In this example, the power pin VBUS of the USB connection port serves as the power interface 411. The present invention does not limit the number of pins of the power interface 411. The power interface 411 may have a single power pin for transmitting a single voltage. In another possible embodiment, the power interface 411 has multiple power pins for transmitting multiple voltages. In other embodiments, the D+ and D- pins or the CC1 and CC2 pins of the USB connection port serve as the communication interface 412. The present invention does not limit the number of pins of the communication interface 412. The communication interface 412 has a single communication pin for transmitting the inquiry signal S_QY1 and the reply signal S_AK1 (or transmitting the inquiry signal S_QY2 and the reply signal S_AK2). In another possible embodiment, the communication interface 412 has at least two communication pins. In this example, a communication pin of the communication interface 412 transmits the inquiry signal S_QY1 (or the response signal S_AK2 ), and another communication pin of the communication interface 412 transmits the response signal S_AK1 (or the inquiry signal S_QY2 ).

[0067] The encoder 420 encodes an output information to generate the inquiry signal S_QY1 or the response signal S_AK2. Figure 1 When the control chip 400 is used as the control chip 110, the encoder 420 encodes an output information INF1 (or an inquiry information) to generate an inquiry signal S_QY1. In this example, the inquiry signal S_QY1 is used to inquire about at least one of the system voltage and the voltage upper limit value of a first external chip (not shown). Figure 1 When the control chip 120 is connected to the encoder 420, the encoder 420 encodes an output information INF2 to generate a response signal S_AK2. In this example, the output information INF2 may represent the voltage value or the voltage upper limit value of the system voltage VSYS of the control chip 400. In this example, a second external chip learns the voltage value or the voltage upper limit value of the system voltage VSYS of the control chip 400 through the response signal S_AK2. The present invention does not limit the architecture of the encoder 420. Any circuit with an encoding function can be used as the encoder 420.

[0068] The decoder 430 decodes the response signal S_AK1 or the inquiry signal S_QY2. For example, when the control chip 400 is used as Figure 1 When the control chip 400 is used as the control chip 110, the decoder 430 decodes the response signal S_AK1 from a first external chip to generate a decoding result S_D1. In this example, the decoding result S_D1 represents the system voltage or the voltage upper limit value of the first external chip. Figure 1 When the control chip 120 is connected to the decoder 430, the decoder 430 decodes the query signal S_QY2 from a second external chip to generate a decoding result S_D2. The present invention does not limit the architecture of the decoder 430. Any circuit with a decoding function can be used as the decoder 430.

[0069] The control circuit 440 provides output information INF1 or INF2 and receives the decoding result S_D1 or S_D2. Figure 1 When the control chip 110 is connected to the control circuit 440 and the control circuit 440 operates in a compensation mode, the control circuit 440 generates output information INF1 to inquire about the system voltage of a first external chip. In this example, the control circuit 440 obtains the system voltage of the first external chip according to the decoding result S_D1. In another possible embodiment, when the control chip 400 is used as Figure 1 When the control chip 110 is connected to the control circuit 440 and the control circuit 440 operates in a setting mode, the control circuit 440 generates output information INF1 to inquire about the voltage upper limit value of the first external chip. In this example, the control circuit 440 learns the voltage upper limit value of the first external chip according to the decoding result S_D1. The control circuit 440 uses the voltage upper limit value of the first external chip as a protection point voltage value and stores the protection point voltage value in a storage circuit (not shown). The storage circuit may be located in the control circuit 440 or independent of the control circuit 440. The present invention does not limit the architecture of the control circuit 440. In one possible embodiment, the control circuit 440 is a micro control unit (MCU).

[0070] In some embodiments, when the control chip 400 is used as Figure 1 When the control chip 120 of the control chip 400 is decoded, the control chip 400 performs a detection operation or a notification operation according to the decoding result S_D1. In one possible embodiment, the control chip 400 detects the voltage value of the system voltage VSYS according to the decoding result S_D1, and generates output information INF2 according to the detection result. In another possible embodiment, the control chip 400 reads a value of a register (i.e., a voltage upper limit value) according to the decoding result S_D1. In this example, the control chip 400 generates information INF2 according to the value of the register.

[0071] In other embodiments, when the control chip 400 is used as Figure 1 When the control chip 110 is connected to the decoder 430, the decoder 430 decodes a request (not shown) from a first external chip to generate a decoding result. The control circuit 440 obtains a required voltage based on the decoding result. In this example, the control circuit 440 determines whether the required voltage required by the first external chip is greater than the protection point voltage value. When the required voltage is not greater than the protection point voltage value, the control circuit 440 sets the output voltage equal to the required voltage. However, when the required voltage is greater than the protection point voltage value, the control circuit 440 ignores the request of the first external chip. In one possible embodiment, the control circuit 440 does not adjust the output voltage VOUT.

[0072] In other embodiments, the control chip 400 further includes a power circuit 450. The power circuit 450 may provide an output voltage VOUT or receive a system voltage VSYS. Figure 1 When the control chip 400 is used as the control chip 110, the power circuit 450 generates the output voltage VOUT. In this example, the control circuit 440 commands the power circuit 450 to adjust the output voltage VOUT. In another possible embodiment, when the control chip 400 is used as the control chip 110, the power circuit 450 generates the output voltage VOUT. Figure 1 When the control chip 120 is connected to the power supply circuit 450, the power supply circuit 450 receives the system voltage VSYS. In this case, the power supply circuit 450 may convert the system voltage VSYS and provide the converted voltage to other circuits of the control chip 400 for use. In one possible embodiment, the control circuit 440 commands the power supply circuit 450 to detect the voltage value of the system voltage VSYS. In this case, the power supply circuit 450 has a voltage divider circuit (not shown). The voltage divider circuit processes the system voltage VSYS to generate a divided voltage (or a detection result). The control circuit 440 generates output information INF2 based on the divided voltage. The present invention does not limit the architecture of the power supply circuit 450. Any circuit that can provide power can be used as the power supply circuit 450. In other embodiments, the power supply circuit 450 has a voltage detector (not shown) to detect the voltage value of the output voltage VOUT or the system voltage VSYS.

[0073] In summary, since the control chip 110 or 400 compensates for the voltage drop caused by the connection line 130, it can ensure that the system voltage VSYS of the external chip (such as 120) is equal to the output voltage VOUT. In addition, the control chip 110 or 400 sets a protection point voltage value in advance. When the external chip (such as 120) issues a request to request the control chip 110 or 400 to increase the output voltage VOUT, or the power circuit 450 is abnormal and mistakenly increases the output voltage VOUT, the control chip 110 or 400 does not output an excessively large output voltage VOUT according to the protection point voltage value to prevent the external chip from being damaged.

[0074] The control method of the present invention, or a specific form or part thereof, may exist in the form of a program. The program may be stored in a physical medium, such as a floppy disk, a CD, a hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product not limited to an external form, wherein when the program is loaded and executed by a machine, such as a computer, the machine becomes a control chip for participating in the present invention. The program may also be transmitted through some transmission media, such as wires or cables, optical fibers, or any transmission mode, wherein when the program is received, loaded and executed by a machine, such as a computer, the machine becomes a control chip for participating in the present invention. When implemented in a general-purpose processing unit, the program combines with the processing unit to provide a unique device that operates similarly to an application-specific logic circuit.

[0075] Unless otherwise defined, all words (including technical and scientific words) herein are generally understood by those with ordinary knowledge in the technical field to which the present invention belongs. In addition, unless expressly indicated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in the relevant technical field, and should not be interpreted as an ideal state or overly formal tone. Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0076] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the definition of the claims.

Claims

1. A control chip, characterized in that: Supplying power to a powered device, and comprising: A connection port, comprising: A power pin for providing an output voltage to the powered device; a communication pin coupled to the power receiving device and providing an inquiry signal to the power receiving device according to a communication protocol, and receiving a response signal provided by the power receiving device; an encoder, encoding an inquiry information to generate the inquiry signal; a decoder, decoding the reply signal to generate a first decoding result; and a control circuit, providing the query information and operating in a compensation mode or a setting mode; in: In the compensation mode, the control circuit learns the voltage actually received by the power receiving device according to the first decoding result, and adjusts the output voltage according to the voltage actually received by the power receiving device; In the setting mode, the control circuit obtains a protection point voltage value of the powered device according to the first decoding result, and adjusts the output voltage according to the protection point voltage value to prevent the output voltage from being greater than the protection point voltage value.

2. The control chip according to claim 1, characterized in that: The connection port is coupled to the power receiving device via a connection line. When the connection line couples the connection port and the power receiving device, the control circuit sets the output voltage to be equal to an initial value.

3. The control chip according to claim 2, characterized in that: In the compensation mode, the control circuit determines whether the output voltage received by the power receiving device is equal to the initial value based on the first decoding result. When the output voltage received by the power receiving device is not equal to the initial value, the control circuit adjusts the output voltage so that the output voltage received by the power receiving device is equal to the initial value.

4. The control chip according to claim 1, characterized in that: In a normal mode, the communication pin receives a request from the powered device, the decoder decodes the request to generate a second decoding result, and the control circuit determines whether to adjust the output voltage according to the second decoding result.

5. The control chip according to claim 4, characterized in that: When the second decoding result requires the control circuit to provide a required voltage, and the required voltage is greater than the protection point voltage value, the control circuit does not adjust the output voltage.

6. The control chip according to claim 5, characterized in that: When the required voltage is less than the protection point voltage value, the control circuit sets the output voltage to be equal to the required voltage.

7. A control chip, characterized in that: include: A connection port, comprising: A power pin for receiving an output voltage from a power supply device; A communication pin coupled to the power supply device, and receiving an inquiry signal from the power supply device according to a communication protocol, and outputting a reply signal; a decoder, decoding the interrogation signal to generate a decoding result; a control circuit, performing a detection operation or a notification operation according to the decoding result, wherein when the control circuit performs the detection operation, the control circuit detects the output voltage to generate a detection result, and when the control circuit performs the notification operation, the control circuit provides a protection point voltage value; and An encoder encodes the detection result or the protection point voltage value to generate the reply signal.

8. The control chip according to claim 7, characterized in that: The communication protocol is a universal serial bus power transmission specification or a fusion fast charging standard specification.

9. A control method, characterized in that: include: Providing an output voltage to a powered device; sending an inquiry signal to the power receiving device; receiving a reply signal provided by the power receiving device; Execute a compensation operation or a setting operation according to the reply signal; The compensation operation adjusts the output voltage so that the output voltage received by the powered device is equal to an initial value, and the setting operation prevents the output voltage from being greater than a protection point voltage value.

10. A control method, characterized in that: include: Receiving an output voltage, and converting the output voltage into a system voltage; receiving an inquiry signal; According to the inquiry signal, a detection operation or a notification operation is performed to generate a reply signal; outputting the reply signal, in The detection operation includes: detecting the system voltage to generate a detection result; and According to the detection result, the reply signal is generated; the notification operation includes: Reading a protection point voltage value; and The reply signal is generated according to the protection point voltage value.

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