55nm CMOS (Complementary Metal Oxide Semiconductor) process SRAM (Static Random Access Memory) memory compiler Liberty file generation method based on neural network

Abstract

The invention discloses a 55nm CMOS (Complementary Metal Oxide Semiconductor) process SRAM (Static Random Access Memory) memory compiler Liberty file generation method based on a neural network, relates to an integrated circuit design technology, and provides a scheme aiming at the problems of insufficient precision and the like in the prior art. The method comprises the following steps: S1, collecting simulation data of a 55nm CMOS process SRAM; s2, adopting a multi-layer perceptron as a basic construction model structure; s3, performing multi-model parallel training by using the collected simulation data; s4, verifying and finely adjusting the trained model to obtain a final model; and S5, automatically generating a Liberty file by utilizing the final model. The method has the advantages that (1) the prediction precision is improved; (2) the data processing capability is enhanced; and (3) the model adaptability is improved.

Description

Technical Field

[0001] The invention relates to integrated circuit design technology, and in particular to a method for generating a Liberty file of a 55nm CMOS process SRAM memory compiler based on a neural network. Background Art

[0002] SRAM is a type of memory; SRAM memory compiler is used to batch generate SRAM array structure; Liberty file is used for Liberty file to describe the timing, power consumption and other electrical characteristics of SRAM in detail. This information is crucial for integrated circuit designers to understand the behavior of SRAM under different working conditions. For example, it contains key parameters such as read and write time, setup time, and hold time of SRAM under different voltages, temperatures, and process corners. Liberty file describes the timing, power consumption and other electrical characteristics of SRAM in detail. This information is crucial for integrated circuit designers to understand the behavior of SRAM under different working conditions. For example, it contains key parameters such as read and write time, setup time, and hold time of SRAM under different voltages, temperatures, and process corners.

[0003] In existing memory compiler technologies, common technical solutions include using linear interpolation algorithms to generate Liberty files. The advantages of this simple linear interpolation are simple calculation and easy implementation; it works well when dealing with linear or approximate linear relationships; and it has low requirements for computing resources. However, these methods have problems of insufficient precision and low adaptability. For example, linear interpolation algorithms are not accurate enough when dealing with complex nonlinear relationships. For high-performance memory in large-scale integrated circuits, existing methods cannot meet the increasing accuracy requirements. In terms of adaptability, it is difficult to dynamically optimize the algorithm according to different process nodes and design specification changes. As integrated circuit design moves towards smaller process nodes, especially in low-voltage SRAM designs that work in the near-threshold and sub-threshold voltage regions, these problems become more prominent. SRAM faces many challenges at low voltages, such as reduced static noise tolerance, reduced read and write stability, and increased impact of process deviations. These complex nonlinear relationships are difficult to accurately describe using simple linear interpolation methods [1].

[0004] With the innovation of SRAM design, in addition to the traditional 6-transistor SRAM cell, there are also 12-transistor SRAM cells, leakage current compensated current-type sense amplifiers, digital double replica bit line delay technology, etc. The traditional Liberty file generation method is difficult to accurately capture the characteristics of these new designs [2]. This not only affects the accuracy of timing analysis, but also may cause deviations in power consumption estimation, thereby affecting the optimization of the entire SoC design. Therefore, a new solution is urgently needed to overcome these shortcomings, improve the accuracy and efficiency of Liberty file generation, and enhance the adaptability of the memory compiler. As the complexity of integrated circuit design continues to increase, it is particularly important to develop an intelligent method that can accurately capture complex parameter relationships. This method should not only be able to handle nonlinear relationships, but also be able to adjust the model to adapt to different process nodes and design specifications.

[0005] [1] Li Xuan. Research on key modules of low voltage SRAM and compiler design[D]. University of Science and Technology of China. 2015.

[0006] [2] Zhang Zhongda. Design of low-power Single Port SRAM Compiler based on 14nm FinFET process[M]. Suzhou University. 2023. Summary of the invention

[0007] The purpose of the present invention is to provide a 55nm CMOS process SRAM memory compiler Liberty file generation method based on a neural network to solve the problems existing in the above-mentioned prior art.

[0008] The method for generating a Liberty file of a 55nm CMOS process SRAM memory compiler based on a neural network in the present invention comprises the following steps:

[0009] S1. Collect simulation data of 55nm CMOS process SRAM;

[0010] S2. Multilayer perceptron is used as the basic model structure;

[0011] S3. Use the collected simulation data to perform multi-model parallel training;

[0012] S4. Validate and fine-tune the trained model to obtain the final model;

[0013] S5. Automatically generate Liberty files using the final model.

[0014] The advantages of the 55nm CMOS process SRAM memory compiler Liberty file generation method based on neural network described in the present invention are: (1) Improving prediction accuracy: By using a deep neural network model to replace the traditional linear interpolation method, it is possible to more accurately capture complex nonlinear relationships and significantly improve the prediction accuracy of Liberty file parameters. On the existing extracted eigenvalues, the existing interpolation accuracy is about 5% and the neural network accuracy is about 2%. (2) Enhancing data processing capabilities: Adopting innovative data preprocessing methods, including data offset, logarithmic transformation and adaptive normalization, the model can effectively handle various data distributions, including negative values ​​and wide range data, thereby improving the stability and generalization ability of the model. (3) Improving model adaptability: By implementing a multi-model parallel training strategy, it is possible to train specialized models for different parameter ranges, greatly improving the adaptability to various memory designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the process of the method described in the present invention.

[0016] Figure 2 It is a structural schematic diagram of the model described in the present invention.

[0017] Figure 3 It is a fitted size distribution diagram after being processed using the method described in the present invention.

[0018] Figure 4 It is a fitting effect diagram after being processed by the method described in the present invention.

[0019] Figure 5 This is the fitting effect diagram after processing using traditional methods. DETAILED DESCRIPTION

[0020] like Figure 1 As shown, the method for generating Liberty files of a 55nm CMOS process SRAM memory compiler based on a neural network in the present invention comprises the following steps:

[0021] S1. Collect simulation data of 55nm CMOS process SRAM, such as Figure 3 As shown:

[0022] S11.Use the industry standard SPICE simulator to simulate under different process corners, temperatures and voltage conditions. The process corners include ss, tt, ff; the temperatures include -40℃, 25℃, 125℃; the voltages include 1.32V, 1.2V, 1.08V.

[0023] S12. Record key timing parameters and power consumption data. Timing parameters include but are not limited to: access time, setup time, and hold time; power consumption data includes dynamic power consumption and static power consumption.

[0024] S13. Normalize the collected simulation data so that the neural network can learn better.

[0025] Specifically, the normalization formula is as follows:

[0026]

[0027] Among them, ε is a small positive number used to prevent division by zero, and its value is preferably 1e-7; Z is the input data, including features and labels; s is the offset.

[0028] First, the input data Z is offset using a configurable offset s, which defaults to 1.0 to ensure that the offset data is positive. Then a logarithmic transformation is applied to the offset data to help handle a wide range of data distributions. Finally, the transformed data is normalized using the minimum-maximum normalization method.

[0029] S14. After normalization, the simulation data is sliced ​​for training. The function of slicing the dataset according to the label range is implemented, allowing flexible selection of labels in a specific range for training and testing. The dataset containing the features is usually a two-dimensional numpy array or a PyTorch tensor. A tuple is used to define the label range of interest. The labels that fall within the specified range are identified by a Boolean mask, and the sliced ​​data and labels are returned by applying the mask to the data and labels.

[0030] S2. Use multi-layer perceptron as the basic model structure:

[0031] Multilayer Perceptron (MLP) is a feedforward neural network consisting of multiple fully connected layers. In this design, MLP is selected for the Liberty file parameter prediction task mainly because of its strong nonlinear mapping ability. MLP is able to learn and represent complex nonlinear relationships, which is crucial for capturing the complex interactions between Liberty file parameters.

[0032] Structure Figure 2 As shown, it includes: input layer, hidden layer and output layer.

[0033] The input layer is used to input size parameters;

[0034] The hidden layer includes 3-4 hidden layers, each layer contains 4-32 neurons, and uses the ReLU function as the activation function;

[0035] The output layer uses a linear activation function to output various timing and power consumption parameters in the Liberty file.

[0036] S3. Use the collected simulation data for multi-model parallel training: divide the dataset into training set and test set; use Adam optimizer and mean square error MSE as the loss function; use early stopping method to prevent overfitting; use learning rate decay strategy to improve model convergence.

[0037] Train independent models for each label range and process multiple target labels in parallel. Each model is trained specifically for a specific label range, which allows the model to better capture specific patterns and relationships within that range. In terms of accuracy, by focusing on a smaller subset of data, each model can more accurately learn the data features within its specific range, thereby improving overall prediction accuracy. In terms of flexibility, the structure and parameters of each model can be adjusted according to the complexity of different label ranges to achieve more flexible modeling. Each model can be optimized independently according to different label values, making it easier to find the local optimal solution, which helps to improve overall performance.

[0038] S4. Verify and fine-tune the trained model to ensure the accuracy of the generated Liberty file: Compare the Liberty file generated by the model with the file generated by the traditional method. Figure 4 and Figure 5 If the deviation exceeds the preset range, the model is fine-tuned using new SPICE simulation data and the verification is repeated until the final model is obtained.

[0039] S5. Automatically generate Liberty files using the final model.

[0040] The present invention automatically generates the Liberty file of 55nm CMOS process SRAM by using deep learning technology, especially neural network model, and provides a novel and effective solution with broad application prospects, and provides new ideas for the development of semiconductor design automation field. The method not only significantly improves the efficiency and accuracy of Liberty file generation, but also opens up a new way for the optimization of SRAM compiler. Traditional Liberty file generation methods usually rely on a large number of SPICE simulations and lookup table interpolation, which is time-consuming and consumes a lot of computing resources. The present invention uses a neural network model to generate accurate Liberty file content in less time, greatly shortening the SRAM design cycle. The neural network model can capture the nonlinear relationship of SRAM characteristics, and can more accurately predict the timing and power consumption parameters under various working conditions compared to the traditional linear interpolation method. This helps to improve the reliability and performance of the overall chip design. Through continuous learning and updating, the method can quickly adapt to process changes and new SRAM architectures, and reduce the liberty file time of SRAM Macro under the new structure. This is of great value in the fast-iterative semiconductor industry.

[0041] For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all of these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims

1. A method for generating Liberty files for a 55nm CMOS process SRAM memory compiler based on a neural network, characterized in that: The following steps are involved: S1. Collect simulation data of 55nm CMOS process SRAM; S2. Multilayer perceptron is used as the basic model structure; S3. Use the collected simulation data to perform multi-model parallel training; S4. Validate and fine-tune the trained model to obtain the final model; S5. Automatically generate Liberty files using the final model.

2. The method for generating Liberty files of a 55nm CMOS process SRAM memory compiler based on a neural network according to claim 1, characterized in that: The step S1 specifically includes the following sub-steps: S11. Use a SPICE simulator to perform simulation under preset process corner, temperature and voltage conditions; S12. Record key timing parameters and power consumption data; S13. normalizing the collected simulation data; S14. After normalization, the simulation data is sliced.

3. The method for generating Liberty files of a 55nm CMOS process SRAM memory compiler based on a neural network according to claim 1, characterized in that: The process angles include ss, tt, and ff; the temperatures include -40°C, 25°C, and 125°C; and the voltages include 1.32V, 1.2V, and 1.08V.

4. The method for generating Liberty files of a 55nm CMOS process SRAM memory compiler based on a neural network according to claim 1, characterized in that: The timing parameters include access time, setup time, and hold time; the power consumption data includes dynamic power consumption and static power consumption.

5. The method for generating Liberty files of a 55nm CMOS process SRAM memory compiler based on a neural network according to claim 1, characterized in that: In the sub-step S13, the normalization processing formula is as follows: Among them, ε is a positive decimal; Z is the input data, including features and labels; s is the offset; First, the input data Z is offset using a configurable offset s to ensure that the offset data is positive. Then a logarithmic transformation is applied to the offset data. Finally, the transformed data is normalized using the min-max normalization method.

6. The method for generating Liberty files of a 55nm CMOS process SRAM memory compiler based on a neural network according to claim 5, characterized in that: The value of ε is 1e-7; the value of the offset s is 1.

0.

7. The method for generating Liberty files of a 55nm CMOS process SRAM memory compiler based on a neural network according to claim 1, characterized in that: In step S3, the Adam optimizer and mean square error (MSE) are used as the loss function; the early stopping method is used to prevent overfitting; and the learning rate decay strategy is used to improve the convergence of the model; Train separate models for each label range and process multiple target labels in parallel.

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