Compiling method and device and electronic equipment

Abstract

Embodiments of the invention provide a compiling method and apparatus, and an electronic device. The method comprises the steps of obtaining a first directed acyclic graph corresponding to a source program code; traversing a vector selection node in the first directed acyclic graph, and determining the vector selection node as a first node; analyzing the dependency relationship of the three operands of each first node in the first directed acyclic graph, and generating a fusion node corresponding to the first node; and updating the first directed acyclic graph according to the fusion nodes corresponding to the first nodes meeting the fusion conditions in the first directed acyclic graph to obtain a target directed acyclic graph so as to generate an executable program corresponding to the to-be-processed service. According to the embodiment of the invention, the compilation performance of the compiler is improved, and the running speed of the subsequently generated executable program is increased.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a compiling method, device and electronic equipment. Background Art

[0002] A compiler (or compiler) is a program that translates a source program written in a high-level programming language into an equivalent machine language format. During the compilation process, the compiler can merge multiple nodes (for example, data nodes, operation nodes, or other undefined nodes) into an equivalent node by node fusion to increase the running speed of the executable program generated subsequently.

[0003] In the related art, the node fusion method is relatively simple. For some complex scenarios, such as complex scenarios where nested ternary operations are used to perform conditional operations on vector data, the compiler's fusion capability is limited and the optimization effect of the node fusion optimization operation is poor. Summary of the invention

[0004] The embodiments of the present invention provide a compilation method, device and electronic device, which can solve the problem that the fusion capability of the compiler is limited and the optimization effect of the node fusion optimization operation is poor in the related art.

[0005] In order to solve the above problem, an embodiment of the present invention discloses a compilation method, which is applied to a compiler and includes:

[0006] Obtaining a first directed acyclic graph corresponding to a source program code; the source program code is a high-level language code corresponding to the business to be processed;

[0007] Traversing the vector selection nodes in the first directed acyclic graph, and determining the vector selection node as the first node;

[0008] Analyze the dependency relationship of the three operands of each of the first nodes in the first directed acyclic graph to generate a fusion node corresponding to the first node; the fusion node is functionally equivalent to each target node involved in the fusion;

[0009] According to the fusion nodes corresponding to the first nodes in the first directed acyclic graph that meet the fusion conditions, the first directed acyclic graph is updated to obtain a target directed acyclic graph to generate an executable program corresponding to the business to be processed; the fusion conditions are determined respectively according to the cost values ​​corresponding to the fusion nodes.

[0010] On the other hand, an embodiment of the present invention discloses a compiling device, which is applied to a compiler, and includes:

[0011] An acquisition module, used to acquire a first directed acyclic graph corresponding to a source program code; the source program code is a high-level language code corresponding to the business to be processed;

[0012] A first determining module, configured to traverse the vector selection nodes in the first directed acyclic graph and determine the vector selection nodes as first nodes;

[0013] A node fusion module, used for analyzing the dependency relationship of the three operands of each of the first nodes in the first directed acyclic graph, and generating a fusion node corresponding to the first node; the fusion node is functionally equivalent to each target node involved in the fusion;

[0014] An update module is used to update the first directed acyclic graph according to the fusion nodes corresponding to each first node that meets the fusion conditions in the first directed acyclic graph, obtain a target directed acyclic graph, and generate an executable program corresponding to the business to be processed; the fusion conditions are determined respectively according to the cost values ​​corresponding to each of the fusion nodes.

[0015] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to perform the aforementioned compilation method.

[0016] The embodiment of the present invention further discloses a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned compiling method.

[0017] The embodiments of the present invention include the following advantages:

[0018] The embodiment of the present invention provides a compilation method, by analyzing the first directed acyclic graph corresponding to the source program code, traversing all vector selection nodes in the first directed acyclic graph, analyzing the dependency relationship of the three operands of each vector selection node in the first directed acyclic graph, generating fusion nodes corresponding to each vector selection node respectively, and further determining the vector selection nodes that meet the fusion condition according to the cost value corresponding to each fusion node, and performing node fusion on the first directed acyclic graph based on the fusion nodes corresponding to each first node that meets the fusion condition in the first directed acyclic graph. The embodiment of the present invention can perform node fusion on multiple vector selection nodes in complex scenarios such as nested ternary operations, fuse multiple target nodes corresponding to the vector selection nodes into one node, and judge whether the vector selection nodes meet the fusion condition based on the cost value of the fusion node, and update the directed acyclic graph only when the vector selection node meets the fusion condition, thereby improving the optimization effect of the node fusion operation while ensuring that the cost value of the fused target directed acyclic graph is less than the cost value of the first directed acyclic graph, which is conducive to improving the compilation performance of the compiler and improving the running speed of the executable program generated subsequently. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments of the present invention are briefly introduced below.

[0020] Figure 1 is a flowchart of steps of an embodiment of a compiling method of the present invention;

[0021] Figure 2 is a degradation flow chart of a scalar data type of the present invention;

[0022] Figure 3 is a directed acyclic graph before node fusion of the present invention;

[0023] Figure 4 It is a directed acyclic graph after node fusion of the present invention;

[0024] Figure 5 is a structural block diagram of an embodiment of a compiling device of the present invention;

[0025] Figure 6 It is a structural block diagram of an electronic device for compiling provided by an example of the present invention. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0027] Method Embodiment

[0028] Reference Figure 1 , shows a flowchart of a compilation method embodiment of the present invention, the method is applied to a compiler, and the method may specifically include the following steps:

[0029] Step 101: Obtain a first directed acyclic graph corresponding to a source program code; the source program code is a high-level language code corresponding to the business to be processed;

[0030] Step 102: traverse the vector selection nodes in the first directed acyclic graph, and determine the vector selection node as the first node;

[0031] Step 103: Analyze the dependency relationship of the three operands of each of the first nodes in the first directed acyclic graph to generate a fusion node corresponding to the first node; the fusion node is functionally equivalent to each target node involved in the fusion;

[0032] Step 104: Update the first directed acyclic graph according to the fusion nodes corresponding to the first nodes that meet the fusion conditions in the first directed acyclic graph to obtain a target directed acyclic graph to generate an executable program corresponding to the business to be processed; the fusion conditions are determined respectively according to the cost values ​​corresponding to the fusion nodes.

[0033] The compilation method provided in the embodiment of the present invention can be applied to a compiler. According to different tasks to be completed, the components of the compiler can be divided into the front end, optimizer and back end. The front end mainly refers to the part related to the source language, including lexical analysis, syntax analysis, semantic analysis and intermediate representation generation. The optimizer is mainly responsible for making various conversion attempts to improve the execution time of the code, such as eliminating redundant calculations. The optimizer is usually independent of the source language, target machine or target platform. The back end mainly refers to the part related to the target machine or target platform, including code optimization, target code generation, etc. This "front end + optimizer + back end" structure can support multiple programming languages ​​(such as C language, Fortan, Ada) as source languages, and support multiple target architectures (such as X86, PowerPC, ARM). For example, C language can be used as source code input, and the code generator of X86 architecture can be selected as the back end. If you want to use a new programming language, you don't need to change the optimizer and the back end, just write the front end of the language. Among them, the compiler in the embodiment of the present invention can be a low level virtual machine (LLVM) compiler.

[0034] It should be noted that the source code in the embodiments of the present invention may refer to a user-readable text file that is not compiled and written in accordance with certain programming language specifications. The source code is written in a high-level language, for example, a high-level language such as C language or C++ may be used. The source code is a high-level language code corresponding to the business to be processed, and the specific content can be determined by the developer according to the actual content of the project.

[0035] The compilation method provided by the embodiment of the present invention can compile source program code containing at least one of a ternary operator and a nested ternary operator. Among them, the ternary operator is also called a conditional operator, which is an important component of computer language (C language, C++, etc.). It is the only operator with 3 operands. For the conditional expression "b?x:y", the condition b is calculated first, and then a judgment is made; if the value of b is true, the value of x is calculated, and the result of the operation is the value of x; otherwise, the value of y is calculated, and the result of the operation is the value of y. When there are multiple conditions, multi-condition judgment can be achieved by nesting ternary operators.

[0036] In the process of compiling source code written in a high-level language to form an equivalent executable program in machine language format, when nested ternary operations are used to perform conditional vector data sign bit conversion operations, multiple nodes such as two comparison operations and two selection operations will be generated during the compilation process. Both comparison nodes and selection nodes are high-cost operation nodes, which correspond to complex and expensive scenarios. The more selection nodes and comparison nodes are generated, the more complex the corresponding semantic graph will be during the compilation process, and the lower the compilation efficiency will be.

[0037] When optimizing nested ternary operations, the related technology only optimizes one selection operation and converts only one selection operation into a node with a lower cost. The semantic scope of the optimization is small and the number of nodes used cannot be effectively reduced.

[0038] In addition, related technologies will also add cost model definitions for some vector data type nodes in the architecture backend of the LLVM compiler, and use the cost model to provide architecture-specific information to guide node selection for loop vectorization and superword parallel vectorization. However, only adding architecture-related cost models can only control part of the conversion process of loop vectorization and superword parallel vectorization, and cannot optimize the entire conversion process; moreover, the cost model has insufficient processing capabilities for complex scenarios such as nested ternary operations, and has limited optimization capabilities for functional modules composed of multiple nodes, and cannot effectively handle node optimization in some complex scenarios, such as optimizing scenarios where nested ternary operations are used to perform conditional operations on vector data.

[0039] The embodiment of the present invention can analyze the first directed acyclic graph corresponding to the source program code, traverse all vector selection nodes in the first directed acyclic graph, analyze the dependency relationship of the three operands of each vector selection node in the first directed acyclic graph, respectively generate fusion nodes corresponding to each vector selection node, and further determine the vector selection nodes that meet the fusion conditions according to the cost values ​​corresponding to each fusion node, and perform node fusion on the first directed acyclic graph based on the fusion nodes corresponding to each first node that meets the fusion conditions in the first directed acyclic graph. The embodiment of the present invention can optimize all vector selection nodes that meet the fusion conditions, that is, optimize multiple selection operations, expand the semantic scope of optimization, and can effectively reduce the number of nodes in the operation due to the conversion of vector data sign bits when using nested ternary operations for conditional operations, thereby reducing the compilation complexity and helping to improve the compilation performance of the compiler. Furthermore, the embodiments of the present invention can analyze various parts of the source program, perform dependency analysis on various vector selection nodes, and combine the cost value of the fusion node to determine the vector selection nodes that meet the fusion conditions and optimize them, thereby enabling the compiler to be applicable to complex scenarios, such as scenarios where nested ternary operations are used to perform conditional operations on vector data, thereby improving the optimization of functional modules composed of multiple nodes.

[0040] Specifically, in an embodiment of the present invention, the first directed acyclic graph corresponding to the source program code is first analyzed. It should be noted that a directed acyclic graph (DAG) is a directed graph without loops, which is used to describe the process of an engineering or system. In an embodiment of the present invention, the source program code can be preprocessed based on a cost model, and the first directed acyclic graph is determined according to the principle of minimum cost value. Among them, the preprocessing can include compilation operations, vectorization processing operations, etc., and the vectorization processing can include loop vectorization (Loop Vectorization), superword-level parallelism vectorization (Superword-Level Parallelism Vectorization, also known as Basic Block Vectorization), etc. The vectorization processing operation can be completed by the common layer of the compiler. The cost model is related to the compiler's compilation architecture and is used to describe the cost of architecture-related nodes and architecture-independent nodes. It should be noted that the cost of a node is measured by the clock cycle consumed when the operation corresponding to the node is executed; the longer the clock cycle consumed when the operation corresponding to the node is executed, the higher the cost of the node. Exemplarily, a cost model can be set based on the characteristics of the compiler architecture corresponding to the compiler, so as to use the cost model to guide the vectorization processing operation for the source program code based on the information specific to the compiler architecture, so as to pass the global compilation information specific to the compiler architecture to the compiler common layer. The compiler's compilation architecture can be related to the processor architecture, and the processor architecture can be a reduced instruction set computer (RISC), a complex instruction set computer (CISC), etc. The directed acyclic graph is constructed by the back end of the compiler according to the intermediate representation of the source program code. Exemplarily, the back end of the compiler will sequentially traverse each statement in the intermediate representation and generate multiple DAG graphs. The cost value of the first directed acyclic graph determined according to the minimum cost principle is the smallest. Among them, the intermediate representation can also be called an intermediate language or intermediate code (IR), such as LLVM IR. The intermediate representation is a notation system with a short structure and clear meaning. The complexity of this notation system is between the source program language and the machine language. The compiler front end analyzes the source program code, converts the source program code into an intermediate representation and passes it to the compiler back end, which translates the intermediate representation into target code.

[0041] Further, before obtaining the first directed acyclic graph of the source program code, the compiler front end can analyze the compilation command line input by the user to determine whether the parameters passed in by the user through the compilation command line indicate to turn on 128-bit vectors or turn on 128-bit vectors and 256-bit vectors at the same time. The compiler front end adds the analysis results to the intermediate representation (such as LLVMIR) and passes the intermediate representation to the compiler back end. It should be noted that the compiler defaults to using only scalar modules for compilation, that is, the compiled instructions are all scalar instructions. "Turn on 128-bit vectors" means that the corresponding vector module in the compiler is turned on for compilation. After the vector module is turned on for compilation, if the program can be optimized using vectors, the compiler will generate vector instructions. At this time, the operation object in the command line of the source program code is not necessarily 128-bit vector data, but can also be scalar data. But at this time, the compiler will try to convert scalar data to vector data, that is, automatic vectorization.

[0042] The compiler backend makes a judgment based on the information transmitted by the frontend. If the user has enabled 128-bit vectors or 256-bit vectors, the intermediate code output by the compiler frontend is vectorized, and based on the code model, the cost values ​​of each directed acyclic graph generated during the vectorization process are recorded, and the directed acyclic graph with the smallest cost value is determined as the first directed acyclic graph. If it is not enabled, the subsequent processes and degradation steps related to the vector function module will not be executed, and only the degradation process of the scalar data type will be executed.

[0043] The function of the vector select node (VSELECT) is to select two vector operands (the second and third operands of the node) using a vector condition (the first operand of the node) and return a result of vector data type. The vector elements in the result may come from the first operand or the second operand depending on the condition. The vector select node requires that all selected vector data types have the same length.

[0044] In the embodiment of the present invention, the vector selection node in the first directed acyclic graph can be determined as the first node, also known as the top node. It is understandable that if the vector selection node does not exist in the first directed acyclic graph, there is no need to perform a node fusion operation on the first directed acyclic graph.

[0045] For each first node, the dependence relationship of the operands of the first node in the first directed acyclic graph is analyzed, and a fusion node corresponding to the first node is generated.

[0046] As an example, the node that has a dependency relationship with the operand of the first node may include a node that has a data flow dependency relationship with the input data flow node (referred to as the second node) of the operand of the first node, and a node that has a control flow dependency relationship with the second node. Among them, the node that has a data flow dependency relationship with the second node may include a node that has a flow dependency, anti-dependency, output dependency, input dependency, etc. relationship with the second node. Exemplarily, in the first directed acyclic graph, if for node m and node n, there is a control path from node m to node n, node n is the post-dominant node of each node on the path except node m, and node n is not the post-dominant node of node m, then it can be considered that node n is control-dependent on node m.

[0047] In the implementation of the present invention, if the second node and each node that has a dependent relationship with the second node meet the first preset condition, the first node, the second node and each node that has a dependent relationship with the second node can be fused into an efficient node, that is, the fused node in the present invention, thereby reducing the number of nodes in the first directed acyclic graph. Among them, the first preset condition may be that the second node and each node having a dependent relationship with the second node meet the preset requirements, for example, the node attribute of the second node is a comparison node (SETCC) or a vector selection node, or, the second node is a node used to construct an all-zero vector, or, the node having a dependent relationship with the second node is an arithmetic operation node (ADD or SUB), or, in the case where the second node is a node used to construct an all-zero vector, the node having a dependent relationship with the second node is also a node used to construct an all-zero vector; or, in the case where the node attributes of the second node and the node having a dependent relationship with the second node are target node attributes, the second node and each node having a dependent relationship with the second node have a designated node whose conditional code is a preset conditional code; or, in the case where the node attributes of the second node and the node having a dependent relationship with the second node are target node attributes, the second node and each node having a dependent relationship with the second node have a designated node whose operand data type is a vector data type, and so on.

[0048] It should be noted that the fusion node in the present invention is equivalent to the node functions of each target node participating in the fusion. Specifically, the semantics represented by the fusion node is the same as the semantics represented by each target node participating in the fusion by performing semantic analysis on the first directed acyclic graph. Among them, each target node participating in the fusion may include a first node, a second node, a node having a dependency relationship with the second node, and so on. Specifically, it can be determined based on the functions and node attributes of the first node, the second node, and each node having a dependency relationship with the second node. The embodiment of the present invention does not specifically limit the target node, as long as the node functions of the fusion node and each target node participating in the fusion are equivalent.

[0049] Further, in order to improve the compilation performance of the compiler and ensure the optimization effect of the node fusion operation, it is possible to judge whether the first node meets the fusion condition, and only optimize the first node that meets the fusion condition. Among them, the fusion condition can be determined according to the cost value corresponding to each fusion node. Exemplarily, the cost value of the fusion node can be analyzed. If the cost value of the fusion node corresponding to the first node is less than the preset threshold, it can be considered that the first node meets the fusion condition. Then, the first directed acyclic graph is updated according to the fusion node corresponding to each first node that meets the fusion condition, ensuring that the cost value of the target directed acyclic graph obtained after the node fusion is less than the cost value of the first directed acyclic graph before the node fusion, thereby improving the compilation performance of the compiler and reducing the running time of the executable program finally generated. Among them, the preset threshold can be the sum of the cost values ​​of each target node participating in the fusion in the first directed acyclic graph, or it can be data set by the user based on the expected cost value, which is not specifically limited in the embodiment of the present invention.

[0050] Furthermore, the compiler can compile the downgraded target directed acyclic graph to generate an executable program corresponding to the service to be processed. After obtaining the executable program, the target platform can implement the corresponding service to be processed according to the executable program.

[0051] The compilation method provided by the embodiment of the present invention can perform node fusion on multiple vector selection nodes in a complex scene, fuse multiple target nodes corresponding to the vector selection node into one node, and judge whether the vector selection node meets the fusion condition based on the cost value of the fused node. The directed acyclic graph is updated only when the vector selection node meets the fusion condition, thereby improving the optimization effect of the node fusion operation while ensuring that the cost value of the fused target directed acyclic graph is less than the cost value of the first directed acyclic graph, which is beneficial to improving the compilation performance of the compiler and improving the running speed of the executable program.

[0052] Optionally, the step 103 of analyzing the dependency relationship of the three operands of each of the first nodes in the first directed acyclic graph to generate a fusion node corresponding to the first node includes:

[0053] Step S11: for each first node, determine a second node according to the data flow dependency in the first directed acyclic graph; the second node is an input data flow node of the three operands;

[0054] Step S12: Generate a fusion node corresponding to the first node according to the node attributes of the second node and the nodes having a dependency relationship with the second node.

[0055] The vector selection node includes three operands. In an embodiment of the present invention, the input data flow node of the three operands of the first node can be determined as the second node according to the data flow dependency in the first directed acyclic graph, and a fusion node corresponding to the first node is generated according to the node attributes of the second node and each node in the first directed acyclic graph that has a dependency relationship with the second node.

[0056] The node having a data flow dependency relationship with the second node may include a node having a flow dependency, anti-dependency, output dependency, input dependency, etc. relationship with the second node. Exemplarily, in the first directed acyclic graph, if for node m and node n, there is a control path from node m to node n, node n is the post-dominant node of each node on the path except node m, and node n is not the post-dominant node of node m, then it can be considered that node n is control-dependent on node m.

[0057] The directed acyclic graph includes attribute characteristics of each node, such as node attributes, each operand of the node, operand attributes, operand type, etc. Based on the attribute characteristics of the second node and each node having a dependency relationship with the second node, a fusion node corresponding to the first node can be generated. Exemplarily, when the attribute characteristics of the second node and each node having a dependency relationship with the second node meet preset requirements, the first node, the second node, and each node having a dependency relationship with the second node can be fused into an efficient node, that is, the fusion node in the present invention, thereby reducing the number of nodes in the first directed acyclic graph.

[0058] Exemplarily, the second node and each node having a dependent relationship with the second node meet preset requirements, which may include at least one of the following:

[0059] The node attribute of the second node is a comparison node (SETCC) or a vector selection node;

[0060] The operand attribute of the second node is a node used to construct an all-zero vector;

[0061] The operand type of the node that has a dependency relationship with the second node is an arithmetic operation node (ADD or SUB);

[0062] In the case where the operand attribute of the second node is a node for constructing an all-zero vector, the operand attribute of the node having a dependency relationship with the second node is also a node for constructing an all-zero vector;

[0063] In the case where the node attributes of the second node and the nodes having a dependency relationship with the second node are target node attributes, there is a designated node whose condition code is a preset condition code among the second node and the nodes having a dependency relationship with the second node;

[0064] When the node attributes of the second node and the nodes having a dependency relationship with the second node are target node attributes, there is a designated node whose operand data type is a vector data type in the second node and each node having a dependency relationship with the second node.

[0065] In an optional embodiment of the present invention, the step S12 of generating a fusion node corresponding to the first node according to the node attribute of the second node and each node having a dependency relationship with the second node includes:

[0066] Sub-step S121: determining the first node as a top-level node, and when the input data flow node T0 of the first operand of the top-level node is a comparison node, and the input data flow node T2 of the third operand of the top-level node is a vector selection node, performing architecture analysis on the second node and each node having a dependency relationship with the second node, to obtain attribute characteristics of the specified node;

[0067] Sub-step S122: when the attribute characteristics of the designated node meet preset requirements, generate the fused node according to the second node and each node having a dependency relationship with the second node.

[0068] In an embodiment of the present invention, the first node, that is, the vector selection node in the first directed acyclic graph, can be used as the top-level node, and the second node can be further obtained according to the data flow dependency in the first directed acyclic graph. In an embodiment of the present invention, the second node can include input data flow nodes of three operands of the top-level node, representing three operands in the ternary operation, wherein the input data flow node of the first operand of the top-level node can be recorded as node T0, the input data flow node of the second operand can be recorded as node T1, and the input data flow node of the third operand can be recorded as T2.

[0069] The directed acyclic graph contains the attribute characteristics of each node, such as node attributes, each operand of the node, operand attributes, operand type, etc. Based on the attribute characteristics of the node, it is possible to determine whether the node meets the preset requirements. Specifically, the input data flow nodes of each operand of the top node can be analyzed first to represent the compilation process of the three operands in the ternary operation. If the node T0 is a comparison node (SETCC) and the node T2 is a vector selection node, the first specified node can be further analyzed, and a fusion node is generated when the attribute characteristics of the first specified node meet the preset requirements. Among them, the return value of the comparison node is the result of the comparison, the operands involved in the comparison are the 0th and 1st operands of the node, and the comparison condition is the second operand of the node. If the operand of the node is a scalar data type, the return value of the comparison node is a Boolean type. If the operand of the node is a vector type, the return value of the comparison node is a vector data type, and the vector element represents the result of the comparison.

[0070] The designated node can be determined according to the actual node fusion requirements. Similarly, the preset requirement can be determined according to the nodes included in the first designated node and the actual node fusion requirements. For example, the designated node can include the input data flow node of the operand of node T2, and the preset requirement can be that the input data flow node of the operand of node T2 is an arithmetic operation node (such as SUB); or, the first designated node can include the top-level node and the three operands of the top-level node, namely nodes T0, T1 and T2, and the preset requirement can be that the designated node is a node related to vector data operation, such as a vector selection node, a node for constructing an all-zero vector, and so on.

[0071] It should be noted that, in an embodiment of the present invention, if node T0 is not a comparison node, or node T2 is not a vector selection node, the next vector selection node in the first directed acyclic graph can be searched for, and the traversed vector selection node can be used as a new top-level node to continue the subsequent processing until all the vector selection nodes in the first directed acyclic graph are traversed.

[0072] Further, before analyzing the first directed acyclic graph, it can be determined whether the first directed acyclic graph has been type-legalized. If the first directed acyclic graph has not been type-legalized, the first directed acyclic graph can be subjected to a type-legalization process of the compiler's common layer. Exemplarily, it can be determined whether the first directed acyclic graph is a type-legalized DAG graph based on information of the compiler's common layer.

[0073] Among them, the information of the compiler common layer refers to the information of the DAG combiner (DAG CombinerInformation), which is used to determine at which stage of the DAG merge the current DAG graph is located. Specifically, it may include information used to indicate whether the current DAG graph is a DAG graph before type legalization, whether the current DAG graph is a DAG graph before operation legalization, whether the current DAG graph is a legalized DAG graph, the merging level of the current DAG graph, and the like.

[0074] Optionally, the designated node includes a first designated node and a second designated node; when the attribute characteristics of the designated node meet preset requirements, generating a fusion node according to the second node and each node having a dependency relationship with the second node includes:

[0075] Step S21: when the node attribute of the first designated node meets the first target requirement, obtain the first condition code of the node T0 and the second condition code of the input data flow node T20 of the first operand of the node T2;

[0076] Step S22: When the first condition code and the second condition code satisfy a second preset condition, perform architecture analysis on the second node and each node having a dependency relationship with the second node to obtain a data type of a destination operand of the second designated node;

[0077] Step S23: When the data type of the destination operand of the second designated node meets the second target requirement, generate the fusion node according to the second node and each node having a dependency relationship with the second node.

[0078] In an embodiment of the present invention, the node attribute of the first designated node, the conditional codes of the node T0 and the node T2, and the data type of the destination operand of the second designated node can be analyzed. If the node attribute of the first designated node meets the first target requirement, and the conditional codes of the node T0 and the node T2 meet the preset condition, and the data type of the destination operand of the second designated node meets the second target requirement, it can be determined that the attribute characteristics of the designated node meet the preset requirement, and then the fusion node is generated.

[0079] The condition code is used to indicate the condition that the node return value is "true". The first target requirement, the second preset condition and the second target requirement in the embodiment of the present invention can be set according to the specific node fusion requirements.

[0080] Optionally, the first designated node includes the following items:

[0081] An input data flow node T20 of the first operand of the node T2;

[0082] An input data flow node T21 of the second operand of the node T2;

[0083] An input data flow node T1 of the second operand of the top-level node;

[0084] An input data flow node T01 of the second operand of the node T0;

[0085] An input data flow node T201 of the second operand of the node T20;

[0086] The first operand of the node T21 is the input data flow node T210.

[0087] The method further comprises:

[0088] When the node attributes of the node T20 and the node T21 satisfy the first target rule, and the node T1, the node T01, the node T201, and the node T210 satisfy the second target rule, it is determined that the node attribute of the first designated node satisfies the first target requirement.

[0089] Optionally, the first target rule includes: the node T20 is a comparison node, and the node T21 is a subtraction operation node.

[0090] The second target rule includes: operand attributes of the node T1, the node T01, the node T201 and the node T210 are all nodes used to construct an all-zero vector.

[0091] The subtraction operation node (SUB) represents the subtraction of the first operand from the second operand, and returns the result of the subtraction. The data type of the operand of the SUB node can be a scalar data type or a vector data type, but the data type of the operands of the same node must be the same.

[0092] If a node is a node for constructing vector data, that is, a build_vector node, and the operands of the node are all 0, then the node can be considered to be a node for constructing an all-zero vector. Among them, the role of the build_vector node is to construct vector data through scalar data, and the returned result must be a vector data type. In an embodiment of the present invention, if node T1, node T01, node T201, and node T210 are all build_vector nodes, and the operands of these nodes are all 0, it can be considered that node T1, node T01, node T201, and node T210 are all nodes for constructing an all-zero vector, that is, the second target rule is met.

[0093] Optionally, the second designated node includes the following items:

[0094] The top-level node;

[0095] An input data flow node T1 of the second operand of the top-level node;

[0096] The node T2;

[0097] An input data flow node T21 of the second operand of the node T2;

[0098] An input data flow node T22 of the third operand of the node T2;

[0099] The node T0;

[0100] The first operand of the node T2 is the input data flow node T20.

[0101] The method further comprises:

[0102] When the data types of the destination operands of the top-level node, the node T1, the node T2, the node T21 and the node T22 satisfy the third target rule, and the data types of the destination operands of the node T0 and the node T20 satisfy the fourth target rule, it is determined that the data type of the destination operand of the second designated node satisfies the second target requirement.

[0103] Optionally, the third target rule includes: data types of destination operands of the top-level node, the node T1, the node T2, the node T21 and the node T22 are the same and are all vector data types.

[0104] Among them, if the destination operand is in the form of "v*i*", it can be considered that the data type of the destination operand is a vector data type. Among them, "v" indicates that the operand is vector data, the "*" after "v" indicates the number of scalar elements contained in the vector data, "i" indicates that the data type of the scalar element is an integer type, and the "*" after "i" indicates the size of the scalar element. Exemplarily, if an operand is "v32i8", it means that the operand is a vector type and contains 32 scalar elements, the data type of these scalar elements is an integer type, and the size of the scalar element is 8 bytes. In an embodiment of the present invention, only when the destination operands of the top-level node, node T1, node T2, node T21 and node T22 are all in the form of "v*i*", and the contents of the "*" part are exactly the same, for example, they are all "v32i8", the data type of the destination operation data of these nodes is considered to meet the third target rule.

[0105] The fourth target rule includes: the data types of the destination operands of the node T0 and the node T20 are the same and are both vector data types, and the data types of the data elements constituting the destination operands of the node T0 and the node T20 are both Boolean types.

[0106] In an embodiment of the present invention, the fourth target rule may also be: the data types of the destination operands of the node T0 and the node T20 are the same and are both vector data types, and the data types of the data elements constituting the destination operands of the node T0 and the node T20 are both i1.

[0107] The data type i1 indicates that the size of the data element is 1 bit. For scalar data, the size of the Boolean data element is the i1 data type. In LLVM, you can determine the type size of the current operand by calling multiple interfaces, such as the getValueSizeInBits() interface. If the return value of the interface is 1, it means that the data type is the i1 data type.

[0108] Optionally, the second preset condition includes: the first condition code is used to indicate that the condition for returning the correct value is that the values ​​of the two compared operands are equal, and the second condition code is used to indicate that the condition for returning the correct value is that the first operand is less than the second operand.

[0109] In an embodiment of the present invention, the second preset condition may be: the first condition code of node T0 is SETEQ, and the second condition code of node T2 is SETLT. SETEQ means: if the values ​​of the two compared operands are equal, true is returned. SETLT means: if the first operand of the node is less than the second operand, true is returned.

[0110] In an optional embodiment of the present invention, generating a fusion node corresponding to the first node includes:

[0111] Step S31, obtaining the data type of the destination operand of the first node and the node T0 of the first operand of the first node;

[0112] Step S32: Generate a fusion node according to the data types of the destination operands of the first node and the node T0.

[0113] In an embodiment of the present invention, a fusion node can be generated according to the data types of the destination operands of the first node and the node T0. It can be understood that the fusion node in the embodiment of the present invention is related to the architecture and is functionally equivalent to the nodes of each target node involved in the fusion. Among them, the way to generate the fusion node can be to add code in the compiler to convert multiple nodes into functionally equivalent fusion nodes.

[0114] After the fusion node is generated, each target node participating in the fusion in the first directed acyclic graph can be replaced with the fusion node to obtain the target directed acyclic graph after the node fusion. For example, a new fusion node can be created by writing code, and the input data stream and output data stream of the combination of multiple target nodes can be handed over to the newly created fusion node, and then useless nodes can be deleted from the first directed acyclic graph to obtain the target directed acyclic graph.

[0115] Optionally, the method further comprises:

[0116] Step S41, calculating the sum of the cost values ​​of the target nodes and the cost value of the fusion node based on the cost model;

[0117] Step S42: When the cost value of the fused node is less than the sum of the cost values ​​of the target nodes, determine that the first node meets the fusion condition.

[0118] In an embodiment of the present invention, the preset threshold value may be the sum of the cost values ​​of each target node involved in the fusion. The cost value of the fused node and the sum of the cost values ​​of each target node are calculated based on the cost model. If the cost value of the fused node is greater than or equal to the sum of the cost values ​​of each target node, it means that this node fusion operation cannot reduce the running time of the executable program finally generated, and the improvement of the compilation performance of the compiler is limited. Therefore, the first directed acyclic graph may not be updated, that is, the node fusion operation is not performed. If the cost value of the fused node is less than the sum of the cost values ​​of each target node, the first directed acyclic graph is updated based on the fused node, thereby improving the compilation performance of the compiler and reducing the running time of the executable program finally generated.

[0119] Optionally, the step 101 of obtaining a first directed acyclic graph corresponding to the source program code includes:

[0120] Step S51, analyzing the source program code to determine whether the source program code contains a target parameter; the target parameter is used to enable the vector module in the compiler for compilation;

[0121] Step S52: when the source program code contains the target parameter, convert the source program code into an intermediate code;

[0122] Step S53, performing vectorization processing on the intermediate code, and recording the cost value of each directed acyclic graph generated during the vectorization processing based on the cost model;

[0123] Step S54: Determine the directed acyclic graph with the smallest cost value among the directed acyclic graphs as the first directed acyclic graph.

[0124] In an embodiment of the present invention, the source program code may be analyzed first to determine whether the source program code contains the target parameter. The analysis of the source program code may include lexical analysis, grammatical analysis, and semantic analysis. Exemplarily, lexical analysis may be a compiler reading the source program code and identifying a string token (Token) through a lexical analyzer. The types of Tokens may include: keywords, identifiers, literals, operands, delimiters, etc. Syntactic analysis may be converting Tokens into a tree data structure that can reflect grammatical rules, such as an abstract syntax tree AST. Semantic analysis may be context analysis based on an abstract syntax tree, including reference resolution, type analysis and checking, etc., and then generating intermediate code based on the analysis results.

[0125] The target parameter is used to enable the vector module in the compiler for compilation. As an example, if the embodiment of the present invention is to optimize the nested ternary operation of 128-bit vector data or 256-bit vector data, the target parameter can be a parameter for indicating the enablement of 128-bit vectors or the simultaneous enablement of 128-bit vectors and 256-bit vectors. Further, before obtaining the first directed acyclic graph of the source program code, the compiler front end can analyze the compilation command line input by the user to determine whether the parameters passed in by the user through the compilation command line indicate the enablement of 128-bit vectors or the simultaneous enablement of 128-bit vectors and 256-bit vectors. The compiler front end adds the analysis results to the intermediate representation (such as LLVM IR) and passes the intermediate representation to the compiler back end. It should be noted that the current compiler defaults to using only the scalar module for compilation, that is, the compiled instructions are all scalar instructions. "Enabling 128-bit vectors" means enabling the vector module in the compiler for compilation. After the vector module is enabled for compilation, if the program can be optimized using vectors, the compiler will generate vector instructions. At this time, the operation object in the command line of the source code is not necessarily 128-bit vector data or 256-bit vector data, but can also be scalar data. However, the compiler will try to convert scalar data to vector data, that is, automatic vectorization.

[0126] In a possible implementation, the compiler front end can traverse the compilation command input by the user, determine whether the user has enabled 128-bit vectors or both 128-bit vectors and 256-bit vectors in the compiler, and add the analysis result to the attribute of the intermediate code output by the compiler front end, and then pass the intermediate code to the compiler back end. The compiler back end makes a judgment based on the information transmitted by the front end. If the user has enabled 128-bit vectors or 256-bit vectors, the intermediate code is vectorized, and based on the code model, the cost value of each directed acyclic graph generated during the vectorization process is recorded, and the directed acyclic graph with the smallest cost value is determined as the first directed acyclic graph.

[0127] The compiling method provided by the present invention will be described below with examples in combination with the aforementioned embodiments.

[0128] As an example, the compilation method provided by the present invention may specifically include the following steps:

[0129] Step 1: The compiler front end analyzes the source code input by the user to determine whether the user indicates to enable 128-bit vectors or both 128-bit vectors and 256-bit vectors in the parameters passed to the compiler. The front end adds the analysis results to the attributes of the LLVM intermediate representation (LLVM IR) and passes the intermediate representation to the back end.

[0130] Step 2: The backend makes a judgment based on the information transmitted by the frontend. If the parameters passed by the user indicate to enable 128-bit vectors or enable both 128-bit vectors and 256-bit vectors, it means that the vector module in the compiler is enabled for compilation, and then proceed to step 3. If it is not enabled, the subsequent processes and downgrade steps related to the vector function module will not be executed, and only the downgrade process of the scalar data type will be executed. When the vector module is not enabled, the subsequent steps will not be executed.

[0131] Reference Figure 2 , shows a scalar data type degradation flow chart. Figure 2 As shown in the figure, when the compiler backend performs the downgrade processing of scalar data types, it converts the intermediate representation LLVM IR passed by the front end into a DAG graph. After the DAG graph is constructed, it will be processed in sequence according to Figure 2 In the order of the one-way arrows in the figure, DAG merging, type legalization, vector legalization, DAG legalization and other operations are performed. In the vector legalization operation, the vector data will be split into scalar data, and after DAG merging, DAG legalization, DAG secondary merging and other processes, the final MIR (Machine IR) will be downgraded to the real instruction. The MIR in the figure can also be changed to an instruction. It should be noted that MIR is a human-readable serialization format used to represent the machine-specific intermediate representation of LLVM.

[0132] Step 3: Build a cost model. Add cost model related code to the backend of the compiler to describe the cost of architecture-related nodes and architecture-independent nodes, so as to evaluate the cost of each target node involved in the fusion and the cost of the fusion node in subsequent steps. The cost of a node is measured by the clock cycles consumed when the operation corresponding to the node is executed. The longer the clock cycle consumed when the operation corresponding to the node is executed, the higher the cost of the node. For example, if the cost of the fusion node corresponding to a vector selection node is less than the sum of the cost values ​​of the target nodes involved in the fusion, the fusion node can be used to replace the target nodes. After the cost model is set, proceed to step 4.

[0133] Step 4: Determine whether the directed acyclic graph contains a VSELECT node, i.e., a vector selection node. If so, jump to step 5. Otherwise, exit the optimization process and do not perform subsequent optimization. The VSELECT node in step 4 is referred to as the top-level node.

[0134] Step 5: Determine whether the current directed acyclic graph is a type-legalized directed acyclic graph based on the information of the compiler's public layer, and then perform vectorization processing. If yes, execute step 6. If not, skip this optimization and perform the type legalization process of the public layer. After the type legalization is completed, jump to step 4.

[0135] Step 6: Get the top-level nodes representing the three operands of the ternary operation in turn, which are called nodes T0, T1, and T2 in turn. Nodes T0, T1, and T2 are collectively referred to as second-layer nodes. Determine whether T0 is a SETCC node, that is, a comparison node. If so, it means that node T0 meets the comparison operation in the nested ternary operation, and then proceed to step 7. Otherwise, jump to step 4 and continue to search for the next VSELECT node in the directed acyclic graph until all VSELECT nodes in the graph are traversed.

[0136] Step 7: Determine whether the T2 node is a VSELECT node. If so, it means that the node T2 meets the selection operation in the nested ternary operation, and then proceed to step 8. Otherwise, jump to step 4 and use the T2 node as the top-level node for subsequent determination.

[0137] Step 8: Get the first operand and the second operand of the T2 node, which are called nodes T20 and T21 respectively. Perform the following two judgments at the same time: judge whether T20 is a SETCC node, and judge whether T21 is a SUB node, that is, a subtraction operation node. When the above two judgments are established at the same time, it means that the node attributes of nodes T20 and T21 meet the first target rule, and continue to step 9. Otherwise, jump to step 4 and continue to find the next VSELECT node in the directed acyclic graph until all VSELECT nodes in the graph are traversed.

[0138] Step 9: Determine whether the second operand T1 node of the top node is a node for constructing an all-zero vector. According to the data flow dependency, obtain the second operand of the T0 node, record it as node T01, and determine whether the function of the node T01 is to construct an all-zero vector data type. Obtain the second operand of the T20 node (recorded as node T201) and the first operand of the T21 node (recorded as node T210), and determine whether the functions of the two acquired nodes T201 and T210 are to construct an all-zero vector data type. When the judgments of the above four nodes are all established, it means that the operand attributes of the nodes T1, T01, T201 and T210 are all nodes for constructing an all-zero vector, that is, the nodes T1, T01, T201 and T210 meet the second target rule, and continue to step 10. Otherwise, jump to step 4 and continue to find the next VSELECT node of the directed acyclic graph until all the VSELECT nodes in the graph are traversed.

[0139] Step 10: Determine the condition code. During the compilation process, obtain the condition code of the T0 node and the condition code of the T20 node. When the condition code of the T0 node is SETEQ and the condition code of the T20 node is SETLT, it means that the first condition code of the node T0 and the second condition code of the node T20 meet the second preset condition, and proceed to step 11. Otherwise, jump to step 4 and continue to look for the next VSELECT node in the directed acyclic graph until all VSELECT nodes in the graph are traversed. Among them, SETEQ means: if the values ​​of the two compared operands are equal, return true. SETLT means: if the first operand of the node is less than the second operand, return true.

[0140] Step 11: according to the data flow dependency, obtain the third operand of T2 node, which is recorded as T23 node. Determine whether the data types of the destination operands of the top node, node T1, node T2, node T21 and node T23 are the same, and are all vector data types. If the data types of the destination operands of the above four nodes are the same and are all vector data types, it means that the data types of the destination operands of the top node, node T1, node T2, node T21 and node T23 meet the third target rule, then record the data type of the top node and proceed to step 12. Otherwise, jump to step 4, continue to look for the next VSELECT node of the directed acyclic graph, until all the VSELECT nodes in the figure are traversed.

[0141] Step 12: Determine whether the data types of the T0 node and the T20 node are the same, and determine whether the data types of the two nodes are both vector data types, and the data type of the data elements that make up the vector data is i1. If the above judgments are all true, it means that the data types of the destination operands of the nodes T0 and T20 are the same, and both are vector data types, and the data types of the data elements that make up the destination operands of the nodes T0 and T20 are both Boolean types, that is, the data types of the destination operands of the nodes T0 and T20 meet the fourth target rule, then record the data type of the T0 node and jump to step 13. If one of the above judgments is not true, jump to step 4 and continue to look for the next VSELECT node of the directed acyclic graph until all VSELECT nodes in the graph are traversed.

[0142] Step 13: Cost analysis before and after conversion. Calculate the total cost of the target nodes involved in the conversion before conversion and the cost of the fused node after conversion. When the cost of the fused node after conversion is less than the sum of the costs of each target node before conversion, proceed with the subsequent conversion process and jump to step 14. Otherwise, jump to step 4.

[0143] Step 14: Perform node conversion. Keeping the data flow dependency and control flow dependency of the nodes before and after the conversion unchanged, generate architecture-related nodes according to the data type of the top-level node and the data type of the T0 node recorded in step 11 and step 12. For top-level nodes and T0 nodes of different data types, generate different architecture-related nodes to update the first directed acyclic graph, and finally obtain the target directed acyclic graph.

[0144] Take an optimization scenario of an embodiment of the present invention as an example:

[0145] typedefsigned charv32i8__attribute__((vector_size(32),aligned(32)));

[0146] v32i8 for_v32i8(v32i8 b,v32i8 c){

[0147] v32i8 a;

[0148] for(int i=0;i<32;i++)

[0149] a[i]=b[i]==0?0:b[i]<0? -c[i]:c[i];

[0150] return a;

[0151] }

[0152] When processing the above scenario, the compilation method provided by the present invention may specifically include the above steps 1 to 14.

[0153] When executing steps 1 and 2, when compiling the above files, you need to add the option of enabling the 256-bit vector function module during compilation in order to enter the subsequent optimization process. If the option of enabling the vector function module is not enabled, the subsequent optimization steps will not be executed.

[0154] It should be noted that when the user passes a parameter to the compiler indicating that 256-bit vectors are enabled, 128-bit vectors are generally enabled by default. However, when the parameter indicates that 128-bit vectors are enabled, 256-bit vectors are disabled by default. The above test case is a test case for 256-bit vectors, so 256-bit vectors need to be enabled.

[0155] When executing step 3, the compiler backend obtains information about the cost model that has been coded based on the specific architecture information.

[0156] Reference Figure 3 , shows a directed acyclic graph before node fusion provided by an embodiment of the present invention. Figure 3 As shown in the above scenario, the directed acyclic graph before node fusion contains a total of 17 nodes. Figure 3 In the DAG, each box represents a node, and the black edges between multiple nodes in the DAG represent the data flow dependencies between the nodes. Each number in the first row of the box represents each operand of the node. The second row represents the node name. The third row represents the node number, and the numbers are used to refer to each node in the following. The fourth row represents the data type of the destination operand of the current node.

[0157] It should be noted that Figure 3 It is the intermediate state of the above code during the compilation process. The node name is the semantic representation generated by the compiler after the compiler parses the semantics of the high-level language. Figure 3 The semantics of the representation are equivalent to the semantics of the code representation. Figure 3 The functional combination of the nodes in represents the semantics of the above code. After the compiler performs lexical analysis, syntax analysis and semantic analysis on the high-level language (the above code), it converts the semantic equivalence of the high-level language into the semantics of a directed acyclic graph.

[0158] Among them, copyfromreg indicates the operation of copying function parameters to registers. The buildvector node indicates the node of creating a vector data type, corresponding to a processing operation in the for loop part of the code.

[0159] Figure 3 The dotted line in indicates that there is a control dependency between the operations of two nodes, that is, one operation must be executed after the other operation. Figure 3 The solid lines in represent data dependencies, where the result of one operation is used as the input of another operation.

[0160] Figure 3 All data types are supported by the compiler architecture. This function can be implemented by calling specific function interfaces within the compiler.

[0161] The function corresponding to the t6 node is to create a vector data type containing 32 elements, so there are 32 operands, and in the vector data type created by t6, each element is 0, so they are all associated with t17.

[0162] The t16 node represents the return operation of the function, corresponding to the return in the code.

[0163] The t15 node indicates that the result of the operation is copied to the register in preparation for return, which also corresponds to the return in the code.

[0164] t18 is the setcc node, and its second operand is the t6 node.

[0165] When executing step 4, if node t21 meets the judgment in step 4, node t21 is taken as the top-level node, and step 5 is continued.

[0166] When executing step 5, you need to write code to determine whether the current DAG graph is a type-legalized DAG graph based on the LLVM public layer information. This step does not involve the information of specific nodes.

[0167] When executing step 6, the top-level node t21 represents three operands of the ternary operation, which are the t18 node, t6 node and t20 node in the figure, and the t18 node, t6 node and t20 node are used as the second-level nodes. It is determined whether the t18 node is a SETCC node. If so, proceed to step 7.

[0168] When executing step 7, it is necessary to determine whether the t20 node is a VSELECT node. In this embodiment, the name corresponding to the t20 node is extracted to obtain that the t20 node is a VSELECT node.

[0169] When executing step 8, you need to obtain the first operand and the second operand of the t20 node, which are the t19 node and the t11 node in the figure respectively. (Here Figure 3The order of the t19 node and the t11 node as the operands of the t20 node is reversed, which may be a compiler visualization bug, but the order in the generated debug information is correct. The generated debug information shall prevail, that is, the order mentioned in the embodiment of the present invention.) The following two judgments need to be performed simultaneously: judging whether t19 is a SETCC node and judging whether t11 is a SUB node. If both are true, proceed to step 9.

[0170] When executing step 9, the second operand t6 node (node ​​T1) of the top node t21, the second operand t6 node (node ​​T01) of the first operand t18 node of the top node t21, the second operand t6 node (node ​​T201) of the first operand t19 node of the third operand t20 node of the top node t21, and the first operand t6 node (node ​​T210) of the second operand t11 node of the third operand t20 node of the top node t21 are judged to determine whether the t6 node is a node for constructing an all-zero vector ( Figure 3 The order of the operands of the t20 node generated in the t19 node and the t11 node is reversed). For example, it can be determined whether the node t6 is a build_vector node. If it is, by calling the function interface, it is determined whether the operands of the node are all 0. If the above two conditions are met, the t6 node is a node for constructing an all-zero vector. At this time, the operands mentioned in step 9 are all t6 nodes, but each operand needs to be judged in the specific judgment process.

[0171] In step 10, the condition code is judged, and two condition code nodes are obtained, namely, node t7 and node t9. It is judged whether the condition code of node t7 is SETEQ, and whether the condition code of node t9 is SETLT. Among them, SETEQ and SETLT are two common condition codes, SETEQ means "equal to", and SETLT means "less than".

[0172] In step 11, the T23 node mentioned in the optimization process is the t4 node in the figure. In this step, the data types of the t4 node, t21 node, t6 node, t20 node and t11 node are judged, and the data types of the above five nodes are required to be the same and all vector data types.

[0173] In step 12, it is determined whether the data types of t18 and t19 are the same and both are vector data types. Figure 3 The data types corresponding to the t18 node and the t19 node are both SETCC, that is, they are comparison nodes. Then, the comparison node type of the t18 node is recorded and the process goes to step 13.

[0174] In step 13, according to Figure 3 The middle node uses the cost model to calculate the conversion before and after Figure 3 The total cost in , after calculation, the cost of the fused node after conversion is less than the sum of the costs of each node before conversion.

[0175] In step 14, different architecture-related nodes are generated according to the data types of the t21 node and the t18 node recorded in step 11 and step 12. Specifically, according to the data types and node types recorded in the above steps, by writing code, semantically equivalent architecture-related nodes are used to replace the original multiple nodes, and the semantic equivalence before and after the replacement is maintained. In this example, the data type of the top-level node t21 node and the first operand t18 node of the top-level node is v32i8, and the architecture-related node A is generated according to this data type. That is, the t21 node, t20 node, t18 node, t19 node, t11 node, t7 node, t9 node, and t6 node are merged in a semantically equivalent manner to obtain a node t17 named A. As shown in FIG. Figure 4 As shown, a directed acyclic graph after node fusion is shown, and the directed acyclic graph after node fusion contains 9 nodes in total. The number of nodes in the directed acyclic graph is reduced by 47% before and after optimization.

[0176] In summary, an embodiment of the present invention provides a compilation method, which analyzes a first directed acyclic graph corresponding to a source program code, traverses all vector selection nodes in the first directed acyclic graph, analyzes the dependency relationship of the operands of each vector selection node in the first directed acyclic graph, generates fusion nodes corresponding to each vector selection node, and further determines the vector selection nodes that meet the fusion condition according to the cost value corresponding to each fusion node, and performs node fusion on the first directed acyclic graph based on the fusion nodes corresponding to each first node that meets the fusion condition in the first directed acyclic graph. The embodiment of the present invention can perform node fusion on multiple vector selection nodes in complex scenarios such as nested ternary operations, fuse multiple target nodes corresponding to the vector selection nodes into one node, and judge whether the vector selection nodes meet the fusion condition based on the cost value of the fusion node, and update the directed acyclic graph only when the vector selection node meets the fusion condition, thereby improving the optimization effect of the node fusion operation while ensuring that the cost value of the fused target directed acyclic graph is less than the cost value of the first directed acyclic graph, which is conducive to improving the compilation performance of the compiler and improving the running speed of the executable program generated subsequently.

[0177] Device Embodiment

[0178] Reference Figure 5 , shows a structural block diagram of a compilation device embodiment of the present invention, the device is applied to a compiler, and the device may specifically include:

[0179] The acquisition module 501 is used to acquire a first directed acyclic graph corresponding to a source program code; the source program code is a high-level language code corresponding to the business to be processed;

[0180] A first determining module 502, configured to traverse the vector selection nodes in the first directed acyclic graph and determine the vector selection node as a first node;

[0181] The node fusion module 503 is used to analyze the dependency relationship of the three operands of each of the first nodes in the first directed acyclic graph, and generate a fusion node corresponding to the first node; the second node is the input data flow node corresponding to the first node; the fusion node is equivalent to the node function of each target node involved in the fusion;

[0182] The update module 504 is used to update the first directed acyclic graph according to the fusion nodes corresponding to each first node that meets the fusion conditions in the first directed acyclic graph, to obtain a target directed acyclic graph, so as to generate an executable program corresponding to the business to be processed; the fusion conditions are determined respectively according to the cost values ​​corresponding to each of the fusion nodes.

[0183] Optionally, the node fusion module includes:

[0184] A node determination submodule, used for determining, for each first node, a second node according to the data flow dependency relationship in the first directed acyclic graph; the second node is an input data flow node of the three operands;

[0185] The fusion submodule is used to generate a fusion node corresponding to the first node according to the node attribute of the second node and each node having a dependency relationship with the second node.

[0186] Optionally, the fusion submodule includes:

[0187] a node determination unit, configured to determine the first node as a top-level node, and when an input data flow node T0 of a first operand of the top-level node is a comparison node and an input data flow node T2 of a third operand of the top-level node is a vector selection node, perform architecture analysis on the second node and each node having a dependency relationship with the second node, and obtain attribute characteristics of the specified node;

[0188] A fusion unit is used to generate the fused node according to the second node and each node having a dependency relationship with the second node when the attribute characteristics of the designated node meet preset requirements.

[0189] Optionally, the designated node includes a first designated node and a second designated node; and the fusion unit includes:

[0190] A first acquisition unit, configured to acquire, when the node attribute of the first designated node meets the first target requirement, a first condition code of the node T0 and a second condition code of the input data flow node T20 of the first operand of the node T2;

[0191] A second acquisition unit is used to perform architecture analysis on the second node and each node having a dependency relationship with the second node to acquire a data type of a destination operand of the second designated node when the first condition code and the second condition code meet a second preset condition;

[0192] A node fusion unit is used to generate a fusion node according to the second node and each node having a dependency relationship with the second node when the data type of the destination operand of the second designated node meets the second target requirement.

[0193] Optionally, the first designated node includes:

[0194] An input data flow node T20 of the first operand of the node T2;

[0195] An input data flow node T21 of the second operand of the node T2;

[0196] An input data flow node T1 of the second operand of the top-level node;

[0197] An input data flow node T01 of the second operand of the node T0;

[0198] An input data flow node T201 of the second operand of the node T20;

[0199] An input data flow node T210 of the first operand of the node T21;

[0200] The fusion unit also includes:

[0201] The first determination unit is used to determine that the node attributes of the first designated node meet the first target requirement when the node attributes of the node T20 and the node T21 meet the first target rule and the node attributes of the node T1, the node T01, the node T201 and the node T210 meet the second target rule.

[0202] Optionally, the first target rule includes: the node T20 is a comparison node, and the node T21 is a subtraction operation node;

[0203] The second target rule includes: the node T1, the node T01, the node T201 and the node T210 are all nodes used to construct an all-zero vector.

[0204] Optionally, the second designated node includes:

[0205] The top-level node;

[0206] An input data flow node T1 of the second operand of the top-level node;

[0207] The node T2;

[0208] An input data flow node T21 of the second operand of the node T2;

[0209] An input data flow node T22 of the third operand of the node T2;

[0210] The node T0;

[0211] An input data flow node T20 of the first operand of the node T2;

[0212] The fusion unit also includes:

[0213] The second determination unit is used to determine that the data type of the destination operand of the second designated node meets the second target requirement when the data types of the destination operands of the top-level node, the node T1, the node T2, the node T21 and the node T22 meet the third target rule and the data types of the destination operands of the node T0 and the node T20 meet the fourth target rule.

[0214] Optionally, the third target rule includes: data types of destination operands of the top-level node, the node T1, the node T2, the node T21 and the node T22 are the same and are all vector data types;

[0215] The fourth target rule includes: the data types of the destination operands of the node T0 and the node T20 are the same and are both vector data types, and the data types of the data elements constituting the destination operands of the node T0 and the node T20 are both Boolean types.

[0216] Optionally, the second preset condition includes: the first condition code is used to indicate that the condition for returning the correct value is that the values ​​of the two compared operands are equal, and the second condition code is used to indicate that the condition for returning the correct value is that the first operand is less than the second operand.

[0217] Optionally, the node fusion module includes:

[0218] An acquisition submodule, used for acquiring the data type of the destination operand of the input data flow node T0 of the first node and the first operand of the first node;

[0219] The second fusion submodule is used to generate a fusion node according to the data types of the destination operands of the first node and the node T0.

[0220] Optionally, the device further comprises:

[0221] A cost analysis module, used for calculating the sum of the cost values ​​of the target nodes and the cost value of the fusion node based on the cost model;

[0222] The condition judgment module is used to determine that the first node meets the fusion condition when the cost value of the fusion node is less than the sum of the cost values ​​of the target nodes.

[0223] Optionally, the acquisition module includes:

[0224] A code analysis submodule, used for analyzing the source program code to determine whether the source program code contains target parameters; the target parameters are used to enable the vector module in the compiler for compilation;

[0225] A code conversion submodule, used for converting the source program code into an intermediate code when the source program code contains the target parameter;

[0226] A cost calculation submodule, used for vectorizing the intermediate code and recording the cost value of each directed acyclic graph generated during the vectorization process based on a cost model;

[0227] The directed acyclic graph determination submodule is used to determine the directed acyclic graph with the smallest cost value among the directed acyclic graphs as the first directed acyclic graph.

[0228] In summary, an embodiment of the present invention provides a compilation device, which can perform node fusion on multiple vector selection nodes in complex scenarios such as nested ternary operations, fuse multiple target nodes corresponding to the vector selection nodes into one node, and judge whether the vector selection node meets the fusion condition based on the cost value of the fused node, and update the directed acyclic graph only when the vector selection node meets the fusion condition, thereby improving the optimization effect of the node fusion operation while ensuring that the cost value of the fused target directed acyclic graph is less than the cost value of the first directed acyclic graph, which is beneficial to improving the compilation performance of the compiler and improving the running speed of the subsequently generated executable program.

[0229] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0230] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0231] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0232] An embodiment of the present invention provides an electronic device, the electronic device comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors, wherein the one or more programs include instructions for performing the following operations:

[0233] A11. Obtain a first directed acyclic graph corresponding to a source program code; the source program code is a high-level language code corresponding to the business to be processed;

[0234] A12. traverse the vector selection nodes in the first directed acyclic graph, and determine the vector selection node as the first node;

[0235] A13. Analyze the dependency relationship of the three operands of each of the first nodes in the first directed acyclic graph to generate a fusion node corresponding to the first node; the fusion node is functionally equivalent to each target node involved in the fusion;

[0236] A14. Update the first directed acyclic graph according to the fusion nodes corresponding to the first nodes that meet the fusion conditions in the first directed acyclic graph to obtain a target directed acyclic graph to generate an executable program corresponding to the business to be processed; the fusion conditions are determined respectively according to the cost values ​​corresponding to the fusion nodes.

[0237] Figure 6 1 is a block diagram of an electronic device 600 for compiling according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0238] Reference Figure 6, the electronic device 600 may include one or more of the following components: a processing component 602 , a memory 604 , a power component 606 , a multimedia component 608 , an audio component 610 , an input / output (I / O) interface 612 , a sensor component 614 , and a communication component 616 .

[0239] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0240] The memory 604 is configured to store various types of data to support operations on the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, videos, etc. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0241] The power supply component 606 provides power to the various components of the electronic device 600. The power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 600.

[0242] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and the rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0243] The audio component 610 is configured to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC), and when the electronic device 600 is in an operating mode, such as a call mode, a recording mode, and a voice information processing mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 604 or sent via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0244] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0245] The sensor assembly 614 includes one or more sensors for providing various aspects of status assessment for the electronic device 600. For example, the sensor assembly 614 can detect the open / closed state of the electronic device 600, the relative positioning of the components, such as the display and keypad of the device 600, and the sensor assembly 614 can also detect the position change of the electronic device 600 or a component of the electronic device 600, the presence or absence of user contact with the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and the temperature change of the electronic device 600. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 614 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0246] The communication component 616 is configured to facilitate wired or wireless communication between the electronic device 600 and other devices. The electronic device 600 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency information processing (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0247] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0248] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, and the instructions can be executed by a processor 620 of an electronic device 600 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0249] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute Figures 1 to 3 The method shown.

[0250] The above is a detailed introduction to a compilation method, device and electronic device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A compilation method, It is characterized in that Applied to a compiler, the method comprises: Obtaining a first directed acyclic graph corresponding to a source program code; the source program code is a high-level language code corresponding to the business to be processed; Traversing the vector selection nodes in the first directed acyclic graph, and determining the vector selection node as the first node; Analyze the dependency relationship of the three operands of each of the first nodes in the first directed acyclic graph to generate a fusion node corresponding to the first node; the fusion node is functionally equivalent to each target node involved in the fusion; According to the fusion nodes corresponding to the first nodes in the first directed acyclic graph that meet the fusion conditions, the first directed acyclic graph is updated to obtain a target directed acyclic graph to generate an executable program corresponding to the business to be processed; the fusion conditions are determined respectively according to the cost values ​​corresponding to the fusion nodes.

2. The method according to claim 1, It is characterized in that The step of analyzing the dependency relationship of the three operands of each of the first nodes in the first directed acyclic graph to generate a fusion node corresponding to the first node includes: For each first node, determining a second node according to the data flow dependency in the first directed acyclic graph; the second node is an input data flow node of the three operands; A fusion node corresponding to the first node is generated according to the node attribute of the second node and each node having a dependency relationship with the second node.

3. The method according to claim 2, It is characterized in that The generating, according to the node attribute of the second node and each node having a dependency relationship with the second node, a fusion node corresponding to the first node includes: Determine the first node as a top-level node, and when the node T0 of the first operand of the top-level node is a comparison node and the node T2 of the third operand of the top-level node is a vector selection node, perform architecture analysis on the second node and each node having a dependency relationship with the second node to obtain attribute characteristics of the specified node; When the attribute characteristics of the designated node meet preset requirements, the fused node is generated according to the second node and each node having a dependency relationship with the second node.

4. The method according to claim 3, It is characterized in that The designated nodes include a first designated node and a second designated node; and generating the fused node according to the second node and each node having a dependency relationship with the second node includes: When the node attribute of the first designated node meets the first target requirement, obtaining a first condition code of the node T0 and a second condition code of the input data flow node T20 of the first operand of the node T2; When the first condition code and the second condition code satisfy a second preset condition, performing architecture analysis on the second node and each node having a dependency relationship with the second node to obtain a data type of a destination operand of the second designated node; When the data type meets the second target requirement, the fusion node is generated according to the second node and each node having a dependency relationship with the second node.

5. The method according to claim 4, It is characterized in that The first designated node includes: An input data flow node T20 of the first operand of the node T2; An input data flow node T21 of the second operand of the node T2; An input data flow node T1 of the second operand of the top-level node; An input data flow node T01 of the second operand of the node T0; An input data flow node T201 of the second operand of the node T20; An input data flow node T210 of the first operand of the node T21; The method also includes: determining that the node attributes of the first designated node meet the first target requirement when the node attributes of the node T20 and the node T21 meet the first target rule and the node attributes of the node T1, the node T01, the node T201 and the node T210 meet the second target rule.

6. The method according to claim 4, It is characterized in that The second designated node includes: The top-level node; An input data flow node T1 of the second operand of the top-level node; The node T2; An input data flow node T21 of the second operand of the node T2; An input data flow node T22 of the third operand of the node T2; The node T0; An input data flow node T20 of the first operand of the node T2; The method also includes: when the data types of the destination operands of the top-level node, the node T1, the node T2, the node T21 and the node T22 satisfy the third target rule, and the data types of the destination operands of the node T0 and the node T20 satisfy the fourth target rule, determining that the data type of the destination operand of the second designated node meets the second target requirement.

7. The method according to any one of claims 4 to 6, It is characterized in that The second preset condition includes: the first condition code is used to indicate that the condition for returning a correct value is that the values ​​of the two compared operands are equal, and the second condition code is used to indicate that the condition for returning a correct value is that the first operand is less than the second operand.

8. The method according to claim 1, It is characterized in that The generating a fusion node corresponding to the first node includes: Obtain the data type of the destination operand of the first node and the node T0 of the first operand of the first node; The fused node is generated according to the data types of the destination operands of the first node and the node T0.

9. The method according to claim 1, It is characterized in that The method further comprises: Calculating the sum of the cost values ​​of the target nodes and the cost value of the fusion node based on the cost model; When the cost value of the fused node is less than the sum of the cost values ​​of the target nodes, it is determined that the first node meets the fusion condition.

10. A compiling device, It is characterized in that The device is applied to a compiler, and comprises: An acquisition module, used to acquire a first directed acyclic graph corresponding to a source program code; the source program code is a high-level language code corresponding to the business to be processed; A first determining module, configured to traverse the vector selection nodes in the first directed acyclic graph and determine the vector selection nodes as first nodes; A node fusion module, used for analyzing the dependency relationship of the three operands of each of the first nodes in the first directed acyclic graph, and generating a fusion node corresponding to the first node; the second node is an input data flow node corresponding to the first node; the fusion node is functionally equivalent to each target node involved in the fusion; An update module is used to update the first directed acyclic graph according to the fusion nodes corresponding to each first node that meets the fusion conditions in the first directed acyclic graph, obtain a target directed acyclic graph, and generate an executable program corresponding to the business to be processed; the fusion conditions are determined respectively according to the cost values ​​corresponding to each of the fusion nodes.

11. The device according to claim 10, It is characterized in that The node fusion module includes: A node determination submodule, used for determining, for each first node, a second node according to the data flow dependency relationship in the first directed acyclic graph; the second node is an input data flow node of the three operands; The fusion submodule is used to generate a fusion node corresponding to the first node according to the node attribute of the second node and each node having a dependency relationship with the second node.

12. The device according to claim 11, It is characterized in that The fusion submodule comprises: a node determination unit, configured to determine the first node as a top-level node, and when an input data flow node T0 of a first operand of the top-level node is a comparison node and an input data flow node T2 of a third operand of the top-level node is a vector selection node, perform architecture analysis on the second node and each node having a dependency relationship with the second node, and obtain attribute characteristics of the specified node; A fusion unit is used to generate the fused node according to the second node and each node having a dependency relationship with the second node when the attribute characteristics of the designated node meet preset requirements.

13. The device according to claim 12, It is characterized in that The designated node includes a first designated node and a second designated node; the fusion unit includes: A first acquisition unit, configured to acquire, when the node attribute of the first designated node meets the first target requirement, a first condition code of the node T0 and a second condition code of the input data flow node T20 of the first operand of the node T2; A second acquisition unit is used to perform architecture analysis on the second node and each node having a dependency relationship with the second node to acquire a data type of a destination operand of the second designated node when the first condition code and the second condition code meet a second preset condition; A node fusion unit is used to generate the fused node according to the second node and each node having a dependency relationship with the second node when the data type meets the second target requirement.

14. The device according to claim 13, It is characterized in that The first designated node includes: An input data flow node T20 of the first operand of the node T2; An input data flow node T21 of the second operand of the node T2; An input data flow node T1 of the second operand of the top-level node; An input data flow node T01 of the second operand of the node T0; An input data flow node T201 of the second operand of the node T20; An input data flow node T210 of the first operand of the node T21; The fusion unit also includes: The first determination unit is used to determine that the node attributes of the first designated node meet the first target requirement when the node attributes of the node T20 and the node T21 meet the first target rule and the node attributes of the node T1, the node T01, the node T201 and the node T210 meet the second target rule.

15. The device according to claim 13, It is characterized in that The second designated node includes: The top-level node; An input data flow node T1 of the second operand of the top-level node; The node T2; An input data flow node T21 of the second operand of the node T2; An input data flow node T22 of the third operand of the node T2; The node T0; An input data flow node T20 of the first operand of the node T2; The fusion unit also includes: The second determination unit is used to determine that the data type of the destination operand of the second designated node meets the second target requirement when the data types of the destination operands of the top-level node, the node T1, the node T2, the node T21 and the node T22 meet the third target rule and the data types of the destination operands of the node T0 and the node T20 meet the fourth target rule.

16. The device according to any one of claims 13 to 15, It is characterized in that The second preset condition includes: the first condition code is used to indicate that the condition for returning a correct value is that the values ​​of the two compared operands are equal, and the second condition code is used to indicate that the condition for returning a correct value is that the first operand is less than the second operand.

17. The device according to claim 10, It is characterized in that The node fusion module includes: An acquisition submodule, used for acquiring the data type of the destination operand of the input data flow node T0 of the first node and the first operand of the first node; The second fusion submodule is used to generate a fusion node according to the data types of the destination operands of the first node and the node T0.

18. The device according to claim 10, It is characterized in that The device also includes: A cost analysis module, used for calculating the sum of the cost values ​​of the target nodes and the cost value of the fusion node based on the cost model; The condition judgment module is used to determine that the first node meets the fusion condition when the cost value of the fusion node is less than the sum of the cost values ​​of the target nodes.

19. An electronic device, It is characterized in that The electronic device comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to execute the compiling method according to any one of claims 1 to 9 by one or more processors.

20. A readable storage medium, It is characterized in that When the instructions in the storage medium are executed by a processor of an electronic device, the processor is enabled to execute the compilation method as claimed in any one of claims 1 to 9.

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