Instruction processing apparatus, instruction processing method, and chip system

Abstract

The embodiment of the invention provides an instruction processing device, an instruction processing method and a chip system. The instruction processing apparatus includes: an instruction receiving module configured to receive a loop initial instruction; an instruction generation module configured to generate a neural network processor executable instruction based on a loop initial instruction for provision to a neural network processor for execution, the loop initial instruction including at least one loop initial instruction segment, the loop initial instruction segment including at least one loop initial instruction segment; each of the at least one loop initial instruction section corresponds to one loop level and comprises a loop level field which represents the loop level where the current loop is located; and at least one operation instruction configured to perform a set data processing operation. According to the instruction processing device, efficient, high-robustness and high-expansibility instruction control and generation can be carried out, the instruction sending efficiency is improved, the load of the coprocessor can be relieved, the performance of the coprocessor can be released for other functions, and the maximum utilization of system resources is achieved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an instruction processing device, an instruction processing method, and a chip system. Background Art

[0002] A neural-network processing unit (NPU) is a type of microprocessor or computing system dedicated to hardware acceleration of artificial intelligence (especially artificial neural networks, machine vision, machine learning, etc.), sometimes also referred to as an artificial intelligence accelerator (AI Accelerator).

[0003] In the NPU system architecture that adopts the instruction-driven mechanism, especially in the complex row-stationary (RS) NPU system architecture, a set of instruction sets is equipped to cope with the processing requirements of the internal loop structure of the RS NPU. The instruction set can cover operations such as data handling, loop end control, and padding. Summary of the invention

[0004] At least one embodiment of the present disclosure provides an instruction processing device, which includes: an instruction receiving module, configured to receive a loop initialization instruction; an instruction generating module, configured to generate a neural network processor executable instruction based on the loop initialization instruction, for providing to the neural network processor for execution, wherein the loop initialization instruction includes at least one loop initialization instruction segment, each of the at least one loop initialization instruction segment corresponds to a loop level and includes: a loop level field, indicating the loop level of the current loop; and at least one operation instruction, configured to perform a set data processing operation.

[0005] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the instruction generation module includes: a first decoding unit, configured to receive the loop initial instruction segment of the current loop and decode it to obtain at least one decoding condition judgment instruction; a condition judgment unit, configured to perform conditional judgment on the at least one decoding condition judgment instruction; an address control unit, configured to determine the corresponding operation instruction according to the second jump address field corresponding to the decoding condition judgment instruction that meets the condition; a second decoding unit, configured to decode the operation instruction to generate a decoding operation instruction executable by a neural network processor, and the address control unit is also configured to determine the next loop according to the first jump address field corresponding to the last decoding condition judgment instruction of the current loop to provide it to the first decoding unit for processing.

[0006] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the instruction generation module includes: a first decoding unit, configured to receive the first conditional judgment instruction of the current loop and decode it to obtain a decoded conditional judgment instruction; a conditional judgment unit, configured to perform conditional judgment on the decoded conditional judgment instruction; an address control unit, configured to determine an operation instruction according to a second jump address field corresponding to the decoded conditional judgment instruction when the condition is met, and to determine the next conditional judgment instruction to provide to the first decoding unit for processing when the condition is not met; a second decoding unit, configured to decode the operation instruction to generate a decoded operation instruction executable by a neural network processor, wherein the address control unit is further configured to determine the next loop according to the first jump address field corresponding to the last conditional judgment instruction of the current loop to provide to the first decoding unit for processing.

[0007] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the instruction generation module includes: a first decoding unit, configured to receive the loop initial instruction segment of the current loop and decode it to obtain at least one decoding condition judgment instruction; a condition judgment unit, configured to perform conditional judgment on the at least one decoding condition judgment instruction; an address control unit, configured to directly determine the operation instruction when there is a decoding condition judgment instruction that meets the condition, if the decoding condition judgment instruction that meets the condition is followed by an operation instruction, if the decoding condition judgment instruction that meets the condition is followed by multiple operation instructions, determine the operation instruction according to the second jump address field corresponding to the decoding condition judgment instruction, and when there is no decoding condition judgment instruction that meets the condition, determine the next loop according to the first jump address field corresponding to the decoding condition judgment instruction to provide it to the first decoding unit for processing; and a second decoding unit, configured to decode the operation instruction to generate a decoding operation instruction executable by a neural network processor.

[0008] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the instruction generation module includes: a first decoding unit, configured to receive the first conditional judgment instruction of the current cycle and decode it to obtain a decoded conditional judgment instruction; a conditional judgment unit, configured to perform conditional judgment on the decoded conditional judgment instruction; an address control unit, configured to directly determine the operation instruction when there is a decoding conditional judgment instruction that meets the condition, if the decoding conditional judgment instruction is followed by an operation instruction, if the decoding conditional judgment instruction that meets the condition is followed by multiple operation instructions, determine the operation instruction according to the second jump address field corresponding to the decoding conditional judgment instruction, and when the condition is not met, determine the next cycle according to the first jump address field corresponding to the decoding conditional judgment instruction to provide it to the first decoding unit for processing; a second decoding unit, configured to decode the operation instruction and generate a decoded operation instruction executable by a neural network processor.

[0009] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the instruction generation module includes: a first decoding unit, configured to receive the first instruction of the current loop and decode it to obtain an operation instruction; a second decoding unit, configured to decode the operation instruction to generate a decoded operation instruction executable by a neural network processor; an address control unit, configured to determine the next instruction according to the third jump address field corresponding to the operation instruction to provide it to the first decoding unit for processing.

[0010] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, it also includes: an instruction analysis module, wherein the instruction generation module also includes a register file, and the instruction analysis module is configured to store the loop initialization instructions in sequence into the register file; the register file is configured to store the loop initialization instructions stored by the instruction analysis module for reading by the first decoding unit and the address control unit.

[0011] For example, in the instruction processing device provided in at least one embodiment of the present disclosure, the instruction receiving module includes an interface management unit and a cache unit, the interface management unit is configured to receive the loop initialization instruction; the cache unit is configured to store the loop initialization instruction received by the interface management unit.

[0012] For example, in the instruction processing device provided in at least one embodiment of the present disclosure, it also includes: an instruction distribution module, which is configured to classify the executable instructions of the neural network processor and send them to the corresponding subsequent module of the instruction processing device.

[0013] At least one embodiment of the present disclosure provides an instruction processing method, which includes: receiving a loop initialization instruction; generating a neural network processor executable instruction based on the loop initialization instruction, so as to provide the instruction to the neural network processor for execution, wherein the loop initialization instruction includes at least one loop initialization instruction segment, each of the at least one loop initialization instruction segment corresponds to a loop level and includes: a loop level field, indicating the loop level of the current loop; and at least one operation instruction, which is configured to perform a set data processing operation.

[0014] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, each of the at least one loop initial instruction segment also includes: at least one conditional judgment instruction, which is configured to perform conditional judgment to control instruction jumping, and in response to the condition being met, jumps to the operation instruction corresponding to the conditional judgment instruction.

[0015] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, the at least one conditional judgment instruction is arranged in sequence, and the at least one operation instruction is set after all the conditional judgment instructions; the first conditional judgment instruction in the at least one conditional judgment instruction includes: a first jump address field, indicating the starting address of the loop to which the condition is jumped when the condition is met; the second conditional judgment instruction in the at least one conditional judgment instruction includes: a second jump address field, indicating the address of the instruction in the current loop to which the condition is jumped when the condition is met.

[0016] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, each of the at least one conditional judgment instruction is followed by one or more operation instructions; each of the conditional judgment instructions includes: a first jump address field, indicating the starting address of the loop to which the condition is jumped when the condition is not met; the conditional judgment instruction followed by multiple operation instructions also includes: a second jump address field, indicating the address of the instruction in the current loop to which the condition is jumped when the condition is met.

[0017] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, each of the at least one conditional judgment instruction includes at least one conditional instruction segment, wherein each of the at least one conditional instruction segment includes: a parameter address field, representing the parameter address of the first operand of the conditional judgment operation; a logical coding field, representing the coding of the comparison operator; and a judgment value field, representing the immediate value of the second operand of the conditional judgment operation.

[0018] For example, in the instruction processing method provided in at least one embodiment of the present disclosure, each of the at least one conditional judgment instruction also includes: an identification bit field, indicating whether the current instruction is a multi-conditional judgment instruction; and a condition number field, indicating the number of conditional instruction segments in the current instruction.

[0019] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, in response to the identification bit field indicating that the current instruction is a multi-condition judgment instruction, each of the at least one conditional instruction segment also includes: a group relationship field, indicating the group relationship between the current condition and other conditions; and a logical relationship field, indicating the logical relationship between the current condition and other conditions.

[0020] For example, in the instruction processing method provided in at least one embodiment of the present disclosure, the setting of data processing operations includes: implementing data transfer or user-defined operations.

[0021] For example, in the instruction processing method provided in at least one embodiment of the present disclosure, the operation instruction includes: an instruction type field, indicating the type of the current instruction; a continuous sending field, indicating whether multiple instructions are sent continuously; an instruction number field, indicating the number of instructions to be sent; and a custom instruction interface field, indicating the interface definition applicable to the custom instruction.

[0022] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, the operation instruction includes: an instruction type field, indicating the type of the current instruction; a data extension field, used to implement the data width expansion of the operation instruction; a segmentation field, used to indicate whether the operation instruction is a segmented instruction; a data length field, used to indicate the length of the data to be moved; an offset step field, indicating the data address offset step of the loop to be jumped to.

[0023] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, the operation instruction further includes: a third jump address field, indicating the address of the loop and instruction to which the operation instruction jumps when the operation instruction is executed.

[0024] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, the loop initialization instruction also includes: a space control field, indicating whether the current loop performs space allocation and the direction of space allocation; and / or a loop initialization instruction set configuration code, which is configured to indicate a valid loop level.

[0025] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, the loop initial instruction set configuration encoding is also configured to set the instruction set parameter bit width.

[0026] At least one embodiment of the present disclosure provides an instruction processing device, which includes: an instruction receiving module, configured to receive a loop initialization instruction; an instruction generating module, configured to generate a neural network processor executable instruction based on the loop initialization instruction, for providing to the neural network processor for execution, wherein the loop initialization instruction includes at least one loop initialization instruction segment, each of the at least one loop initialization instruction segment corresponds to a loop level and includes: a loop level field, indicating the loop level of the current loop; and at least one operation instruction, configured to perform a set data processing operation.

[0027] At least one embodiment of the present disclosure provides a chip system, which includes: an instruction processing device provided according to at least one embodiment of the present disclosure; and a neural network processor configured to execute executable instructions of the neural network processor.

[0028] For example, in the chip system provided by at least one embodiment of the present disclosure, it also includes: a processor configured to send the loop initialization instruction to the instruction processing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0030] Figure 1 A flowchart of an instruction processing method provided for at least one embodiment of the present disclosure;

[0031] Figure 2 A schematic diagram of a loop initial instruction segment provided for at least one embodiment of the present disclosure;

[0032] Figure 3 A conditional instruction segment provided for at least one embodiment of the present disclosure;

[0033] Figure 4A A schematic diagram of a single conditional judgment instruction provided for at least one embodiment of the present disclosure;

[0034] Figure 4B A schematic diagram of a multi-conditional judgment instruction provided for at least one embodiment of the present disclosure;

[0035] Figure 5A A schematic diagram of an operation instruction provided for at least one embodiment of the present disclosure;

[0036] Figure 5B A schematic diagram of another operation instruction provided for at least one embodiment of the present disclosure;

[0037] Figure 6A schematic diagram of a loop initial instruction segment provided for at least one embodiment of the present disclosure;

[0038] Fig. 7A A schematic diagram of a single conditional judgment instruction provided for at least one embodiment of the present disclosure;

[0039] Figure 7B A schematic diagram of a single conditional judgment instruction provided for at least one embodiment of the present disclosure;

[0040] Figure 8 A schematic diagram of a loop initial instruction segment provided for at least one embodiment of the present disclosure;

[0041] Fig.9A A schematic diagram of an operation instruction provided for at least one embodiment of the present disclosure;

[0042] Fig. 9B A schematic diagram of another operation instruction provided for at least one embodiment of the present disclosure;

[0043] Fig.10 A schematic block diagram of an instruction processing device provided for at least one embodiment of the present disclosure;

[0044] Fig.11 A schematic block diagram of another instruction processing device provided for at least one embodiment of the present disclosure;

[0045] Fig.12 A schematic block diagram of another instruction processing device provided for at least one embodiment of the present disclosure;

[0046] Fig.13A A schematic block diagram of a chip system provided for at least one embodiment of the present disclosure; and

[0047] Fig. 13B A schematic block diagram of a chip system provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0049] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0050] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components (elements) may be omitted. When any part (element) of the embodiments of the present disclosure appears in more than one figure, the part (element) is represented by the same or similar reference numeral in each figure.

[0051] Traditional system-on-chip (SoC) architectures usually only include a central processing unit (CPU) and an NPU. In this architecture, the CPU acts as the main controller, responsible for managing the entire system-on-chip, and the NPU is used to perform neural network computing tasks (such as convolution calculations, etc.). However, in this architecture, the CPU is heavily loaded, resulting in a decrease in the performance of the entire system. This is because in addition to conventional management and control tasks, the CPU also needs to coordinate a large amount of data transmission and complex neural network computing tasks. To improve this problem, a common approach is to introduce a coprocessor (usually one or more small CPUs) into the SoC architecture, which is specifically used to control the NPU, thereby reducing the burden on the CPU as the main controller.

[0052] Row Stationary (RS) data flow is a data layout and computation strategy designed for NPUs, especially when processing convolution operations of convolutional neural networks (CNNs). The processing unit array in RS NPUs (such as Eyeriss architecture NPUs) implements row stationary data flow by reusing rows of filter weights horizontally between processing units and rows of input feature map feature values ​​diagonally between processing units.

[0053] In the NPU system architecture that adopts the instruction-driven mechanism, especially in the complex RS NPU system architecture, a set of instruction sets is equipped to cope with the processing requirements of the internal loop structure of the RS NPU. The instruction set can cover operations such as data handling, loop end control, and filling.

[0054] The inventors of the present disclosure note that although the complexity and flexibility of the above loop structure design are high, the overly complex loop logic will lead to a sharp increase in the number of instructions, and a large number of complex instruction streams will be generated during actual operation. On the other hand, after the coprocessor is introduced into the traditional SoC architecture, although the performance of the system is improved to a certain extent, the function and load capacity of the coprocessor are also limited. When faced with complex and large neural network models, a large number of instructions will significantly increase the load of the coprocessor, so that its instruction sending ability becomes the performance bottleneck of the entire system. At the same time, this also increases the complexity and difficulty of software-level implementation.

[0055] At least one embodiment of the present disclosure provides an instruction processing method, which includes: receiving a loop initialization instruction; generating a neural network processor executable instruction based on the loop initialization instruction, so as to provide the instruction to the neural network processor for execution, wherein the loop initialization instruction includes at least one loop initialization instruction segment, each of the at least one loop initialization instruction segment corresponds to a loop level and includes: a loop level field, indicating the loop level of the current loop; and at least one operation instruction, which is configured to perform a set data processing operation.

[0056] The instruction processing method provided by at least one embodiment of the present disclosure can perform efficient, highly robust, and highly scalable instruction control and generation through instructions based on an efficient instruction set, thereby improving instruction sending efficiency, reducing coprocessor load, and releasing coprocessor performance for other functions, thereby maximizing system resource utilization. Furthermore, the instruction set is flexible in design and exhibits extremely high adaptability and scalability. It only needs to appropriately adjust and update the relevant module design inside the instruction processing device to adapt to and be compatible with different instruction set systems, without the need to comprehensively transform the infrastructure of the instruction processing device, thereby greatly simplifying the development process and reducing maintenance costs.

[0057] Figure 1 A flowchart of an instruction processing method provided by at least one embodiment of the present disclosure. Figure 1 As shown, the instruction processing method provided by the embodiment of the present disclosure includes the following steps S101 to S102.

[0058] Step S101: receiving a loop initialization instruction.

[0059] Step S102: Generate a neural network processor executable instruction based on the loop initial instruction, so as to provide it to the neural network processor for execution.

[0060] For example, the loop initialization instruction includes at least one loop initialization instruction segment, each of the at least one loop initialization instruction segment corresponds to a loop level, and each of the at least one loop initialization instruction segment includes a loop level field and at least one operation instruction. For example, the loop level field indicates the loop level of the current loop, and the operation instruction is configured to perform a set data processing operation.

[0061] For example, the loop level field is used to identify the specific loop level corresponding to the loop initial instruction segment, such as level 0, level 1, etc., to ensure that the instruction sequence is correctly executed in the nested loop. For example, the operation instruction is configured to perform a set data processing operation in the corresponding loop level, such as convolution, matrix multiplication, data handling, user-defined operations, etc.

[0062] For example, a loop initialization instruction sent by a host (such as a central processing unit CPU, a coprocessor, etc.) is received, and according to the host's instruction set architecture and the characteristics of the NPU, a high-level computing task based on the loop initialization instruction is converted into a low-level instruction sequence that the NPU can understand and execute, namely, a neural network processor executable instruction. These neural network processor executable instructions can be loaded into the NPU for execution, thereby efficiently completing the computing task of the neural network loop structure.

[0063] Figure 2 A schematic diagram of a loop initial instruction segment provided for at least one embodiment of the present disclosure.

[0064] For example, the loop initialization instruction segment includes a loop level field and at least one operation instruction. Figure 2 As shown, the loop initial instruction segment includes the loop level field ID and operation instructions OP0 to OP4. It should be noted that, Figure 2 Only the case where the loop initial instruction segment includes multiple operation instructions is shown. According to actual needs, the loop initial instruction segment may also include only one operation instruction. The embodiments of the present disclosure do not limit the number of operation instructions in the loop initial instruction segment.

[0065] For example, the loop level field ID indicates the loop level that the current loop is in. For example, when the loop level field ID is 0x02, it indicates that the current loop is a level 2 loop; when the loop level field ID is 0x20, it indicates that the current loop is a level 32 loop.

[0066] For example, the operation instructions OP0-OP4 are configured to execute a set data processing operation. For example, the set data processing operation includes implementing data transfer or user-defined operations.

[0067] For example, the loop initial instruction segment may also include at least one conditional judgment instruction. Figure 2 As shown, the loop initial instruction segment includes conditional judgment instructions JC0~JC2. It should be noted that, Figure 2 Only the case where the loop initial instruction segment includes multiple conditional judgment instructions is shown. According to actual needs, the loop initial instruction segment may also include only one conditional judgment instruction. The embodiments of the present disclosure do not limit the number of conditional judgment instructions in the loop initial instruction segment.

[0068] For example, the conditional judgment instructions JC0-JC2 are configured to perform conditional judgment to control instruction jumps, and in response to the condition being met, jump to the operation instruction corresponding to the conditional judgment instruction.

[0069] For example, at least one conditional judgment instruction is arranged in sequence, and at least one operation instruction is set after all conditional judgment instructions. Figure 2 As shown, the conditional judgment instructions JC0-JC2 are arranged in sequence, and the operation instructions OP0-OP4 are arranged after all the conditional judgment instructions.

[0070] For example, according to the position of the conditional judgment instruction, it can be divided into a first conditional judgment instruction and a second conditional judgment instruction, and the first conditional judgment instruction is the last conditional judgment instruction among the multiple conditional judgment instructions arranged in sequence (for example Figure 2 JC2 in the example, the second conditional judgment instruction is a conditional judgment instruction other than the first conditional judgment instruction (for example Figure 2 JC0 and JC1 in ).

[0071] For example, the first conditional judgment instruction includes a first jump address field, indicating the starting address of the loop to which the condition is satisfied. For example, the second conditional judgment instruction includes a second jump address field, indicating the address of the instruction in the current loop to which the condition is satisfied.

[0072] For example, if the condition corresponding to the conditional judgment instruction JC0 is established, then according to the second jump address field, it jumps to the operation instruction corresponding to the conditional judgment instruction JC0, and after the corresponding operation instruction is executed, it returns to the conditional judgment instruction JC1 to continue the conditional judgment; if the condition corresponding to the conditional judgment instruction JC0 is not established, then it sequentially executes to the conditional judgment instruction JC1 for judgment. And so on, until the last conditional judgment instruction JC2 is judged, if the condition corresponding to the conditional judgment instruction JC2 is established, it jumps to the corresponding loop level according to the first jump address field.

[0073] For example, each conditional judgment instruction also includes at least one conditional instruction segment.

[0074] Figure 3A conditional instruction segment is provided for at least one embodiment of the present disclosure. For example, Figure 3 As shown, each conditional instruction segment includes a parameter address field Param Addr, a logic encoding field Encode and a judgment value field Value.

[0075] For example, the parameter address field Param Addr represents the parameter address of the first operand of the conditional judgment operation, that is, the memory address of the variable or expression being judged.

[0076] For example, the logical encoding field Encode represents the encoding of the comparison operator. For example, Table 1 shows the correspondence between different comparison operators and encodings. It should be noted that Table 1 is only an example, and the above-mentioned various comparison operators may also correspond to other encoding schemes different from those shown in Table 1, and the embodiments of the present disclosure are not limited to this.

[0077] Table 1 Correspondence between comparison operators and encodings

[0078] Comparison Operators ＝ > < >＝ <＝ ！＝ coding 0b000 0b001 0b010 0b011 0b100 0b101

[0079] For example, the judgment value field Value represents an immediate value that is the second operand of the conditional judgment operation, that is, a specific value used for comparison with the first operand.

[0080] For example, assuming that the parameter address field Param Addr is 0x12345678, the logic encoding field Encode is 0b001, and the judgment value field Value is 0b1010, the conditional instruction segment is used to determine whether the data stored at the address 0x12345678 is greater than 10.

[0081] For example, if a conditional judgment instruction includes only one conditional instruction segment, the conditional judgment instruction is a single conditional judgment instruction. Figure 4A A schematic diagram of a single conditional judgment instruction provided for at least one embodiment of the present disclosure.

[0082] For example, Figure 4A As shown, the conditional judgment instruction includes a conditional instruction segment C0 and a jump address field (a first jump address field Loop Addr or a second jump address field Instr Addr). As described above, if the condition is met, the instruction jumps to the corresponding instruction or loop according to the jump address field.

[0083] For example, if a conditional judgment instruction includes multiple conditional instruction segments, the conditional judgment instruction is a multi-conditional judgment instruction. Figure 4B A schematic diagram of a multi-condition judgment instruction provided for at least one embodiment of the present disclosure.

[0084] For example, Figure 4BAs shown, the conditional judgment instruction includes conditional instruction segments C1 to C4 (C2 and C3 are not shown) and a jump address field (a first jump address field Loop Addr or a second jump address field Instr Addr). It should be noted that, Figure 4B This is only an example of a multi-conditional judgment instruction, and the embodiment of the present disclosure does not limit the number of conditional instruction segments.

[0085] For example, Figure 4B As shown, the conditional judgment instruction also includes a flag field Flag and a condition number field CNum.

[0086] For example, the flag field Flag indicates whether the current instruction is a multi-condition judgment instruction. For example, when the flag field Flag is a first value (e.g., 0), it indicates that the current instruction is not a multi-condition judgment instruction, and when the flag field Flag is a second value (e.g., 1), it indicates that the current instruction is a multi-condition judgment instruction.

[0087] For example, the condition number field CNum indicates the number of conditional instruction segments in the current instruction. For example, when the condition number field CNum is 0b0100, it means that the conditional judgment instruction includes 4 conditional instruction segments.

[0088] For example, Figure 4B As shown, in response to the identification bit field indicating that the current instruction is a multi-condition judgment instruction, each conditional instruction segment may further include a group relationship field Group and a logic relationship field Relation.

[0089] For example, the group relationship field Group represents the group relationship between the current condition and other conditions. For example, assuming that the group relationship field Group of conditional instruction segment C1 is 0b00, the group relationship field Group of conditional instruction segment C2 is 0b00, the group relationship field Group of conditional instruction segment C3 is 0b01, and the group relationship field Group of conditional instruction segment C4 is 0b01, then conditional instruction segment C1 and conditional instruction segment C2 are the same group, and conditional instruction segment C3 and conditional instruction segment C4 are the same group. The group relationship field can be used to represent the combination and priority relationship of a group of conditions in logical operations.

[0090] For example, the logical relationship field Relation indicates the logical relationship between the current condition and other conditions. For example, the logical relationship may include logical AND (AND, &&) and logical OR (OR, ||). For example, when the logical relationship field Relation is a first value (for example, 0), it indicates logical AND, and when the logical relationship field Relation is a second value (for example, 1), it indicates logical OR.

[0091] The group relationship field Group and the logical relationship field Relation can be used to describe the combination and priority relationship between multiple conditions in a multi-condition judgment instruction, clearly reflecting the nesting level and execution order of the condition judgment.

[0092] For example, the operation instruction is configured to execute a set data processing operation, where the set data processing operation includes implementing data transfer or a user-defined operation. Figure 5A A schematic diagram of an operation instruction provided for at least one embodiment of the present disclosure. Figure 5B A schematic diagram of another operation instruction provided for at least one embodiment of the present disclosure.

[0093] For example, if you set the data processing operation to a user-defined operation, such as Figure 5A As shown, the operation instruction includes: an instruction type field Type, a continuous sending field Seq / Non-Seq, an instruction number field Num, and a custom instruction interface field RS.

[0094] For example, if the data processing operation is set as a data transfer operation, such as Figure 5B As shown, the operation instruction includes: an instruction type field Type, a data extension field Fmt, a segment field Seg / Non-Seg, a data length field Length and an offset step field Stride.

[0095] For example, the instruction type field Type indicates the type of the current instruction. For example, when the instruction type field Type is a first value (for example, 0), it indicates that the data processing operation is set to a user-defined operation. When the instruction type field Type is a second value (for example, 1), it indicates that the data processing operation is set to a data transfer operation.

[0096] For example, the continuous sending field Seq / Non-Seq indicates whether multiple instructions are sent continuously. For example, when the continuous sending field Seq / Non-Seq is a first value (for example, 0), it means that multiple instructions are not sent continuously. When the continuous sending field Seq / Non-Seq is a second value (for example, 1), it means that multiple instructions are sent continuously.

[0097] For example, the instruction number field Num indicates the number of instructions to be sent. For example, when the instruction number field Num is 0b0010, 2 custom instructions will be sent in the continuous sending mode; when the instruction number field Num is 0b0101, 5 custom instructions will be sent in the continuous sending mode.

[0098] The embodiments of the present disclosure can indicate the sending tasks of multiple instructions at one time through a single field by setting a continuous sending field and an instruction number field, thereby improving instruction transmission efficiency and reducing unnecessary interaction overhead.

[0099] For example, the custom instruction interface field RS represents an interface definition applicable to a custom instruction, and the instruction content can be customized by software. For example, there can be only one custom instruction interface field RS, or there can be multiple custom instruction interface fields RS (such as RS1, RS2) according to actual needs, corresponding to different interface definitions, which is not limited in the embodiments of the present disclosure.

[0100] The above-mentioned embodiments of the present disclosure enhance the flexibility and scalability of the system by customizing the instruction interface field RS, so that the software can control and parse the custom instructions more accurately and efficiently.

[0101] For example, the data extension field Fmt is used to implement the data width expansion of the operation instruction. For example, when the data extension field Fmt is a first value (e.g., 0b00), it indicates that no expansion is performed; when the data extension field Fmt is a second value (e.g., 0b01), it indicates that the data width of the operation instruction is expanded by 32 bits; when the data extension field Fmt is a third value (e.g., 0b10), it indicates that the data width of the operation instruction is expanded by 64 bits. It should be noted that the expanded data width can be set according to actual needs, and the present disclosure does not limit this.

[0102] For example, the data extension field Fmt can be used to increase the bit width of the data length field Length and / or the offset step field Stride to indicate more data or a longer address distance. For example, when the data extension field Fmt is a first value (e.g., 0b00), it indicates that no extension is performed; when the data extension field Fmt is a second value (e.g., 0b01), it indicates that the bit width of the data length field Length is extended alone or the bit width of the offset step field Stride is extended alone; when the data extension field Fmt is a third value (e.g., 0b10), it indicates that the bit widths of the data length field Length and the offset step field Stride are extended at the same time.

[0103] For example, the segmentation field Seg / Non-Seg is used to indicate whether the operation instruction is a segmentation instruction. For example, when the segmentation field Seg / Non-Seg is a first value (for example, 0), it indicates that the operation instruction is not a segmentation instruction. When the segmentation field Seg / Non-Seg is a second value (for example, 1), it indicates that the operation instruction is a segmentation instruction.

[0104] For example, the data length field Length is used to indicate the length of the data to be transferred. For example, when the data length field Length is 0x0400, it means that the length of the data to be transferred is 1024 bytes. It should be noted that the unit of the data length can be set according to actual needs, and the embodiment of the present disclosure does not limit this.

[0105] For example, the offset step field Stride represents the data address offset step of the loop to be jumped to, that is, the offset that needs to be added to the data address corresponding to the current loop to obtain the data address corresponding to the next level loop. For example, when the offset step field Stride is 0x0100, it means that the offset step is 256 bytes. It should be noted that the unit of the offset step can be set according to actual needs, and the embodiments of the present disclosure do not limit this.

[0106] It should be noted that Figure 5A and Figure 5B It is only an example of the operation instruction provided in the embodiment of the present disclosure. Parameters may be increased or decreased according to actual needs, and the embodiment of the present disclosure does not limit this.

[0107] For example, an example of step S102 includes the following steps S201 to S206.

[0108] Step S201: receiving the loop initial instruction segment of the current loop.

[0109] Step S202: Decode the loop initial instruction segment to obtain at least one decoded conditional judgment instruction, wherein the at least one decoded conditional judgment instruction corresponds to at least one conditional judgment instruction in the loop initial instruction segment.

[0110] Step S203: Perform conditional judgment on at least one decoding conditional judgment instruction.

[0111] Step S204: determining the corresponding operation instruction according to the second jump address field corresponding to the decoding condition judgment instruction that meets the condition.

[0112] Step S205: Decode the operation instruction to obtain a decoded operation instruction executable by the neural network processor.

[0113] Step S206: Determine the first jump address field corresponding to the last decoding condition of the current loop and determine the next loop, and return to the above step S201.

[0114] For example, another example of step S102 includes the following steps S301 to S307 .

[0115] Step S301: receiving the first conditional judgment instruction of the current cycle.

[0116] Step S302: Decode the conditional judgment instruction to obtain a decoded conditional judgment instruction.

[0117] Step S303: Perform conditional judgment on the decoding conditional judgment instruction. If the condition is met, execute step S304, otherwise execute step S307.

[0118] Step S304: Determine the operation instruction according to the second jump address field corresponding to the decoding condition judgment instruction.

[0119] Step S305: Decode the operation instruction to obtain a decoded operation instruction executable by the neural network processor.

[0120] Step S306: Determine the next loop according to the first jump address field corresponding to the last conditional judgment instruction of the current loop, and return to execute step S301.

[0121] Step S307: Determine the next conditional judgment instruction, and execute the above steps S302 to S303 in a loop until the current loop ends.

[0122] The instruction processing method provided in the above-mentioned embodiments of the present disclosure provides an efficient instruction set definition, which enables the instruction processing device to perform efficient, highly robust, and highly scalable instruction control and generation, improves the efficiency of instruction sending, reduces the coprocessor load, and releases the coprocessor performance for other functions, thereby maximizing the utilization of system resources.

[0123] Figure 6 A schematic diagram of a loop initial instruction segment provided for at least one embodiment of the present disclosure.

[0124] For example, the loop initialization instruction segment includes a loop level field, at least one operation instruction, and at least one conditional judgment instruction. Figure 6 As shown, the loop initial instruction segment includes a loop level field ID, operation instructions OP0-OP4 and condition judgment instructions JC0-JC2.

[0125] For the related description of the loop level field and the operation instruction, please refer to the related content in the aforementioned embodiment, which will not be repeated here.

[0126] For example, in at least one example, each conditional judgment instruction in at least one conditional judgment instruction of the initial instruction segment of the loop is followed by one or more operation instructions. Figure 6 As shown, the conditional judgment instruction JC0 is followed by the operation instruction OP0, the conditional judgment instruction JC1 is followed by the operation instruction OP1, and the conditional judgment instruction JC2 is followed by the operation instructions OP2 to OP4.

[0127] For example, each conditional judgment instruction includes a first jump address field, which indicates the starting address of the loop to which the operation is to be jumped when the condition is not met. Figure 6 JC2 in also includes a second jump address field, which indicates the address of the instruction in the current loop to which the condition is jumped when the condition is met.

[0128] For example, if the condition corresponding to the conditional judgment instruction JC0 is established, the operation instruction OP0 following it is executed in sequence, and after the operation instruction OP0 is executed, it returns to the conditional judgment instruction JC1 to continue the conditional judgment; if the condition corresponding to the conditional judgment instruction JC0 is not established, it jumps to the corresponding loop level according to the first jump address field. For example, if the condition corresponding to the conditional judgment instruction JC2 is established, it jumps to the operation instruction corresponding to the conditional judgment instruction JC2 according to the second jump address field; if the condition is not established, it jumps to the corresponding loop level according to the first jump address field.

[0129] For example, each conditional judgment instruction also includes at least one conditional instruction segment.

[0130] Fig. 7A A schematic diagram of a single conditional judgment instruction provided for at least one embodiment of the present disclosure.

[0131] Take the conditional judgment instruction that is followed by only one operation instruction as an example, for example, Fig. 7A As shown, the conditional judgment instruction includes a conditional instruction segment C0 and a first jump address field Loop Addr. As described above, if the condition is not met, the first jump address field Loop Addr jumps to the corresponding loop level. The description of the conditional instruction segment C0 can refer to the relevant content of the above embodiment, which will not be repeated here.

[0132] Figure 7B A schematic diagram of a single conditional judgment instruction provided for at least one embodiment of the present disclosure.

[0133] Take the conditional judgment instruction followed by multiple operation instructions as an example, for example, Figure 7B As shown, the conditional judgment instruction includes a conditional instruction segment C0, a first jump address field Loop Addr and a second jump address field Instr Addr. As described above, if the condition is met, the corresponding operation instruction is jumped to according to the second jump address field Instr Addr. If the condition is not met, the corresponding loop level is jumped to according to the first jump address field Loop Addr.

[0134] The situation of multiple conditional judgment instructions is similar to the above and will not be repeated here.

[0135] For example, another example of step S102 includes the following steps S401 to S406.

[0136] Step S401: receiving the loop initial instruction segment of the current loop.

[0137] Step S402: Decode the loop initial instruction segment to obtain at least one decoded conditional judgment instruction, wherein the at least one decoded conditional judgment instruction corresponds to at least one conditional judgment instruction in the loop initial instruction segment.

[0138] Step S403: Perform conditional judgment on at least one decoding condition judgment instruction. If there is a decoding condition judgment instruction that meets the condition, execute step S404; otherwise, execute step S406.

[0139] Step S404: if the decoding condition judgment instruction that meets the condition is followed by an operation instruction, the operation instruction is directly determined; if the decoding condition judgment instruction that meets the condition is followed by multiple operation instructions, the operation instruction is determined according to the second jump address field corresponding to the decoding condition judgment instruction.

[0140] Step S405: Decode the operation instruction to obtain a decoded operation instruction executable by the neural network processor.

[0141] Step S406: Jump to the next loop according to the first jump address field corresponding to the instruction determined by the decoding condition, and return to the above step S401.

[0142] For example, yet another example of step S102 includes the following steps S501 to S506.

[0143] Step S501: receiving the first conditional judgment instruction of the current cycle.

[0144] Step S502: Decode the conditional judgment instruction to obtain a decoded conditional judgment instruction.

[0145] Step S503: Perform conditional judgment on the decoding condition judgment instruction. If there is a decoding condition judgment instruction that meets the condition, execute step S504, otherwise execute step S506.

[0146] Step S504: if the decoding condition judgment instruction is followed by an operation instruction, the operation instruction is directly determined; if the decoding condition judgment instruction is followed by multiple operation instructions, the operation instruction is determined according to the second jump address field corresponding to the decoding condition judgment instruction.

[0147] Step S505: Decode the operation instruction to obtain a decoded operation instruction executable by the neural network processor.

[0148] Step S506: Determine the next loop based on the first jump address field corresponding to the decoding condition judgment instruction, and return to the above step S501.

[0149] The instruction processing method provided in the above-mentioned embodiments of the present disclosure provides an efficient instruction set definition, in which each conditional judgment instruction and its corresponding operation instruction are pre-arranged by software, thereby reducing instruction jumps, thereby reducing hardware complexity and improving execution efficiency.

[0150] Figure 8 A schematic diagram of a loop initial instruction segment provided for at least one embodiment of the present disclosure.

[0151] For example, the loop initial instruction segment includes a loop level field and at least one operation instruction, but does not include a conditional judgment instruction. Figure 8 As shown, the loop initial instruction segment includes a loop level field ID and operation instructions OP0-OP5.

[0152] For the relevant description of the cycle level field, reference can be made to the relevant content in the aforementioned embodiment, which will not be repeated here.

[0153] Fig.9A A schematic diagram of an operation instruction provided by at least one embodiment of the present disclosure, Fig. 9B A schematic diagram of another operation instruction provided for at least one embodiment of the present disclosure.

[0154] For example, Fig.9A and Fig. 9B As shown, based on the operation instruction described in the above embodiment, the operation instruction may further include a third jump address field LoopInstr Addr.

[0155] For example, the third jump address field LoopInstr Addr indicates the address of the loop and instruction to which the operation instruction jumps when the operation instruction is executed, that is, the third jump address field LoopInstr Addr not only identifies the starting address of the loop, but also identifies the starting address of the instruction to be executed in the loop. For example, the third jump address field LoopInstrAddr can be used to jump to the position of the corresponding instruction in the corresponding loop level.

[0156] In this embodiment of the present disclosure, conditional judgment is performed by software instead of hardware, that is, the conditional judgment logic is transferred to the software level for organization and execution. In this case, the hardware no longer provides special conditional branch instructions or hardware circuits to perform conditional judgments. Instead, the software pre-calculates the sequence of operation instructions to be executed when the conditions are met, and arranges them in order according to the conditions (for example, Figure 8The operation instructions OP0~OP5 shown in the figure are used to simulate the conditional branch behavior. After executing the current instruction, based on the software's prediction and arrangement of the conditional judgment result in advance, it directly jumps to the next preset location for execution according to the content of the third jump address field LoopInstr Addr. In this way, it is only necessary to execute according to the instruction sequence arranged by the software, which reduces the hardware complexity and judgment logic, improves the working speed of the hardware, and also gives the software greater flexibility to better adapt to the dynamically changing conditional judgment needs.

[0157] For example, yet another example of step S102 includes the following steps S601 to S604.

[0158] Step S601: Receive the first instruction of the current cycle.

[0159] Step S602: Decode the instruction to obtain an operation instruction.

[0160] Step S603: Decode the operation instruction to obtain a decoded operation instruction executable by the neural network processor.

[0161] Step S604: Determine the next instruction according to the third jump address field corresponding to the operation instruction, and return to the above step S602 until all loops are completed.

[0162] For example, each of the at least one loop initial instruction segment provided by at least one embodiment may further include a space control field. The space control field indicates whether the current loop performs space allocation and the direction of space allocation.

[0163] For example, in physical space, there is a two-dimensional array composed of multiple space blocks (Packs), such as m space blocks in the X-axis direction and n space blocks in the Y-axis direction (a total of m×n space blocks). The data required for the current loop can be flexibly allocated and parallel processing can be performed according to different settings of the space control field.

[0164] For example, when the space control field is the first value (for example, 0b00), it indicates that no space allocation is performed; when the space control field is the second value (for example, 0b01), it indicates that the data required for the current loop is divided into m parts, which are respectively allocated to m space blocks in the X-axis direction to achieve parallel processing; when the space control field is the third value (for example, 0b10), it indicates that the data required for the current loop is divided into n parts, which are respectively allocated to n space blocks in the Y-axis direction to achieve parallel processing; when the space control field is the fourth value (for example, 0b11), it indicates that the data required for the current loop is divided into m×n parts, which are respectively allocated to m×n space blocks to achieve parallel processing.

[0165] The spatial control field determines how data is distributed in physical space to facilitate the parallel execution of cyclic tasks. It can flexibly adapt to the parallel computing needs in different scenarios, thereby greatly improving the speed of processing large amounts of data.

[0166] For example, the loop initialization instruction provided in at least one embodiment above may also include a loop initialization instruction set configuration code, and the loop initialization instruction set configuration code is configured to indicate a valid loop level. For example, the loop initialization instruction set configuration code includes a valid level field, which can be represented by a set of one-hot codes (One-Hot), and the invalid loop level corresponds to the first value (e.g., 0), and the valid loop level corresponds to the second value (e.g., 1). For example, assuming that there are 8 loop levels (0 to 7), if loop levels 0, 1, 6, and 7 are valid, and other loop levels (2 to 5) are invalid, then the one-hot code is represented as 11000011, where the 0th, 1st, 6th, and 7th bits of the binary number correspond to loop levels 0, 1, 6, and 7, respectively, and their values ​​are 1, indicating that these levels are valid, and the values ​​of other bits (2nd to 5th bits) are 0, indicating that these levels are invalid. It should be noted that the size of the valid level field can be set according to actual needs, such as 32bit, 64bit, etc., and the embodiments of the present disclosure are not limited to this.

[0167] For example, the loop initial instruction set configuration code is also configured to set the instruction set parameter bit width. For example, the loop initial instruction set configuration code includes a parameter bit width selection field. For example, when the parameter bit width selection field is a first value (for example, 0), the parameter bit width of the instruction is set to 16 bits; when the parameter bit width selection field is a second value (for example, 1), the parameter bit width of the instruction is set to 32 bits. When the parameter bit width of the instruction is set to 16 bits, a maximum of 64 layers of loops are supported. It should be noted that the parameter bit width of the instruction is set to 16 bits / 32 bits is only an example, and can also be set to other sizes according to actual needs. The embodiments of the present disclosure are not limited to this.

[0168] By configuring the initial instruction set of the loop, the attribute configuration of the instruction itself can be realized to indicate the number of loop levels.

[0169] At least one embodiment of the present disclosure also provides an instruction processing device, which provides an efficient instruction set, capable of efficient, highly robust, and highly scalable instruction control and generation, improving instruction sending efficiency, reducing coprocessor load, and releasing coprocessor performance for other functions, thereby maximizing system resource utilization. Furthermore, the instruction set design is relatively flexible, showing extremely high adaptability and scalability. It only needs to appropriately adjust and update the relevant module design inside the instruction processing device to adapt to and be compatible with different instruction set systems, and there is no need to comprehensively transform the infrastructure of the instruction processing device, thereby greatly simplifying the development process and reducing maintenance costs. For example, the instruction processing device can be a processing module that cooperates with the CPU provided in a central processing unit (CPU) or a system on chip (SOC), or it can be a coprocessor.

[0170] Fig.10 A schematic block diagram of an instruction processing device provided for at least one embodiment of the present disclosure.

[0171] For example, Fig.10 As shown, the instruction processing device 1000 includes an instruction receiving module 1001 and an instruction generating module 1002 .

[0172] For example, in at least one embodiment of the present disclosure, the instruction receiving module 1001 is configured to receive a loop initialization instruction. For example, the instruction receiving module 1001 can implement step S101, and its specific implementation method can refer to the relevant description of step S101, which will not be repeated here.

[0173] For example, in at least one embodiment of the present disclosure, the instruction generation module 1002 is configured to generate an executable instruction for the neural network processor based on the loop initial instruction, so as to provide it to the neural network processor for execution. The instruction generation module 1002 can set one or more instructions to support different contents, which can be set according to actual needs. For example, the instruction generation module 1002 can implement step S102, and its specific implementation method can refer to the relevant description of step S102, which will not be repeated here.

[0174] Fig.11 A schematic block diagram of another instruction processing device provided for at least one embodiment of the present disclosure.

[0175] For example, Fig.11 As shown, in at least one embodiment of the present disclosure, the instruction generation module 1002 includes a first decoding unit 1021 , a condition judgment unit 1022 , an address control unit 1023 , and a second decoding unit 1024 .

[0176] For example, in at least one embodiment of the present disclosure, the first decoding unit 1021 is configured to receive the loop initial instruction segment of the current loop and decode it to obtain at least one decoding condition judgment instruction; the condition judgment unit 1022 is configured to perform condition judgment on at least one decoding condition judgment instruction; the address control unit 1023 is configured to determine the corresponding operation instruction according to the second jump address field corresponding to the decoding condition judgment instruction that meets the condition; the second decoding unit 1024 is configured to decode the operation instruction to generate a decoding operation instruction executable by the neural network processor, and the address control unit 1023 is also configured to determine the next loop according to the first jump address field corresponding to the last decoding condition judgment instruction of the current loop to provide it to the first decoding unit 1021 for processing. For example, the instruction generation module 1002 can implement steps S201 to S205, and its specific implementation method can refer to the relevant description of steps S201 to S205, which will not be repeated here.

[0177] For example, in at least one embodiment of the present disclosure, the first decoding unit 1021 is configured to receive the first conditional judgment instruction of the current cycle and decode it to obtain a decoded conditional judgment instruction; the conditional judgment unit 1022 is configured to perform conditional judgment on the decoded conditional judgment instruction; the address control unit 1023 is configured to determine the operation instruction according to the second jump address field corresponding to the decoded conditional judgment instruction when the condition is met, and to determine the next conditional judgment instruction to provide to the first decoding unit 1021 for processing when the condition is not met; the second decoding unit 1024 is configured to decode the operation instruction to generate a decoded operation instruction executable by the neural network processor, wherein the address control unit 1023 is further configured to determine the next cycle according to the first jump address field corresponding to the last conditional judgment instruction of the current cycle to provide to the first decoding unit 1021 for processing. For example, the instruction generation module 1002 can implement steps S301 to S307, and its specific implementation method can refer to the relevant description of steps S301 to S307, which will not be repeated here.

[0178] For example, in at least one embodiment of the present disclosure, the first decoding unit 1021 is configured to receive the loop initial instruction segment of the current loop and decode it to obtain at least one decoding condition judgment instruction; the condition judgment unit 1022 is configured to perform conditional judgment on at least one decoding condition judgment instruction; the address control unit 1023 is configured to, when there is a decoding condition judgment instruction that meets the condition, directly determine the operation instruction if the decoding condition judgment instruction that meets the condition is followed by an operation instruction, and if the decoding condition judgment instruction that meets the condition is followed by multiple operation instructions, determine the operation instruction according to the second jump address field corresponding to the decoding condition judgment instruction, and when there is no decoding condition judgment instruction that meets the condition, determine the next loop according to the first jump address field corresponding to the decoding condition judgment instruction to provide it to the first decoding unit 1021 for processing; and the second decoding unit 1024 is configured to decode the operation instruction to generate a decoding operation instruction executable by the neural network processor. For example, the instruction generation module 1002 may implement steps S401 to S406 , and the specific implementation method thereof may refer to the relevant description of steps S401 to S406 , which will not be described in detail here.

[0179] For example, in at least one embodiment of the present disclosure, the first decoding unit 1021 is configured to receive the first conditional judgment instruction of the current cycle and decode it to obtain a decoding conditional judgment instruction; the conditional judgment unit 1022 is configured to perform conditional judgment on the decoding conditional judgment instruction; the address control unit 1023 is configured to directly determine the operation instruction if the decoding conditional judgment instruction is followed by an operation instruction when there is a decoding conditional judgment instruction that meets the condition, and if the decoding conditional judgment instruction that meets the condition is followed by multiple operation instructions, determine the operation instruction according to the second jump address field corresponding to the decoding conditional judgment instruction, and when the condition does not meet the condition, determine the next cycle according to the first jump address field corresponding to the decoding conditional judgment instruction to provide it to the first decoding unit 1021 for processing; the second decoding unit 1024 is configured to decode the operation instruction and generate a decoding operation instruction executable by the neural network processor. For example, the instruction generation module 1002 can implement steps S501 to S506, and its specific implementation method can refer to the relevant description of steps S501 to S506, which will not be repeated here.

[0180] Fig.12 A schematic block diagram of yet another instruction processing device provided for at least one embodiment of the present disclosure.

[0181] For example, in at least one embodiment of the present disclosure, the instruction generation module 1002 includes a first decoding unit 1021 , an address control unit 1023 , and a second decoding unit 1024 .

[0182] For example, in at least one embodiment of the present disclosure, the first decoding unit 1021 is configured to receive the first instruction of the current loop and decode it to obtain an operation instruction; the second decoding unit 1024 is configured to decode the operation instruction to generate a decoded operation instruction executable by the neural network processor; the address control unit 1023 is configured to determine the next instruction according to the third jump address field corresponding to the operation instruction to provide it to the first decoding unit 1021 for processing. For example, the instruction generation module 1002 can implement steps S601 to S603, and its specific implementation method can refer to the relevant description of steps S601 to S603, which will not be repeated here.

[0183] For example, Fig.11 and Fig.12 As shown, the instruction processing device 1000 provided by at least one embodiment of the present disclosure further includes an instruction analysis module 1003, and the instruction generation module 1002 further includes a register file 1025. For example, the instruction analysis module 1003 is configured to store the loop initialization instruction in sequence into the register file 1025. For example, the register file 1025 is configured to store the loop initialization instruction stored by the instruction analysis module 1003 for reading by the first decoding unit 1021 and the address control unit 1023.

[0184] For example, Fig.11 and Fig.12 As shown, in the instruction processing device 1000 provided in at least one embodiment of the present disclosure, the instruction receiving module 1001 includes an interface management unit 1011 and a cache unit 1012, the interface management unit 1011 is configured to receive a loop initialization instruction; the cache unit 1012 is configured to store the loop initialization instruction received by the interface management unit 1011.

[0185] In some examples, the cache unit 1012 is configured to store loop descriptors. In some examples, the cache unit 1012 can be a Ping-Pong Cache. For example, the Ping-Pong Cache includes at least two caches, each of which can read and write data independently. In practical applications, the number of caches can also be increased as needed. For example, when a cache is being written to a loop descriptor by an interface management unit, another cache can be read by other modules, and when the read and write operations are completed, the two roles are exchanged. By switching between the two caches, the idle waiting time between data reading and data writing can be avoided, the concurrent processing capability of the instruction processing device is enhanced, and the instruction processing device can efficiently process continuous instruction streams and data streams, ensuring the efficient execution of neural network calculations and the full utilization of resources.

[0186] For example, Fig.11 and Fig.12As shown, the instruction processing device 1000 provided by at least one embodiment of the present disclosure also includes an instruction distribution module 1004, which is configured to classify the executable instructions of the neural network processor and send them to the corresponding subsequent modules of the instruction processing device.

[0187] For example, the executable instructions of a neural network processor can be classified according to the functional characteristics and application purposes in a neural network processor or similar computing architecture. For example, the executable instructions of a neural network processor can be divided into standard instructions and custom instructions. Standard instructions usually include basic operations that are predefined, widely applicable and well-defined in hardware design, such as data handling instructions, loop end control instructions, filling instructions, etc.; custom instructions are designed to meet special needs in specific models or computing layers, and are defined at the software level to solve the problem that standard instructions may not be sufficient to efficiently execute certain highly optimized or novel algorithm operations in some complex neural network structures. Different types of executable instructions for neural network processors are sent to different post-level modules for processing through preset interfaces.

[0188] For example, Fig.11 and Fig.12 As shown, the instruction processing device 1000 provided by at least one embodiment of the present disclosure further includes an event synchronization module 1005, which is configured to coordinate event synchronization between different hardware modules.

[0189] For example, in at least one embodiment of the present disclosure, the loop initialization instruction includes at least one loop initialization instruction segment, each of the at least one loop initialization instruction segment corresponds to a loop level and includes: a loop level field, indicating the loop level of the current loop; and at least one operation instruction, configured to perform a set data processing operation.

[0190] For example, in at least one embodiment of the present disclosure, each of at least one loop initial instruction segment also includes: at least one conditional judgment instruction, configured to perform conditional judgment to control instruction jumping, and in response to the condition being met, jump to the operation instruction corresponding to the conditional judgment instruction.

[0191] For example, in at least one embodiment of the present disclosure, at least one conditional judgment instruction is arranged in sequence, and at least one operation instruction is set after all the conditional judgment instructions; the first conditional judgment instruction in at least one conditional judgment instruction includes: a first jump address field, indicating the starting address of the loop to which the condition is jumped when the condition is met; the second conditional judgment instruction in at least one conditional judgment instruction includes: a second jump address field, indicating the address of the instruction in the current loop to which the condition is jumped when the condition is met.

[0192] For example, in at least one embodiment of the present disclosure, each conditional judgment instruction in at least one conditional judgment instruction is followed by one or more operation instructions; each conditional judgment instruction includes: a first jump address field, indicating the starting address of the loop to which the condition is jumped when the condition is not met; the conditional judgment instruction followed by multiple operation instructions also includes: a second jump address field, indicating the address of the instruction in the current loop to which the condition is jumped when the condition is met.

[0193] For example, in at least one embodiment of the present disclosure, each of at least one conditional judgment instruction includes at least one conditional instruction segment, and each of at least one conditional instruction segment includes: a parameter address field, representing the parameter address of the first operand of the conditional judgment operation; a logical coding field, representing the coding of the comparison operator; and a judgment value field, representing the immediate value of the second operand of the conditional judgment operation.

[0194] For example, in at least one embodiment of the present disclosure, each of the at least one conditional judgment instruction also includes: an identification bit field, indicating whether the current instruction is a multi-conditional judgment instruction; and a condition number field, indicating the number of conditional instruction segments in the current instruction.

[0195] For example, in at least one embodiment of the present disclosure, in response to the identification bit field indicating that the current instruction is a multi-condition judgment instruction, each of the at least one conditional instruction segment also includes: a group relationship field, indicating the group relationship between the current condition and other conditions; and a logical relationship field, indicating the logical relationship between the current condition and other conditions.

[0196] For example, in at least one embodiment of the present disclosure, setting a data processing operation includes implementing data transfer or user-defined operations.

[0197] For example, in at least one embodiment of the present disclosure, the operation instruction includes: an instruction type field, indicating the type of the current instruction; a continuous sending field, indicating whether multiple instructions are sent continuously; an instruction number field, indicating the number of instructions that need to be sent; and a custom instruction interface field, indicating the interface definition applicable to the custom instruction.

[0198] For example, in at least one embodiment of the present disclosure, an operation instruction includes: an instruction type field, indicating the type of the current instruction; a data extension field, used to implement data width expansion of the operation instruction; a segmentation field, used to indicate whether the operation instruction is a segmented instruction; a data length field, used to indicate the length of the data to be moved; an offset step field, indicating the data address offset step of the loop to be jumped to.

[0199] For example, in at least one embodiment of the present disclosure, the operation instruction further includes: a third jump address field, indicating the address of the loop and instruction to which the operation instruction jumps when the operation instruction is executed.

[0200] For example, in at least one embodiment of the present disclosure, the loop initialization instruction also includes: a space control field indicating whether the current loop performs space allocation and the direction of space allocation; and / or a loop initialization instruction set configuration code configured to indicate a valid loop level.

[0201] For example, in at least one embodiment of the present disclosure, the loop initialization instruction set configuration encoding is further configured to set the instruction set parameter bit width.

[0202] It should be understood that the instruction processing device 1000 provided in at least one embodiment of the present disclosure can be used to implement the aforementioned instruction processing method, and can also achieve technical effects similar to the aforementioned instruction processing method, which will not be elaborated herein.

[0203] It should be noted that in the embodiments of the present disclosure, the instruction processing device 1000 may include more or fewer modules or units, and the connection relationship between the modules or units is not limited and can be determined according to actual needs. The specific configuration of each module is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or in other applicable ways.

[0204] Fig.13A A schematic block diagram of a chip system provided for at least one embodiment of the present disclosure.

[0205] For example, Fig.13A As shown, at least one embodiment of the present disclosure provides a chip system 1100, and the chip system 1100 includes an instruction processing device 1101 and a neural network processor 1102. For example, the instruction processing device 1101 is an instruction processing device provided by at least one embodiment of the present disclosure, for example, Fig.10. For example, the neural network processor 1102 is configured to execute neural network processor executable instructions. For example, the instruction processing device 1101 and the neural network processor 1102 may be a microprocessor or computing system for artificial intelligence hardware acceleration. For example, the instruction processing device 1101 and the neural network processor 1102 may be implemented based on an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). For example, the instruction processing device 1101 and the neural network processor 1102 may be integrated in a system-on-chip (SoC). For example, the neural network processor 1102 may be a row-fixed neural network processor (RS NPU). For example, the neural network processor 1102 may include a processing unit (PE) array, a global cache, and a memory. The processing unit array includes multiple rows and columns of processing units, which are coupled to each other through on-chip interconnects and share a global cache, and the on-chip interconnect is, for example, a network on chip (NoC). Each processing unit has a computing function, and for example, may also have its own local cache, such as a cache or register array including a multiplier accumulator and a vector (or matrix) for caching input. Each processing unit can access other processing units around it, its own local cache and global cache. The global cache is further coupled to the memory through, for example, a bus. The instruction processing device 1101 and the neural network processor 1102 can be connected through a custom interface.

[0206] Fig. 13B A schematic block diagram of a chip system provided for at least one embodiment of the present disclosure. For example, the chip system 1100 provided for at least one embodiment of the present disclosure further includes a processor 1103. For example, the processor 1103 is configured to send a loop initialization instruction to the instruction processing device 1101. For example, the processor may be a coprocessor, a central processing unit (CPU), or a general-purpose graphics processing unit (GPGPU), etc. For example, the instruction processing device 1101 may be driven and configured by the processor 1103, and the instruction processing device 1101 and the processor 1103 may be connected via an on-chip interconnect, such as an on-chip network (NoC). In addition, it is also possible to choose to connect via a custom interface.

[0207] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0208] There are a few points to note about this disclosure:

[0209] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0210] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0211] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0212] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An instruction processing device, comprising: An instruction receiving module is configured to receive a loop initialization instruction; An instruction generation module is configured to generate an executable instruction for a neural network processor based on the loop initial instruction, so as to provide the instruction to the neural network processor for execution. The loop initialization instruction includes at least one loop initialization instruction segment, each of the at least one loop initialization instruction segment corresponds to a loop level and includes: The loop level field indicates the loop level of the current loop; and At least one operation instruction is configured to execute a set data processing operation.

2. The instruction processing device according to claim 1, wherein the instruction generation module comprises: A first decoding unit is configured to receive and decode the loop initial instruction segment of the current loop to obtain at least one decoding condition judgment instruction; a conditional judgment unit, configured to perform conditional judgment on the at least one decoding conditional judgment instruction; An address control unit is configured to determine a corresponding operation instruction according to a second jump address field corresponding to the decoding condition judgment instruction that meets the condition; The second decoding unit is configured to decode the operation instruction to generate a decoding operation instruction executable by the neural network processor, The address control unit is further configured to determine the next cycle according to the first jump address field corresponding to the last decoding condition judgment instruction of the current cycle to provide it to the first decoding unit for processing.

3. The instruction processing device according to claim 1, wherein the instruction generation module comprises: A first decoding unit is configured to receive and decode the first conditional judgment instruction of the current cycle to obtain a decoded conditional judgment instruction; A conditional judgment unit, configured to perform conditional judgment on the decoding conditional judgment instruction; An address control unit configured to determine an operation instruction according to a second jump address field corresponding to the decoding condition judgment instruction when the condition is met, and to determine a next condition judgment instruction to provide to the first decoding unit for processing when the condition is not met; The second decoding unit is configured to decode the operation instruction to generate a decoding operation instruction executable by the neural network processor, The address control unit is further configured to determine the next cycle according to the first jump address field corresponding to the last conditional judgment instruction of the current cycle to provide it to the first decoding unit for processing.

4. The instruction processing device according to claim 1, wherein the instruction generation module comprises: A first decoding unit is configured to receive and decode the loop initial instruction segment of the current loop to obtain at least one decoding condition judgment instruction; a conditional judgment unit, configured to perform conditional judgment on the at least one decoding conditional judgment instruction; The address control unit is configured to, when there is a decoding condition judgment instruction that meets the condition, directly determine the operation instruction if the decoding condition judgment instruction that meets the condition is followed by an operation instruction, and if the decoding condition judgment instruction that meets the condition is followed by multiple operation instructions, determine the operation instruction according to the second jump address field corresponding to the decoding condition judgment instruction, and when there is no decoding condition judgment instruction that meets the condition, determine the next cycle according to the first jump address field corresponding to the decoding condition judgment instruction to provide it to the first decoding unit for processing; as well as The second decoding unit is configured to decode the operation instruction to generate a decoding operation instruction executable by the neural network processor.

5. The instruction processing device according to claim 1, wherein the instruction generation module comprises: A first decoding unit is configured to receive and decode the first conditional judgment instruction of the current cycle to obtain a decoded conditional judgment instruction; A conditional judgment unit, configured to perform conditional judgment on the decoding conditional judgment instruction; The address control unit is configured to, when there is a decoding condition judgment instruction that meets the condition, directly determine the operation instruction if the decoding condition judgment instruction is followed by an operation instruction, determine the operation instruction according to a second jump address field corresponding to the decoding condition judgment instruction if the decoding condition judgment instruction that meets the condition is followed by multiple operation instructions, and when the condition does not meet the condition, determine the next cycle according to a first jump address field corresponding to the decoding condition judgment instruction to provide it to the first decoding unit for processing; The second decoding unit is configured to decode the operation instruction to generate a decoding operation instruction executable by the neural network processor.

6. The instruction processing device according to claim 1, wherein the instruction generation module comprises: A first decoding unit is configured to receive and decode the first instruction of the current cycle to obtain an operation instruction; A second decoding unit is configured to decode the operation instruction to generate a decoded operation instruction executable by the neural network processor; The address control unit is configured to determine the next instruction according to the third jump address field corresponding to the operation instruction to provide the next instruction to the first decoding unit for processing.

7. The instruction processing device according to any one of claims 2 to 6, further comprising: Instruction analysis module, Wherein, the instruction generation module also includes a register file, The instruction analysis module is configured to store the loop initialization instructions in the register file in sequence; The register file is configured to store the loop initialization instruction stored by the instruction analysis module for reading by the first decoding unit and the address control unit.

8. The instruction processing device according to claim 1, wherein: The instruction receiving module includes an interface management unit and a cache unit. The interface management unit is configured to receive the cycle initialization instruction; The cache unit is configured to store the loop initiation instruction received by the interface management unit.

9. The instruction processing apparatus according to claim 1, further comprising: The instruction distribution module is configured to classify the executable instructions of the neural network processor and send them to the subsequent modules corresponding to the instruction processing device.

10. A method for processing an instruction, comprising: Receive loop initialization instructions; generating a neural network processor executable instruction based on the loop initial instruction, so as to provide the instruction to the neural network processor for execution, The loop initialization instruction includes at least one loop initialization instruction segment, each of the at least one loop initialization instruction segment corresponds to a loop level and includes: The loop level field indicates the loop level of the current loop; and At least one operation instruction is configured to execute a set data processing operation.

11. The instruction processing method according to claim 10, wherein: Each of the at least one loop initialization instruction segments further comprises: At least one conditional judgment instruction is configured to perform conditional judgment to control instruction jumping, and in response to the condition being met, jump to the operation instruction corresponding to the conditional judgment instruction.

12. The instruction processing method according to claim 11, wherein: The at least one conditional judgment instruction is arranged in sequence, and the at least one operation instruction is arranged after all the conditional judgment instructions; The first conditional judgment instruction in the at least one conditional judgment instruction comprises: The first jump address field indicates the starting address of the loop to which the condition is to be jumped when it is met; The second conditional judgment instruction in the at least one conditional judgment instruction comprises: The second jump address field indicates the address of the instruction in the current loop to which the jump occurs when the condition is met.

13. The instruction processing method according to claim 11, wherein: Each of the at least one conditional judgment instruction is followed by one or more operation instructions; Each conditional judgment instruction includes: The first jump address field indicates the starting address of the loop to which the condition jumps when the condition is not met; the condition judgment instruction following multiple operation instructions also includes: The second jump address field indicates the address of the instruction in the current loop to which the jump occurs when the condition is met.

14. The instruction processing method according to claim 11, wherein: Each of the at least one conditional judgment instruction includes at least one conditional instruction segment, wherein each of the at least one conditional instruction segment includes: The parameter address field indicates the parameter address of the first operand of the conditional judgment operation; Logical code field, indicating the code of the comparison operator; The judgment value field indicates the immediate value of the second operand of the conditional judgment operation.

15. The instruction processing method according to claim 14, wherein: Each of the at least one conditional judgment instructions further includes: The identification bit field indicates whether the current instruction is a multi-condition judgment instruction; The condition number field indicates the number of conditional instruction segments in the current instruction.

16. The instruction processing method according to claim 15, wherein: In response to the identification bit field indicating that the current instruction is a multi-condition judgment instruction, each of the at least one conditional instruction segment further includes: The group relationship field indicates the group relationship between the current condition and other conditions; The logical relationship field indicates the logical relationship between the current condition and other conditions.

17. The instruction processing method according to any one of claims 10 to 16, wherein: The setting of data processing operations includes: implementing data transfer or user-defined operations.

18. The instruction processing method according to claim 10, wherein: The operation instructions include: The instruction type field indicates the type of the current instruction; The continuous sending field indicates whether multiple instructions are sent continuously; The instruction number field indicates the number of instructions that need to be sent; The custom directive interface field indicates the interface definition applicable to the custom directive.

19. The instruction processing method according to claim 10, wherein: The operation instructions include: The instruction type field indicates the type of the current instruction; The data extension field is used to extend the data width of the operation instruction; A segmentation field is used to indicate whether the operation instruction is a segmentation instruction; The data length field is used to indicate the length of the data to be transferred; The offset step field indicates the data address offset step of the loop to be jumped to.

20. The instruction processing method according to claim 18 or 19, wherein: The operation instructions also include: The third jump address field indicates the address of the loop and instruction to which the operation instruction jumps when the operation instruction is executed.

21. The instruction processing method according to any one of claims 10 to 16, wherein: Each of the at least one loop initialization instruction segments further comprises: The space control field indicates whether the current loop performs space allocation and the direction of space allocation.

22. The instruction processing method according to claim 21, wherein: The loop initialization instructions also include: The loop initialization instruction set configuration encoding is configured to indicate the effective loop level and set the instruction set parameter bit width.

23. A chip system, comprising: The instruction processing device as claimed in claim 1; as well as A neural network processor is configured to execute the neural network processor executable instructions.

24. The chip system according to claim 23, further comprising: The processor is configured to send the loop initialization instruction to the instruction processing device.

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