A fault processing method, device and equipment

Abstract

The application relates to a fault processing method, device and equipment applied to a baseboard management controller (BMC), the method comprises the following steps: receiving an interrupt message triggered when a target server fails, obtaining a target number of target memory banks (Banks) corresponding to the fault; taking a preset position as a starting point, reading storage data of a first register of the target number from a fault file, and respectively determining a target Bank comprising the first register based on the storage data of each first register; the fault file is generated when the target server fails, and is used for storing information related to the current fault of the target server; the preset position is a starting position of the storage data of the first register related to the fault in the fault file; for each target Bank, the fault information corresponding to the target Bank is queried from the fault file, and a fault log is generated based on the fault information corresponding to the target Bank, so that the comprehensiveness and accuracy of RAS fault detection are improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a fault handling method, device, and equipment. Background Art

[0002] Currently, servers not only occupy a core position in traditional applications, but also play a vital role in emerging fields such as cloud computing, big data analysis, and artificial intelligence. While servers are widely used due to their excellent performance, problems with fault diagnosis and maintenance are gradually emerging.

[0003] In related technologies, when a server restarts due to a RAS (Reliability, Availability and Serviceability) failure, the BIOS (Basic Input / Output System) is triggered to read register information and transmit the register information to the BMC (Board Management Controller) through the IPMI (Intelligent Platform Management Interface) protocol for fault analysis.

[0004] However, when a RAS failure occurs on a server, other situations may occur besides server restart, such as server hang. In this case, the BIOS cannot be triggered to obtain register information, and thus the fault cannot be detected. Summary of the Invention

[0005] The present invention provides a fault handling method, apparatus and device for detecting RAS faults and generating corresponding fault logs when a RAS fault occurs in a server and does not result in a restart, thereby improving the comprehensiveness and accuracy of fault detection.

[0006] In a first aspect, the present application provides a fault handling method applied to a baseboard management controller (BMC), the method comprising:

[0007] Receive an interrupt message triggered when a target server fails, and obtain a target number of target memory banks corresponding to the failure; each target bank corresponds to a different failure type, and each target bank includes its own first register;

[0008] read, from the fault file, storage data of the target quantity of first registers starting from a preset position, and respectively determine a target Bank including the first registers based on the storage data of each first register; the fault file is generated when the target server fails, and is used to store information related to the current failure of the target server; the preset position is a starting position of the storage data of the first register related to the failure in the fault file;

[0009] For each target Bank, query the failure information corresponding to the target Bank from the fault file, and generate a failure log based on the failure information corresponding to the target Bank.

[0010] The above method can be applied to the case where the server fails in RAS and does not restart, and improves the comprehensiveness of failure detection. The BMC monitors the interrupt message in real time, obtains the storage data of the first register through the number of Banks after receiving the interrupt message, locates the Bank based on the storage data, and obtains the key register failure data based on the Bank. Not only can the register information of the Bank be accurately collected and analyzed, but also the corresponding log can be automatically generated and reported based on the analyzed failure information. At the same time, the BMC can independently perform RAS failure detection of the server without relying on other components, greatly improving the reliability and maintenance efficiency of the system.

[0011] In a possible implementation, the target quantity of Banks corresponding to the failure is obtained by:

[0012] The target quantity of Banks corresponding to the failure is obtained by calling a communication register between the BMC and a host of the target server through an advanced platform management link (AMPL);

[0013] Before the reading, from the fault file, storage data of the target quantity of first registers starting from a preset position, the method further includes:

[0014] It is determined that the target quantity is not zero.

[0015] The above method obtains the number of Banks corresponding to the failure effect through the AMPL to call the communication register, accurately obtains the number of Banks corresponding to the failure effect, and obtains the storage data of the register when the number is not zero, which can avoid resource waste caused by information acquisition when failure detection is not needed.

[0016] In a possible implementation, the storage data of the first register is data stored in a high address; and the target Bank including the first register is determined based on the storage data of each first register, including:

[0017] For each first register, split the stored data of the first register into first data corresponding to a high byte and second data corresponding to a low byte; the low byte represents a hard disk identifier corresponding to the target Bank; and the high byte represents an architecture type corresponding to the target Bank;

[0018] Based on the first data and the second data, query a target Bank including the first register from a data table; the data table is used to store a hard disk identifier and an architecture type corresponding to each Bank.

[0019] The above method splits the stored data of the first register, and combines and queries the Bank including the first register based on the split high byte and low byte, so as to accurately locate the target Bank.

[0020] In a possible implementation, the target Bank further includes at least one second register; the failure information corresponding to the target Bank includes stored data of each second register; and the querying of the failure information corresponding to the target Bank from the failure file includes:

[0021] Based on the identifier of the target Bank, determining address offset information of each second register included in the target Bank;

[0022] For each second register, based on the address offset information of the second register, querying the stored data of the second register from the failure file.

[0023] The above method determines the address offset information of each second register based on the identifier of the target Bank, and then queries the stored data of the second register based on the address offset information, thereby providing a specific and accurate way to obtain the stored data of each second register.

[0024] In a possible implementation, the method further includes:

[0025] If the interrupt message is not received and it is determined that the target server restarts, register information sent by a basic input output system (BIOS) is obtained, and a failure log is generated based on the register information.

[0026] The above method obtains the register information sent by the BIOS for the failure that cannot trigger the above interrupt message, and generates a failure log based on the register information, so as to be analyzed and processed subsequently. Through the cooperation of the above two methods, the comprehensive detection and response to the system failure of the server are ensured.

[0027] In a possible implementation, the fault log includes a device type corresponding to the fault, and the generating of the fault log based on the fault information corresponding to the target Bank includes:

[0028] The fault information corresponding to the target Bank is matched with reference fault information corresponding to each type of device to determine a device type corresponding to the fault information, wherein the device type includes at least one of a processor, a memory, and a bus.

[0029] The above method provides a specific fault information analysis method, and by matching the fault information with reference fault information corresponding to each type of device, the device type corresponding to the fault information can be accurately determined.

[0030] In a second aspect, an embodiment of the present application provides a fault processing apparatus applied to a baseboard management controller (BMC), and the apparatus includes:

[0031] A receiving module is configured to receive an interrupt message triggered when a target server fails, and to obtain a target number of target Banks corresponding to the fault; each target Bank corresponds to a different fault type, and each target Bank includes a respective first register.

[0032] A determining module is configured to read storage data of the target number of first registers from a fault file starting from a preset position, and to determine a target Bank including each first register based on the storage data of each first register; the fault file is generated when the target server fails, and is used to store information related to a current fault of the target server; and the preset position is a starting position of the storage data of the first register related to the fault in the fault file.

[0033] A generating module is configured to query, for each target Bank, fault information corresponding to the target Bank from the fault file, and to generate a fault log based on the fault information corresponding to the target Bank.

[0034] In a possible implementation, the receiving module is specifically configured to:

[0035] The receiving module is specifically configured to:

[0036] Before the determining module reads the values of the target number of first registers from the fault file starting from the preset position, the determining module is further configured to:

[0037] The determining module determines that the target number is not zero.

[0038] In a possible implementation, the stored data of the first register is data stored in a high address; the determining module is specifically configured to:

[0039] For each first register, the stored data of the first register is split into first data corresponding to a high byte and second data corresponding to a low byte; the low byte represents a hard disk identifier corresponding to the target Bank; and the high byte represents an architecture type corresponding to the target Bank.

[0040] Based on the first data and the second data, a target Bank including the first register is queried from a data table; the data table is configured to store a hard disk identifier and an architecture type corresponding to each Bank.

[0041] In a possible implementation, the target Bank further includes at least one second register; the failure information corresponding to the target Bank includes stored data of each second register; and the generating module is specifically configured to:

[0042] Based on the identifier of the target Bank, address offset information of each second register included in the target Bank is determined;

[0043] For each second register, based on the address offset information of the second register, stored data of the second register is queried from the failure file.

[0044] In a possible implementation, the apparatus further includes an obtaining module, which is specifically configured to:

[0045] If the interrupt message is not received and it is determined that the target server is restarted, register information sent by a basic input output system (BIOS) is obtained, and a failure log is generated based on the register information.

[0046] In a possible implementation, the failure log includes a device type corresponding to a failure; and the generating module is specifically configured to:

[0047] The failure information corresponding to the target Bank is matched with reference failure information corresponding to each type of device to determine a device type corresponding to the failure information; the device type includes at least one of a processor, a memory, and a bus.

[0048] In a third aspect, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor; when the processor executes the computer program, the steps in the failure processing method are implemented.

[0049] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, having stored thereon a computer program, which, when executed by a processor, implements the steps of the fault processing method of the present application.

[0050] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program stored in a computer readable storage medium; when a processor of a memory access device reads the computer program from the computer readable storage medium, the processor executes the computer program, so that the memory access device executes the steps of the fault processing method of the present application.

[0051] The technical effects of each of the above-mentioned second to fifth aspects and each aspect that can be achieved are described above with respect to the first aspect or the various possible schemes in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0053] Figure 1 A flowchart of a fault processing method provided by an embodiment of the present application;

[0054] Figure 2 A schematic diagram of a fault processing process provided by an embodiment of the present application;

[0055] Figure 3 A schematic diagram of a fault processing device provided by an embodiment of the present application;

[0056] Figure 4 A schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. The specific operation methods in the method embodiments can also be applied to the device embodiments or system embodiments.

[0058] In the description of the present application, "multiple" is understood as "at least two". The association relationship of "and / or" describing the associated objects means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. A is connected with B, which can represent: A is directly connected with B and A is connected with B through C. In addition, in the description of the present application, "first", "second", and the like are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor indicating or implying order.

[0059] In order for those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, the professional terms involved are briefly described as follows:

[0060] (1) BMC (Baseboard Management Controller): a dedicated management microcontroller for servers. It provides a standard interface and management tool for system monitoring, management and maintenance. BMC monitors the hardware state of the device and performs remote management operations through the hardware manager integrated in the server, network device and other computer systems.

[0061] (2) MailBox: a set of registers for communication between BMC and server host, used for remote management and monitoring of server hardware.

[0062] (3) SB-RMI (Sideband Remote Management Interface): a remote management interface related to APML (Advanced Platform Management Link).

[0063] (4) RAS: refers to the reliability (Reliability), availability (Availability) and serviceability (Serviceability) of the machine.

[0064] (5) BIOS (Basic Input Output System): a set of programs solidified to the motherboard in the computer system, used to detect whether any hardware device in the computer system has an error, and when any hardware device is detected to have an error, corresponding processing is performed according to the severity of the error.

[0065] (6) PCIe (PCI Express): A kind of Peripheral Component Interconnect (PCI) computer bus, PCIe devices are devices that comply with the high-speed serial computer expansion bus standard, such as network cards, graphics cards, hard drives, and GPUs (graphics processing units).

[0066] Currently, servers not only occupy a core position in traditional applications, but also play a crucial role in emerging fields such as cloud computing, big data analysis, and artificial intelligence. Among them, AMD servers are widely used due to their excellent performance, and their fault diagnosis and maintenance problems have gradually become prominent. Currently, many manufacturers often face the problem of inaccurate diagnosis when dealing with RAS (Reliability, Availability and Serviceability) faults of servers. Specifically, due to the inability to clearly distinguish specific fault components, the troubleshooting efficiency is low, and the maintainability of the server is challenged. To improve the reliability and maintainability of the server, when a RAS fault occurs, it is necessary to deeply analyze the register information and accurately locate the fault source through precise data analysis to ensure the efficiency and accuracy of server fault handling, and thus ensure the stable operation of the server system.

[0067] In related technologies, when a server restarts due to a RAS fault, the BIOS (Basic Input Output System) reads the register information and transmits the register information to the BMC (Board Management Controller) through the IPMI (Intellingent Platform Management Interface) protocol for fault analysis.

[0068] However, this method has certain limitations. First, the BIOS fault detection method requires server restart to trigger, and when the server has a RAS fault, there may be other situations besides restart, such as hanging, etc. In this case, BIOS cannot be triggered to obtain register information, and further fault detection cannot be performed, so the BIOS can only detect a limited type of fault, and there is a risk of omission. Second, BIOS can only deliver fault information to BMC after server restart, which may cause the fault server environment to be damaged, affecting the real-time and accuracy of fault troubleshooting. In addition, since BMC cannot directly access the original register information when a RAS fault occurs in this method, but relies on BIOS to deliver information, this indirect method reduces the reliability of information transmission, and limits the types and number of fault analysis by BMC, making it difficult to achieve accurate analysis of RAS faults. If BIOS misreports, it will greatly affect the number and accuracy of RAS fault detection.

[0069] To improve the comprehensiveness and accuracy of fault handling, and the reliability and maintainability of the server, the embodiments of the present application provide a fault handling method applied to this scenario. When the server encounters a RAS fault during operation, the APML (Advanced Platform Management Link) triggers an interrupt response in real time. Subsequently, the BMC starts the register information capture process after receiving the APML interrupt message, directly reads the relevant register information when the RAS fault occurs, and performs in-depth analysis on it, and generates the corresponding SEL (System Event Log) for subsequent review. This method can significantly improve the comprehensiveness and accuracy of server fault response, thereby providing more stable and reliable services for users.

[0070] The present application will be described in further detail below with reference to the accompanying drawings, which shows Figure 1 The method is applied to a BMC integrated in a target server, and the specific implementation process is as follows:

[0071] Step S101, receiving an interrupt message triggered when a target server has a fault, obtaining a target number of target Banks corresponding to the fault;

[0072] In the embodiments of the present application, the target server includes a plurality of Banks (memory banks), such as LS, IF, L2, L3, etc., each target Bank corresponds to a different fault type, and each target Bank includes a respective first register, specifically, each Bank includes a plurality of registers including the first register; the registers include but are not limited to: CTL register, STATUS register, IPID register, etc.; in some embodiments, the first register is an IPID register, which is used to record error-related physical location information.

[0073] In a possible implementation, the above interrupt message is an Alert interrupt message, which is triggered by APML when the target server has a fault (such as Fatal Error, etc.) and the CPU in the target server remains Hang (suspended state) without restarting. After the CPU triggers the interrupt message, the interrupt message is reported to the BMC.

[0074] In some embodiments, after the BMC receives the interrupt message, the BMC obtains the register information related to the fault through the SB-RMI register.

[0075] In a possible implementation, the BMC obtains the target number of target Banks corresponding to the fault by invoking the communication register between the BMC and the host of the target server through AMPL; specifically, the BMC detects the interrupt message, invokes APML to send a command (specifically, 0x43 command) to the MailBox, and the MailBox obtains the number of Banks (i.e., the target number) corresponding to the current fault based on the command and returns it to the BMC.

[0076] In some embodiments, after obtaining the target number, the BMC further performs the following operations: determining whether there is an UCE (Uncorrectable Memory Error) fault based on the target number, triggering subsequent fault handling operations if it is determined that there is an UCE fault, and not performing the following steps S202-S203 if it is determined that there is no UCE fault. In a specific implementation, if it is determined that the target number is not zero, it can be determined that there is an UCE fault.

[0077] In the embodiments of the present application, after the BMC determines that the target server has an UCE fault based on the target number, the CPU of the target server is triggered to collect fault information from each register of the target server, and save the obtained fault information into a fault file according to a preset rule (i.e., the rule of the storage location of each type of fault information). In a specific implementation, the fault file can be a ras-error.cper file.

[0078] In a possible implementation, to ensure comprehensive detection of server failures, the failure processing process in the embodiments of the present application specifically includes the following two aspects:

[0079] For the failure that can trigger the above interrupt message, the BMC will collect Bank information by invoking the BailBox command after receiving the interrupt message, and generate the related failure log.

[0080] For the failure that cannot trigger the above interrupt message, such as PCIe failure, when the BMC does not receive the interrupt message and determines that the target server restarts, the register information sent by the BIOS is obtained, and the failure log is generated based on the register information.

[0081] In a specific implementation, when the target server fails and restarts, the BIOS performs failure detection and transmits the related register information to the BMC through the IPMI command; the BMC analyzes the register information sent by the BIOS and generates the failure log after receiving the register information, for subsequent analysis and processing. Through the cooperation of the above two methods, comprehensive detection and response to system failures of the server are ensured.

[0082] In step S102, the storage data of the target number of first registers is read from the failure file starting from the preset position, and the target Bank including the first registers is determined based on the storage data of each first register.

[0083] The failure file is generated when the target server fails, and is used to store information related to the current failure of the target server. The preset position is the starting position of the storage data of the first register related to the failure in the failure file.

[0084] In some embodiments, the failure file is that the CPU of the target server collects failure information from each register of the target server, and saves it into the failure file according to a preset rule. The preset rule includes the storage position (i.e. address offset information) of each type of failure information, for example, the position corresponding to the IPID register information related to the failure.

[0085] Optionally, the storage position corresponding to each type of failure information is specified in advance and recorded in a record manual, so that the storage position of each type of failure information can be directly queried from the record manual in the future, and the corresponding register data is read from the failure file.

[0086] In some embodiments, the first register is an IPID register, and the process of reading the target number of storage data of the first register from the failure file starting from the preset position is: obtaining address offset information corresponding to the IPID register (i.e., the preset position), and determining target positions of each first register to be read based on the target number and the address offset information, and reading the storage data of each first register from the failure file based on the target positions.

[0087] In a specific implementation, the address offset information is queried from the record manual, and the address offset information corresponding to each register includes a high-bit address offset Offset_High and a low-bit address offset Offset_Low. The preset position in the present application refers to the high-bit address offset of the IPID register. Since the storage data of the IPID register includes 8 bytes, the high-bit address offset refers to the offset corresponding to the high 4 bytes, which can be specifically 0x2c. Based on the high-bit address offset and the target number, the storage data of each first register related to the current failure can be obtained.

[0088] In a possible real-time manner, when the target positions of each first register to be read are determined, a subscript corresponding to the target number can be obtained based on a preset mapping relationship between the target number and the subscript. It should be noted that the mapping relationship is preset, and the number of subscripts is the target number. For example, when the target number is 1, the subscript is 0; when the target number is 2, the subscripts are 0 and 1; when the target number is 3, the subscripts are 0, 1, and 2, and so on.

[0089] After obtaining the subscript corresponding to the target number, the target positions of each first register to be read are determined based on each subscript and the preset position. In a specific implementation, the value of each subscript can be added to the target position (i.e., the high-bit address offset), that is, the target position is obtained by offsetting 0x2c based on the value of the subscript, and the storage data of each first register is read therefrom.

[0090] In a possible embodiment, the first storage data is data stored in a high-bit address of the corresponding first register; and the target Bank including the first register is determined based on the first storage data of each first register, specifically including:

[0091] For each first register, the first storage data of the first register is split into first data corresponding to a high-bit byte and second data corresponding to a low-bit byte; wherein the low-bit byte represents a hard disk identifier corresponding to the target Bank, and the high-bit byte represents an architecture type corresponding to the target Bank.

[0092] query a target Bank including the first register from a data table based on the first data and the second data, wherein the data table is configured to store a hard disk identifier corresponding to each Bank and an architecture type.

[0093] In a specific implementation, the storage data of the IPID register includes 8 bytes, and the data stored in the high address of the IPID register is the high 4 bytes of the storage data. In the 4 bytes, the low 2 bytes represent a hard disk identifier HardWareID corresponding to the target Bank, and the high 2 bytes represent an McaType (Machine Check Architecture Type) corresponding to the target Bank. Through the two key identifiers HardWareID and McaType, the BMC can accurately locate the Bank including the IPID register, that is, locate the Bank where the RAS fault occurs. After the target Bank is determined, the BMC can accurately obtain the register information under the target Bank.

[0094] For example, the Bank is LS, after the data stored in the high address of the IPID register is read, the second data HardWareID corresponding to the low byte is obtained, and the value of the second data is 0xb0. At the same time, the first data McaType corresponding to the high byte is obtained, and the value of the first data is 0x10. Since the data table stores the HardWareID value and the McaType value corresponding to each Bank, the Bank is matched to LS from the data table based on the first data and the second data.

[0095] In step S103, for each target Bank, the fault information corresponding to the target Bank is queried from the fault file, and the fault log is generated based on the fault information corresponding to the target Bank.

[0096] In a possible implementation, the target Bank further includes at least one second register, and the fault information corresponding to the target Bank includes the storage data of each second register. The fault information corresponding to the target Bank is queried from the fault file, and specifically includes:

[0097] Based on the identifier of the target Bank, the address offset information of each second register included in the target Bank is determined. For each second register, the storage data corresponding to the second register is queried from the fault file based on the address offset information of the second register.

[0098] In some embodiments, each target Bank includes a plurality of registers, such as an IPID register, a CTL register, a STATUS register, an ADDR register, and the like. The second register in the embodiments of the present application refers to a pre-designated register from the plurality of registers, and the designated relationship can be set based on requirements. For example, when it is required to obtain the register information of the CTL register and the STATUS register corresponding to the target Bank, the second register can include the CTL register and the STATUS register.

[0099] In some embodiments, the storage locations corresponding to the respective registers (i.e., the address offset information described above) are pre-stored in the embodiments of the present application. For each register, the storage location corresponding thereto includes a high-bit address offset and a low-bit address offset. Therefore, when the storage data corresponding to the second register is queried from the fault file, the high-bit address offset and the low-bit address offset of the second register are first obtained, the high-bit data corresponding to the second register is queried from the fault file based on the high-bit address offset, and the low-bit data corresponding to the second register is queried from the fault file based on the low-bit address offset. The high-bit data and the low-bit data are combined to obtain the storage data of the second register.

[0100] Optionally, when the storage data of the register is 8 bytes, the querying process adopts 4 bytes as a unit, that is, each register needs to be queried twice through the high bit (4 bytes) and the low bit (4 bytes) and then combined.

[0101] In a possible implementation, since only the partial storage data corresponding to the high-bit address offset is queried when the storage data of the IPID register is queried, when the fault information corresponding to the target Bank is queried from the fault file, the low-bit address offset corresponding to the IPID register also needs to be obtained, the low-bit data corresponding to the IPID register is queried from the fault file based on the low-bit address offset, and the low-bit data is combined with the high-bit data queried previously to obtain the complete storage data of the IPID register.

[0102] In some embodiments, the fault information corresponding to the target Bank is queried from the fault file, and the fault information is saved in a file in a Json format. Then, the parsing module of the BMC parses the Json file to generate a corresponding fault log.

[0103] It should be noted that the file format described above is not limited to Json, but can also be a file in another format.

[0104] In a possible implementation, the fault log described above includes the device type corresponding to the fault, and the fault log is generated based on the fault information corresponding to the target Bank, and specifically includes:

[0105] Match the fault information corresponding to the target Bank with the reference fault information corresponding to each type of device to determine the device type corresponding to the fault information; wherein the device type includes: at least one of: processor (such as CPU), memory and bus (such as PCIe).

[0106] In the specific implementation, the BMC performs an in-depth analysis of the file storing the fault information, and determines the fault type of the target server based on the fault information. The fault type can be classified into three major categories (i.e., device type): CPU, memory, and PCIe. Each major category can be further refined into multiple specific subcategories to ensure the accuracy of fault identification. It should be noted that this application does not impose any restrictions on the division of the fault category, and the degree of refinement and number of the divided types can be determined based on demand. After the analysis is completed, the BMC generates the corresponding SEL log based on the parsed register information and fault type, and saves it to the specified file.

[0107] Optionally, the process of the BMC parsing the fault information may include: presetting reference fault information corresponding to each fault type, matching the acquired fault information with each reference fault information, and determining the current fault type.

[0108] In some embodiments, the present application can also trigger an alarm operation after querying the fault information, for example, by generating an alarm log and notifying related personnel (which can be set based on needs, such as setting it to operation and maintenance personnel), to promptly remind related personnel to handle the fault.

[0109] By viewing the SEL log, server operation and maintenance personnel can quickly and accurately locate the server's operating status and specific sub-category faults in the CPU, memory, or PCIe, and promptly replace and repair faulty components, thereby significantly improving the server's maintainability and operational stability.

[0110] With the above method, when a server fails, the CPU triggers an Alert interrupt message and sends it to the BMC. After receiving the interrupt message, the BMC uses APML technology to efficiently collect register information related to the fault, and performs fault analysis and comprehensive diagnosis on the collected information, thereby accurately detecting RAS faults in the server. This can greatly improve the accuracy of server diagnosis. After testing, its fault accuracy can be increased to more than 95% (fault accuracy = fault that can be clearly monitored specifications / total number of faults). This method significantly improves the efficiency and accuracy of server fault handling, providing strong support for server operation and maintenance.

[0111] The following combination Figure 2 The above troubleshooting process is described in detail using a specific example. The process specifically includes the following steps:

[0112] Step S201, when the RAS fault occurs, the BMC determines whether the Alert interrupt message is received; if yes, step S202 is executed, otherwise step S205 is executed;

[0113] Step S202, the MailBox command is sent through the APML to collect the IPID register information related to the current fault; the register information is the storage data corresponding to the high address offset of the IPID register;

[0114] Step S203, according to the HardWare ID and the Mca Type in the IPID register information, the target Bank is matched from each Bank;

[0115] Optionally, each Bank includes LS, IF, L2, PCIe and the like.

[0116] Step S204, the register information corresponding to the target Bank is collected and saved in the Json file;

[0117] Step S205, the fault detection is performed through the BIOS to collect the register information and save it in the Json file;

[0118] Step S206, the Json file is parsed to determine the device type (i.e. specific component) corresponding to the current fault; the device type includes but is not limited to CPU, memory and PCIe.

[0119] Step S207, the SEL log is generated based on the parsing result and saved to the specified file; so as to be viewed by the operation and maintenance personnel.

[0120] Optionally, the SEL log can also carry the processing suggestion for each RAS fault, which can be implemented in the following manner: the processing suggestions corresponding to various RAS faults are set in advance, after the Json file is parsed to determine each RAS fault, the processing suggestion corresponding to the RAS fault is obtained and stored in the SEL log, so as to facilitate the operation and maintenance personnel to diagnose and handle the fault.

[0121] The application is directed to a high-efficiency fault processing mechanism for RAS failure of a server. When the RAS failure occurs, the BMC detects the Alert interrupt message sent by the CPU and collects the key register data in real time and stores the register data in the BMC. The process ensures that the server can accurately collect and analyze the Bank register information after the failure. The BMC generates and reports the corresponding SEL log according to the analyzed register information, and saves the register information to a local file. The logs and files provide detailed fault information for the server operation and maintenance personnel, ensure accurate positioning of the server running state, and quickly identify the problematic components. Based on the logs and fault information files, the operation and maintenance personnel can quickly replace the problematic components, thereby accurately and quickly troubleshooting. In summary, the method not only improves the maintainability of the server, but also greatly shortens the troubleshooting and repair time, effectively ensuring the stable operation of the server.

[0122] Based on the same inventive concept, the application also provides a fault processing device, see Figure 3 The device comprises:

[0123] The receiving module 301 is configured to receive an interrupt message triggered when a target server fails, and obtain a target number of target banks corresponding to the failure; each target bank corresponds to a different fault type, and each target bank comprises a first register thereof;

[0124] The determining module 302 is configured to read the storage data of the first registers of the target number from a fault file from a preset position as a starting point, and determine the target bank comprising the first registers based on the storage data of each first register; the fault file is generated when the target server fails, and is used to store information related to the current failure of the target server; and the preset position is the starting position of the storage data of the first registers related to the failure in the fault file;

[0125] The generating module 303 is configured to query the fault information corresponding to each target Bank from the fault file, and generate a fault log based on the fault information corresponding to the target Bank.

[0126] In a possible implementation, the receiving module 301 is specifically configured to:

[0127] The communication register between the BMC and the host of the target server is called through the advanced platform management link (AMPL) to obtain the target number of target Banks corresponding to the failure;

[0128] Before reading the values ​​of the target number of first registers from the fault file starting from the preset position, the determination module 302 is further configured to:

[0129] Make sure the target quantity above is not zero.

[0130] In a possible implementation manner, the data stored in the first register is data stored in a high-order address; and the determining module 302 is specifically configured to:

[0131] For each first register, split the stored data of the first register into first data corresponding to a high-order byte and second data corresponding to a low-order byte; the low-order byte represents a hard disk identifier corresponding to the target bank; the high-order byte represents an architecture type corresponding to the target bank;

[0132] Based on the first data and the second data, the target bank including the first register is searched from the data table; the data table is used to store: the hard disk identifier and architecture type corresponding to each bank.

[0133] In a possible implementation, the target Bank further includes at least one second register; the fault information corresponding to the target Bank includes the stored data of each second register; and the generating module 303 is specifically configured to:

[0134] Determining address offset information of each second register included in the target bank based on the identifier of the target bank;

[0135] For each second register, based on the address offset information of the second register, the stored data of the second register is queried from the fault file.

[0136] In a possible implementation, the apparatus further includes an acquisition module, specifically configured to:

[0137] If the interrupt message is not received and it is determined that the target server has been restarted, register information sent through a basic input and output system BIOS is obtained, and a fault log is generated based on the register information.

[0138] In a possible implementation, the fault log includes the device type corresponding to the fault, and the generating module 303 is specifically configured to:

[0139] Match the fault information corresponding to the target Bank with the reference fault information corresponding to each type of device to determine the device type corresponding to the fault information; wherein the device type includes at least one of a processor, a memory, and a bus.

[0140] Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which can realize the functions of the foregoing fault processing apparatus, and refer to Figure 4 , the electronic device comprises:

[0141] at least one processor 401 and a memory 402 connected with the at least one processor 401, and the specific connection medium between the processor 401 and the memory 402 is not limited in the embodiment of the present application, Figure 4 In the embodiment, the connection between the processor 401 and the memory 402 is taken as an example of connection through a bus 400. The bus 400 is used to connect Figure 4 In the embodiment, the connection between the processor 401 and the memory 402 is taken as an example of connection through a bus 400. The bus 400 is used to connect Figure 4 In the embodiment, the connection between the processor 401 and the memory 402 is taken as an example of connection through a bus 400. The bus 400 is used to connect

[0142] In the embodiment of the present application, the memory 402 stores instructions executable by the at least one processor 401, and the at least one processor 401 can execute the fault processing method discussed above by executing the instructions stored in the memory 402. The processor 401 can realize the functions of various modules in the apparatus shown in Figure 3

[0143] In the embodiment of the present application, the memory 402 stores instructions executable by the at least one processor 401, and the at least one processor 401 can execute the fault processing method discussed above by executing the instructions stored in the memory 402. The processor 401 can realize the functions of various modules in the apparatus shown in

[0144] In a possible design, the processor 401 can include one or more processing units, and the processor 401 can integrate an application processor and a modem processor, wherein the application processor mainly processes operating systems, user interfaces, application programs and the like, and the modem processor mainly processes wireless communication. It can be understood that the foregoing modem processor can also not be integrated into the processor 401. In some embodiments, the processor 401 and the memory 402 can be implemented on the same chip, and in some embodiments, they can also be implemented on independent chips respectively.

[0145] ​The processor 401 can be a general processor, such as a central processing unit (CPU), a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, and can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or any conventional processor. The steps of the fault processing method disclosed in the embodiments of the present application can be directly embodied as execution of a hardware processor, or execution of a combination of hardware and software modules in the processor.

[0146] The memory 402 is a non-volatile computer readable storage medium, which can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 402 can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card type memory, random access memory (RAM), static random access memory (SRAM), programmable read only memory (PROM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. The memory 402 is any other medium capable of carrying or storing desired program code in the form of instructions or data structures and capable of being accessed by a computer, but is not limited to this. The memory 402 in the embodiments of the present application can also be a circuit or any other device capable of realizing a storage function, used to store program instructions and / or data.

[0147] By designing and programming the processor 401, the code corresponding to the application exception detection method introduced in the foregoing embodiments can be fixed in the chip, so that the chip can execute the steps of the fault processing method of the embodiments shown in the running time. Figure 1 How to design and program the processor 401 is a technology known to those skilled in the art, which will not be described here.

[0148] The embodiments of the present application also provide a computer readable storage medium storing computer executable instructions required for execution of the processor, which contains programs required for execution of the processor.

[0149] In some possible implementation, each of the aspects of the fault processing method provided by the present application can also be implemented in the form of a program product, which includes program codes for causing an electronic device to perform the steps of the fault processing method according to various exemplary embodiments of the present application described in the specification when the program product is run on the electronic device.

[0150] Those skilled in the art should understand that embodiments of the present application can be provided in the form of a method, device, or computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) containing computer-usable program code.

[0151] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (apparatuses), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as a combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions that are executed by the processor of the computer or other programmable data processing apparatus generate an apparatus that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The flow or multiple flows and / or blocks Figure 1 The apparatus that implements the functions specified in the flow or multiple flows and / or blocks.

[0152] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction apparatus, which implements the functions specified in the flow or multiple flows and / or blocks. Figure 1 The flow or multiple flows and / or blocks Figure 1 The apparatus that implements the functions specified in the flow or multiple flows and / or blocks.

[0153] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide a process for implementing the functions specified in the flow or multiple flows and / or blocks. Figure 1 The flow or multiple flows and / or blocks Figure 1 The apparatus that implements the functions specified in the flow or multiple flows and / or blocks.

[0154] While the preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the present disclosure without departing from the spirit and scope of the application. Accordingly, it is intended that such additions and modifications be included within the scope of the application. It is the following claims, including any amendments thereto, which define the scope of the application.

[0155] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A fault handling method, characterized in that: Applied to a baseboard management controller (BMC), the method includes: Receive an interrupt message triggered when a target server fails, and obtain a target number of target memory banks corresponding to the failure; each target bank corresponds to a different failure type, and each target bank includes its own first register; Starting from a preset position, reading the stored data of the target number of first registers from the fault file, and determining a target bank including the first registers based on the stored data of each first register; the fault file is generated when a fault occurs on the target server and is used to store information related to the current fault of the target server; the preset position is the starting position of the stored data of the first register related to the fault in the fault file; For each target Bank, the fault information corresponding to the target Bank is searched from the fault file, and a fault log is generated based on the fault information corresponding to the target Bank.

2. The method according to claim 1, characterized in that Obtaining the target number of target banks corresponding to the fault includes: Calling the communication register between the BMC and the host of the target server through the Advanced Platform Management Link (AMPL) to obtain the target number of the target bank corresponding to the fault; Before reading the stored data of the target number of first registers from the fault file starting from the preset position, the method further includes: Determine that the target quantity is not zero.

3. The method according to claim 1, characterized in that The storage data of the first register is data stored in a high-order address; and determining a target bank including the first register based on the storage data of each first register, comprising: For each first register, split the stored data of the first register into first data corresponding to a high-order byte and second data corresponding to a low-order byte; the low-order byte represents a hard disk identifier corresponding to the target bank; the high-order byte represents an architecture type corresponding to the target bank; Based on the first data and the second data, the target bank including the first register is queried from a data table; the data table is used to store: the hard disk identifier and architecture type corresponding to each bank.

4. The method according to claim 1, wherein The target Bank further includes at least one second register; the fault information corresponding to the target Bank includes stored data of each second register; and querying the fault information corresponding to the target Bank from the fault file includes: Determining address offset information of each second register included in the target Bank based on the identifier of the target Bank; For each second register, based on the address offset information of the second register, the stored data of the second register is queried from the fault file.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: If the interrupt message is not received and it is determined that the target server is restarted, register information sent through a basic input and output system BIOS is obtained, and a fault log is generated based on the register information.

6. The method according to any one of claims 1 to 4, characterized in that: The fault log includes the device type corresponding to the fault, and generating the fault log based on the fault information corresponding to the target bank includes: Match the fault information corresponding to the target Bank with the reference fault information corresponding to each type of device to determine the device type corresponding to the fault information; wherein the device type includes: at least one of: a processor, a memory, and a bus.

7. A fault handling device, characterized in that: Applied to a baseboard management controller (BMC), the device includes: a receiving module, configured to receive an interrupt message triggered when a target server fails, and obtain a target number of target banks corresponding to the failure; each target bank corresponds to a different failure type, and each target bank includes its own first register; a determination module, configured to read the stored data of the target number of first registers from a fault file starting from a preset position, and determine a target bank including the first registers based on the stored data of each first register; the fault file is generated when a fault occurs on the target server and is configured to store information related to the current fault of the target server; the preset position is the starting position of the stored data of the first register related to the fault in the fault file; The generation module is used to query the fault information corresponding to each target Bank from the fault file, and generate a fault log based on the fault information corresponding to the target Bank.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the method according to any one of claims 1 to 6 when executing the computer program stored in the memory.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A computer program product, characterized in that The computer program product comprises: a computer program code, and when the computer program code is run on a computer, the computer is enabled to execute the method according to any one of claims 1 to 6.

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