Data access method, device, electronic device and storage medium

Abstract

Embodiments of the present application disclose a data access method, apparatus, electronic device, and storage medium. In the present application, the stored data in a dynamic random access memory is copied, and the copied data is stored in other storage units different from the original stored data. In this way, when an access request is received, the target address corresponding to the access request is determined through the access address included in the access request, the load information of the corresponding storage unit can be found, and it is compared with the load information of the storage unit corresponding to the access address, and the storage unit with the smallest load is selected for data access. In this way, when the load of one of the storage units is high, by selecting another storage unit with a lower load for data access, the number of occurrences of storage unit conflicts can be fundamentally reduced, thereby reducing the latency during parallel data access to the dynamic random access memory.

Description

Technical Field

[0001] The present application relates to the field of data access, and more particularly, to a data access method, apparatus, electronic device, and storage medium. Background Art

[0002] Currently, as the frequency of the CPU (Central Processing Unit) continues to increase, the latency of accessing DRAM (Dynamic Random Access Memory) has become a key bottleneck in the entire SoC (System-on-Chip) system, especially when multiple processes access DRAM in parallel, which is particularly evident.

[0003] In the related art, when multiple processes access DRAM in parallel, there may be a situation where read and write commands continuously access different rows in the same memory bank or memory bank group of a storage unit, resulting in memory bank conflicts and memory bank group conflicts, which causes access latency in DRAM data access. Summary of the Invention

[0004] To solve the above technical problems, embodiments of the present application provide a data access method, apparatus, electronic device, and storage medium, so as to reduce the access latency during parallel data access to a dynamic random access memory.

[0005] According to one aspect of the embodiments of the present application, a data access method is provided, including: in the case of receiving an access request, determining a target address having a mapping relationship with the access address according to the access address included in the access request for storing data; the target address is the storage address of replicated data identical to the stored data, but the replicated data and the stored data are stored in different memory units respectively; determining the load information of the memory unit storing the replicated data according to the target address, and determining the load information of the memory unit storing the stored data according to the access address; comparing all the obtained load information to determine the memory unit with the smallest load, and performing data access in the memory unit with the smallest load.

[0006] In some embodiments, before determining the corresponding target address according to the access address included in the access request, the method further includes: determining, from historical data access records, stored data whose access latency is greater than a preset latency threshold and whose access frequency is greater than a preset frequency threshold; copying the stored data to obtain copied data of the stored data; determining the storage address of the copied data of the stored data according to the storage address of the stored data; storing the copied data according to the storage address of the copied data, and establishing a mapping relationship between the storage address of the stored data and the storage address of the copied data.

[0007] In some embodiments, a data storage area includes a plurality of storage unit groups, each storage unit group includes a plurality of storage units, and each storage unit includes a first storage area and a second storage area. The first storage area is used to store stored data, and the second storage area is used to store copied data; the storage address includes a storage unit group address and a storage unit address; determining the storage address of the copied data according to the storage address of the stored data includes: respectively performing modulo operations on the storage unit group address and the storage unit address of the stored data to obtain the storage unit group address and the storage unit address of the copied data; storing the copied data according to the storage address of the copied data includes: storing the copied data into an empty row in the second storage area corresponding to the storage unit group address and the storage unit address of the copied data.

[0008] In some embodiments, determining the load information of the storage unit storing the copied data according to the target address and determining the load information of the storage unit storing the stored data according to the access address includes: obtaining the tag information corresponding to the target address; determining whether the copied data corresponding to the target address is valid data according to the tag information; if the copied data is valid data, determining the load information of the storage unit storing the copied data according to the target address, and determining the load information of the storage unit storing the stored data according to the access address.

[0009] In some embodiments, the method further includes: monitoring the data access bandwidth, and when the data access bandwidth is lower than a preset bandwidth threshold, counting the access frequencies of all copied data; determining the copied data with an access frequency lower than the preset threshold as data to be updated, and updating the data to be updated.

[0010] In some embodiments, updating the data to be updated includes: determining new stored data from historical data access records, where the access latency is greater than a preset latency threshold and the number of accesses is greater than a preset number threshold; copying the new stored data to obtain a copy of the new stored data; storing the copy of the new stored data at the storage address of the data to be updated, and establishing a mapping relationship between the storage address of the new stored data and the storage address of the copy of the new stored data.

[0011] In some embodiments, the method further includes: when a data rewrite instruction for a target storage unit is detected, obtaining the load information of the target storage unit; where the target storage unit is two storage units storing the same data; when the load information of both storage units is less than a preset load threshold, performing data rewrite on both storage units simultaneously; or, when the load information of only one storage unit is less than the preset load threshold, performing data rewrite on the first storage unit with load information less than the preset load threshold, and monitoring the load information of the second storage unit with load information greater than the preset load threshold; when the load information of the second storage unit is monitored to be less than the preset load threshold, reading out the rewritten stored data from the first storage unit and performing data rewrite on the second storage unit according to the rewritten stored data. In some embodiments,

[0012] According to one aspect of the embodiments of the present application, there is provided a data access device, including: a first determination module configured to, when receiving an access request, determine a target address having a mapping relationship with the access address according to the access address of the stored data included in the access request; the target address is the storage address of a copy of the stored data that is the same as the stored data, but the copy of the data and the stored data are stored in different storage units respectively; a second determination module configured to determine the load information of the storage unit storing the copy of the data according to the target address and determine the load information of the storage unit storing the stored data according to the access address; a data access module configured to compare all the obtained load information, determine the storage unit with the smallest load, and perform data access in the storage unit with the smallest load.

[0013] According to one aspect of the embodiments of the present application, there is provided an electronic device, including: one or more processors; a storage device for storing one or more programs, which when executed by the one or more processors, cause the electronic device to implement the data access method as described above.

[0014] According to one aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the above data access method.

[0015] In the technical solution provided by the embodiments of the present application, by copying the stored data stored in a dynamic random access memory and storing the copied data in other storage units different from the original stored data, in this way, when an access request is received, the corresponding target address is determined through the access address included in the access request, the load information of the corresponding storage unit can be found out, and it is compared with the load information of the storage unit corresponding to the access address, and the storage unit with the smallest load is selected for data access. In this way, when the load of one of the storage units is relatively high, by selecting another storage unit with a relatively low load for data access, the occurrence frequency of bank conflict can be fundamentally reduced, thereby reducing the latency during parallel data access to the dynamic random access memory.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0018] Figure 1 is a schematic structural diagram of a DRAM shown in an exemplary embodiment of the present application;

[0019] Figure 2 is an application schematic diagram of the storage unit access process shown in an exemplary embodiment of the present application;

[0020] Figure 3 is a schematic diagram of an exemplary implementation environment of the present application;

[0021] Figure 4 is a flowchart of a data access method shown in an exemplary embodiment of the present application;

[0022] Figure 5 is a flowchart of a data access method shown in another exemplary embodiment of the present application;

[0023] Figure 6 is a schematic structural diagram of a memory chip shown in an exemplary embodiment of the present application;

[0024] Figure 7 is a flowchart of a data access method shown in another exemplary embodiment of the present application;

[0025] Figure 8 is a flowchart of a data access method shown in another exemplary embodiment of the present application;

[0026] Figure 9 is a flowchart of a data access method shown in another exemplary embodiment of the present application;

[0027] Figure 10 is a schematic structural diagram of a data access device according to an exemplary embodiment of the present application;

[0028] Figure 11 is a schematic structural diagram of a computer system of an electronic device according to an exemplary embodiment of the present application. Detailed Description of the Embodiments

[0029] Here, an exemplary embodiment will be described in detail, and its examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments of the present application. On the contrary, they are merely examples of devices and methods that are the same as some aspects of the present application as detailed in the appended claims.

[0030] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in the form of application programs, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0031] The flowcharts shown in the drawings are only exemplary descriptions, and do not necessarily include all contents and operations / steps, nor do they necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined. Therefore, the actual execution order may change according to the actual situation.

[0032] It should be noted that the term "plurality" mentioned in the present application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0033] The following is an introduction and explanation of the technical terms and background technology involved in the present application:

[0034] Cache (Cache Memory): It is located between the CPU (Central Processing Unit) and the main memory DRAM (Dynamic Random Access Memory), and is usually composed of SRAM (Static Random-Access Memory). The speed of the CPU is much higher than that of the memory. When the CPU directly accesses data from the memory, it has to wait for a certain number of clock cycles. However, the Cache has a fast access speed and can store a part of the data that the CPU has just used or will reuse. If the CPU needs to use this part of the data again, it can directly call it from the Cache, thus avoiding accessing data from the memory with a long delay and reducing the waiting time of the CPU, thereby improving the efficiency of the system.

[0035] DRAM: It is mainly used to store temporary data during the operation of the computer, including program code, variables, stack, etc. As the main memory of the computer, DRAM provides a relatively large storage capacity and moderate access speed. Compared with SRAM, DRAM has a higher density and lower cost. This makes DRAM the main component of the main memory in modern computer systems.

[0036] Please refer to Figure 1 and Figure 2 , Figure 1 which is a schematic structural diagram of DRAM shown in an exemplary embodiment of the present application, Figure 2 and which is an application schematic diagram of the storage unit access process shown in an exemplary embodiment of the present application; wherein, the DRAM physical address is composed of channel, rank, bank group, bank, row, and column. The physical address determines the specific location where the read / write data is stored.

[0037] When accessing a bank for reading and writing, the following process is included:

[0038] 1) The controller first sends an activation command. According to the row address in the access address of the access request, it is decoded by the row decoder, and then the stored data in the storage unit is read out. For example, row0 in bank1 is read out and placed in the row buffer, as shown by the data stream ① in Figure 2 This process is called activation.

[0039] 2) According to the physical address corresponding to column, i.e., the column address, data is parsed from the row buffer through the Column Mux (column multiplexer) and returned to the controller;

[0040] 3) When the row accessed by the access request is row1, the data of row0 stored in the row buffer needs to be first written back to bank1, as shown by the data stream ②, and this process is called precharge; in addition, continuously accessing different rows in the same memory cell is called bank conflict; Figure 2 as shown in the data stream ②.

[0041] 4) Then the controller sends an activation command to read row1 in bank1 and place it in the row buffer. Finally, according to the physical address corresponding to column, read / write operations are performed on the data of row1 in the row buffer.

[0042] Moreover, when accessing the stored data in the bank, accessing different banks, bank groups, rows, etc. has different time requirements, as shown in Table 1. Table 1 is an example table of the timing parameters of DRAM.

[0043]

[0044] Table 1

[0045] In Table 1, the timing parameter tCCD_S is used to characterize the delay of consecutive identical read / write commands to the banks in different bank groups of the same rank, which is 4 cycles; the timing parameter tCCD_L is used to characterize the delay of consecutive identical read / write commands to the banks in the same bank group of the same rank, which is 8 cycles; the timing parameter tRTP is used to characterize the delay between the read / write command and the charge command in the same bank, which is 12 cycles; the timing parameter tRAS is used to characterize the delay between the activation command and the precharge command in the same bank, which is 56 cycles; the timing parameter tRP is used to characterize the delay between the precharge command and the activation command in the same bank, which is 22 cycles; the timing parameter tRCD is used to characterize the delay between the activation command and the read / write command in the same bank, which is 22 cycles. It can be seen that the tRAS delay time is the longest. Therefore, when actually accessing DRAM, row switching in the same bank should be avoided as much as possible, that is, bank conflict should be avoided.

[0046] In the related art, since the lower physical address changes the fastest and the higher physical address changes the slowest, to reduce row conflict, the row address is placed at the highest bit of the physical address, the column address is placed at the lowest bit of the physical address, and the Bank address / bank group address is placed between the row address and the column address. This address mapping method will result in very poor bank group interleaving, and read / write requests will enter the same bank group, increasing the access conflicts between different bank groups and banks, reducing the actual throughput of the memory, and thus increasing the access latency of the DRAM.

[0047] Based on this, the embodiments of the present application propose a data access method, device, electronic device, and storage medium. By copying the stored data in the DRAM and storing the copied data in other storage units different from the original stored data, when an access request is received, the target address corresponding to the access address included in the access request can be determined, the load information of the corresponding storage unit can be found, and it is compared with the load information of the storage unit corresponding to the access address, and the storage unit with the smallest load is selected for data access. In this way, when the load of one of the storage units is relatively high, by selecting another storage unit with a lower load for data access, the occurrence times of bank conflict and bank group conflict can be fundamentally reduced, thereby reducing the latency during parallel data access to the dynamic random access memory.

[0048] Please refer to Figure 3 , Figure 3 which is a schematic diagram of an exemplary implementation environment of the present application. As Figure 3 shown, this implementation environment includes a DRAM controller 110 and a DRAM 120. Among them, a communication connection is pre-established between the DRAM controller 110 and the DRAM 120.

[0049] The DRAM controller 110 is used to manage and schedule data transmission between the DRAM 120 and the CPU, ensuring that data can flow accurately and efficiently between these two components. The DRAM controller 110 performs necessary control over the access to the DRAM 120 according to certain timing rules, including the control of address signals, data signals, and various command signals, enabling the master device (such as the CPU) to access the stored data on the DRAM 120. For example, the DRAM controller receives the address signal from the CPU, decodes it into the storage address inside the DRAM 120, and according to the read / write instructions of the CPU, the DRAM controller 110 exchanges data with the DRAM 120 through the data bus; in a read operation, the DRAM controller 110 reads data from the DRAM 120 and sends it to the CPU; in a write operation, the DRAM controller writes the data provided by the CPU into the DRAM 120. Additionally, since the storage cells of the DRAM 120 are composed of capacitors and transistors, and the capacitors have a leakage phenomenon, it is necessary to refresh regularly to maintain the accuracy of the data. The DRAM controller 110 is used to control the execution of the refresh operation to ensure that the data in the DRAM 120 is not lost.

[0050] The storage cells of the DRAM 120 are composed of a capacitor and a transistor (or other switching circuits). The capacitor is used to store charge, and the transistor acts as a switch to control the charging and discharging process of the capacitor and the read / write operation of the data. Since the capacitor leaks electricity, the DRAM 120 needs to be refreshed regularly to maintain the accuracy of the data. The refresh operation is automatically executed by the DRAM controller 110 to ensure that the data stored in the DRAM 120 is not lost.

[0051] In some embodiments, when the DRAM controller 110 receives an access request, according to the access address for the stored data included in the access request, it determines the target address that has a mapping relationship with the access address; the target address is the storage address of the replicated data that is the same as the stored data, but the replicated data and the stored data are stored in different storage cells respectively; the DRAM controller 110 determines the load information of the storage cell storing the replicated data according to the target address, and determines the load information of the storage cell storing the stored data according to the access address; the DRAM controller 110 compares all the obtained load information, determines the storage cell with the minimum load, and accesses the data in the storage cell with the minimum load.

[0052] Please refer to Figure 4 , Figure 4 which is a flowchart of the data access method shown in an exemplary embodiment of the present application. This method can be applied to an electronic device provided with a memory chip, and the memory chip includes a DRAM controller and a DRAM. Among them, the electronic device includes but is not limited to a computer, a server, a tablet computer, or a mobile phone, etc.

[0053] The following takes a computer as a specific execution entity to introduce in detail the data access method proposed in the embodiments of the present application.

[0054] As Figure 4 shown, in an exemplary embodiment, the data access method at least includes steps S410 to S430, which are introduced in detail as follows:

[0055] Step S410, in the case of receiving an access request, determine a target address that has a mapping relationship with the access address according to the access address included in the access request. Wherein, the target address is the storage address of the replicated data that is the same as the stored data, but the replicated data and the stored data are stored in different storage units respectively.

[0056] It can be understood that the access request includes an access address, which is used to access data in the corresponding storage unit in the DRAM; the data storage area in the DRAM includes a first area and a second area, wherein the stored data is stored in the storage unit in the first area, and the replicated data that is the same as the stored data is stored in the storage unit in the second area.

[0057] Step S420, determine the load information of the storage unit storing the replicated data according to the target address, and determine the load information of the storage unit storing the stored data according to the access address.

[0058] It can be understood that in the embodiments of the present application, a storage unit status information library can be set in the DRAM controller, and the real-time load information of each storage unit can be found through this storage unit status information library, so that it is convenient for the DRAM controller to select the storage unit with the smallest load for data access.

[0059] Exemplarily, determining the load information of the storage unit storing the replicated data according to the target address includes: finding out the load information of the storage unit corresponding to the target address from a preset storage unit status information library. Wherein, the corresponding relationship between the target address and the load information of the storage unit is stored in the storage unit status information library.

[0060] Exemplarily, determining the load information of the storage unit storing the stored data according to the target address includes: finding out the load information of the storage unit corresponding to the access address from a preset storage unit status information library. Wherein, the corresponding relationship between the access address and the load information of the storage unit is stored in the storage unit status information library.

[0061] Step S430, compare all the obtained load information, determine the storage unit with the smallest load, and perform data access in the storage unit with the smallest load.

[0062] In the embodiments of the present application, by counting the number of times each storage unit of the access request in the historical data access record is accessed, copying the frequently accessed data, and storing the frequently accessed data in different banks. When one of them is in a high access state, by accessing the bank with low load, data can be obtained faster. At the same time, the present application does not change any structure of the DRAM. Only by adjusting the address mapping method of the DRAM controller and adding additional circuit logic, the DRAM can be accessed quickly to obtain data faster.

[0063] Combined with Figure 5 as shown Figure 5 is a flowchart of a data access method shown in another exemplary embodiment of the present application. Before the above step S410, the data access method further includes at least steps S510 to S540, which are introduced in detail as follows:

[0064] S510, determine the stored data in the historical data access record whose access delay is greater than a preset delay threshold and the number of accesses is greater than a preset number threshold.

[0065] S520, copy the stored data whose access delay is greater than a preset delay threshold and the number of accesses is greater than a preset number threshold to obtain a copy of the stored data.

[0066] S530, determine the storage address of the copy of the stored data according to the storage address of the stored data.

[0067] In the embodiments of the present application, the data storage area includes multiple storage unit groups, each storage unit group includes multiple storage units, and each storage unit includes a first storage area and a second storage area. The first storage area is used to store the stored data, and the second storage area is used to store the copy of the data; the storage address includes a storage unit group address and a storage unit address. The bank address and the bank group address in the storage address of the stored data can be simply adjusted to obtain the storage address of the copy of the stored data, so as to reduce the complexity of the storage address of the copy of the stored data.

[0068] In some embodiments, the storage address of the copy of the stored data can be determined according to the storage address of the stored data through the following process: perform modulo operations on the storage unit group address and the storage unit address of the stored data respectively to obtain the storage unit group address and the storage unit address of the copy of the stored data.

[0069] Exemplarily, the modulo operation includes: New_bank_addr = old_bank_addr+ 1(mod 4) and New_bg_addr= old_bg_addr+ 1(mod 4). Wherein, New_bank_addr is the storage unit address in the storage address of the replicated data, old_bank_addr is the storage unit address in the storage address of the stored data, New_bg_addr is the storage unit group address in the storage address of the replicated data, old_bg_addr is the storage unit group address in the storage address of the stored data, and (mod 4) is used to represent the modulo operation with a modulus of 4.

[0070] For example, the data storage area includes 4 bank groups, such as bank group1, bank group2, bank group3, and bank group4, and each bank group includes 4 banks, such as bank1, bank2, bank3, and bank4. When the storage unit group address of the stored data is bank group4, it can be known from New_bg_addr= old_bg_addr+ 1(mod 4) that bank group1+1 is bank group5, but there is no bank group5 in the data storage area. Taking the modulo 4 of bank group5, the storage unit group address of the replicated data is obtained as bank group1; when the storage unit address of the stored data is bank4, it can be known from New_bank_addr = old_bank_addr+ 1(mod 4) that bank4+1 is bank5. Taking the modulo 4 of bank5, New_bank_addr is obtained as bank1, and the storage unit address of the replicated data is bank1. Therefore, the replicated data is stored in the empty row of bank2 in bank group2. In this way, by adjusting both the storage unit group address and the storage unit address, the replicated data can be stored in different banks in a bank group different from the stored data, which can not only reduce the occurrence times of bank conflict, but also reduce the occurrence times of bank group conflict, thus achieving a better effect of reducing access latency.

[0071] For example, the modulo operation can also be performed only on the storage unit address. In this way, only the storage unit address is adjusted, so that the replicated data can be stored in different banks in the same bank group as the stored data, which can reduce the occurrence times of bank conflict, thus achieving the effect of reducing access latency.

[0072] It is understandable that the storage addresses in the embodiments of the present application include a storage unit group address, a storage unit address, a row address, and a column address. Among them, the column address of the copied data remains unchanged, that is, the column address in the new storage address is the same as the column address in the original storage address; while the row address will change. A preset area is divided in each bank specifically for storing the copied data. For example, the area from row 65530 to row 65536 in the bank. In this way, after determining the bank group and bank addresses, the copied data will be stored in the empty rows in the area from row 65530 to row 65536 in the bank address. When storing in this preset area, it can be randomly stored in any empty row or stored in a preset order.

[0073] S540, store the copied data according to the storage address of the copied data, and establish a mapping relationship between the storage address of the stored data and the storage address of the copied data.

[0074] It is understandable that after determining the storage unit group address and the storage unit address, the copied data is stored in the empty rows in the second storage area corresponding to the storage unit group address and the storage unit address of the copied data.

[0075] In this way, in the embodiments of the present application, by copying the frequently accessed data and then storing the frequently accessed data in different banks, it can be ensured that when one of them is in a high access state, the low-load bank can be accessed, so as to obtain data faster and reduce access latency.

[0076] Combined Figure 6 as shown Figure 6 is a schematic structural diagram of a memory chip shown in an exemplary embodiment of the present application; Figure 6 The memory chip in [figure number] includes a DRAM controller and a DRAM. The mapping relationship between the storage address of the stored data and the storage address of the copied data is recorded in the DRAM controller. Each data storage area in the DRAM includes a first storage area and a second storage area. The first storage area is used for storing data, and the second storage area is used for storing copied data; the sizes of the first storage area and the second storage area can be set according to actual needs.

[0077] In some embodiments, a tag SRAM (tag static random access memory) is preset in the DRAM controller. The tag SRAM adopts a fully associative manner and is used to record the mapping relationship between the storage address of the stored data and the storage address of the copied data. The mapping relationship can be recorded in the tag SRAM in the form of a cache line Cacheline, as Figure 6As shown in the figure, a cache line includes tag label information, index information, and offset information. Among them, the tag label information includes a tag valid field, a tag addr field, an activate cnt field, and a col valid field. The tag valid field is used to indicate whether the entire row of data in the bank is valid. The tag addr field is used to indicate the storage address of the replicated data. The activate cnt (activation count) field is used to indicate the number of page misses in the bank. The col calid field is used to indicate whether the entire column of data in the bank is valid. In some embodiments, the replicated data is valid only when both the tag valid field and the col valid field are valid.

[0078] In this way, when the DRAM controller receives an access request, it will first search for the corresponding tag in the tag SRAM according to the access address included in the access request. If there is a cache hit and the data is valid, it is considered that there is corresponding replicated data for the access request. Then, the load information of the storage units corresponding to the replicated data and the stored data is searched in the storage unit status information library in the DRAM controller, and then one of the storage units with the lowest load is selected for access to obtain the corresponding data. The above lookup table process can obtain the result within 1 cycle, so the overall access time is smaller than the bank conflict time.

[0079] In some embodiments, the mapping relationship between the storage address of the stored data and the storage address of the replicated data can also be stored in the DRAM. In this way, after the DRAM controller receives an access request, it searches for the storage address of the corresponding replicated data in the DRAM according to the address included in the access request, then obtains the load information of the corresponding storage unit, and then selects one of the storage units with the lowest load for access to obtain the corresponding data.

[0080] Please refer to Figure 7 , Figure 7 which is a flowchart of a data access method shown in another exemplary embodiment of the present application. As Figure 7 shown, in an exemplary embodiment, the data access method further includes at least steps S710 to S730, which are introduced in detail as follows:

[0081] Step S710, obtaining the tag information corresponding to the target address.

[0082] Step S720, determining whether the replicated data corresponding to the target address is valid according to the tag information.

[0083] In the embodiments of the present application, the label information corresponding to the target address is used to characterize whether the replicated data is valid data. Since there is a situation where the same data (i.e., the stored data and the replicated data identical to the stored data) is stored in different banks, when the data in one bank is rewritten, the data in the corresponding other bank also needs to be updated in a timely manner to ensure data consistency; and if the data in one bank is inconsistent with the data in the corresponding other bank, the replicated data is then invalid data.

[0084] Step S730, if the replicated data is valid data, determine the load information of the storage unit storing the replicated data according to the target address, and determine the load information of the storage unit storing the stored data according to the access address.

[0085] In the embodiments of the present application, by obtaining the load information of the corresponding storage unit when the replicated data is valid data, data access can be performed more accurately, and the accuracy of data access can be improved while ensuring the data access speed.

[0086] It should be noted that the step content related in the embodiments of the present application is consistent with the corresponding step content recorded in the foregoing embodiments. Therefore, for the detailed description of these steps, please refer to the records in the foregoing embodiments, and the embodiments of the present application will not be elaborated herein.

[0087] Please refer to Figure 8 , Figure 8 which is a flowchart of a data access method shown in another exemplary embodiment of the present application. As Figure 8 shown, in an exemplary embodiment, the data access method further includes at least steps S810 to S820, which are introduced in detail as follows:

[0088] Step S810, monitor the data access bandwidth, and count the access times of all replicated data when the data access bandwidth is lower than the preset bandwidth threshold.

[0089] It can be understood that during the process of data access for DRAM, if the data access bandwidth is large, it will cause the reduction of the overall system bandwidth, and if data update is performed at this time, it is likely to affect the parallelism and efficiency of data access. Therefore, by performing data update when the data access bandwidth is small, the parallelism and efficiency of data access can be guaranteed.

[0090] Step S820, determine the replicated data with access times lower than the preset threshold as the data to be updated, and update the data to be updated.

[0091] It can be understood that, due to certain limitations in the tag SRAM space and the randomness of data access, when the tag SRAM is full, it is also necessary to consider replacing the cache lines that are not frequently used. Replacement can be performed periodically by deleting the cache lines that are not frequently accessed and then adding new cache lines. And every once in a while, the invalid data in the data cache is replaced. Of course, this replacement has flexibility. For example, when the read / write requests are few, the replacement frequency can be increased; when the read / write requests are many, the replacement frequency can be decreased.

[0092] In the embodiments of the present application, the data to be updated can be updated through the following process, including:

[0093] Step S821, determine new stored data from the historical data access records whose access latency is greater than a preset latency threshold and whose access frequency is greater than a preset frequency threshold;

[0094] Step S822, copy the new stored data to obtain a copy of the new stored data;

[0095] Step S823, store the copy of the new stored data at the storage address of the data to be updated, and establish a mapping relationship between the storage address of the new stored data and the storage address of the copy of the new stored data.

[0096] In this way, by re-determining the newly frequently accessed data from the historical data access records to replace the data that is not frequently accessed in the storage unit. Of course, this replacement has flexibility. For example, when the read / write requests are few, the replacement frequency can be increased; when the read / write requests are many, the replacement frequency can be decreased. By replacing the data that is not frequently accessed in the storage unit, it can ensure that the data accessed is frequently accessed data, which can minimize the access latency to the greatest extent and thus improve the user experience.

[0097] Please refer to Figure 9 , Figure 9 which is a flowchart of a data access method shown in another exemplary embodiment of the present application. As Figure 9 shown, in an exemplary embodiment, the data access method further includes at least steps S910 to S930, which are introduced in detail as follows:

[0098] Step S910, when a data rewrite instruction for a target storage unit is detected, obtain the load information of the target storage unit. Here, the target storage unit is two storage units storing the same data.

[0099] Step S920, when the load information of both storage units is less than a preset load threshold, rewrite the data of both storage units simultaneously.

[0100] Step S930: When the load information of only one storage unit is less than a preset load threshold, rewrite the data of the first storage unit whose load is less than the preset load threshold, and monitor the load information of the second storage unit whose load is greater than the preset load threshold.

[0101] Step S940: When it is monitored that the load information of the second storage unit is less than the preset load threshold, read out the rewritten storage data from the first storage unit, and rewrite the data of the second storage unit according to the rewritten storage data.

[0102] It can be understood that in the embodiments of the present application, since there is a situation where a certain piece of data exists in different banks, when the data in a certain bank is rewritten, the data in the corresponding other bank also needs to be updated in a timely manner to ensure data consistency. This process can be divided into the following situations. When the loads of both banks are small, the corresponding data of both banks can be replaced simultaneously. When the load of bank1 is small, the data in bank1 can be replaced first. When the load of bank2 becomes small, the DRAM controller reads out the data in bank1 and then writes it back to bank2 to replace the data in bank2, so as to ensure the consistency of the replicated data in bank1 and the data in bank2.

[0103] Combined with Figure 10 as shown in Figure 10 FIG. 14 is a data access device shown in an exemplary embodiment of the present application. The device includes a first determination module 1010, a second determination module 1020, and a data access module 1030. The first determination module 1010 is configured to, when receiving an access request, determine a target address having a mapping relationship with the access address according to the access address included in the access request; the target address is the storage address of the replicated data identical to the storage data, but the replicated data and the storage data are stored in different storage units respectively; the second determination module 1020 is configured to determine the load information of the storage unit storing the replicated data according to the target address, and determine the load information of the storage unit storing the storage data according to the access address; the data access module 1030 is configured to compare all the obtained load information, determine the storage unit with the smallest load, and perform data access in the storage unit with the smallest load.

[0104] In some embodiments, before determining a corresponding target address based on the access address included in the access request, the first determination module 1010 is further configured to determine, from historical data access records, stored data with an access latency greater than a preset latency threshold and an access count greater than a preset count threshold; copy the stored data to obtain a copy of the stored data; determine the storage address of the copy of the stored data according to the storage address of the stored data; store the copy of the data according to the storage address of the copy of the data, and establish a mapping relationship between the storage address of the stored data and the storage address of the copy of the stored data.

[0105] In some embodiments, the data storage area includes multiple storage unit groups, and each storage unit group includes multiple storage units; the storage address includes a storage unit group address and a storage unit address; determining the storage address of the copy of the stored data according to the storage address of the stored data includes: performing a modulo operation on the storage unit group address and the storage unit address of the stored data respectively to obtain the storage unit group address and the storage unit address of the copy of the stored data; storing the copy of the data according to the storage address of the copy of the stored data includes: storing the copy of the data in an empty row in the storage area corresponding to the storage unit group address and the storage unit address of the copy of the stored data.

[0106] In some embodiments, the second determination module 1020 is configured to determine the load information of the storage unit storing the replicated data based on the target address and determine the load information of the storage unit storing the stored data based on the access address by the following method, including: obtaining the label information corresponding to the target address; determining whether the replicated data corresponding to the target address is valid data according to the label information; if the replicated data is valid data, determining the load information of the storage unit storing the replicated data based on the target address and determining the load information of the storage unit storing the stored data based on the access address.

[0107] In some embodiments, the data access device further includes an update module, and the update module is configured to count the access times of all replicated data every preset period; determine the replicated data with an access count lower than a preset threshold as the data to be updated, and update the data to be updated.

[0108] In some embodiments, the update module is configured to update the data to be updated by the following method, including: determining, from historical data access records, new stored data with an access latency greater than a preset latency threshold and an access count greater than a preset count threshold; copying the new stored data to obtain a copy of the new stored data; storing the copy of the new stored data in the storage address of the data to be updated, and establishing a mapping relationship between the storage address of the new stored data and the storage address of the copy of the new stored data.

[0109] In some embodiments, the update module is further configured to obtain the load information of a target storage unit when detecting a data rewrite instruction for the target storage unit; wherein the target storage unit is two storage units storing the same data; when the load information of both storage units is less than a preset load threshold, rewrite the data of both storage units simultaneously; or, when the load information of only one storage unit is less than the preset load threshold, rewrite the data of the first storage unit less than the preset load threshold, and monitor the load information of the second storage unit greater than the preset load threshold; when it is detected that the load information of the second storage unit is less than the preset load threshold, read out the rewritten storage data from the first storage unit, and rewrite the data of the second storage unit according to the rewritten storage data.

[0110] Embodiments of the present disclosure further provide an electronic device, including: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory so that the electronic device executes the above method.

[0111] Figure 11 The structural schematic diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application is shown. It should be noted that, Figure 11 The shown computer system 1100 of the electronic device is only an example, and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0112] As Figure 11 shown, the computer system 1100 includes a central processing unit (CPU) 1101, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1102 or the program loaded from the storage section 1108 into the random access memory (RAM) 1103, such as executing the method in the above embodiments. In the random access memory 1103, various programs and data required for system operation are also stored. The central processing unit 1101, the read-only memory 1102, and the random access memory 1103 are connected to each other through a bus 1104. The input / output (I / O) interface 1105 is also connected to the bus 1104.

[0113] The following components are connected to the input / output interface 1105: an input section 1106 including a keyboard, a mouse, etc.; an output section 1107 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc. and a speaker, etc.; a storage section 1108 including a hard disk, etc.; and a communication section 1109 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to the input / output interface 1105 as required. A removable medium 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1110 as required so that a computer program read therefrom is installed into the storage section 1108 as required.

[0114] Specifically, according to an embodiment of the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, an embodiment of the present application includes a computer program product that includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication section 1109, and / or installed from the removable medium 1111. When the computer program is executed by a central processing unit (CPU) 1101, various functions defined in the system of the present application are executed.

[0115] The embodiments of the present disclosure also provide a computer-readable storage medium, on which computer-readable instructions are stored, and when the computer-readable instructions are executed by a processor of the computer, the computer is caused to execute the above data access method.

[0116] It should be noted that the computer-readable medium shown in the embodiments of the present application may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0117] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. Among them, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the above module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0118] The units involved in the embodiments of the present application can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation on the units themselves in some cases.

[0119] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the data access method described above is implemented. The computer-readable storage medium may be included in the electronic device described in the above embodiments, or may exist alone without being assembled into the electronic device.

[0120] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation of the present application. Those of ordinary skill in the art can easily make corresponding adaptations or modifications according to the main concept and spirit of the present application. Therefore, the protection scope of the present application should be subject to the protection scope required by the claims.

Claims

1. A data access method, characterized in that: The method is applied to an electronic device provided with a memory chip, the memory chip includes a DRAM controller and a DRAM, and the method is specifically performed by the DRAM controller; The method comprises: In the case of receiving an access request, determining a target address having a mapping relationship with the access address according to an access address for stored data included in the access request; the target address is a storage address of duplicated data identical to the stored data, but the duplicated data and the stored data are stored in different storage units respectively; the data storage area of ​​each storage unit in the DRAM includes a first storage area and a second storage area, wherein the first storage area is used for the stored data, and the second storage area is used for the duplicated data; Determining load information of a storage unit storing the copied data according to the target address, and determining load information of a storage unit storing the stored data according to the access address; Comparing all the acquired load information, determining the storage unit with the smallest load, and accessing data in the storage unit with the smallest load; Before receiving the access request, the method further includes: determining, from historical data access records, storage data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; copying the storage data to obtain copy data of the storage data; determining, according to the storage address of the storage data, the storage address of the copy data of the storage data; storing the copy data according to the storage address of the copy data, and establishing a mapping relationship between the storage address of the storage data and the storage address of the copy data; The method further includes: monitoring the data access bandwidth, and counting the number of accesses to all replicated data when the data access bandwidth is lower than a preset bandwidth threshold; determining the replicated data with the number of accesses lower than the preset threshold as data to be updated, and updating the data to be updated.

2. The method according to claim 1, characterized in that: The data storage area includes a plurality of storage unit groups, each storage unit group includes a plurality of storage units, each storage unit includes a first storage area and a second storage area, the first storage area is used to store storage data, and the second storage area is used to store duplicate data; The storage address includes a storage unit group address and a storage unit address; The step of determining the storage address of the duplicated data of the stored data according to the storage address of the stored data comprises: Performing a modulo operation on the storage unit group address and the storage unit address of the storage data respectively to obtain the storage unit group address and the storage unit address of the copied data; Storing the copied data according to the storage address of the copied data includes: The copied data is stored in an empty row in a second storage area corresponding to the storage unit group address and the storage unit address of the copied data.

3. The method according to claim 1, characterized in that The step of determining the load information of the storage unit storing the copied data according to the target address, and determining the load information of the storage unit storing the stored data according to the access address, comprises: Obtaining label information corresponding to the target address; Determine whether the copied data corresponding to the target address is valid data according to the tag information; If the copied data is valid data, the load information of the storage unit storing the copied data is determined according to the target address, and the load information of the storage unit storing the storage data is determined according to the access address.

4. The method according to claim 1, characterized in that The updating of the data to be updated includes: Determine from the historical data access records new stored data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; Copying the new stored data to obtain copy data of the new stored data; The duplicate data of the newly stored data is stored in the storage address of the data to be updated, and a mapping relationship is established between the storage address of the newly stored data and the storage address of the duplicate data of the newly stored data.

5. The method according to claim 1, characterized in that The method further comprises: When a data rewrite instruction for a target storage unit is detected, load information of the target storage unit is acquired; wherein the target storage units are two storage units storing the same data; When the load information of the two storage units is less than a preset load threshold, rewriting data of the two storage units simultaneously; Or, when the load information of only one storage unit is less than the preset load threshold, data is rewritten on the first storage unit whose load information is less than the preset load threshold, and the load information of the second storage unit whose load information is greater than the preset load threshold is monitored; when it is monitored that the load information of the second storage unit is less than the preset load threshold, the rewritten storage data is read from the first storage unit, and data is rewritten on the second storage unit according to the rewritten storage data.

6. A data access device, characterized in that: The device comprises: A first determination module is configured to determine, upon receiving an access request, a target address that is mapped to the access address according to the access address for the stored data contained in the access request; the target address is a storage address of duplicated data that is the same as the stored data, but the duplicated data and the stored data are stored in different storage units; the data storage area of ​​each storage unit includes a first storage area and a second storage area, wherein the first storage area is used for the stored data, and the second storage area is used for the duplicated data; a second determination module configured to determine load information of a storage unit storing the copied data according to the target address, and to determine load information of a storage unit storing the stored data according to the access address; A data access module is configured to compare all acquired load information, determine a storage unit with the smallest load, and perform data access in the storage unit with the smallest load; Before receiving an access request, determine from historical data access records storage data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; copy the storage data to obtain copy data of the storage data; determine the storage address of the copy data of the storage data according to the storage address of the storage data; store the copy data according to the storage address of the copy data, and establish a mapping relationship between the storage address of the storage data and the storage address of the copy data; The data access bandwidth is monitored, and when the data access bandwidth is lower than a preset bandwidth threshold, the access times of all the replicated data are counted; the replicated data with access times lower than the preset threshold is determined as data to be updated, and the data to be updated is updated.

7. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, enables the electronic device to implement the data access method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that: Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the data access method according to any one of claims 1 to 5.

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