Vector operation circuit, vector operation method, and chip

Abstract

The invention discloses a vector operation circuit, a vector operation method and a chip, and belongs to the technical field of computers. The circuit comprises N levels of sharing circuits and a target selection module, the ith-level sharing circuit comprises at least one first sharing module, i is any one of 1 to N-1, and the first sharing module is used for carrying out vector operation on a pair of first data with a first length to obtain a first operation result with the first length; the Nth-level sharing circuit comprises a second sharing module, and the second sharing module is used for carrying out vector operation on a pair of second data with a second length to obtain a second operation result with the second length; and the target selection module is used for selecting and outputting the second operation result or the first operation result obtained by the first sharing module included in the (N-1) th-level sharing circuit. Circuit functions are added, the number of circuits is reduced, and the size of the chip can be reduced when the circuits are arranged in the chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a vector operation circuit, a vector operation method and a chip. Background Art

[0002] With the development of computer technology, there are more and more types of processors with vector computing engines. For example, artificial intelligence (AI) processors in computer systems and central processing units (CPUs) with vector operation instruction set architectures can all perform vector operations.

[0003] In the related art, it is necessary to design multiple vector operation circuits. One vector operation circuit is used to perform a vector operation of a type of operation on vector data of a data format, and any two vector operation circuits correspond to at least one of different data formats and different operation types. Since one vector operation circuit corresponds to a single data format and a single operation type, the function is relatively single, which leads to the need to design different vector operation circuits, increasing resource usage. Generally, the circuit can be laid out in the chip, and laying out the above-mentioned multiple vector operation circuits in the chip will result in a larger chip area. Summary of the invention

[0004] The present application provides a vector operation circuit, a vector operation method and a chip, which can increase circuit functions, reduce the number of circuits, and thus reduce chip area. The technical solution includes the following contents.

[0005] In one aspect, a vector operation circuit is provided, the vector operation circuit comprising N-level shared circuits and a target selection module, wherein N is a positive integer greater than 1;

[0006] The i-th level shared circuit in the N-level shared circuits includes at least one first shared module, the j-th level shared circuit includes a first shared module and the j-th level shared circuit includes two first shared modules connected to each other, i is any one of 1 to N-1, and j is any one of 2 to N-1;

[0007] The first sharing module is used to perform a vector operation on a pair of first data to obtain a first operation result, the lengths of the first data and the first operation result are both the first length, and when the first sharing module is located in the j-th level sharing circuit, the first data is the first operation result obtained by the first sharing module connected to the first sharing module and included in the j-1-th level sharing circuit;

[0008] The N-th level shared circuit includes a second shared module, and the second shared module is connected to the first shared module included in the N-1-th level shared circuit;

[0009] The second sharing module is used to perform a vector operation on a pair of second data to obtain a second operation result, wherein the pair of second data is obtained by splitting a first operation result obtained by the first sharing module included in the N-1th level sharing circuit, and the lengths of the second data and the second operation result are both the second length;

[0010] The target selection module is connected to the second sharing module and the first sharing module included in the N-1th level sharing circuit respectively; the target selection module is used to select and output the second operation result or the first operation result obtained by the first sharing module included in the N-1th level sharing circuit.

[0011] On the other hand, a vector operation method is provided, the method being executed by the above-mentioned vector operation circuit, the method comprising:

[0012] For a first shared module included in an i-th level shared circuit, a first operation result is obtained by performing a vector operation on a pair of first data through the first shared module, the lengths of the first data and the first operation result are both the first length, and when the first shared module is located in a j-th level shared circuit, the first data is a first operation result obtained by a first shared module connected to the first shared module and included in a j-1-th level shared circuit;

[0013] For a second shared module included in the N-th level shared circuit, a vector operation is performed on a pair of second data by the second shared module to obtain a second operation result, where the pair of second data is obtained by splitting a first operation result obtained by the first shared module included in the N-1-th level shared circuit, and the lengths of the second data and the second operation result are both the second length;

[0014] The target selection module selects and outputs the second operation result or the first operation result obtained by the first sharing module included in the N-1th level sharing circuit.

[0015] On the other hand, a chip is provided, wherein the chip includes the above-mentioned vector operation circuit.

[0016] The technical solution provided by this application brings at least the following beneficial effects:

[0017] In the vector operation circuit provided by the present application, a vector operation is performed on a pair of first data of a first length through a first shared module to obtain a first operation result of the first length, and a vector operation is performed on a pair of second data of a second length through a second shared module to obtain a second operation result of the second length. The target selection module selects to output the second operation result or the first operation result, thereby realizing vector operation of data of the first length and vector operation of data of the second length in one circuit, increasing circuit functions, and reducing the number of circuits, so that when the vector operation circuit is laid out in a chip, the chip size can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a schematic diagram of an implementation environment of a vector operation circuit provided in an embodiment of the present application;

[0020] Figure 2 is a structural schematic diagram of a vector operation circuit provided in an embodiment of the present application;

[0021] Figure 3 is a structural diagram of a first sharing module provided in an embodiment of the present application;

[0022] Figure 4 is a structural schematic diagram of a summing unit provided in an embodiment of the present application;

[0023] Figure 5 It is a structural schematic diagram of a maximum value unit provided in an embodiment of the present application;

[0024] Figure 6 is a port diagram of a first shared module provided in an embodiment of the present application;

[0025] Figure 7 is a structural diagram of a second sharing module provided in an embodiment of the present application;

[0026] Figure 8 This is a schematic diagram of the structure of a maximum value submodule provided in an embodiment of the present application;

[0027] Fig. 9 is a port diagram of a second shared module provided in an embodiment of the present application;

[0028] Fig.10 is a structural schematic diagram of another vector operation circuit provided in an embodiment of the present application;

[0029] Fig.11 It is a structural diagram of a 32-bit summation module provided in an embodiment of the present application;

[0030] Fig.12 It is a structural schematic diagram of a 32-bit maximum value module provided in an embodiment of the present application;

[0031] Fig.13 It is a flow chart of a vector operation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0033] Figure 1 is a schematic diagram of an implementation environment of a vector operation circuit provided in an embodiment of the present application, such as Figure 1 As shown, the implementation environment includes a terminal device 101 and a server 102. The vector operation circuit in the embodiment of the present application can be arranged in the terminal device 101, can also be arranged in the server 102, or can be arranged in the terminal device 101 and the server 102.

[0034] The terminal device 101 can be a smart phone, a game console, a desktop computer, a tablet computer, a laptop computer, a smart TV, a smart car device, an intelligent voice interaction device, a smart home appliance, etc. The server 102 can be a single server, or a server cluster consisting of multiple servers, or any one of a cloud computing platform and a virtualization center, which is not limited in the embodiments of the present application. The server 102 can be connected to the terminal device 101 through a wired network or a wireless network. The server 102 can have functions such as data processing, data storage, and data transmission and reception, which are not limited in the embodiments of the present application. The number of terminal devices 101 and servers 102 is not limited and can be one or more.

[0035] Generally, a processor with a vector computing engine can perform vector operations. In the related art, it is necessary to design multiple vector operation circuits, one vector operation circuit is used to perform a vector operation of a type of operation on vector data of a data format, and any two vector operation circuits correspond to at least one of different data formats and different operation types. Since a vector operation circuit corresponds to a single data format and a single operation type, the function is relatively single, resulting in the need to design different vector operation circuits, which increases resource usage. The circuit can be laid out in the chip, and laying out the above-mentioned multiple vector operation circuits in the chip will result in a larger chip area.

[0036] The present application embodiment provides a vector operation circuit, which can increase circuit functions, reduce the number of circuits, and thus reduce chip area. Figure 2 As an example, a vector operation circuit provided by an embodiment of the present application is described. Figure 2 As shown, the vector operation circuit includes N levels of shared circuits and target selection modules, where N is a positive integer greater than 1. The shared circuits and target selection modules of each level are introduced in turn below.

[0037] First, any one of the first N-1 levels of shared circuits is introduced. Set i to any one of 1 to N-1, and j to any one of 2 to N-1. On this basis, the i-th level shared circuit includes at least one first shared module, and the j-th level shared circuit includes a first shared module that is connected to the two first shared modules included in the j-1-th level shared circuit.

[0038] It should be noted that any two first shared modules included in the j-th level shared circuit are connected to different first shared modules included in the j-1-th level shared circuit. In other words, different first shared modules of the j-th level shared circuit are connected to different first shared modules of the j-1-th level shared circuit. In a possible implementation, the number of first shared modules included in the j-1-th level shared circuit is twice the number of first shared modules included in the j-th level shared circuit. Every two first shared modules included in the j-1-th level shared circuit are connected in turn to each first shared module included in the j-th level shared circuit.

[0039] For example, in Figure 2 In the embodiment, the first-level shared circuit includes at least four first shared modules, the N-2-level shared circuit includes two first shared modules, and the N-1-level shared circuit includes one first shared module. The first shared module included in the N-1-level shared circuit is connected to the two first shared modules included in the N-2-level shared circuit. Similarly, one first shared module included in the N-2-level shared circuit is connected to the two first shared modules included in the N-3-level shared circuit, and another first shared module included in the N-2-level shared circuit is connected to another two first shared modules included in the N-2-level shared circuit.

[0040] Optionally, the first shared module is used to perform vector operations on a pair of first data of a first length to obtain a first operation result of the first length. When the first shared module is located in the j-th level shared circuit, the first data is the first operation result of the first shared module connected to the first shared module included in the j-1-th level shared circuit.

[0041] The embodiment of the present application does not limit the first length. For example, the first length is 32, 64, 128, etc. The length of the first data is the first length, which means that the first data is represented by characters of the first length, and the characters can be numbers, letters, etc. For example, when the first data is binary data, the character is 0 or 1, and when the first data is decimal data, the character is any one of 0 to 9.

[0042] A first shared module can perform vector operations on two first data to obtain a first operation result. Figure 2 In the example, a first shared module in the first-level shared circuit can perform vector operations on the first data a1 and the first data b1 to obtain a first operation result 1; another first shared module in the first-level shared circuit can perform vector operations on the first data a2 and the first data b2 to obtain a first operation result 2. The vector operations include but are not limited to summing, difference, and maximum value operations. The length of the first operation result is the first length, that is, the first operation result can be represented by characters of the first length.

[0043] Next, the Nth level shared circuit is introduced. The Nth level shared circuit includes a second shared module, and the second shared module is connected to the first shared module included in the N-1th level shared circuit. Figure 2 In the embodiment, the N-th level shared circuit includes a second shared module, the N-1-th level shared circuit includes a first shared module, and the second shared module is connected to the first shared module.

[0044] It can be understood that the data input to the vector operation circuit includes the first data of each first shared module located in the first level shared circuit. Figure 2 In , the data input to the vector operation circuit includes first data a1, first data b1, first data a2, first data b2, first data a3, first data b3, first data a4, and first data b4. In addition, the first data of any first shared module located in the j-th level shared circuit includes the first operation result obtained by the first shared module located in the j-1-th level shared circuit and connected to the first shared module. For example, in Figure 2 In the figure, the first data a7 of the first shared module located at the N-1th level shared circuit is the first operation result 5 obtained by the first shared module located at the N-2th level shared circuit, and the first data b7 of the first shared module located at the N-1th level shared circuit is the first operation result 6 obtained by the first shared module located at the N-2th level shared circuit.

[0045] The second shared module is used to perform vector operation on a pair of second data of second length to obtain a second operation result of the second length, and the pair of second data of second length is obtained by splitting the first operation result of the first shared module included in the N-1th level shared circuit.

[0046] The length of the first operation result is the first length, and the first operation result can be split into a pair of second data by bit. Figure 2 , the first operation result 7 is split into second data a and second data b. The length of the second data is the second length, and the first length is twice the second length. For example, if the first length is 32, the second length is 16, and if the first length is 64, the second length is 32. Generally, data with a length of 64 is referred to as 64-bit data, data with a length of 32 is referred to as 32-bit data, and data with a length of 16 is referred to as 16-bit data.

[0047] That is to say, the first operation result is split into the first second length data and the second length data by bit, wherein the first second length data is also called high-order data, which is one second data, and the second length data is also called low-order data, which is another second data. For example, 32-bit data is split into high-order 16-bit data and low-order 16-bit data to obtain a pair of second data. The high-order data and the low-order data are described below and will not be repeated here.

[0048] A second shared module can perform vector operations on two second data to obtain a second operation result. Figure 2 In the N-th level shared circuit, a second shared module can perform vector operations on the second data a and the second data b to obtain a second operation result, wherein the vector operations include but are not limited to summing, difference, and maximum value operations. The length of the second operation result is the second length, that is, the second operation result can be represented by characters of the second length.

[0049] Next, the target selection module is introduced. The target selection module is connected to the second shared module and the first shared module included in the N-1th level shared circuit respectively. The target selection module is used to select and output the second operation result or the first operation result of the first shared module included in the N-1th level shared circuit.

[0050] For example, in Figure 2 In the example, the target selection module is connected to the second shared module included in the Nth level shared circuit, and is connected to the first shared module included in the N-1th level shared circuit. The input of the target selection module is the second operation result and the first operation result 7. The second operation result can be selected as the target selection result, and the first operation result 7 can be selected as the target selection result.

[0051] Optionally, the length signal is input into the target selection module, and the target selection module selects the target selection result from the second operation result and the first operation result of the first shared module included in the N-1th level shared circuit according to the data length indicated by the length signal. The data length is the first length or the second length. In other words, the length signal is used to indicate the first length or the second length. The value of the length signal is different, and the content indicated by the length signal is also different. For example, when the value of the length signal is 0, the length signal is used to indicate the first length, and when the value of the length signal is 1, the length signal is used to indicate the second length.

[0052] If the length signal indicates a first length, the target selection module selects the first operation result of the first shared module included in the N-1th level shared circuit as the target selection result. If the length signal indicates a second length, the target selection module selects the second operation result as the target selection result.

[0053] In a possible implementation, any one of the N levels of shared circuits includes a beat register ( Figure 2 (not shown), there is at least one beat register. Among them, a first shared module included in the j-th level shared circuit is connected to the two first shared modules included in the j-1-th level shared circuit through a beat register included in the j-1-th level shared circuit. That is to say, a beat register included in the j-1-th level shared circuit is connected to a first shared module included in the j-th level shared circuit, and is connected to the two first shared modules included in the j-1-th level shared circuit. Similarly, the second shared module is connected to the first shared module included in the N-1-th level shared circuit through a beat register included in the N-1-th level shared circuit. The target selection module is connected to the second shared module through a beat register included in the N-th level shared circuit, and is connected to the second shared module included in the N-1-th level shared circuit through a beat register included in the N-1-th level shared circuit.

[0054] It should be noted that the structures and functions of the first shared modules are similar, and therefore, the structure and functions of a first shared module are introduced below.

[0055] In an embodiment of the present application, the first data includes low-order data of the second length and high-order data of the second length. Among them, the low-order data includes the second-length characters on the right of the first data, and the high-order data includes the second-length characters on the left of the first data. Taking the first data as 32-bit data as an example, the low-order data includes 16-bit data on the right, and the high-order data includes 16-bit data on the left. Assume that the first data is recorded as a[31:0], indicating that the first data includes data from the 0th to the 31st bit. Then the high-order data can be recorded as a[31:16], indicating that the high-order data includes data from the 16th to the 31st bit on the left; the low-order data can be recorded as a[15:0], indicating that the low-order data includes data from the 0th to the 15th bit on the left.

[0056] like Figure 3 As shown, Figure 3 1 is a schematic diagram of the structure of a first shared module provided in an embodiment of the present application. The first shared module includes a low-order processing submodule, a high-order processing submodule and a determination submodule, the low-order processing submodule is connected to the determination submodule, and the high-order processing submodule is also connected to the determination submodule. The following introduces these three modules in turn.

[0057] First, the low-bit processing submodule is introduced. The low-bit processing submodule is used to perform vector operations on a pair of low-bit data according to the operation type indicated by the operation signal to obtain a low-bit operation result.

[0058] In the embodiment of the present application, the operation signal is input into the low-order processing submodule. The operation signal indicates the operation type of the vector operation, and the operation type includes but is not limited to summing, subtraction, and maximum value. The low-order processing submodule performs the vector operation of the operation type on the two low-order data according to the operation type indicated by the operation signal to obtain the low-order operation result. For example, if the operation signal indicates summing, the sum of the two low-order data is calculated to obtain the low-order operation result; if the operation signal indicates subtraction, the difference of the two low-order data is calculated to obtain the low-order operation result.

[0059] Alternatively, if Figure 3 As shown, the low-bit processing submodule includes a low-bit inversion unit and a low-bit addition unit, and the low-bit inversion unit and the low-bit addition unit are connected.

[0060] Among them, the low-bit inversion unit is used to invert a low-bit data to obtain a low-bit inversion result when the operation type is to take the maximum value, or, when the operation type is to sum, use a low-bit data as the low-bit inversion result; the low-bit addition unit is used to add another low-bit data and the low-bit inversion result according to the operation signal to obtain the low-bit operation result.

[0061] In the embodiment of the present application, the maximum value can be converted into subtraction logic. One low-order data is used as the subtrahend, and the other low-order data is used as the minuend. The minuend is subtracted from the minuend to obtain the difference between the two low-order data. If the difference is a positive number, it means that the minuend is greater than the minuend. If the difference is zero, it means that the minuend is equal to the minuend. If the difference is a negative number, it means that the minuend is less than the minuend. Among them, subtraction logic is equivalent to addition logic, so the maximum value can be converted into addition logic.

[0062] The following takes the two low-order data as two 32-bit unsigned data as an example to explain the process of converting the maximum value into the addition logic. Exemplarily, the two low-order data are a[31:0] and b[31:0]. If the two low-order data are summed, the addition logic is sum[32:0]=a[31:0]+b[31:0], where sum[32:0] is the sum of the two low-order data. If the two low-order data take the maximum value, taking the maximum value as an example, the maximum value logic is max_value=max(a,b)=(a>=b)? a:b, max_value represents the maximum value of the two low-order data. The maximum value logic can be converted into subtraction logic to reuse the addition logic, that is, the comparison result of a[31:0] and b[31:0] can be judged by sum[32:0]=a[31:0]-b[31:0], and sum[32:0] represents the difference result of the two low-order data, which is 33-bit signed data. That is, sum[32:0] includes data from bit 0 to bit 32, and bit 32 is a sign bit. Optionally, if bit 32 is equal to 1, that is, sum

[32] =1, indicating that the sign is negative, then a[31:0] is less than b[31:0]; if bit 32 is equal to 0, that is, sum

[32] =0, indicating that the sign is positive, then a[31:0] is greater than b[31:0].

[0063] In the embodiment of the present application, the subtraction logic can be converted into addition logic by first expanding the high bit of b[31:0] with a 1-bit 0 value, and the expanded b[31:0] is 33-bit data, inverting the 33-bit data, and then adding it to a[31:0], and then adding 1. The above process can be expressed as: a[31:0]-b[31:0]=a[31:0]+(~b[31:0])+1, ~ represents the inversion sign.

[0064] Based on the above principles, Figure 3As shown, the low-order processing submodule includes a low-order inversion unit and a low-order addition unit. Taking the low-order data as 16-bit data as an example, the two low-order data are a[15:0] and b[15:0]. The operation signal cmp_sel is input into the low-order inversion unit. If the operation signal indicates that the operation type is to take the maximum value, for example, cmp_sel=1, the low-order inversion unit inverts the low-order data b[15:0] to obtain the low-order inversion result b_mux[15:0]=~b[15:0]. If the operation signal indicates that the operation type is to sum, for example, cmp_sel=0, the low-order inversion unit uses the low-order data b[15:0] as the low-order inversion result b_mux[15:0]=b[15:0]. The operation signal cmp_sel is input to the low-order addition unit. If the operation signal indicates that the operation type is to take the maximum value, for example, cmp_sel=1, the low-order addition unit adds the low-order data a[15:0] and the low-order inverted result b_mux[15:0]=~b[15:0], and then adds 1 to obtain the low-order operation result sum0[16:0]=a[15:0]+(~b[15:0])+1. If the operation signal indicates that the operation type is to sum, for example, cmp_sel=0, the low-order addition unit adds the low-order data a[15:0] and the low-order inverted result b_mux[15:0]=b[15:0] to obtain the low-order operation result sum0[16:0]=a[15:0]+b[15:0].

[0065] In summary, the low-order processing submodule is used to perform addition or subtraction operations on two low-order data according to the operation signal to obtain the low-order operation result. The logic formula of the low-order processing submodule can be expressed as: sum0[16:0]=cmp_sel? a[15:0]+~b[15:0]+1:a[15:0]+b[15:0], which indicates that when the operation signal indicates to take the maximum value, cmp_sel=1, sum0[16:0]=a[15:0]+~b[15:0]+1, and when the operation signal indicates to sum, cmp_sel=0, sum0[16:0]=a[15:0]+b[15:0].

[0066] Next, the high-bit processing submodule is introduced. The high-bit processing submodule is used to perform vector operations on a pair of high-bit data according to the operation type to obtain a first high-bit operation result without overflow and a second high-bit operation result with overflow.

[0067] In the embodiment of the present application, the operation signal is input into the high-order processing submodule, and the high-order processing submodule performs a vector operation of the operation type indicated by the operation signal on the two high-order data. For example, if the operation signal indicates a summation, the sum of the two high-order data is calculated; if the operation signal indicates a difference, the difference between the two high-order data is calculated to obtain a first high-order operation result and a second high-order operation result.

[0068] The first high-order operation result represents the vector operation result of the two high-order data when there is no overflow in the two low-order data. The second high-order operation result represents the vector operation result of the two high-order data when there is an overflow in the two low-order data. Among them, the overflow includes the overflow for signed numbers and the overflow for unsigned numbers, and the overflow for unsigned numbers can be called a carry. It can be understood that the first data includes low-order data and high-order data. Due to the existence of the carry principle, the operation of the high-order data is affected by the low-order data. When adding operands with the same sign, when the sign bit of the addition result is different from the sign bit of the operand, it indicates that an overflow has occurred.

[0069] That is to say, if a positive vector is added to a positive vector to obtain a negative vector, or a negative vector is added to a negative vector to obtain a positive vector, it indicates that an overflow exists. Take A=15, B=124 as an example, convert A and B into 8-bit data (the first data is the sign bit), then A=00001111, B=01111100, A+B=10001011. The sign bits of A and B are both 0, which belongs to the addition of operands with the same sign, and the sign bit of the addition result is 1, which is different from the sign bit of the operand. In this case, an overflow exists. Among them, 10001011 is equivalent to -117, that is, the positive number 15 and the positive number 124 are added to obtain the negative number -117. In this case, an overflow exists.

[0070] Alternatively, if Figure 3 As shown, the high-bit processing submodule includes a high-bit inversion unit and a high-bit addition unit, and the high-bit inversion unit and the high-bit addition unit are connected.

[0071] The high-order inversion unit is used to invert a high-order data to obtain a high-order inversion result when the operation type is to obtain the maximum value, or, when the operation type is to sum, use a high-order data as the high-order inversion result; the high-order addition unit is used to add another high-order data and the high-order inversion result to obtain a first high-order operation result, and add another high-order data, the high-order inversion result and the data used to indicate the overflow to obtain a second high-order operation result.

[0072] Taking the high-order data as 16-bit data as an example, the two high-order data are a[31:16] and b[31:16]. The operation signal cmp_sel is input to the high-order inversion unit. If the operation signal indicates that the operation type is to take the maximum value, for example, cmp_sel=1, the high-order inversion unit inverts the high-order data b[31:16] to obtain the high-order inversion result b_mux[31:16]=~b[31:16]. If the operation signal indicates that the operation type is to sum, for example, cmp_sel=0, the high-order inversion unit uses the high-order data b[31:16] as the high-order inversion result b_mux[31:16]=b[31:16].

[0073] In summary, the high-order inversion unit is used to invert or not invert the high-order data according to the operation signal cmp_sel to obtain the high-order inversion result. The above process can be expressed as a logical formula: b_mux[31:16]=cmp_sel?~b[31:16]:b[31:16], which indicates that when the operation signal indicates to take the maximum value, cmp_sel=1, b_mux[31:16]=~b[31:16], and when the operation signal indicates to sum, cmp_sel=0, b_mux[31:16]=b[31:16].

[0074] The overflow can be indicated by the number 1. The high-order addition unit adds the high-order data a[31:16] and the high-order inverted result b_mux[31:16] to obtain the first high-order operation result sum1[16:0]=a[31:16]+b_mux[31:16]. The high-order addition unit adds the high-order data a[31:16] and the high-order inverted result b_mux[31:16], and then adds 1 (i.e., data indicating the overflow) to obtain the second high-order operation result sum1_p1[16:0]=a[31:16]+b_mux[31:16]+1.

[0075] Next, the determination submodule is introduced. The determination submodule is used to determine the first operation result based on the low-order operation result, the first high-order operation result, and the second high-order operation result. The embodiment of the present application does not limit the determination method. The structure of the determination submodule is different, and the determination method of the first operation result is also different.

[0076] It can be understood that in addition to inputting the low-order operation result, the first high-order operation result and the second high-order operation result into the determination submodule, other information can also be input. The embodiment of the present application does not limit the other information. Exemplarily, the other information includes at least one of a sign signal, an operation signal, a length signal, a type signal, a data signal, the first data, etc. Each signal has a corresponding description below and will not be repeated here.

[0077] like Figure 3 As shown, the input of the determination submodule includes the low-order operation result sum0[16:0], the first high-order operation result sum1[16:0], the second high-order operation result sum1_p1[16:0], the sign signal unsign_sel, the length signal data_type_16, the type signal max_sel, the data signal fp_sel, the first data a[31:0], the first data b[31:0], etc.

[0078] Alternatively, if Figure 3 As shown, the determination submodule includes a summing unit, a maximum value unit and a first selection unit, the summing unit is connected to the high-order addition unit, the low-order addition unit and the first selection unit, and the maximum value unit is also connected to the high-order addition unit, the low-order addition unit and the first selection unit.

[0079] The summing unit is used to determine a first summing result based on the low-order operation result, the first high-order operation result, and the second high-order operation result, wherein the first summing result represents a result obtained by summing a pair of first data, and the length of the first summing result is the first length. The embodiment of the present application does not limit the determination method, and the structure of the summing unit is different, and the determination method of the first summing result is also different.

[0080] It can be understood that in addition to inputting the low-order operation result, the first high-order operation result and the second high-order operation result into the summation unit, other information can also be input, including at least one of a sign signal, an operation signal, a length signal, a type signal, a data signal, a first data, etc.

[0081] like Figure 3 As shown, the input of the summing unit includes the low-order operation result sum0[16:0], the first high-order operation result sum1[16:0], the second high-order operation result sum1_p1[16:0], the sign signal unsign_sel, the length signal data_type_16, etc. The summing unit determines the first summing result add_res[31:0] according to the aforementioned input.

[0082] For example, Figure 4 As shown, Figure 4 1 is a schematic diagram of a structure of a summing unit provided in an embodiment of the present application. The first summing result includes a first processing result and a second processing result, and the summing unit includes a first determining subunit, a first processing subunit, and a second processing subunit.

[0083] The first determining subunit is used to determine a reference operation result from a first high-bit operation result and a second high-bit operation result according to the low-bit operation result and a length signal indicating the first length or the second length.

[0084] In the embodiment of the present application, the low-order operation result, the length signal, the first high-order operation result, and the second high-order operation result are input into the first determination subunit, and the first determination subunit can determine the reference operation result according to the aforementioned input. The reference operation result is the first high-order operation result or the second high-order operation result. It is understood that in addition to the aforementioned input, other information can also be input into the first determination subunit, and the other information may include but is not limited to at least one of a sign signal, an operation signal, a type signal, a data signal, and the first data.

[0085] Alternatively, if Figure 4 As shown, the first determining subunit includes a first logic gate component and a first selection component, and the first logic gate component is connected to the first selection component. The first logic gate component may include at least one logic gate. The embodiment of the present application does not limit the type of logic gate included in the first logic gate component. For example, Figure 4 In the embodiment, the first logic gate component includes an AND gate. In an exemplary embodiment, the first logic gate component may further include at least one of an OR gate, an XOR gate, an XNOR gate, and the like.

[0086] The first logic gate component is used to determine a reference signal according to the low-order operation result and the length signal, and the reference signal is used to indicate whether the length is the first length and an overflow exists. The first selection component is used to select the second high-order operation result as the reference operation result when the reference signal indicates the first length and an overflow exists, and select the first high-order operation result as the reference operation result when the reference signal indicates at least one of the second length and the absence of an overflow.

[0087] like Figure 4 As shown, the length signal data_type_b16 can be inverted to obtain the inverted length signal ~data_type_b16, wherein the data length indicated by ~data_type_b16 is opposite to the data length indicated by data_type_b16. For example, when the value of data_type_b16 is 1, it indicates 16-bit data, and when the value is 0, it indicates 32-bit data. Then, when the value of ~data_type_b16 is 1, it indicates 32-bit data, and when the value is 0, it indicates 16-bit data. The low-order operation result sum0[16:0] and the inverted length signal ~data_type_b16 are input into the first logic gate component, and the logic gate operation is performed by the first logic gate component to obtain the reference signal plus1_sel.

[0088] It can be understood that the low-bit operation result is signed data, and the first logic gate component can select the sign bit in the low-bit operation result, perform logic gate operation on the sign bit and the inverted length signal ~data_type_b16, and obtain a reference signal. Figure 4In the example, the first logic gate component includes an AND gate, and an AND gate operation is performed on the sign bit sum0

[16] in the low-order operation result sum0[16:0] and the inverted length signal ˜data_type_b16 to obtain a reference signal plus1_sel. The logic formula is plus1_sel=sum0

[16] &~data_type_b16.

[0089] The reference signal is used to indicate whether it is the first length and whether the low-order operation result has an overflow. If the reference signal indicates the first length and there is an overflow, the first selection component selects the second high-order operation result as the reference operation result. If the reference signal indicates the second length and there is an overflow, or the reference signal indicates the first length and there is no overflow, or the reference signal indicates the second length and there is no overflow, the first selection component selects the first high-order operation result as the reference operation result.

[0090] For example, in Figure 4 In the example, when the reference signal plus1_sel indicates 32-bit fixed-point data and the addition of the lower 16 bits overflows, in this case, the first selection component selects the second higher-order operation result sum1_p1[16:0] as the reference operation result sum1_mux[16:0]. Otherwise, the first selection component selects the first higher-order operation result sum116:0] as the reference operation result sum1_mux[16:0]. The logic formula can be expressed as: sum1_mux[16:0]=plus1_sel? sum1_p1[16:0]:sum1[16:0].

[0091] The first selection component is connected to the first processing subunit and the second processing subunit. The two modules are introduced in turn below.

[0092] First, the first processing subunit is introduced. The first processing subunit is used to determine a first overflow signal indicating whether there is an overflow situation according to a reference operation result and a sign signal indicating whether there is a signed or unsigned condition, and determine a first processing result according to the sign signal, the first overflow signal and the reference operation result, wherein the first processing result is the reference operation result or is obtained by saturating the reference operation result.

[0093] In an embodiment of the present application, a sign signal is used to indicate whether it is signed or unsigned. Wherein, the value of the sign signal is different, and the content indicated by the sign signal is also different. For example, when the value of the sign signal is 1, the sign signal is used to indicate that it is unsigned, and when the value of the sign signal is 0, the sign signal is used to indicate that it is signed. Optionally, fixed-point data includes unsigned fixed-point data and signed fixed-point data, and floating-point numbers are all signed data. Therefore, when the data is floating-point data, the sign signal indicates that it is signed, or the sign signal is an invalid signal. When the data is fixed-point data, the sign signal indicates that it is signed or unsigned. That is to say, when the data signal indicates floating-point data, the sign signal indicates that it is signed or is an invalid signal, and when the data signal indicates fixed-point data, the sign signal indicates that it is signed or unsigned.

[0094] like Figure 4 As shown, the reference operation result sum1_mux[16:0] and the sign signal unsign_sel are input into the first processing subunit, and the first overflow signal b32_ovf is determined by the first processing module according to the reference operation result sum1_mux[16:0] and the sign signal unsign_sel. The first overflow signal is used to indicate whether the fixed-point data of the first length has an overflow or whether the high-order fixed-point data of the second length in the fixed-point data of the first length has an overflow. If the first length is 32 and the second length is 16, the first overflow signal is used to indicate whether the 32-bit fixed-point data has an overflow or whether the high-order 16-bit fixed-point data has an overflow. The logical formula of the first overflow signal can be expressed as: b32_ovf=unsign_sel? sum1_mux

[16] :(sum1_mux

[16] ^sum1_mux

[15] ).

[0095] Next, the first processing module determines the first processing result add_res[31:16] according to the sign signal unsign_sel, the first overflow signal b32_ovf and the reference operation result sum1_mux[16:0]. The first processing result is obtained by saturating the reference operation result or the reference operation result. The logical formula of the first processing result is: add_res[31:16]=b32_ovf?(unsign_sel?16'hffff:{sum1_mux

[16] ,{15{~sum1_mux

[16] }}}):sum1_mux[15:0].

[0096] Next, the second processing subunit is introduced. The second processing subunit is used to determine the second overflow signal indicating whether there is an overflow situation according to the reference operation result, the first overflow signal, the length signal and the low-bit operation result, and determine the second processing result according to the sign signal, the first overflow signal, the second overflow signal, the length signal and the low-bit operation result, wherein the first processing result is the low-bit operation result or is obtained by saturating the low-bit operation result.

[0097] like Figure 4 As shown, the reference operation result sum1_mux[16:0], the first overflow signal b32_ovf, the length signal data_type_b16 and the low-bit operation result sum0[16:0] are input into the second processing subunit, and the second overflow signal b16_ovf is determined by the second processing subunit. The second overflow signal is used to indicate whether there is an overflow in the low-bit fixed-point data of the second length in the fixed-point data of the first length. If the first length is 32 and the second length is 16, the second overflow signal is used to indicate whether there is an overflow in the low-bit 16-bit fixed-point data. The logical formula of the second overflow signal can be expressed as: b16_ovf=unsign_sel? sum0

[16] :(sum0

[16] ^sum0

[15] ).

[0098] Next, the second processing subunit determines the second processing result add_res[15:0] according to the sign signal unsign_sel, the first overflow signal b32_ovf, the second overflow signal b16_ovf, the length signal data_type_b16 and the low-bit operation result sum0[16:0]. The second processing result is the low-bit operation result or the low-bit operation result is saturated. The logical formula of the second processing result can be expressed as follows.

[0099] add_res[15:0]=b32_ovf&~data_type_b16?

[0100] (unsign_sel?16'hffff:{16{~sum1_mux

[16] }}}):

[0101] b16_ovf&data_type_b16? (unsign_sel?16'hffff:{sum0

[16] ,16{~sum0

[16] }}}):

[0102] sum0[15:0].

[0103] The first processing result and the second processing result can be combined into a first summation result. Figure 4In the embodiment, the first processing result add_res[31:16] and the second processing result add_res[15:0] can be combined into the first summation result add_res[31:0].

[0104] Next, the maximum value unit is introduced. The maximum value unit is used to determine a first maximum value result based on the low-order operation result, the first high-order operation result, and the second high-order operation result. The first maximum value result represents the result obtained by performing the maximum value operation on a pair of first data, and the length of the first maximum value result is the first length. The embodiment of the present application does not limit the determination method. The structure of the maximum value unit is different, and the determination method of the first maximum value result is also different.

[0105] It can be understood that in addition to inputting the low-order operation result, the first high-order operation result and the second high-order operation result into the summation unit, other information can also be input, including at least one of a sign signal, an operation signal, a length signal, a type signal, a data signal, a first data, etc.

[0106] like Figure 3 As shown, the input of the maximum value unit includes the low-order operation result sum0[16:0], the first high-order operation result sum1[16:0], the second high-order operation result sum1_p1[16:0], the data signal fp_sel, the sign signal unsign_sel, the type signal max_sel, the length signal data_type_16, the first data a[31:0], the first data b[31:0], etc. The maximum value unit determines the first maximum value result cmp_res[31:0] according to the above input.

[0107] For example, Figure 5 As shown, Figure 5 1 is a schematic diagram of a structure of a maximum value unit provided in an embodiment of the present application. Optionally, the first maximum value result includes a third processing result and a fourth processing result, and the maximum value unit includes a second determination subunit, a third processing subunit and a fourth processing subunit. The second determination subunit is connected to the third processing subunit, and the second determination subunit is connected to the fourth processing subunit.

[0108] The second determination subunit is used to determine the first comparison signal and the second comparison signal based on the low-order operation result, the first high-order operation result and the second high-order operation result, the first comparison signal is used to indicate the absolute value comparison result of a pair of first data in the case of a first length, or the absolute value comparison result of a pair of high-order data in the case of a second length, and the second comparison signal is used to indicate the absolute value comparison result of a pair of first data in the case of the first length, or the absolute value comparison result of a pair of low-order data in the case of the second length.

[0109] The second determination subunit can determine the first comparison signal high16_abs_bLarger based on the low-order operation result sum0[16:0], the first high-order operation result sum1[16:0], and the second high-order operation result sum1_p1[16:0]. Optionally, the first comparison signal is used to indicate the absolute value comparison result of a pair of first data in the case of a first length. For example, for 32-bit data, the first comparison signal can be used to indicate the absolute value comparison result of the first data a[31:0] and the first data b[31:0]. That is, the first comparison signal can indicate that the absolute value of the first data a[31:0] is greater than, equal to, or less than the absolute value of the first data b[31:0]. Alternatively, the first comparison signal is used to indicate the absolute value comparison result of a pair of high-order data in the case of a second length. For example, the first data a[31:0] can be split into high-order data a[31:16] and low-order data a[15:0], and the first data b[31:0] can be split into high-order data b[31:16] and low-order data b[15:0]. For 16-bit data, the first comparison signal can be used to indicate the absolute value comparison result of the high-order data a[31:16] and the high-order data b[31:16]. In other words, the first comparison signal can indicate that the absolute value of the high-order data a[31:16] is greater than, equal to, or less than the absolute value of the high-order data b[31:16].

[0110] The second determination subunit can also determine the second comparison signal low16_abs_bLarger based on the low-order operation result sum0[16:0], the first high-order operation result sum1[16:0] and the second high-order operation result sum1_p1[16:0]. Optionally, the second comparison signal is used to indicate the absolute value comparison result of a pair of first data under the first length. For example, for 32-bit data, the second comparison signal can be used to indicate the absolute value comparison result of the first data a[31:0] and the first data b[31:0]. Alternatively, the second comparison signal is used to indicate the absolute value comparison result of a pair of low-order data under the second length. For example, the first data a[31:0] can be split into high-order data a[31:16] and low-order data a[15:0], and the first data b[31:0] can be split into high-order data b[31:16] and low-order data b[15:0]. For 16-bit data, the second comparison signal can be used to indicate the absolute value comparison result of the lower data a[15:0] and the lower data b[15:0]. In other words, the first comparison signal can indicate that the absolute value of the lower data a[15:0] is greater than, equal to, or less than the absolute value of the lower data b[15:0].

[0111] In a possible implementation, the second determining subunit includes a second logic gate component and a second selection component. Figure 5 As shown, the second logic gate component and the second selection component are connected.

[0112] The second logic gate component is used to determine the first comparison signal based on the low-bit operation result, the first high-bit operation result, the second high-bit operation result and the length signal; the second selection component is used to determine the second comparison signal based on the length signal, the first comparison signal and the low-bit operation result.

[0113] In an embodiment of the present application, the low-bit operation result, the first high-bit operation result, the second high-bit operation result and the length signal are input into the second logic gate component, and the logic gate operation is performed by the second logic gate component to obtain a first comparison signal. Among them, the second logic gate component includes at least one logic gate. The embodiment of the present application does not limit the type and quantity of the logic gates included in the second logic gate component. Exemplarily, the second logic gate component can include at least one AND gate, at least one OR gate, at least one XOR gate, at least one XOR gate, etc. The second logic gate component includes different logic gates, and the logic gate operation method is also different.

[0114] by Figure 5 Taking the second logic gate component shown as an example, the second logic gate component includes an AND gate and an OR gate. First, the length signal data_type_b16 is inverted to obtain the inverted length signal ~data_type_b16. Then, the low-order operation result sum0[16:0], the first high-order operation result sum1[16:0] and the inverted length signal ~data_type_b16 are input into the AND gate, and the AND operation is performed through the AND gate to obtain the AND operation result. Among them, when the low-order operation result sum0[16:0] is performed with the AND operation, the sign bit sum0

[16] can be extracted from the low-order operation result sum0[16:0] for the AND operation. Similarly, when the first high-order operation result sum1[16:0] is performed with the AND operation, the sign bit sum1

[16] can be extracted from the first high-order operation result sum1[16:0] for the AND operation. After that, the AND operation result and the second high-order operation result sum1_p1[16:0] are input into the OR gate, and the OR operation is performed through the OR gate to obtain the first comparison signal high16_abs_bLarger. Among them, when the second high-order operation result sum1_p1[16:0] is ORed, the sign bit sum1_p1

[16] can be extracted from the second high-order operation result sum1_p1[16:0] for OR operation. The logical formula of this process is: high16_abs_bLarger=sum1_p1

[16] |sum1

[16] &sum0

[16] &~data_type_b16. Among them, "|" is the OR operation symbol, and "&" is the AND operation symbol.

[0115] The first comparison signal high16_abs_bLarger is used to indicate the absolute value comparison result of a pair of first data in the case of the first length, or the absolute value comparison result of a pair of high-order data in the case of the second length. Taking the first length as 32 and the second length as 16 as an example, for 16-bit data, the first comparison signal high16_abs_bLarger indicates that the absolute value of the high 16-bit data b[31:16] is greater than the absolute value of the high 16-bit data a[31:16], or, for 32-bit data, the first comparison signal high16_abs_bLarger indicates that the absolute value of the 32-bit data b[31:0] is greater than the absolute value of the 32-bit data a[31:0].

[0116] The content indicated by the first comparison signal can be divided into two cases. One case is sum1_p1

[16] =1, indicating that the second high-order operation result is a negative number. In this case, whether it is 16-bit data or 32-bit data, the absolute value of b[31:16] is greater than the absolute value of a[31:16]. The other case is for 32-bit data, if sum1_p1

[16] =0, and sum1

[16] =1, it is equivalent to the high 16-bit data a[31:16] is equal to b[31:16]. In this case, the low 16-bit data needs to be compared. When sum0

[16] =1, it means that the low-order operation result is a negative number. In this case, the absolute value of the low 16-bit b[15:0] is greater than the absolute value of a[15:0], which is equivalent to the absolute value of b[31:0] is greater than the absolute value of a[31:0] for 32-bit data.

[0117] Next, the length signal, the first comparison signal and the low-order operation result are input into the second selection component, and the second comparison signal is determined by the second selection component. Figure 5, the length signal data_type_b16, the first comparison signal high16_abs_bLarger and the low-bit operation result sum0[16:0] are all input into the second selection component. If the length signal data_type_b16 indicates the second length, for example, 16-bit data, the second selection component selects the sign bit sum0

[16] in the low-bit operation result sum0[16:0] as the value of the second comparison signal, thereby indicating the absolute value comparison result of a pair of low-bit data in the case of the second length. If the length signal data_type_b16 indicates the first length, for example, 32-bit data, the second selection component selects the first comparison signal high16_abs_bLarger as the second comparison signal, thereby indicating the absolute value comparison result of a pair of first data in the case of the first length. The logical formula of the process is: low16_abs_bLarger=data_type_b16? sum0

[16] :high16_abs_bLarger.

[0118] Taking the first length being 32 and the second length being 16 as an example, for 16-bit data, the second comparison signal low16_abs_bLarger indicates that the absolute value of the lower 16-bit data b[15:0] is greater than the absolute value of the lower 16-bit data a[15:0], or, for 32-bit data, the second comparison signal low16_abs_bLarger indicates that the absolute value of the 32-bit data b[31:0] is greater than the absolute value of the 32-bit data a[31:0].

[0119] In the embodiment of the present application, the first comparison signal needs to be input into the third processing subunit, and the third processing subunit is connected to the second determination subunit. The third processing subunit is used to take the maximum value of a pair of high-order data based on the first comparison signal to obtain a third processing result. It can be understood that in addition to inputting the first comparison signal and the high-order data into the third processing subunit, other information can also be input, and the other information includes but is not limited to at least one of a sign signal, an operation signal, a length signal, a type signal, a data signal, etc.

[0120] For example, Figure 5 As shown, the third processing subunit includes a first determining component and a third selecting component. The first determining component is connected to the second selecting component, and the first determining component is connected to the third selecting component.

[0121] The first determination component is used to determine a first selection signal based on a sign signal, a first comparison signal, a data signal indicating floating-point data or fixed-point data, and a type signal indicating a maximum value or a minimum value, the first selection signal being used to indicate whether to select specified high-order data in a pair of high-order data; the third selection component is used to select a third processing result from a pair of high-order data based on the first selection signal.

[0122] In the embodiment of the present application, the data signal is used to indicate floating-point data or fixed-point data. The value of the data signal is different, and the content indicated by the data signal is also different. For example, when the value of the data signal is 0, the data signal is used to indicate fixed-point data, and when the value of the data signal is 1, the data signal is used to indicate floating-point data.

[0123] The type signal is used to indicate whether to take the maximum value or the minimum value. The type signal indicates different contents depending on the value of the type signal. For example, when the type signal is 0, the type signal indicates the minimum value, and when the type signal is 1, the type signal indicates the maximum value.

[0124] At least one of the sign signal unsign_sel, the first comparison signal high16_abs_bLarger, the data signal fp_sel, and the type signal max_sel is input into the first determination component, and the first selection signal high16_b_sel is determined by the first determination component. The first selection signal is used to indicate whether to select a specified high-order data in a pair of high-order data. For example, if the pair of high-order data is a[31:16] and b[31:16], the first selection signal is used to indicate whether to select b[31:16].

[0125] Alternatively, if Figure 5 As shown, the second determination subunit further includes a fifth selection component and a sixth selection component. The fifth selection component is used to select a first sign bit from a sign bit of high-order data included in a first data and a sign bit of low-order data included in the first data according to the length signal. The sixth selection component is used to select a second sign bit from a sign bit of high-order data included in another first data and a sign bit of low-order data included in the first data according to the length signal.

[0126] If the length signal indicates the first length, the fifth selection component selects a sign bit of the high-order data included in one of the first data as the first sign bit, and the sixth selection component selects a sign bit of the high-order data included in another of the first data as the second sign bit. If the length signal indicates the second length, the fifth selection component selects a sign bit of the low-order data included in one of the first data as the first sign bit, and the sixth selection component selects a sign bit of the low-order data included in another of the first data as the second sign bit.

[0127] The logic formula of the fifth selection component can be expressed as a_sign_mux=data_type_b16?a

[15] :a

[31] , and the logic formula of the sixth selection component can be expressed as b_sign_mux=data_type_b16?b

[15] :b

[31] . Wherein, a_sign_mux represents the first sign bit, b_sign_mux represents the second sign bit, data_type_b16 represents the length signal, a

[15] and a

[31] represent the sign bit of the low-order data included in one first data and the sign bit of the high-order data included in the first data, respectively, and b

[15] and b

[31] represent the sign bit of the low-order data included in another first data and the sign bit of the high-order data included in the first data, respectively.

[0128] At least one of the sign signal unsign_sel, the first comparison signal high16_abs_bLarger, the data signal fp_sel, the type signal max_sel, the first sign bit a

[31] and the second sign bit b

[31] may be input into the first determination component, and the first selection signal high16_b_sel may be determined by the first determination component.

[0129] The following describes the process of determining the first selection signal by the first determination component. It can be understood that the implementation principle of the determination process is similar to the implementation principle of the maximum value submodule mentioned below. Among them, the implementation principle of the maximum value submodule is described in detail below, and the implementation principle of the first determination component is briefly described here.

[0130] First, the first determination component is used to determine the first high-order signal fp_bLarger according to the first sign bit a_sign_mux, the second sign bit b_sign_mux and the first comparison signal high16_abs_bLarger. The first high-order signal fp_bLarger is used to indicate the comparison result of a pair of high-order data when a pair of high-order data is floating-point data. The logical formula can be expressed as: fp_bLarger = ~(a_sign_mux^b_sign_mux)? ~(a_sign_mux^high16_abs_bLarger):

[0131] (a_sign_mux&~b_sign_mux).

[0132] Next, the first determination component is used to determine the second high-order signal signedInt_bLarger according to the first sign bit a_sign_mux, the second sign bit b_sign_mux and the first comparison signal high16_abs_bLarger, and the second high-order signal signedInt_bLarger is used to indicate the comparison result of a pair of high-order data when a pair of high-order data is signed fixed-point data. The logic formula can be expressed as: signedInt_bLarger = (a_sign_mux^b_sign_mux)? (a_sign_mux&~b_sign_mux):high16_abs_bLarger.

[0133] Then, the first determination component is used to determine the third high-bit signal int_bLarger according to the second high-bit signal signedInt_bLarger, the first comparison signal high16_abs_bLarger and the sign signal unsign_sel, and the third high-bit signal int_bLarger is used to indicate the comparison result of a pair of high-bit data when the pair of high-bit data is fixed-point data. The logical formula can be expressed as: int_bLarger=unsign_sel?high16_abs_bLarger:signedInt_bLarger.

[0134] Next, the first determining component is used to determine the high-order comparison signal bLarger according to the first high-order signal fp_bLarger, the third high-order signal int_bLarger and the data signal fp_sel, and the high-order comparison signal bLarger is used to indicate the comparison result of a pair of high-order data. The logical formula can be expressed as: bLarger=fp_sel?fp_bLarger:int_bLarger.

[0135] Afterwards, the first determination component is used to perform an XOR operation on the high-order comparison signal bLarger and the type signal max_sel to obtain a first selection signal high16_b_sel. The logic formula can be expressed as: high16_b_sel = ~(bLarger^max_sel).

[0136] Next, the first selection signal high16_b_sel, the high-order data a[31:16], and the high-order data b[31:16] are input into the third selection component. If the first selection signal indicates to select the specified high-order data, for example, the specified high-order data is b[31:16], then the third selection component selects b[31:16] as the third processing result. If the first selection signal indicates not to select the specified high-order data, then the third selection component selects a[31:16] as the third processing result. The logic formula of the third selection component is: cmp_res[31:16]=high16_b_sel? b[31:16]:a[31:16], cmp_res[31:16] represents the third processing result.

[0137] In the embodiment of the present application, the second comparison signal needs to be input into the fourth processing subunit, and the fourth processing subunit is connected to the second determination subunit. The fourth processing subunit is used to take the maximum value of a pair of low-order data based on the second comparison signal to obtain a fourth processing result. It can be understood that in addition to inputting the second comparison signal and the low-order data into the fourth processing subunit, other information can also be input, and the other information includes but is not limited to at least one of a sign signal, an operation signal, a length signal, a type signal, a data signal, etc.

[0138] For example, Figure 5 As shown, the fourth processing subunit includes a second determining component and a fourth selecting component. The second determining component is connected to the second selecting component, and the second determining component is connected to the fourth selecting component.

[0139] The second determination component is used to determine a second selection signal based on the sign signal, the second comparison signal, the data signal and the type signal, and the second selection signal is used to indicate whether to select specified low-order data in a pair of low-order data; the fourth selection component is used to select a fourth processing result from a pair of low-order data based on the second selection signal.

[0140] At least one of the sign signal unsign_sel, the second comparison signal low16_abs_bLarger, the data signal fp_sel, and the type signal max_sel is input into the second determination component, and the second selection signal low16_b_sel is determined by the second determination component. Optionally, the second determination subunit further includes a fifth selection component and a sixth selection component. In this case, at least one of the sign signal unsign_sel, the second comparison signal low16_abs_bLarger, the data signal fp_sel, the type signal max_sel, the first sign bit a

[15] and the second sign bit b

[15] is input into the second determination component, and the second selection signal low16_b_sel is determined by the second determination component. The second selection signal is used to indicate whether to select a specified low-order data in a pair of low-order data. For example, if a pair of low-order data is a[15:0] and b[15:0], the second selection signal is used to indicate whether to select b[15:0].

[0141] The process of determining the second selection signal by the second determination component is described below. It can be understood that the implementation principle of the determination process is similar to the implementation principle of the maximum value submodule mentioned below. Among them, the implementation principle of the maximum value submodule is described in detail below, and the implementation principle of the second determination component is briefly described here.

[0142] First, the second determination component is used to determine the first low-bit signal fp_bLarger according to the first sign bit a_sign_mux, the second sign bit b_sign_mux and the second comparison signal low16_abs_bLarger. The first low-bit signal fp_bLarger is used to indicate the comparison result of a pair of low-bit data when a pair of low-bit data is floating-point data. The logical formula can be expressed as: fp_bLarger = ~(a_sign_mux^b_sign_mux)? ~(a_sign_mux^low16_abs_bLarger):

[0143] (a_sign_mux&~b_sign_mux).

[0144] Next, the second determination component is used to determine the second low-bit signal signedInt_bLarger according to the first sign bit a_sign_mux, the second sign bit b_sign_mux and the second comparison signal low16_abs_bLarger, and the second low-bit signal signedInt_bLarger is used to indicate the comparison result of a pair of low-bit data when a pair of low-bit data is signed fixed-point data. The logic formula can be expressed as: signedInt_bLarger = (a_sign_mux^b_sign_mux)? (a_sign_mux&~b_sign_mux):low16_abs_bLarger.

[0145] Then, the second determination component is used to determine the third low-bit signal int_bLarger according to the second low-bit signal signedInt_bLarger, the second comparison signal low16_abs_bLarger and the sign signal unsign_sel, and the third low-bit signal int_bLarger is used to indicate the comparison result of a pair of low-bit data when the pair of low-bit data is fixed-point data. The logical formula can be expressed as: int_bLarger=unsign_sel?low16_abs_bLarger:signedInt_bLarger.

[0146] Next, the second determining component is used to determine the low-bit comparison signal bLarger according to the first low-bit signal fp_bLarger, the third low-bit signal int_bLarger and the data signal fp_sel, and the low-bit comparison signal bLarger is used to indicate the comparison result of a pair of low-bit data. The logical formula can be expressed as: bLarger=fp_sel?fp_bLarger:int_bLarger.

[0147] Afterwards, the second determination component is used to perform an XOR operation on the low-bit comparison signal bLarger and the type signal max_sel to obtain a second selection signal low16_b_sel. The logic formula can be expressed as: low16_b_sel = ~(low16_bLarger^max_sel).

[0148] Next, the second selection signal low16_b_sel, the low-order data a[15:0], and the low-order data b[15:0] are input into the fourth selection component. If the second selection signal indicates to select the designated low-order data, for example, the designated low-order data is b[15:0], then b[15:0] is selected as the fourth processing result by the fourth selection component. If the second selection signal indicates not to select the designated low-order data, then a[15:0] is selected as the fourth processing result by the fourth selection component. The logic formula of the fourth selection component is: cmp_res[15:0]=low16_b_sel? b[15:0]:a[15:0], cmp_res[15:0] represents the fourth processing result.

[0149] In the embodiment of the present application, the third processing result cmp_res[31:16] and the fourth processing result cmp_res[15:0] can be combined into the first maximum value result.

[0150] In summary, the first summation result can be determined by the summation unit, and the first maximum value result can be determined by the maximum value unit. The first summation result and the first maximum value result are both input into the first selection unit, and the first selection unit is used to select the first summation result as the first operation result when the operation type is summation, and select the first maximum value result as the first operation result when the operation type is maximum value.

[0151] like Figure 3 As shown, if the operator cmp_sel indicates summation, the first selection unit selects the first summation result add_res[31:0] as the first operation result result[31:0]. If the operator cmp_sel indicates maximum value, the first selection unit selects the first maximum value result cmp_res[31:0] as the first operation result result[31:0]. The logic formula of the first selection unit is: result[31:0]=cmp_sel? cmp_res[31:0]:add_res[31:0].

[0152] Based on the above description of the first sharing module, it can be seen that Figure 6 As shown, taking 32-bit data as an example, it is necessary to input at least one of the two first data a[31:0] and b[31:0], the data signal fp_sel, the sign signal unsign_sel, the operation signal cmp_sel, the type signal max_sel and the length signal data_type_b16 into the first shared module, and determine the first operation result result[31:0] through the first shared module.

[0153] Optionally, a[31:0] and b[31:0] represent the input 32-bit data. When fp_sel is 1, it indicates that the input data is floating-point data, and when fp_sel is 0, it indicates that the input data is fixed-point data. unsign_sel is valid when fp_sel = 0, unsign_sel is 1, it indicates that the input data is unsigned fixed-point data, and unsign_sel is 0, it indicates that the input data is signed fixed-point data. When cmp_sel is 1, it indicates a maximum value operation, and when cmp_sel is 0, it indicates a sum operation. max_sel is valid when cmp_sel = 1, when max_sel is 1, it indicates a maximum value, and when max_sel is 0, it indicates a smaller value. When data_type_b16 is 1, it indicates 16-bit data, and when data_type_b16 is 0, it indicates 32-bit data. result[31:0] is the output 32-bit data.

[0154] Next, the second shared module is introduced. Figure 7 As shown, the second sharing module includes a summing submodule, a first processing submodule, a maximum value submodule and a selection submodule. The summing submodule is connected to the first processing submodule and to the maximum value submodule. The selection submodule is also connected to the first processing submodule and to the maximum value submodule.

[0155] The summation submodule is used to sum a pair of second data to obtain a second summation result when the operation signal indicates summation, or to sum a second data and another second data after inversion to obtain a second summation result when the operation signal indicates taking a maximum value. The length of the second summation result is the second length.

[0156] See also Figure 7 , taking the second length of 32 as an example, a pair of second data are a[31:0] and b[31:0] respectively. The summing submodule includes a first inverting unit, a second selecting unit and a first adding unit, the first adding unit is connected to the first inverting unit and is connected to the second selecting unit.

[0157] The first inversion unit is used to use a second data as a first inversion result when the operation signal indicates summation, and to use an inverted second data as the first inversion result when the operation signal indicates maximum value.

[0158] That is, the operation signal cmp_sel and the second data b[31:0] are input into the first inversion unit. If the operation signal cmp_sel indicates summing, the first inversion unit uses the second data b[31:0] as the first inversion result b_mux[31:0], that is, b_mux[31:0]=b[31:0]. If the operation signal cmp_sel indicates taking the maximum value, the first inversion unit inverts the second data b[31:0] to obtain the first inversion result b_mux[31:0], that is, b_mux[31:0]=~b[31:0]. The logic formula of the first inversion unit is: b_mux[31:0]=cmp_sel?~b[31:0]:b[31:0].

[0159] The second selection unit is used to select target data from the first specified data and the second specified data according to the operation signal. The embodiment of the present application does not limit the first specified data and the second specified data, and the first specified data and the second specified data can be any two different data. Optionally, if the operation signal indicates to sum, the second selection unit selects the first specified data as the target data, and if the operation signal indicates to take the maximum value, the second selection unit selects the second specified data as the target data.

[0160] exist Figure 7 , the first designated data is 0, and the second designated data is 1. If the operation signal cmp_sel indicates summation, the second selection unit selects 0 as the target data, and if the operation signal cmp_sel indicates maximum value, the second selection unit selects 1 as the target data. Optionally, when the value of the operation signal cmp_sel is 0, it indicates summation, and when the value is 1, it indicates maximum value. That is to say, when the value of the operation signal cmp_sel is 0, the second selection unit selects 0 as the target data, and when the value of the operation signal cmp_sel is 1, the second selection unit selects 1 as the target data. In short, the target data obtained by the second selection unit is the same as the operation signal cmp_sel.

[0161] The first adding unit is used to add another second data and the first inverted result according to the target data to obtain a second summation result.

[0162] Please continue to see Figure 7. Input the target data, the second data a[31:0] and the first inverted result b_mux[31:0] into the first adding unit. Optionally, the target data and the operation signal cmp_sel are the same. If the operation signal cmp_sel indicates to take the maximum value, for example, cmp_sel=1, the first adding unit adds the second data a[31:0], the first inverted result b_mux[31:0] and 1 to obtain sum[32:0]=a[31:0]+b_mux[31:0]+1; if the operation signal cmp_sel indicates to sum, for example, cmp_sel=0, the first adding unit adds the second data a[31:0] and the first inverted result b_mux[31:0] to obtain sum[32:0]=a[31:0]+b_mux[31:0]. The logic formula of the first addition unit is: sum[32:0]=a[31:0]+b_mux[31:0]+cmp_sel.

[0163] The first processing submodule is used to determine a third overflow signal for indicating whether there is an overflow based on the sign signal and the second summation result, and determine a fifth processing result based on the sign signal, the third overflow signal and the second summation result, wherein the fifth processing result is the second summation result or is obtained by saturating the second summation result.

[0164] In an embodiment of the present application, a sign signal is used to indicate whether it is signed or unsigned. Optionally, if a pair of second data is unsigned fixed-point data, since unsigned fixed-point data has no sign bit, the unsigned fixed-point data can be regarded as a positive number. In this case, if the second summation result sum[32:0] has an overflow, the sign bit of the second summation result is 1, that is, sum

[32] =1 indicates that the second summation result has an overflow. If a pair of second data is signed fixed-point data, since the signed fixed-point data has a sign bit, a positive number or a negative number can be indicated by the sign bit. In this case, the second summation result has two sign bits, and if the second summation result sum[32:0] has an overflow, the values ​​of the two sign bits are different, that is, when sum

[32] is different from sum

[31] , it indicates that the second summation result has an overflow. Optionally, if sum

[31] =0, it indicates that the second summation result has a positive overflow, and if sum

[31] =1, it indicates that the second summation result has a negative overflow.

[0165] Based on the above principle, the first processing submodule can determine the third overflow signal based on the sign signal and the second summation result, and the third overflow signal is used to indicate whether the second summation result has an overflow, and when the second summation result has an overflow, the third overflow signal can indicate whether the overflow of the second summation result is a positive overflow or a negative overflow. Among them, the positive overflow is also called positive overflow (Positive Overflow), and the negative overflow is also called negative overflow (Negative Overflow).

[0166] Optionally, the logic formula of the third overflow signal ovf_detect can be expressed as: ovf_detect=unsign_sel?sum

[32] ^sum

[31] :sum

[32] .

[0167] The first processing submodule may also determine whether to perform saturation processing on the second summation result according to the sign signal and the third overflow signal.

[0168] Optionally, if the sign signal indicates unsigned, and the third overflow signal indicates that the second summation result does not have an overflow situation, the first processing submodule determines not to perform saturation processing on the second summation result, and the second summation result can be used as the fifth processing result. If the sign signal indicates unsigned, and the third overflow signal indicates that the second summation result has an overflow situation, the first processing submodule determines to perform saturation processing on the second summation result, and the second summation result can be reset to the maximum value of the second length data, and the maximum value of the second length data is the fifth processing result. For example, when the second summation result is 32-bit data, the maximum value of the 32-bit data can be expressed as 32'hffff_ffff.

[0169] Optionally, if the sign signal indicates that there is a sign, and the third overflow signal indicates that there is no overflow in the second summation result, the first processing submodule determines not to perform saturation processing on the second summation result, and the second summation result can be used as the fifth processing result. If the sign signal indicates that there is a sign, and the third overflow signal indicates that there is a positive overflow in the second summation result, the first processing submodule determines to perform saturation processing on the second summation result, and the second summation result can be reset to the maximum positive value of the second length data, and the maximum positive value of the second length data is the fifth processing result. For example, when the second summation result is 32-bit data, the maximum positive value of the 32-bit data can be expressed as 32'h7fff_ffff. If the sign signal indicates that there is a sign, and the third overflow signal indicates that there is a negative overflow in the second summation result, the first processing submodule determines to perform saturation processing on the second summation result, and the second summation result can be reset to the minimum negative value of the second length data, and the minimum negative value of the second length data is the fifth processing result. For example, when the second summation result is 32-bit data, the minimum negative value of the 32-bit data may be represented by 32'h8000_0000.

[0170] Optionally, the logical formula of the fifth processing result can be expressed as: add_res[31:0]=ovf_detect?(unsign_sel?32'hffff_ffff:{sum

[32] ,{31{~sum

[32] }}}):sum[31:0].

[0171] The maximum value submodule is used to perform maximum value extraction on a pair of second data based on the type signal to obtain a second maximum value extraction result.

[0172] In the embodiment of the present application, if the type signal indicates to take the maximum value, the maximum value submodule selects the largest second data from a pair of second data as the second maximum value result. If the type signal indicates to take the minimum value, the maximum value submodule selects the smallest second data from a pair of second data as the second maximum value result.

[0173] Optionally, the data signal is input to the maximum value submodule. If the data signal indicates floating-point data, the second maximum value result is determined according to the sign bit of a pair of second data. If the sign bit of one second data in a pair of second data indicates that the second data is a positive number, for example, b

[31] =0, and the sign bit of the other second data indicates that the second data is a negative number, for example, a

[31] =1, in this case, it can be determined that the positive number is greater than the negative number, that is, the 32-bit floating-point data b[31:0] is greater than the 32-bit floating-point data a[31:0]. If the sign bits of both second data indicate that the second data is a positive number or a negative number, the maximum value submodule determines the second maximum value result according to the fifth processing result.

[0174] Exemplarily, in the case of taking the maximum value, the fifth processing result sum[32:0]=a[31:0]+~b[31:0]+1, if the sign bits of the two second data both indicate that the second data is a positive number, then when the sign bit of the fifth processing result indicates a negative number, for example, sum

[32] =1, it means that b[31:0] is greater than a[31:0], and when the sign bit of the fifth processing result indicates a positive number, it means that b[31:0] is less than a[31:0]. Similarly, if the sign bits of the two second data both indicate that the second data is a negative number, then when the sign bit of the fifth processing result indicates a positive number, for example, sum

[32] =0, it means that b[31:0] is greater than a[31:0], and when the sign bit of the fifth processing result indicates a negative number, it means that b[31:0] is less than a[31:0].

[0175] If the data signal indicates fixed-point data, the sign signal can be input into the maximum value submodule, and the maximum value submodule determines the second maximum value result according to the fifth processing result. Exemplarily, if the sign signal indicates unsigned, when the sign bit of the fifth processing result sum[32:0] indicates a negative number, for example, sum

[32] =1, it means that the 32-bit unsigned fixed-point data b[31:0] is greater than the 32-bit unsigned fixed-point data a[31:0], and when the sign bit of the fifth processing result sum[32:0] indicates a positive number, it means that b[31:0] is less than a[31:0]. If the sign signal indicates a sign, then if the sign bit of one of the pair of second data indicates that the second data is a positive number, for example, b

[31] =0, and the sign bit of the other second data indicates that the second data is a negative number, for example, a

[31] =1, in this case, it can be determined that the positive number is greater than the negative number, that is, the 32-bit signed fixed-point data b[31:0] is greater than the 32-bit signed fixed-point data a[31:0]. If the sign bits of both second data indicate that the second data is a positive number or a negative number, the maximum value submodule determines the second maximum value result according to the fifth processing result.

[0176] Exemplarily, in the case of taking the maximum value, the fifth processing result sum[32:0]=a[31:0]+~b[31:0]+1. If the sign bits of the two second data both indicate that the second data is a positive number or a negative number, then when the sign bit of the fifth processing result indicates a negative number, for example, sum

[32] =1, it means that b[31:0] is greater than a[31:0]. When the sign bit of the fifth processing result indicates a positive number, it means that b[31:0] is less than a[31:0].

[0177] Based on the above content, we can know that Figure 7As shown, the type signal max_sel, the data signal fp_sel, the sign signal unsign_sel, the second data a[31:0], the second data b[31:0] and the fifth processing result sum[32:0] are input into the maximum value submodule, and the maximum value submodule determines the second maximum value result cmp_res[31:0] in the second data a[31:0] and the second data b[31:0].

[0178] See also Figure 8 , Figure 8 1 is a schematic diagram of a maximum value submodule provided in an embodiment of the present application. The maximum value submodule includes a first processing unit, a second processing unit, a third processing unit and a third selection unit.

[0179] The first processing unit is used to determine a first signal according to a pair of second data and a fifth processing result, and the first signal is used to indicate a comparison result of a pair of second data when the pair of second data is floating-point data. Taking the second data as 32-bit floating-point data as an example, that is, the first processing unit can determine the first signal fp_bLarger according to the second data a[31:0], the second data b[31:0] and the fifth processing result sum[32:0], and indicate through the first signal fp_bLarger whether the second data a[31:0] is greater than or less than the second data b[31:0].

[0180] Alternatively, if Figure 8 As shown, the first processing unit includes a first XNOR gate, a second XNOR gate, a first AND gate and a first selection subunit.

[0181] The first XNOR gate is used to determine a first XNOR result based on a pair of sign bits of the second data. Figure 8 In the example, the first XOR gate determines the first XOR result ~(a

[31] ^b

[31] ) according to the sign bit a

[31] of the second data a[31:0] and the sign bit b

[31] of the second data b[31:0]. Wherein ^ represents the XOR sign, ~ represents the inversion sign, and the XOR result is equivalent to the inversion of the XOR result.

[0182] The second XNOR gate is used to determine a second XNOR result based on a sign bit of the second data and a sign bit of the fifth processing result. Figure 8 In the example, the second XNOR gate determines the second XNOR result ˜(a

[31] ^sum

[32] ) according to the sign bit a

[31] of the second data a[31:0] and the sign bit sum

[32] of the fifth processing result sum[32:0].

[0183] The first AND gate is used to determine the first AND gate result based on the inversion result of the sign bit of one second data and the sign bit of another second data. Figure 8 In the first AND gate, the first AND gate determines the first AND gate result a

[31] &(~b

[31] ) according to the sign bit a

[31] of the second data a[31:0] and the inverted result ~b

[31] of the sign bit of the second data b[31:0].

[0184] The first selection subunit is used to determine the first signal according to the first XEN_OR result, the second XEN_OR result and the first AND gate result. Figure 8 In the example, the first signal fp_bLarger is determined according to the first XOR result ~(a

[31] ^b

[31] ), the second XOR result ~(a

[31] ^sum

[32] ) and the first AND gate result a

[31] &(~b

[31] ). At this time, the logical formula is: fp_bLarger = ~(a

[31] ^b

[31] )? ~(a

[31] ^sum

[32] ):(a

[31] &~b

[31] ).

[0185] Optionally, when a pair of second data are both 32-bit floating point data, if fp_bLarger=1, it means that the second data b[31:0] is larger than the second data a[31:0].

[0186] The second processing unit is used to determine a second signal according to a pair of second data and a fifth processing result, wherein the second signal is used to indicate a comparison result of a pair of second data when the pair of second data is signed fixed-point data. Taking the second data as 32-bit signed fixed-point data as an example, that is, the second processing unit can determine a second signal signedInt_bLarger according to the second data a[31:0], the second data b[31:0] and the fifth processing result sum[32:0], and indicate through the second signal signedInt_bLarger whether the second data a[31:0] is greater than or less than the second data b[31:0].

[0187] Alternatively, if Figure 8 As shown, the second processing unit includes a second AND gate, an XOR gate and a second selection subunit.

[0188] The second AND gate is used to determine the second AND gate result based on the inversion result of the sign bit of one second data and the sign bit of another second data. Figure 8 In the embodiment, the second AND gate determines the second AND gate result a

[31] &(~b

[31] ) according to the sign bit a

[31] of the second data a[31:0] and the inverted result ~b

[31] of the sign bit of the second data b[31:0].

[0189] An XOR gate is used to determine an XOR result based on a sign bit of a pair of second data. Figure 8In the embodiment, the XOR gate determines the XOR result a

[31] ^b

[31] according to the sign bit a

[31] of the second data a[31:0] and the sign bit b

[31] of the second data b[31:0].

[0190] The second selection subunit is used to determine the second signal based on the fifth processing result, the second AND gate result and the XOR result. Figure 8 In the example, the second signal signedInt_bLarger is determined according to the second AND gate result, the XOR result a

[31] ^b

[31] and the sign bit sum

[32] of the fifth processing result. At this time, the logical formula is: signedInt_bLarger = (a

[31] ^b

[31] )? (a

[31] &~b

[31] ):sum

[32] .

[0191] Optionally, when a pair of second data are both 32-bit signed fixed-point data, if signedInt_bLarger=1, it means that the second data b[31:0] is greater than the second data a[31:0].

[0192] The third processing unit is used to determine a third selection signal according to the first signal, the second signal and the fifth processing result, and the third selection signal is used to indicate whether to select the specified second data in the pair of second data. Taking the second data as 32-bit data as an example, that is, the third processing unit can determine the third selection signal b_sel according to the first signal fp_bLarger, the second signal signedInt_bLarger and the fifth processing result sum[32:0], and indicate whether to select the second data b[31:0] through the third selection signal b_sel.

[0193] Alternatively, if Figure 8 As shown, the third processing unit includes a third selection subunit, a fourth selection subunit and a third XNOR gate.

[0194] The third selection subunit is used to determine a third signal according to the second signal, the fifth processing result and the sign signal, and the third signal is used to indicate the comparison result of a pair of second data when the pair of second data is fixed-point data. Take the second data as 32-bit fixed-point data as an example, that is, Figure 8As shown, the third selection subunit can determine the third signal int_bLarger according to the second signal signedInt_bLarger, the sign bit sum

[32] of the fifth processing result sum[32:0] and the sign signal unsign_sel, and indicate through the third signal int_bLarger whether the second data a[31:0] is greater than or less than the second data b[31:0]. The logical formula is: int_bLarger=unsign_sel? sum

[32] :signedInt_bLarger.

[0195] Optionally, if the sign signal unsign_sel indicates a sign, indicating that the pair of second data are both 32-bit signed fixed-point data, then int_bLarger=signedInt_bLarger, and the comparison result of the pair of second data is determined according to the second signal signedInt_bLarger. If the sign signal unsign_sel indicates an unsigned sign, indicating that the pair of second data are both 32-bit unsigned fixed-point data, then int_bLarger=sum

[32] , and the comparison result of the pair of second data is determined according to the sign bit sum

[32] of the fifth processing result. Optionally, when the pair of second data are both 32-bit unsigned fixed-point data, if sum

[32] =1, it means that the second data b[31:0] is greater than the second data a[31:0].

[0196] The fourth selection subunit is used to determine a comparison signal according to the first signal, the third signal and the data signal, wherein the comparison signal is used to indicate a comparison result of a pair of second data. For example, the second data is 32-bit data. That is, if Figure 8 As shown, the fourth selection subunit can determine the comparison signal bLarger according to the first signal fp_bLarger, the third signal int_bLarger and the data signal fp_sel, and indicate through the comparison signal bLarger whether the second data a[31:0] is greater than or less than the second data b[31:0]. The logical formula is: bLarger=fp_sel?fp_bLarger:int_bLarger.

[0197] The third XOR gate performs XOR operation on the comparison signal and the type signal to obtain the third selection signal. Figure 8 As shown, the third XOR gate performs an XOR operation on the comparison signal bLarger and the type signal max_sel to obtain the third selection signal b_sel. The logic formula is: b_sel = ~(bLarger^max_sel).

[0198] The third selection unit is used to select a second maximum value result from a pair of second data according to a third selection signal. Optionally, if the third selection signal indicates to take the maximum value, the designated second data in the pair of second data is selected as the second maximum value result; if the third selection signal indicates to take the minimum value, the non-designated second data in the pair of second data is selected as the second maximum value result.

[0199] Taking the second data as 32-bit data as an example, Figure 8 In the embodiment, the third selection unit selects the second maximum value result cmp_res[31:0] from the second data a[31:0] and the second data b[31:0] according to the third selection signal b_sel. The logical formula is: cmp_res[31:0]=b_sel?b[31:0]:a[31:0].

[0200] The selection submodule is used to select the fifth processing result as the second operation result when the operation signal indicates summation, or to select the second maximum value result as the second operation result when the operation signal indicates maximum value.

[0201] like Figure 7 As shown, the operation signal cmp_sel, the fifth processing result add_res[31:0] and the second maximum value result cmp_res[31:0] are input into the selection submodule. If the operation signal cmp_sel indicates summation, for example, cmp_sel=0, the fifth processing result add_res[31:0] is selected as the second operation result result[31:0] by the selection submodule. If the operation signal cmp_sel indicates maximum value, for example, cmp_sel=1, the second maximum value result cmp_res[31:0] is selected as the second operation result result[31:0] by the selection submodule. The logical formula is: result[31:0]=cmp_sel? cmp_res[31:0]:add_res[31:0].

[0202] Based on the above description of the second shared module, it can be seen that Fig. 9 As shown, taking 32-bit data as an example, it is necessary to input at least one of the two second data a[31:0] and b[31:0], the data signal fp_sel, the sign signal unsign_sel, the operation signal cmp_sel, and the type signal max_sel into the second shared module, and determine the second operation result result[31:0] through the second shared module.

[0203] Optionally, a[31:0] and b[31:0] represent the input 32-bit data. When fp_sel is 1, it indicates that the input data is floating-point data, and when fp_sel is 0, it indicates that the input data is fixed-point data. unsign_sel is valid when fp_sel = 0, and when unsign_sel is 1, it indicates that the input data is unsigned fixed-point data, and when unsign_sel is 0, it indicates that the input data is signed fixed-point data. When cmp_sel is 1, it indicates a maximum value operation, and when cmp_sel is 0, it indicates a summation operation. max_sel is valid when cmp_sel = 1, and when max_sel is 1, it indicates taking the maximum value, and when max_sel is 0, it indicates taking the smaller value.

[0204] In the above-mentioned vector operation circuit, a vector operation is performed on a pair of first data of a first length through a first shared module to obtain a first operation result of the first length, and a vector operation is performed on a pair of second data of a second length through a second shared module to obtain a second operation result of the second length. The target selection module selects to output the second operation result or the first operation result, thereby realizing vector operation of data of the first length and vector operation of data of the second length in one circuit, increasing circuit functions, and reducing the number of circuits, so that when the vector operation circuit is laid out in a chip, the chip volume can be reduced.

[0205] See also Fig.10 , Fig.10 is a schematic diagram of the structure of another vector operation circuit provided in an embodiment of the present application. Fig.10 As shown, the vector operation circuit includes 4 levels of shared circuits and a target selection module. The first level of shared circuits includes four first shared modules, the second level of shared circuits includes two first shared modules, the third level of shared circuits includes one first shared module, and each first shared module is connected to a beat register.

[0206] The first two first shared modules included in the first-level shared circuit are connected to the first first shared module included in the second-level shared circuit through their respective beat registers. Similarly, the last two first shared modules included in the first-level shared circuit are connected to the second first shared module included in the second-level shared circuit through their respective beat registers. The two first shared modules included in the second-level shared circuit are connected to the first shared module included in the third-level shared circuit.

[0207] The first shared module is used to perform a vector operation on a pair of first data to obtain a first operation result. The lengths of the first data and the first operation result are the same, both being the first length. Wherein, when the first shared module is located in the second-level shared circuit, the first data is the first operation result obtained by the first shared module connected to the first shared module included in the first-level shared circuit. Similarly, when the first shared module is located in the third-level shared circuit, the first data is the first operation result of the first shared module connected to the first shared module included in the second-level shared circuit.

[0208] Taking the first length of 32 bits as an example, a first shared module included in the first-level shared circuit performs vector operation on the first data din[255:224] and the first data din[223:192] to obtain a first operation result level1_res[127:96]. Another first shared module included in the first-level shared circuit performs vector operation on the first data din[191:160] and the first data din[159:128] to obtain a first operation result level1_res[95:64]. The first operation result level1_res[127:96] and the first operation result level1_res[95:64] are used as two first data of a first shared module included in the second-level shared circuit.

[0209] The second-level sharing circuit includes a first sharing module that performs vector operation on the first data level1_res[127:96] and the first data level1_res[95:64] to obtain a first operation result level2_res[63:32]. And so on, which will not be repeated here.

[0210] The fourth-level shared circuit includes a second shared module, and the second shared module is connected to the first shared module included in the third-level shared circuit through a beat register. The first operation result obtained by the first shared module included in the third-level shared circuit is split into a pair of second data, and the second shared module is used to perform vector operation on the pair of second data to obtain a second operation result. The length of the second data and the second operation result is both the second length, and the second length is half of the first length.

[0211] Still taking the first length of 32 bits as an example, the second length is 16 bits. The first operation result level3_res[31:0] obtained by the first sharing module included in the third-level sharing circuit is split into second data level3_res[31:16] and second data level3_res[15:0]. The second sharing module performs vector operation on the second data level3_res[31:16] and the second data level3_res[15:0] to obtain a second operation result b16_res[15:0].

[0212] The target selection module is connected to the second shared module and the first shared module included in the third-level shared circuit through the beat register. The target selection module is used to select and output the second operation result b16_res[15:0] or the first operation result b32_res[31:0] of the first shared module included in the third-level shared circuit to obtain the target selection result result[31:0].

[0213] It should be noted that the structures, functions, etc. of the first sharing module, the second sharing module, and the target selection module have been described above and will not be repeated here.

[0214] In the embodiment of the present application, a first shared module for performing vector operations on first data of a first length and a second shared module for performing vector operations on second data of a second length are combined and designed, thereby increasing circuit functions and reducing circuit data. Taking the first length as 32 bits and the second length as 16 as an example, the first shared module can be called a 32-bit functional module and the second shared module can be called a 16-bit functional module. By splitting the 32-bit functional module into two 16-bit logical operations internally, the resources of the 16-bit functional module are saved.

[0215] Among them, vector operations include sum operations. Fig.11 As shown, Fig.11 1 is a schematic diagram of a 32-bit summing module provided in an embodiment of the present application, wherein the 32-bit summing module is used to perform a summing operation on 32-bit unsigned data a[31:0] and 32-bit unsigned data b[31:0]. The summing operation on the 32-bit unsigned data can be divided into the summing operation on two 16-bit unsigned data.

[0216] The 32-bit summing module includes a high 16-bit adding submodule, a low 16-bit adding submodule, a first selecting submodule, a 32-bit saturation processing submodule, a high 16-bit saturation processing submodule, a low 16-bit saturation processing submodule and a second selecting submodule.

[0217] The lower 16-bit addition submodule is used to add the lower 16-bit data a[15:0] in a 32-bit unsigned data a[31:0] and the lower 16-bit data b[15:0] in another 32-bit unsigned data b[31:0] to obtain the addition result sum0[16:0] of 17-bit data. The sign bit sum0

[16] in the addition result sum0[16:0] will be input into the first selection submodule as a selection signal.

[0218] The upper 16-bit addition submodule is used to add the upper 16-bit data a[31:16] in a 32-bit unsigned data a[31:0] and the upper 16-bit data b[31:16] in another 32-bit unsigned data b[31:0] to obtain the addition results of two 17-bit data, namely, the addition result sum1[16:0] and the addition result sum1_p1[16:0]. The logical formula of sum1[16:0] is: sum1[16:0]=a[31:16]+b[31:16]. The logical formula of sum1_p1[16:0] is: sum1_p1[16:0]=a[31:16]+b[31:16]+1.

[0219] The first selection submodule is used to select the addition result sum1[16:0] or the addition result sum1_p1[16:0] as the first selection result sum1_mux[16:0] according to the sign bit sum0

[16] . The logic formula of the first selection result is: sum1_mux[16:0]=sum0

[16] ?sum1_p1[16:0]:sum1[16:0].

[0220] The 32-bit saturation processing submodule is used to determine whether there is an overflow according to the addition result sum0[16:0] and the first selection result sum1_mux[16:0]. If there is an overflow, the addition result sum0[16:0] and the first selection result sum1_mux[16:0] are saturated to obtain the maximum value 32'hffff_ffff of the 32-bit data, which is the 32-bit saturation processing result. If there is no overflow, the addition result sum0[16:0] and the first selection result sum1_mux[16:0] are merged to obtain a 32-bit saturation processing result. Optionally, the logical formula of the 32-bit saturation processing result b32_res[31:0] is: b32_res[31:0]=sum1_mux

[16] ? 32'hffff_ffff:{sum1_mux[15:0],sum0[15:0]}.

[0221] The upper 16-bit saturation processing submodule is used to determine whether there is an overflow based on the addition result sum1[16:0]. If there is an overflow, the addition result sum1[16:0] is saturated to obtain the maximum value 16'hffff of the 16-bit data, which is the upper 16-bit saturation processing result. If there is no overflow, the upper 16-bit saturation processing result is obtained based on the addition result sum1[16:0]. Optionally, the logic formula of the upper 16-bit saturation processing result b16_1_res[15:0] is: b16_1_res[15:0]=sum1

[16] ? 16'hffff:sum1[15:0].

[0222] The lower 16-bit saturation processing submodule is used to determine whether there is an overflow based on the addition result sum0[16:0]. If there is an overflow, the addition result sum0[16:0] is saturated to obtain the maximum value 16'hffff of the 16-bit data, which is the lower 16-bit saturation processing result. If there is no overflow, the lower 16-bit saturation processing result is obtained based on the addition result sum0[16:0]. Optionally, the logic formula of the lower 16-bit saturation processing result b16_0_res[15:0] is: b16_1_res[15:0]=sum0

[16] ? 16'hffff:sum0[15:0].

[0223] The second selection submodule is used to select a summation result from the 32-bit saturation processing result b32_res[31:0], the upper 16-bit saturation processing result b16_1_res[15:0], and the lower 16-bit saturation processing result b16_0_res[15:0] according to the length signal data_type_b16, and the summation result is obtained by summing a[31:0] and b[31:0] through the 32-bit summation module.

[0224] Optionally, if the length signal data_type_b16 indicates 16 bits, the second selection submodule selects the upper 16-bit saturation processing result b16_1_res[15:0] and the lower 16-bit saturation processing result b16_0_res[15:0] as the summation operation result. If the length signal data_type_b16 indicates 32 bits, the second selection submodule selects the 32-bit saturation processing result b32_res[31:0] as the summation operation result. Optionally, the logical formula of the summation operation result result[31:0] is: result[31:0]=data_type_b16? {b16_1_res[15:0], b16_0_res[15:0]}: b32_res[31:0].

[0225] Among them, vector operations also include maximum value operations. Fig.12 As shown, Fig.12 1 is a schematic diagram of the structure of a 32-bit maximum value module provided in an embodiment of the present application, and the 32-bit maximum value module is used to perform a maximum value operation on 32-bit unsigned data a[31:0] and 32-bit unsigned data b[31:0]. The maximum value operation on the 32-bit unsigned data can be divided into the maximum value operation on two 16-bit unsigned data.

[0226] The 32-bit maximum value module includes a high 16-bit comparison submodule, a high 16-bit equal submodule, a low 16-bit comparison submodule, a 32-bit processing submodule, a third selection submodule, a fourth selection submodule, a fifth selection submodule and a sixth selection submodule.

[0227] The upper 16-bit comparison submodule is used to compare the upper 16-bit data a[31:16] in the 32-bit unsigned data a[31:0] with the upper 16-bit data b[31:16] in the 32-bit unsigned data b[31:0] to obtain the upper 16-bit comparison signal b16_1_bLarger. The upper 16-bit comparison signal b16_1_bLarger is used to indicate whether the upper 16-bit data b[31:16] is greater than the upper 16-bit data a[31:16]. Optionally, the logic formula of the upper 16-bit comparison signal b16_1_bLarger is: b16_1_bLarger=(b[31:16]>a[31:16]).

[0228] The upper 16-bit equal submodule is used to determine whether the upper 16-bit data a[31:16] is equal to the upper 16-bit data b[31:16], and obtain the upper 16-bit equal signal b16_1_equal. Optionally, the logic formula of the upper 16-bit equal signal b16_1_equal is: b16_1_equal=(b[15:0]==a[15:0]).

[0229] The lower 16-bit comparison submodule is used to compare the lower 16-bit data a[15:0] and the lower 16-bit data b[15:0] to obtain the lower 16-bit comparison signal b16_0_bLarger. The lower 16-bit comparison signal b16_0_bLarger is used to indicate whether the lower 16-bit data b[15:0] is greater than the lower 16-bit data a[15:0]. Optionally, the logic formula of the lower 16-bit comparison signal b16_0_bLarger is: b16_0_bLarger=(b[15:0]>a[15:0]).

[0230] The third selection submodule is used to select a third selection result from the upper 16-bit data a[31:16] and the upper 16-bit data b[31:16] according to the upper 16-bit comparison signal b16_1_bLarger. Optionally, if the upper 16-bit comparison signal b16_1_bLarger indicates that b[31:16] is greater than a[31:16], the third selection submodule selects b[31:16] as the third selection result, otherwise, the third selection submodule selects a[31:16] as the third selection result. The logic formula of the third selection result b16_res[31:16] is: b16_res[31:16]=b16_1_bLarger? b[31:16]:a[31:16].

[0231] The fourth selection submodule is used to select a fourth selection result from the lower 16-bit data a[15:0] and the lower 16-bit data b[15:0] according to the lower 16-bit comparison signal b16_0_bLarger. Optionally, if the lower 16-bit comparison signal b16_0_bLarger indicates that b[15:0] is greater than a[15:0], the fourth selection submodule selects b[15:0] as the fourth selection result, otherwise, the fourth selection submodule selects a[15:0] as the fourth selection result. The logic formula of the fourth selection result b16_res[15:0] is: b16_res[15:0]=b16_0_bLarger? b[15:0]:a[15:0].

[0232] The 32-bit processing submodule is used to determine a 32-bit comparison signal according to the upper 16-bit comparison signal b16_1_bLarger, the upper 16-bit equal signal b16_1_equal and the lower 16-bit comparison signal b16_0_bLarger, wherein the 32-bit comparison signal is used to indicate a comparison result between 32-bit unsigned data a[31:0] and 32-bit unsigned data b[31:0].

[0233] Optionally, if the upper 16-bit comparison signal b16_1_bLarger indicates that b[31:16] is greater than a[31:16], for example, b16_1_bLarger=1, indicating that b[31:0] is greater than a[31:0], then the 32-bit comparison signal b32_bLarger indicates that b[31:0] is greater than a[31:0]. If the upper 16-bit comparison signal b16_1_bLarger indicates that b[31:16] is not greater than a[31:16], for example, b16_1_bLarger=0, and the upper 16-bit equal signal b16_1_equal indicates that b[31:16] is equal to a[31:16], for example, b16_1_equal=1, then: when the lower 16-bit comparison signal b16_0_bLarger indicates that b[15:0] is greater than a[15:0], for example, b16_0_bLarger=1, indicating that b[31:0] is greater than a[31:0], then the 32-bit comparison signal b32_bLarger indicates that b[31:0] is greater than a[31:0].

[0234] Optionally, the logic formula of the 32-bit comparison signal b32_bLarger is: b32_bLarger=b16_1_bLarger|~16_1_bLarger&b16_1_euqal&b16_0_bLarger=b16_1_bLarger|b16_1_euqal&b16_0_bLarger.

[0235] The fifth selection submodule is used to select a fifth selection result from the 32-bit unsigned data a[31:0] and the 32-bit unsigned data b[31:0] according to the 32-bit comparison signal b32_bLarger. Optionally, if the 32-bit comparison signal b32_bLarger indicates that b[31:0] is greater than a[31:0], the fifth selection submodule selects b[31:0] as the fifth selection result b32_res[31:0], otherwise, the fifth selection submodule selects a[31:0] as the fifth selection result b32_res[31:0]. The logic formula of the fifth selection submodule is: b32_res[31:0]=b32_bLarger? b[31:0]:a[31:0].

[0236] The sixth selection submodule is used to select the sixth selection result result[31:0] from the fifth selection result b32_res[31:0], the third selection result b16_res[31:16], and the fourth selection result b16_res[15:0] according to the length signal data_type_b16, and the sixth selection result is the maximum value of a[31:0] and b[31:0]. Optionally, if the length signal data_type_b16 indicates 32 bits, the sixth selection submodule selects the fifth selection result b32_res[31:0] as the sixth selection result result[31:0]. If the length signal data_type_b16 indicates 16 bits, the sixth selection submodule selects b16_res[31:0] as the sixth selection result result[31:0]. Optionally, the logical formula of the sixth selection result is: result[31:0]=data_type_b16? b16_res[31:0]:b32_res[31:0].

[0237] according to Fig.11 and Fig.12 According to the principle shown, the first sharing module and the second sharing module mentioned above can be designed. The first sharing module is used to sum or take the maximum value of the two first data to obtain a first operation result, and the first data and the first operation result are both of the first length. The second sharing module is used to sum or take the maximum value of the two second data to obtain a second operation result, and the second data and the second operation result are both of the second length.

[0238] Since the vector operation circuit of the embodiment of the present application has multiple functions, the number of circuits can be reduced, so the chip area can be effectively reduced. After testing, the chip area can be reduced by about 20%, reducing the hardware overhead. In addition, since the vector operation circuit has multiple functions, the complexity of layout and wiring can be reduced. After testing, the number of wiring can be reduced by about 1 / 6.

[0239] The embodiment of the present application also provides a vector operation method, which is executed by the above-mentioned vector operation circuit. Fig.13 As shown, the method includes:

[0240] Step 1301, for the first shared module included in the i-th level shared circuit, a vector operation is performed on a pair of first data through the first shared module to obtain a first operation result, the lengths of the first data and the first operation result are both the first length, and when the first shared module is located in the j-th level shared circuit, the first data is the first operation result obtained by the first shared module connected to the first shared module included in the j-1-th level shared circuit.

[0241] It is understandable that the implementation method of step 1301 can be found in the description of the first sharing module, which will not be repeated here.

[0242] Step 1302, for the second shared module included in the N-th level shared circuit, a vector operation is performed on a pair of second data through the second shared module to obtain a second operation result, and the pair of second data is obtained by splitting the first operation result obtained by the first shared module included in the N-1-th level shared circuit, and the length of the second data and the second operation result are both the second length.

[0243] It is understandable that the implementation method of step 1302 can be found in the description of the second sharing module, which will not be repeated here.

[0244] Step 1303: The target selection module selects to output the second operation result or the first operation result obtained by the first sharing module included in the N-1th level sharing circuit.

[0245] It is understandable that the implementation method of step 1303 can be found in the description of the target selection module, which will not be repeated here.

[0246] In the above method, a first shared module is used to perform vector operations on a pair of first data of a first length to obtain a first operation result of the first length, and a second shared module is used to perform vector operations on a pair of second data of a second length to obtain a second operation result of the second length. The target selection module is used to select and output the second operation result or the first operation result, thereby realizing vector operations on data of the first length and vector operations on data of the second length in one circuit, increasing circuit functions, and reducing the number of circuits, so that when the vector operation circuit is laid out in the chip, the chip size can be reduced.

[0247] In an exemplary embodiment, a chip is provided, which includes the vector operation circuit mentioned above. The chip includes but is not limited to an AI processor, a CPU with a vector operation instruction set architecture, and any other processor with a vector computing engine.

[0248] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0249] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0250] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A vector operation circuit, characterized in that: The vector operation circuit includes N-level shared circuits and a target selection module, where N is a positive integer greater than 1; The i-th level shared circuit in the N-level shared circuits includes at least one first shared module, the j-th level shared circuit includes a first shared module and the j-th level shared circuit includes two first shared modules connected to each other, i is any one of 1 to N-1, and j is any one of 2 to N-1; The first sharing module is used to perform a vector operation on a pair of first data to obtain a first operation result, the lengths of the first data and the first operation result are both the first length, and when the first sharing module is located in the j-th level sharing circuit, the first data is the first operation result obtained by the first sharing module connected to the first sharing module and included in the j-1-th level sharing circuit; The N-th level shared circuit includes a second shared module, and the second shared module is connected to the first shared module included in the N-1-th level shared circuit; The second sharing module is used to perform a vector operation on a pair of second data to obtain a second operation result, wherein the pair of second data is obtained by splitting a first operation result obtained by the first sharing module included in the N-1th level sharing circuit, and the lengths of the second data and the second operation result are both the second length; The target selection module is connected to the second sharing module and the first sharing module included in the N-1th level sharing circuit respectively; the target selection module is used to select and output the second operation result or the first operation result obtained by the first sharing module included in the N-1th level sharing circuit.

2. The circuit according to claim 1, characterized in that The first data includes low-order data of the second length and high-order data of the second length, and the first sharing module includes a low-order processing submodule, a high-order processing submodule and a determination submodule; The low-bit processing submodule is used to perform a vector operation on a pair of low-bit data according to the operation type indicated by the operation signal to obtain a low-bit operation result; The high-order processing submodule is used to perform a vector operation on a pair of high-order data according to the operation type to obtain a first high-order operation result without overflow and a second high-order operation result with overflow; The determining submodule is used to determine the first operation result based on the low-bit operation result, the first high-bit operation result and the second high-bit operation result.

3. The circuit according to claim 2, characterized in that The low-bit processing submodule includes a low-bit inversion unit and a low-bit addition unit; The low-order inversion unit is used to invert one low-order data in the pair of low-order data to obtain a low-order inversion result when the operation type is to obtain the maximum value, or to use the one low-order data as the low-order inversion result when the operation type is to obtain the sum; The low-bit adding unit is used to add the other low-bit data in the pair of low-bit data and the low-bit inverted result according to the operation signal to obtain the low-bit operation result.

4. The circuit according to claim 2, characterized in that The high-bit processing submodule includes a high-bit inversion unit and a high-bit addition unit; The high-order inversion unit is used to invert one high-order data in the pair of high-order data to obtain a high-order inversion result when the operation type is to obtain the maximum value, or to use the one high-order data as the high-order inversion result when the operation type is to obtain the sum; The high-order addition unit is used to add the other high-order data in the pair of high-order data and the high-order inverted result to obtain the first high-order operation result, and to add the other high-order data, the high-order inverted result and the data used to indicate the overflow situation to obtain the second high-order operation result.

5. The circuit according to claim 2, characterized in that The determination submodule includes a summing unit, a maximum value unit and a first selection unit; The summing unit is used to determine a first summing result based on the low-bit operation result, the first high-bit operation result and the second high-bit operation result, wherein the first summing result represents a result obtained by summing a pair of first data; The maximum value unit is used to determine a first maximum value result based on the low-bit operation result, the first high-bit operation result and the second high-bit operation result, wherein the first maximum value result represents a result obtained by performing maximum value operation on the pair of first data; The first selection unit is used to select the first summation result as the first operation result when the operation type is summation, and to select the first maximum value result as the first operation result when the operation type is maximum value.

6. The circuit according to claim 5, characterized in that The first summation result includes a first processing result and a second processing result, and the summation unit includes a first determining subunit, a first processing subunit and a second processing subunit; The first determining subunit is used to determine a reference operation result from the first high-bit operation result and the second high-bit operation result according to the low-bit operation result and a length signal indicating the first length or the second length; The first processing subunit is used to determine, according to the reference operation result and a sign signal indicating whether there is a signed or unsigned condition, a first overflow signal indicating whether there is the overflow condition, and determine, according to the sign signal, the first overflow signal and the reference operation result, the first processing result being the reference operation result or being obtained by performing saturation processing on the reference operation result; The second processing sub-unit is used to determine the second overflow signal for indicating whether the overflow situation exists based on the reference operation result, the first overflow signal, the length signal and the low-bit operation result, and determine the second processing result based on the sign signal, the first overflow signal, the second overflow signal, the length signal and the low-bit operation result, the first processing result is the low-bit operation result or is obtained by saturating the low-bit operation result.

7. The circuit according to claim 6, characterized in that The first determination subunit includes a first logic gate component and a first selection component; The first logic gate component is used to determine a reference signal according to the low-bit operation result and the length signal, wherein the reference signal is used to indicate whether the first length is reached and the overflow condition exists; The first selection component is used to select the second high-bit operation result as the reference operation result when the reference signal indicates the first length and the overflow situation exists, and to select the first high-bit operation result as the reference operation result when the reference signal indicates at least one of the second length and the absence of the overflow situation.

8. The circuit according to claim 5, characterized in that The first maximum value result includes a third processing result and a fourth processing result, and the maximum value unit includes a second determining subunit, a third processing subunit and a fourth processing subunit; The second determining subunit is used to determine a first comparison signal and a second comparison signal based on the low-order operation result, the first high-order operation result and the second high-order operation result, the first comparison signal being used to indicate an absolute value comparison result of a pair of first data in the case of the first length, or, in the case of the second length, an absolute value comparison result of the pair of high-order data, and the second comparison signal being used to indicate an absolute value comparison result of a pair of first data in the case of the first length, or, in the case of the second length, an absolute value comparison result of the pair of low-order data; The third processing subunit is used to extract the maximum value of the pair of high-order data based on the first comparison signal to obtain the third processing result; The fourth processing sub-unit is used to extract the maximum value of the pair of low-order data based on the second comparison signal to obtain the fourth processing result.

9. The circuit according to claim 8, characterized in that The second determination subunit includes a second logic gate component and a second selection component; The second logic gate component is used to determine the first comparison signal based on the low-bit operation result, the first high-bit operation result, the second high-bit operation result and the length signal; The second selection component is used to determine the second comparison signal based on the length signal, the first comparison signal and the low-bit operation result.

10. The circuit according to claim 8, characterized in that The third processing subunit includes a first determining component and a third selecting component; The first determining component is used to determine a first selection signal according to the sign signal, the first comparison signal, a data signal indicating floating-point data or fixed-point data, and a type signal indicating taking a maximum value or taking a minimum value, wherein the first selection signal is used to indicate whether to select a specified high-order data in the pair of high-order data; The third selection component is used to select the third processing result from the pair of high-bit data according to the first selection signal.

11. The circuit according to claim 8, characterized in that The fourth processing subunit includes a second determining component and a fourth selecting component; The second determining component is used to determine a second selection signal according to the sign signal, the second comparison signal, the data signal and the type signal, wherein the second selection signal is used to indicate whether to select the specified lower-bit data in the pair of lower-bit data; The fourth selection component is used to select the fourth processing result from the pair of low-bit data according to the second selection signal.

12. The circuit according to any one of claims 1 to 11, characterized in that The second sharing module includes a summing submodule, a first processing submodule, a maximum value submodule and a selection submodule; The summing submodule is used to sum the pair of second data of the second length to obtain a second summing result when the operation signal indicates summing, or to sum one second data and another second data after being inverted to obtain a second summing result when the operation signal indicates taking a maximum value; The first processing submodule is used to determine a third overflow signal indicating whether the overflow situation exists based on the sign signal and the second summation result, and determine a fifth processing result according to the sign signal, the third overflow signal and the second summation result, wherein the fifth processing result is the second summation result or is obtained by performing saturation processing on the second summation result; The maximum value submodule is used to perform maximum value extraction on the pair of second data based on the type signal to obtain a second maximum value extraction result; The selection submodule is used to select the fifth processing result as the second operation result when the operation signal indicates summation, or to select the second maximum value result as the second operation result when the operation signal indicates maximum value.

13. The circuit according to claim 12, characterized in that The maximum value submodule includes a first processing unit, a second processing unit, a third processing unit and a third selection unit; The first processing unit is used to determine a first signal according to the pair of second data and the fifth processing result, wherein the first signal is used to indicate a comparison result of the pair of second data when the pair of second data is floating-point data; The second processing unit is used to determine a second signal according to the pair of second data and the fifth processing result, wherein the second signal is used to indicate a comparison result of the pair of second data when the pair of second data is signed fixed-point data; The third processing unit is used to determine a third selection signal according to the first signal, the second signal and the fifth processing result, wherein the third selection signal is used to indicate whether to select a specified second data in the pair of second data; The third selection unit is used to select the second maximum value result from the pair of second data according to the third selection signal.

14. A vector operation method, characterized in that: The method is performed by the vector operation circuit according to any one of claims 1 to 13, and the method comprises: For a first shared module included in an i-th level shared circuit, a first operation result is obtained by performing a vector operation on a pair of first data through the first shared module, the lengths of the first data and the first operation result are both the first length, and when the first shared module is located in a j-th level shared circuit, the first data is a first operation result obtained by a first shared module connected to the first shared module and included in a j-1-th level shared circuit; For a second shared module included in the N-th level shared circuit, a vector operation is performed on a pair of second data by the second shared module to obtain a second operation result, where the pair of second data is obtained by splitting a first operation result obtained by the first shared module included in the N-1-th level shared circuit, and the lengths of the second data and the second operation result are both the second length; The target selection module selects and outputs the second operation result or the first operation result obtained by the first sharing module included in the N-1th level sharing circuit.

15. A chip, characterized in that: The chip comprises the vector operation circuit as described in any one of claims 1 to 13.

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