Server startup method, device, computer equipment, and storage medium

Abstract

The present invention relates to the field of server technology, and discloses a server startup method, apparatus, computer equipment, and storage medium. The method is applied to a target logic device and includes: after the server is powered on, verifying first firmware in a first memory and second firmware in a second memory; if the first firmware passes the verification, sending a first selection signal to a first multiplexer so that the first multiplexer cuts off a first link between the first memory and the target logic device and connects a second link between the first memory and a baseboard management controller, and the baseboard management controller starts based on the first firmware; if the second firmware passes the verification, sending a second selection signal to a second multiplexer so that the second multiplexer cuts off a third link between the second memory and the target logic device and connects a fourth link between the second memory and a central processing unit, and the central processing unit starts an input and output system based on the second firmware. The present invention improves the security of the server.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a server startup method, device, computer equipment and storage medium. Background Art

[0002] With the booming big data and cloud computing industries, servers, as core components of these industries, face increasingly stringent security requirements. The security of the firmware for the Baseboard Management Controller (BMC) and Basic Input / Output System (BIOS) directly impacts server security. Therefore, ensuring the security of these firmware is crucial.

[0003] In related technologies, before a server is started, the BMC firmware and BIOS firmware are verified by a Trusted Platform Module (TPM) or a Trusted Cryptography Module (TCM). If the firmware passes the verification, the BMC and the Central Processing Unit (CPU) load the firmware to start the server.

[0004] However, because the TPM or TCM is connected in parallel between the chip containing the BMC firmware and the BMC, and between the chip containing the BIOS firmware and the CPU, if the BMC firmware or BIOS firmware is tampered with or a virus is implanted, the TPM or TCM verification can be bypassed to directly control the BMC or CPU to operate the server, resulting in low server security. Summary of the Invention

[0005] In view of this, the present invention provides a server startup method, apparatus, computer equipment and storage medium to solve the problem in the related art that when the BMC firmware or BIOS firmware is tampered with or a virus is implanted, the BMC or CPU can be directly controlled to operate the server by bypassing the TPM or TCM verification, resulting in low server security.

[0006] In a first aspect, the present invention provides a server startup method, applied to a target logic device, the method comprising:

[0007] After the server is powered on, verifying the first firmware in the first memory and the second firmware in the second memory, wherein the first firmware is firmware of the baseboard management controller and the second firmware is firmware of the input / output system;

[0008] If the first firmware passes verification, sending a first strobe signal to a first multiplexer, so that the first multiplexer cuts off a first link between the first memory and the target logic device based on the first strobe signal and connects a second link between the first memory and a baseboard management controller, and the baseboard management controller obtains the first firmware based on the second link and starts based on the first firmware;

[0009] If the second firmware passes the verification, a second selection signal is sent to the second multiplexer, so that the second multiplexer cuts off the third link between the second memory and the target logic device based on the second selection signal, and connects the fourth link between the second memory and the central processing unit. The central processing unit obtains the second firmware based on the fourth link and starts the input and output system based on the second firmware.

[0010] The server startup method provided in this embodiment verifies the firmware of the baseboard management controller and the firmware of the input and output system through the target logic. During the verification process, there is no connection link between the first memory storing the first firmware and the baseboard management controller, and there is no connection link between the second memory storing the second firmware and the central processing unit. Only when the first firmware passes the verification will the link between the first memory and the baseboard management controller be enabled; only when the second firmware passes the verification will the link between the second memory and the central processing unit be enabled. This ensures that the firmware cannot bypass the verification to directly control the baseboard management controller or the central processing unit to operate the server, thereby improving the security of the server.

[0011] In an optional implementation, verifying the first firmware in the first memory includes:

[0012] Obtain a first verification code;

[0013] Parsing the first firmware to obtain a second verification code;

[0014] Comparing the first verification code with the second verification code to obtain a first comparison result;

[0015] If the first comparison result is that the first verification code is consistent with the second verification code, it is determined that the first firmware has passed verification.

[0016] The server startup method provided in this embodiment obtains a first verification code through a target logic device, and compares the first verification code with a second verification code obtained by parsing the first firmware to determine whether the first firmware has passed the verification, thereby avoiding the insecurity of using an external card such as TPM or TCM to verify the firmware.

[0017] In an optional implementation, verifying the second firmware in the second memory includes:

[0018] Obtain a first verification code;

[0019] parsing the second firmware to obtain a third verification code;

[0020] Comparing the first verification code with the third verification code to obtain a second comparison result;

[0021] If the second comparison result is that the first verification code is consistent with the third verification code, it is determined that the second firmware passes verification.

[0022] The server startup method provided in this embodiment obtains a first verification code through a target logic device, and compares the first verification code with a third verification code obtained by parsing the second firmware to determine whether the second firmware has passed the verification, thereby avoiding the insecurity of using an external card such as TPM or TCM to verify the firmware.

[0023] In an optional embodiment, the method further includes:

[0024] If the first firmware fails verification, ending the step of verifying the second firmware in the second memory;

[0025] If the second firmware fails the verification, the step of verifying the first firmware in the first memory ends.

[0026] The server startup method provided in this embodiment immediately stops verifying the firmware in the second memory when the first firmware fails to be verified, and vice versa. This can avoid unnecessary verification operations and save time and system resources.

[0027] In an optional embodiment, the method further includes:

[0028] Based on the verification status of the first firmware, sending a corresponding lighting signal to the first light-emitting diode to indicate the verification status of the first firmware;

[0029] Based on the verification status of the second firmware, a corresponding lighting signal is sent to the second light emitting diode to indicate the verification status of the second firmware.

[0030] The server startup method provided in this embodiment allows users or maintenance personnel to intuitively understand the verification progress and results of each firmware through the lighting status of the first light-emitting diode and the second light-emitting diode, without having to check complex system logs or display information, thereby improving user experience and maintenance efficiency.

[0031] In an optional embodiment, the sending a corresponding lighting signal to the first light-emitting diode based on the verification status of the first firmware includes:

[0032] When the verification state of the first firmware is that the first firmware is being verified, controlling the first lighting signal sent to the first light-emitting diode to flip the high and low levels at a first frequency, so that the state of the first light-emitting diode is a green flashing state, indicating that the first firmware is being verified;

[0033] When the verification status of the first firmware is verified to be passed, controlling the first lighting signal sent to the first light-emitting diode to be low level, so that the state of the first light-emitting diode is a green and steady state, indicating that the first firmware verification has passed;

[0034] When the verification status of the first firmware is verification failure, controlling the second lighting signal sent to the first light-emitting diode to be low level, so that the state of the first light-emitting diode is a red and steady light state, indicating that the first firmware verification has failed;

[0035] The step of sending a corresponding lighting signal to the second light emitting diode based on the verification status of the second firmware includes:

[0036] When the verification state of the second firmware is that the second firmware is being verified, controlling the third lighting signal sent to the second light-emitting diode to flip the high and low levels at the first frequency, so that the state of the second light-emitting diode is a green flashing state, indicating that the second firmware is being verified;

[0037] When the verification status of the second firmware is passed, the third lighting signal sent to the second light-emitting diode is controlled to be low level, so that the state of the second light-emitting diode is a green and steady state, indicating that the second firmware has passed the verification;

[0038] When the verification status of the second firmware is verification failure, the fourth lighting signal sent to the second light-emitting diode is controlled to be low level, so that the state of the second light-emitting diode is a long red state, indicating that the second firmware verification has failed.

[0039] The server startup method provided in this embodiment provides clear, easy-to-understand visual feedback to users and maintenance personnel through LEDs of different colors (green, red) and states (flashing, solid). This allows users and maintenance personnel to quickly identify whether firmware verification is in progress, passed, or failed, without having to delve into system logs or use complex diagnostic tools. This not only improves the efficiency and convenience of system maintenance, but also enhances the user's interactive experience.

[0040] In an optional implementation, obtaining the first verification code includes:

[0041] Based on a plurality of lines correspondingly connected to a plurality of check code acquisition pins in the target logic device, obtaining a level corresponding to each line;

[0042] A first check code is determined based on the level corresponding to each line.

[0043] The server startup method provided in this embodiment directly reads the check code through a physical line, reducing potential errors in the data transmission process. Compared with the software reading method, it is more stable and reliable, and enhances the overall security and data integrity of the system.

[0044] In a second aspect, the present invention provides a server startup device, the device comprising:

[0045] A verification module, configured to verify, after the server is powered on, a first firmware in a first memory and a second firmware in a second memory, wherein the first firmware is firmware of a baseboard management controller and the second firmware is firmware of an input / output system;

[0046] a first sending module, configured to send a first selection signal to a first multiplexer if the first firmware passes verification, so that the first multiplexer disconnects a first link between the first memory and the target logic device based on the first selection signal and connects a second link between the first memory and a baseboard management controller, so that the baseboard management controller obtains the first firmware based on the second link and starts based on the first firmware;

[0047] The second sending module is used to send a second selection signal to the second multiplexer when the second firmware passes the verification, so that the second multiplexer cuts off the third link between the second memory and the target logic device based on the second selection signal, and connects the fourth link between the second memory and the central processing unit. The central processing unit obtains the second firmware based on the fourth link and starts the input and output system based on the second firmware.

[0048] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the server startup method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0049] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the server startup method of the first aspect or any corresponding embodiment thereof.

[0050] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, which are used to enable a computer to execute the server startup method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in related technologies, the following briefly introduces the drawings required for use in the specific embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 It is a structural block diagram of firmware verification in the related art;

[0053] Figure 2 is a flow chart of a server startup method according to an embodiment of the present invention;

[0054] Figure 3 is a structural block diagram of firmware verification according to an embodiment of the present invention;

[0055] Figure 4 is a schematic diagram of another server startup process according to an embodiment of the present invention;

[0056] Figure 5 is a schematic diagram of a verification status indication circuit according to an embodiment of the present invention;

[0057] Figure 6 is a schematic structural diagram of a check code generating circuit according to an embodiment of the present invention;

[0058] Figure 7 is a structural block diagram of a server startup device according to an embodiment of the present invention;

[0059] Figure 8 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0060] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0061] Servers are core components of industries like big data and cloud computing. With the continuous development of these industries, server security requirements are becoming increasingly stringent. The BMC (Baseboard Management Console) (BMC) is responsible for server system management, fault monitoring and alarming, network service provision, fan control, and other functions. The BIOS (Basic Input and Output) program is a set of programs stored on the server's motherboard flash memory. It stores the server's most important basic input and output programs, post-boot self-test programs, and system startup programs. Its primary function is to provide the lowest-level, most direct hardware configuration and control for the server. Given the critical role of the BMC and BIOS in server systems, the security of their firmware directly impacts the server's security level. Tampering with the BMC or BIOS firmware poses a serious threat to server security. Therefore, ensuring the security of the BMC and BIOS firmware is crucial.

[0062] The BMC and BIOS firmware are stored in the flash chip on the server motherboard. When the server is powered on, the BMC and BIOS firmware are loaded from the flash chip to start the boot process.

[0063] In related technologies, to ensure the security of BMC and BIOS firmware, the BMC firmware and BIOS firmware are verified through a TPM or TCM before the server is started. Figure 1 This is a structural diagram of firmware verification in related technologies. Figure 1 As shown in the figure, the TPM / TCM is connected in parallel to the link between the BMC Flash chip and the BMC, and in parallel to the link between the BIOS Flash chip and the CPU. After the server is powered on, the TPM / TCM verifies the BMC firmware stored in the BMC Flash chip and the BIOS firmware stored in the BIOS Flash chip.

[0064] It should be noted that the BMC Flash chip is used to store BMC firmware, and the BIOS Flash chip is used to store BIOS firmware. The BMC Flash chip and BMC are connected via the Serial Peripheral Interface (SPI). The BIOS Flash chip and CPU are also connected via SPI.

[0065] If the firmware verification passes, the BMC and CPU load the corresponding firmware to start the server. However, because the TPM or TCM is connected in parallel between the BMC's firmware chip (the BMC Flash chip) and the BMC, and between the BIOS's firmware chip (the BIOS Flash chip) and the CPU, the path between the BMC Flash chip and the BMC and the path between the BIOS Flash chip and the CPU always exist. As a result, if the BMC firmware or BIOS firmware is tampered with or a virus is implanted, it is possible to bypass the TPM or TCM verification and directly control the BMC or CPU to operate the server, thereby threatening the server's security and reducing the server's security.

[0066] That is, the related technology cannot isolate the path between the Flash chip and the BMC and CPU before completing the firmware verification, and thus cannot prevent the threat to server security caused by tampering with the BMC and BIOS firmware.

[0067] Furthermore, TPMs and TCMs are external modules for servers, and their firmware can be tampered with or infected with viruses. Inadequate management and control of TPM / TCM firmware can increase server security risks. Furthermore, using an external TPM or TCM to verify firmware increases server costs.

[0068] An embodiment of the present invention provides a server startup method that verifies the firmware of a baseboard management controller and the firmware of an input / output system through a target logic device. During the verification process, no connection link is established between a first memory storing the first firmware and the baseboard management controller, and no connection link is established between a second memory storing the second firmware and a central processing unit. Only when the first firmware passes the verification is the link between the first memory and the baseboard management controller enabled; only when the second firmware passes the verification is the link between the second memory and the central processing unit enabled, thereby ensuring that the firmware cannot bypass the verification and directly control the baseboard management controller or the central processing unit to operate the server, thereby improving the security of the server.

[0069] According to an embodiment of the present invention, an embodiment of a server startup method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0070] In this embodiment, a server startup method is provided, which can be used in a mobile terminal, such as a target logic in a server, Figure 2 Flowchart of a server startup method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0071] Step S201 : After the server is powered on, first firmware in a first memory and second firmware in a second memory are verified, wherein the first firmware is firmware of a baseboard management controller and the second firmware is firmware of an input / output system.

[0072] The target logic device is a complex programmable logic device (CPLD), which is used for timing control, logic control, etc. in server systems. The input and output system is the BIOS.

[0073] Figure 3 FIG. 1 is a block diagram of a structure for verifying firmware according to an embodiment of the present invention. Figure 3 As shown, the BMC Flash chip is used to store BMC firmware, and the BIOS Flash chip is used to store BIOS firmware. A first multiplexer (MUX chip 1) is used to switch the SPI bus between the BMC Flash chip, CPLD, and BMC. The BMC Flash chip's SPI signal is connected to terminal A of MUX chip 1, the CPLD's SPI signal is connected to terminal B1 of MUX chip 1, and the BMC's SPI signal is connected to terminal B2 of MUX chip 1.

[0074] When the server is powered on, terminals A and B1 of MUX chip 1 are connected by default, allowing the CPLD to verify the BMC firmware in the BMC Flash chip. Terminals A and B2 of MUX chip 1 are disconnected, preventing the BMC firmware from controlling the BMC until verification is complete.

[0075] It is understandable that the first memory is a BMC Flash chip.

[0076] like Figure 3 As shown, the second multiplexer (MUX chip 2) is used to switch the SPI bus between the BIOS Flash chip, CPLD, and CPU. The SPI signal of the BIOS Flash chip is connected to the A terminal of MUX chip 2, the SPI signal of the CPLD is connected to the B1 terminal of MUX chip 2, and the SPI signal of the CPU is connected to the B2 terminal of MUX chip 2.

[0077] When the server is powered on, terminals A and B1 of MUX chip 2 are connected by default, allowing the CPLD to verify the BIOS firmware in the BIOS Flash chip. Terminals A and B2 of MUX chip 2 are disconnected, preventing the BIOS firmware from controlling the CPU until verification is complete.

[0078] It is understandable that the second memory is a BIOS Flash chip.

[0079] The target logic device is used to verify the first firmware and the second firmware, and is also used to control the path switching of the first multiplexer after the first firmware passes the verification, and to control the path switching of the second multiplexer after the second firmware passes the verification.

[0080] Step S202, when the first firmware is verified to be passed, a first selection signal is sent to the first multiplexer, so that the first multiplexer cuts off the first link between the first memory and the target logic device based on the first selection signal, and connects the second link between the first memory and the baseboard management controller. The baseboard management controller obtains the first firmware based on the second link and starts based on the first firmware.

[0081] The fact that the first firmware passes the verification indicates that the first firmware is safe, and the BMC can be started using the first firmware.

[0082] When the first firmware passes the verification, the CPLD sends a first selection signal (selection signal 1) to the first multiplexer, and cuts off the link between the A end and the B1 end of the MUX chip 1. That is, the first multiplexer cuts off the first link between the first memory and the target logic device based on the first selection signal, and connects the link between the A end and the B2 end of the MUX chip 1. That is, the second link between the first memory and the baseboard management controller is connected, and a path between the BMC Flash chip and the BMC is established, so that the BMC obtains the first firmware based on the second link and starts based on the first firmware.

[0083] In step S203, when the second firmware passes the verification, a second selection signal is sent to the second multiplexer, so that the second multiplexer cuts off the third link between the second memory and the target logic device based on the second selection signal, and connects the fourth link between the second memory and the central processing unit. The central processing unit obtains the second firmware based on the fourth link and starts the input and output system based on the second firmware.

[0084] The server startup includes the startup of the BMC and the startup of the input and output system.

[0085] The fact that the second firmware passes the verification indicates that the second firmware is safe, and the CPU can start the BIOS through the second firmware.

[0086] When the second firmware is verified to be passed, the CPLD sends a second selection signal (selection signal 2) to the second multiplexer, and cuts off the link between the A end and the B1 end of the MUX chip 2. That is, the second multiplexer cuts off the third link between the second memory and the target logic device based on the second selection signal, and connects the link between the A end and the B2 end of the MUX chip 2, that is, connects the fourth link between the second memory and the central processing unit, and establishes a path between the BIOS Flash chip and the CPU, so that the CPU obtains the second firmware based on the fourth link and performs BIOS startup based on the second firmware.

[0087] It should be noted that after the BMC and BIOS are started normally, the server can enter the normal startup state.

[0088] The server startup method provided in this embodiment verifies the firmware of the baseboard management controller and the firmware of the input and output system through the target logic. During the verification process, there is no connection link between the first memory storing the first firmware and the baseboard management controller, and there is no connection link between the second memory storing the second firmware and the central processing unit. That is, before the verification passes, the SPI path between the first memory storing the first firmware and the baseboard management controller is cut off, and the SPI path between the second memory storing the second firmware and the central processing unit is cut off, and the unverified BMC firmware and BIOS firmware are isolated to avoid posing a threat to the security of the server. Only when the first firmware verification passes, the link between the first memory and the baseboard management controller will be enabled; only when the second firmware verification passes, the link between the second memory and the central processing unit will be enabled. It ensures that the firmware cannot bypass the verification to directly control the baseboard management controller or the central processing unit to operate the server, thereby improving the security of the server.

[0089] Furthermore, this embodiment uses the inherent CPLD chip on the server motherboard to complete the verification of the BMC firmware and the BIOS firmware, saving the cost of using a TPM / TCM plug-in card and further ensuring the security of the server.

[0090] In this embodiment, a server startup method is provided, which can be used in a mobile terminal, such as a target logic in a server, Figure 4 Flowchart of a server startup method according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0091] Step S401 : After the server is powered on, first firmware in a first memory and second firmware in a second memory are verified, wherein the first firmware is firmware of a baseboard management controller and the second firmware is firmware of an input / output system.

[0092] Specifically, the above step S401 includes:

[0093] Step S4011, obtaining a first verification code.

[0094] Among them, such as Figure 3 As shown, the CPLD obtains the first check code through the check code generation circuit. The check code generation circuit is used to generate the first check code.

[0095] Step S4012: parse the first firmware to obtain a second verification code.

[0096] After the server is powered on, the target logic device parses the first firmware in the first memory to obtain the second verification code.

[0097] Parsing the first firmware to obtain the second verification code specifically includes:

[0098] Based on the preset position information of the second verification code, the second verification code is obtained from the first firmware.

[0099] It should be noted that the preset position information of the second verification code is the position information of the second verification code in the first firmware, which is preset by a technician.

[0100] Step S4013: Compare the first verification code with the second verification code to obtain a first comparison result.

[0101] After obtaining the first verification code and the second verification code, the first verification code is compared with the second verification code to obtain a first comparison result.

[0102] Step S4014 , when the first comparison result is that the first verification code is consistent with the second verification code, it is determined that the first firmware has passed verification.

[0103] It is understandable that if the first verification code is inconsistent with the second verification code, it is determined that the first firmware has failed verification and an abnormality exists in the first firmware.

[0104] Step S402: If the first firmware passes the verification, a first selection signal is sent to the first multiplexer, so that the first multiplexer cuts off the first link between the first memory and the target logic device based on the first selection signal and connects the second link between the first memory and the baseboard management controller. The baseboard management controller obtains the first firmware based on the second link and starts based on the first firmware. For details, please refer to Figure 2 Step S202 of the illustrated embodiment will not be described in detail here.

[0105] In step S403, if the second firmware passes the verification, a second selection signal is sent to the second multiplexer, so that the second multiplexer cuts off the third link between the second memory and the target logic device based on the second selection signal and connects the fourth link between the second memory and the central processing unit. The central processing unit obtains the second firmware based on the fourth link and starts the input and output system based on the second firmware. For details, please refer to Figure 2 Step S203 of the illustrated embodiment will not be described in detail here.

[0106] The server startup method provided in this embodiment obtains a first verification code through a target logic device, and compares the first verification code with a second verification code obtained by parsing the first firmware to determine whether the first firmware has passed the verification, thereby avoiding the insecurity of using an external card such as TPM or TCM to verify the firmware.

[0107] In some optional implementations, the above step S201 further includes:

[0108] Step a1, obtain the first verification code. Figure 3 As shown, the CPLD obtains the first check code through the check code generation circuit.

[0109] Step a2: parse the second firmware to obtain a third verification code.

[0110] After the server is powered on, the target logic device parses the second firmware in the second memory to obtain a third check code.

[0111] Parsing the second firmware to obtain the third verification code specifically includes:

[0112] Based on the preset position information of the third verification code, the third verification code is obtained from the second firmware.

[0113] It should be noted that the preset position information of the third verification code is the position information of the third verification code in the second firmware, which is preset by a technician.

[0114] Step a3: Compare the first check code with the third check code to obtain a second comparison result.

[0115] After obtaining the first verification code and the third verification code, the first verification code is compared with the third verification code to obtain a second comparison result.

[0116] Step a4: If the second comparison result shows that the first verification code is consistent with the third verification code, it is determined that the second firmware has passed the verification.

[0117] It is understandable that if the first verification code is inconsistent with the third verification code, it is determined that the second firmware has failed verification and an abnormality exists in the second firmware.

[0118] The server startup method provided in this embodiment obtains a first verification code through a target logic device, and compares the first verification code with a third verification code obtained by parsing the second firmware to determine whether the second firmware has passed the verification, thereby avoiding the insecurity of using an external card such as TPM or TCM to verify the firmware.

[0119] In some optional implementations, the server startup method further includes:

[0120] Step b1, when the first firmware fails to pass the verification, end the step of verifying the second firmware in the second memory.

[0121] It is understandable that the verification of the first firmware and the verification of the second firmware can be performed simultaneously or sequentially.

[0122] If the first firmware fails verification, it indicates an anomaly in the first firmware and the server cannot boot normally. If the second firmware verification step is currently in progress, the second firmware verification step is terminated. If the second firmware verification step has not yet been completed, the second firmware verification step does not need to be performed.

[0123] Step b2: If the second firmware fails the verification, end the step of verifying the first firmware in the first memory.

[0124] If the second firmware fails verification, it indicates an anomaly in the second firmware and the server cannot boot normally. If the first firmware verification step is currently in progress, the first firmware verification step is terminated. If the first firmware verification step has not yet been completed, the first firmware verification step does not need to be performed.

[0125] The server startup method provided in this embodiment immediately stops verifying the firmware in the second memory when the first firmware fails to be verified, and vice versa. This can avoid unnecessary verification operations and save time and system resources.

[0126] In some optional implementations, the server startup method further includes:

[0127] Step c1: Based on the verification status of the first firmware, a corresponding lighting signal is sent to the first light-emitting diode to indicate the verification status of the first firmware.

[0128] The server includes a verification status indication circuit, which is used to indicate the verification status of the firmware. Figure 5 FIG. 1 is a schematic diagram of a verification status indication circuit according to an embodiment of the present invention. Figure 5As shown, the verification status indication circuit includes a target logic and two red and green dual-color light emitting diodes LED1 and LED2. The following description will be made with the first light emitting diode being LED1 and the second light emitting diode being LED2.

[0129] The status of LED1 is controlled by the CPLD. The first on-signal (on-signal G1) sent from the CPLD's M pin controls the green state of LED1. The second on-signal (on-signal R1) sent from the CPLD's N pin controls the red state of LED1.

[0130] It should be noted that the state of the first light emitting diode is used to indicate the verification state of the first firmware. The CPLD sends a corresponding lighting signal to the first light emitting diode according to the verification state of the first firmware to indicate different verification states of the first firmware.

[0131] Step c2: Based on the verification status of the second firmware, a corresponding lighting signal is sent to the second light-emitting diode to indicate the verification status of the second firmware.

[0132] The CPLD controls the state of LED2. The third on-signal (on-signal G2) from the CPLD's P pin controls the green state of LED2. The fourth on-signal (on-signal R2) from the CPLD's Q pin controls the red state of LED2.

[0133] It should be noted that the state of the second LED is used to indicate the verification state of the second firmware. The CPLD sends a corresponding lighting signal to the second LED according to the verification state of the second firmware to indicate different verification states of the second firmware.

[0134] The server startup method provided in this embodiment allows users or maintenance personnel to intuitively understand the verification progress and results of each firmware through the lighting status of the first light-emitting diode and the second light-emitting diode, without having to check complex system logs or display information, thereby improving user experience and maintenance efficiency.

[0135] In some optional embodiments, step c1 includes:

[0136] In step c11, when the verification status of the first firmware is that the first firmware is being verified, the first lighting signal sent to the first light-emitting diode is controlled to flip the high and low levels at a first frequency, so that the state of the first light-emitting diode is a green flashing state, indicating that the first firmware is being verified.

[0137] LED1 indicates the BMC firmware verification status, i.e., the verification status of the first firmware. When LED1 is off, verification of the first firmware has not yet begun. When LED1 flashes green, it indicates that the CPLD is verifying the first firmware. When LED1 is solid green, verification of the first firmware has passed. When LED1 is solid red, verification of the first firmware has failed.

[0138] When the first lighting signal is high, LED 1 is in the green off state. When the first lighting signal is low, LED 1 is in the green steady on state. When the first lighting signal is high and low at a first frequency, i.e., when the first lighting signal is high and low at a first frequency, LED 1 is in the green flashing state. The first frequency is set by a technician and, for example, is 1 Hz. The green steady on state is the green light that is constantly on, and the green flashing state is the green light that is flashing.

[0139] In step c12, when the verification status of the first firmware is passed, the first lighting signal sent to the first light-emitting diode is controlled to be low level, so that the state of the first light-emitting diode is green and long-on state, indicating that the first firmware verification has passed.

[0140] The first lighting signal is at a low level, and the state of LED1 is a steady green state, indicating that the first firmware verification has passed.

[0141] In step c13, when the verification status of the first firmware is verification failure, the second lighting signal sent to the first light-emitting diode is controlled to be low level, so that the state of the first light-emitting diode is a long red state, indicating that the first firmware verification has failed.

[0142] When the second lighting signal is at a high level, LED 1 is in the red off state. When the second lighting signal is at a low level, LED 1 is in the red steady on state. When the second lighting signal is high and low and toggles at a first frequency, LED 1 is in the red flashing state. The red steady on state is when the red light is constantly on, and the red flashing state is when the red light is flashing.

[0143] The second lighting signal is at a low level, and the state of LED1 is a steady red state, indicating that the first firmware verification has failed.

[0144] Step c2 includes:

[0145] Step c21, when the verification status of the second firmware is that the second firmware is being verified, control the third lighting signal sent to the second light-emitting diode to flip the high and low levels at the first frequency, so that the state of the second light-emitting diode is a green flashing state, indicating that the second firmware is being verified.

[0146] LED2 indicates the verification status of the BIOS firmware, that is, the verification status of the second firmware. When LED2 is off, verification of the second firmware has not yet begun. When LED2 flashes green, it indicates that the CPLD is verifying the second firmware. When LED2 is solid green, verification of the second firmware has passed. When LED2 is solid red, verification of the second firmware has failed.

[0147] When the third lighting signal is at a high level, LED 2 is in a green off state. When the third lighting signal is at a low level, LED 2 is in a green steady on state. When the third lighting signal is at a high level and toggles between high and low levels at a first frequency, LED 2 is in a green flashing state.

[0148] Step c22, when the verification status of the second firmware is verification passed, control the third lighting signal sent to the second light-emitting diode to be low level, so that the state of the second light-emitting diode is green and long-on state, indicating that the second firmware verification has passed.

[0149] The third lighting signal is at a low level, and the state of LED2 is a steady green state, indicating that the second firmware verification has passed.

[0150] Step c23, when the verification status of the second firmware is verification failure, control the fourth lighting signal sent to the second light-emitting diode to be low level, so that the state of the second light-emitting diode is red and long-on state, indicating that the second firmware verification has failed.

[0151] When the fourth lighting signal is at a high level, LED 2 is in a red off state. When the fourth lighting signal is at a low level, LED 2 is in a red steady on state. When the fourth lighting signal is at a high level and toggles between high and low levels at a first frequency, LED 2 is in a red flashing state.

[0152] The fourth lighting signal is at a low level, and the state of LED2 is a steady red state, indicating that the second firmware verification has failed.

[0153] The server startup method provided in this embodiment provides clear, easy-to-understand visual feedback to users and maintenance personnel through LEDs of different colors (green, red) and states (flashing, solid). This allows users and maintenance personnel to quickly identify whether firmware verification is in progress, passed, or failed, without having to delve into system logs or use complex diagnostic tools. This not only improves the efficiency and convenience of system maintenance, but also enhances the user's interactive experience.

[0154] This embodiment uses a simple LED circuit to indicate the verification process and results, which facilitates rapid problem location during debugging.

[0155] In some optional implementations, the above step S4011 or step a1 includes:

[0156] Step d1, based on multiple lines connected to multiple check code acquisition pins in the target logic device, obtain the level corresponding to each line.

[0157] Figure 6 FIG. 1 is a schematic diagram of a check code generating circuit according to an embodiment of the present invention. Figure 6 As shown, the check code generation circuit includes 8 groups of level setting circuits composed of pull-up and pull-down resistors.

[0158] The level setting circuit composed of the first pull-up resistor R1 and the second pull-down resistor R2 is connected to the A pin among the multiple check code acquisition pins of the CPLD to set the level of the A pin.

[0159] When the first pull-up resistor R1 is connected and the second pull-down resistor R2 is not connected, the CPLD's A pin is set to a high level because the first pull-up resistor R1 is connected to the power supply. It should be noted that resistor connection generally refers to the process of attaching a resistor component to a printed circuit board (PCB) or other circuit carrier during the electronics assembly or production process.

[0160] When the first pull-up resistor R1 is not connected and the second pull-down resistor R2 is connected, the A pin of the CPLD is set to a low level because the second pull-down resistor R2 is connected to the ground. The CPLD records a high level as 1 and a low level as 0.

[0161] The level setting circuit composed of the third pull-up resistor R3 and the fourth pull-down resistor R4 is connected to the B pin among the multiple check code acquisition pins of the CPLD, and is used to set the level of the B pin.

[0162] When the third pull-up resistor R3 is on and the fourth pull-down resistor R4 is not on, the B pin of the CPLD is set to a high level because the third pull-up resistor R3 is connected to the power supply (Power).

[0163] When the third pull-up resistor R3 is not pulled up and the fourth pull-down resistor R4 is pulled up, the B pin of the CPLD is set to a low level because the fourth pull-down resistor R4 is connected to the ground.

[0164] The level setting circuit composed of the fifth pull-up resistor R5 and the sixth pull-down resistor R6 is connected to the C pin among the multiple check code acquisition pins of the CPLD, and is used to set the level of the C pin.

[0165] When the fifth pull-up resistor R5 is turned on and the sixth pull-down resistor R6 is turned off, the C pin of the CPLD is set to a high level because the fifth pull-up resistor R5 is connected to the power supply (Power).

[0166] When the fifth pull-up resistor R5 is not on and the sixth pull-down resistor R6 is on, the C pin of the CPLD is set to a low level because the sixth pull-down resistor R6 is connected to the ground.

[0167] The level setting circuit composed of the seventh pull-up resistor R7 and the eighth pull-down resistor R8 is connected to the D pin among the multiple check code acquisition pins of the CPLD, and is used to set the level of the D pin.

[0168] When the seventh pull-up resistor R7 is on and the eighth pull-down resistor R8 is not on, the D pin of the CPLD is set to a high level because the seventh pull-up resistor R7 is connected to the power supply (Power).

[0169] When the seventh pull-up resistor R7 is not on and the eighth pull-down resistor R8 is on, the D pin of the CPLD is set to a low level because the eighth pull-down resistor R8 is connected to the ground.

[0170] The level setting circuit composed of the ninth pull-up resistor R9 and the tenth pull-down resistor R10 is connected to the E pin among the multiple check code acquisition pins of the CPLD, and is used to set the level of the E pin.

[0171] When the ninth pull-up resistor R9 is on and the tenth pull-down resistor R10 is not on, since the ninth pull-up resistor R9 is connected to the power supply (Power), the E pin of the CPLD is set to a high level.

[0172] When the ninth pull-up resistor R9 is not on and the tenth pull-down resistor R10 is on, the E pin of the CPLD is set to a low level because the tenth pull-down resistor R10 is connected to the ground.

[0173] The level setting circuit composed of the eleventh pull-up resistor R11 and the twelfth pull-down resistor R12 is connected to the F pin among the multiple check code acquisition pins of the CPLD, and is used to set the level of the F pin.

[0174] When the eleventh pull-up resistor R11 is turned on and the twelfth pull-down resistor R12 is not turned on, the F pin of the CPLD is set to a high level because the eleventh pull-up resistor R11 is connected to the power supply (Power).

[0175] When the eleventh pull-up resistor R11 is not on and the twelfth pull-down resistor R12 is on, the F pin of the CPLD is set to a low level because the twelfth pull-down resistor R12 is connected to the ground.

[0176] The level setting circuit composed of the thirteenth pull-up resistor R13 and the fourteenth pull-down resistor R14 is connected to the G pin among the multiple check code acquisition pins of the CPLD, and is used to set the level of the G pin.

[0177] When the thirteenth pull-up resistor R13 is turned on and the fourteenth pull-down resistor R14 is not turned on, the G pin of the CPLD is set to a high level because the thirteenth pull-up resistor R13 is connected to the power supply (Power).

[0178] When the thirteenth pull-up resistor R13 is not on and the fourteenth pull-down resistor R14 is on, the G pin of the CPLD is set to a low level because the fourteenth pull-down resistor R14 is connected to the ground.

[0179] The level setting circuit composed of the fifteenth pull-up resistor R15 and the sixteenth pull-down resistor R16 is connected to the H pin among the multiple check code acquisition pins of the CPLD, and is used to set the level of the H pin.

[0180] When the fifteenth pull-up resistor R15 is on and the sixteenth pull-down resistor R16 is not on, since the fifteenth pull-up resistor R15 is connected to the power supply (Power), the H pin of the CPLD is set to a high level.

[0181] When the fifteenth pull-up resistor R15 is not on and the sixteenth pull-down resistor R16 is on, since the sixteenth pull-down resistor R16 is connected to the ground, the H pin of the CPLD is set to a low level.

[0182] It should be noted that the technicians decide whether to power on each resistor, and then the CPLD determines the levels of multiple lines connected to the corresponding pins of multiple check codes according to the power-on status of each resistor.

[0183] Step d2: determining a first check code based on the level corresponding to each line.

[0184] The first verification code is determined based on the level corresponding to each line. In this embodiment, the levels corresponding to eight lines are obtained, so the first verification code is an 8-digit number. The order can be the level of the line corresponding to pin A, the level of the line corresponding to pin B, the level of the line corresponding to pin C, the level of the line corresponding to pin D, the level of the line corresponding to pin E, the level of the line corresponding to pin F, the level of the line corresponding to pin G, and the level of the line corresponding to pin H. Of course, other orders are also possible. The specific order of the corresponding numbers in the first verification code can be set by technical personnel and is not specifically limited here.

[0185] The CPLD compares the 8-bit check code received from the check code generation circuit with the check code parsed from the SPI signal of the BMC Flash chip. If the two are consistent, it is considered that the first firmware has passed the verification; otherwise, the verification fails.

[0186] The CPLD compares the 8-bit check code received from the check code generation circuit with the check code parsed from the SPI signal of the BIOS Flash chip. If the two are consistent, it is considered that the second firmware has passed the verification; otherwise, the verification has failed.

[0187] The server startup method provided in this embodiment directly generates a check code through a physical line, that is, a pure hardware circuit, which reduces potential errors in the data transmission process. Compared with the software reading method, it is simpler, more stable, reliable, and tamper-proof, thereby enhancing the overall security and data integrity of the system and avoiding the security risks that may be introduced by TPM / TCM external cards.

[0188] In some optional implementations, the above step S4013 includes:

[0189] Step e1: compare the first check code and the second check code bit by bit.

[0190] In step e2, when every bit of the first check code and the second check code are identical, determining that the first comparison result is that the first check code and the second check code are consistent.

[0191] In step e3, when there is at least one difference between the first check code and the second check code, determining that the first comparison result is that the first check code and the second check code are inconsistent.

[0192] The server startup method provided in this embodiment can accurately detect the difference between the second verification code of the first firmware and the obtained first verification code by comparing the verification code bit by bit, ensuring that the first firmware is determined to have passed the verification only when the second verification code and the first verification code are completely consistent, thereby improving the reliability and accuracy of the first firmware when the server is started.

[0193] In some optional implementations, the above step a3 includes:

[0194] Step a31: compare the first check code and the third check code bit by bit.

[0195] Step a32: When every bit of the first check code and the third check code are identical, determining that the second comparison result is that the first check code and the third check code are identical.

[0196] Step a33: When there is at least one bit difference between the first check code and the third check code, determine that the second comparison result is that the first check code and the third check code are inconsistent.

[0197] The server startup method provided in this embodiment can accurately detect the difference between the third verification code of the second firmware and the obtained first verification code by comparing the verification code bit by bit, ensuring that the second firmware is determined to have passed the verification only when the third verification code and the first verification code are completely consistent, thereby improving the reliability and accuracy of the second firmware when the server is started.

[0198] To make the embodiments of the present invention clearer, a specific embodiment is described below.

[0199] 1) Power on the server. Connect terminals A and B1 of MUX chip 1, and establish an SPI path between the CPLD and the BMC Flash chip. Connect terminals A and B1 of MUX chip 2, and establish an SPI path between the CPLD and the BIOS Flash chip.

[0200] 2) The CPLD starts verifying the BMC firmware and controls the green LED1 to flash at a 1 Hz frequency. The CPLD parses the verification code information in the BMC firmware through the SPI link and compares it with the verification code read from the verification code generation circuit.

[0201] 3) When the information in step 2) matches, the CPLD controls LED 1 to light up green, indicating that the verification has passed. At the same time, it sends a selection signal 1 to MUX chip 1, disconnecting the link between A and B1 of MUX chip 1 and reconnecting the link between A and B2.

[0202] 4) When the information comparison in step 2) is inconsistent, the CPLD controls LED1 to make it light red, indicating that the verification has failed, and ends the verification process without further BIOS firmware verification.

[0203] 5) The CPLD starts to verify the BIOS firmware and controls the green LED2 to flash at a frequency of 1 Hz. The CPLD parses the checksum information in the BIOS firmware through the SPI link and compares it with the checksum read from the checksum generation circuit.

[0204] 6) When the information in step 5) matches, the CPLD controls LED 2 to light up green, indicating that the verification has passed. At the same time, it sends a selection signal 2 to MUX chip 2, disconnecting the link between A and B1 of MUX chip 2 and reconnecting the link between A and B2.

[0205] 7) If the information in step 5) is not consistent, the CPLD controls LED2 to light up red, indicating that the verification has failed, and ends the verification process without further BMC firmware verification.

[0206] 8) After verification, the server can be safely started.

[0207] If the information comparison in step 2) and the information comparison in step 5) are consistent, the server can perform a secure boot. That is, the BMC boots the BMC based on the BMC firmware, and the CPU boots the BIOS based on the BIOS firmware.

[0208] The server startup method provided in this embodiment uses a simple resistor, an LED, and a CPLD chip inherent in the motherboard to complete the verification of the BMC firmware and the BIOS firmware, thereby saving the cost of using a TPM / TCM plug-in card.

[0209] This embodiment also provides a server startup device for implementing the above-mentioned embodiments and preferred implementations. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0210] This embodiment provides a server startup device, such as Figure 7 Shown, including:

[0211] The verification module 701 is used to verify the first firmware in the first memory and the second firmware in the second memory after the server is powered on, wherein the first firmware is the firmware of the baseboard management controller and the second firmware is the firmware of the input and output system.

[0212] The first sending module 702 is used to send a first selection signal to the first multiplexer when the first firmware is verified, so that the first multiplexer cuts off the first link between the first memory and the target logic device based on the first selection signal, and connects the second link between the first memory and the baseboard management controller. The baseboard management controller obtains the first firmware based on the second link and starts based on the first firmware.

[0213] The second sending module 703 is used to send a second selection signal to the second multiplexer when the second firmware is verified, so that the second multiplexer cuts off the third link between the second memory and the target logic device based on the second selection signal, and connects the fourth link between the second memory and the central processing unit. The central processing unit obtains the second firmware based on the fourth link and starts the input and output system based on the second firmware.

[0214] In some optional implementations, the verification module 701 includes:

[0215] The first acquiring unit is configured to acquire a first verification code.

[0216] The first parsing unit is configured to parse the first firmware to obtain a second verification code.

[0217] The first comparison unit is used to compare the first check code with the second check code to obtain a first comparison result.

[0218] The first determining unit is configured to determine that the first firmware has passed verification if the first comparison result is that the first verification code is consistent with the second verification code.

[0219] In some optional implementations, the verification module 701 includes:

[0220] The second acquiring unit is configured to acquire a first verification code.

[0221] The second parsing unit is configured to parse the second firmware to obtain a third check code.

[0222] The second comparison unit is used to compare the first check code with the third check code to obtain a second comparison result.

[0223] The second determining unit is configured to determine that the second firmware passes verification if the second comparison result is that the first verification code is consistent with the third verification code.

[0224] In some optional implementations, the server startup device further includes:

[0225] The first ending execution module is used to end the step of verifying the second firmware in the second memory if the first firmware fails to pass the verification.

[0226] The second ending execution module is used to end the step of verifying the first firmware in the first memory if the second firmware fails to pass the verification.

[0227] In some optional implementations, the server startup device further includes:

[0228] The third sending module is used to send a corresponding lighting signal to the first light-emitting diode based on the verification status of the first firmware to indicate the verification status of the first firmware.

[0229] The fourth sending module is used to send a corresponding lighting signal to the second light-emitting diode based on the verification status of the second firmware to indicate the verification status of the second firmware.

[0230] In some optional implementations, the third sending module includes:

[0231] The first sending unit is used to control the first lighting signal sent to the first light-emitting diode to flip the high and low levels at a first frequency when the verification status of the first firmware is that the first firmware is being verified, so that the state of the first light-emitting diode is a green flashing state, indicating that the first firmware is being verified.

[0232] The second sending unit is used to control the first lighting signal sent to the first light-emitting diode to be low level when the verification status of the first firmware is verification passed, so that the state of the first light-emitting diode is green and long-on state, indicating that the first firmware verification has passed.

[0233] The third sending unit is used to control the second lighting signal sent to the first light-emitting diode to be low level when the verification status of the first firmware is verification failure, so that the state of the first light-emitting diode is a long red state, indicating that the first firmware verification has failed.

[0234] The fourth sending module includes:

[0235] The fourth sending unit is used to control the third lighting signal sent to the second light-emitting diode to flip the high and low levels at the first frequency when the verification status of the second firmware is that the second firmware is being verified, so that the state of the second light-emitting diode is a green flashing state, indicating that the second firmware is being verified.

[0236] The fifth sending unit is used to control the third lighting signal sent to the second light-emitting diode to be low level when the verification status of the second firmware is passed, so that the state of the second light-emitting diode is green and long-on state, indicating that the second firmware verification has passed.

[0237] The sixth sending unit is used to control the fourth lighting signal sent to the second light-emitting diode to be low level when the verification status of the second firmware is verification failure, so that the state of the second light-emitting diode is red and long-on state, indicating that the second firmware verification has failed.

[0238] In some optional implementations, the first acquisition unit or the second acquisition unit includes:

[0239] The acquisition subunit is used to obtain the level corresponding to each line based on multiple lines connected to the multiple check code acquisition pins in the target logic device.

[0240] The third determining unit is configured to determine a first check code based on a level corresponding to each line.

[0241] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0242] The server startup device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0243] The embodiment of the present invention also provides a computer device having the above Figure 7 The server boot device is shown.

[0244] See also Figure 8 , Figure 8 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 8 As shown, the computer device includes: one or more processors 801, memory 802, and the interface for connecting each component, including high-speed interface and low-speed interface. Each component utilizes different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instruction executed in the computer device, including being stored in the memory or on the memory to display the graphic information of the GUI on an external input / output device (such as, being coupled to the display device of the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides the necessary operation of part (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 A processor 801 is taken as an example.

[0245] Processor 801 may be a central processing unit, a network processor, or a combination thereof. Processor 801 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0246] The memory 802 stores instructions that can be executed by at least one processor 801, so as to enable the at least one processor 801 to execute the method shown in the above embodiment.

[0247] The memory 802 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 802 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 802 may optionally include a memory remotely located relative to the processor 801, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0248] The memory 802 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 802 may also include a combination of the above types of memory.

[0249] The computer device further includes a communication interface 803 for the computer device to communicate with other devices or a communication network.

[0250] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0251] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0252] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A server startup method, characterized in that: Applied to a target logic device, the method includes: After the server is powered on, verifying a first firmware in a first memory and a second firmware in a second memory, wherein the first firmware is firmware of a baseboard management controller and the second firmware is firmware of an input / output system, the target logic obtaining a first verification code through a verification code generation circuit, the verification code generation circuit being configured to generate a first verification code, the first verification code being used to verify the first firmware and the second firmware; If the first firmware passes verification, sending a first strobe signal to a first multiplexer, so that the first multiplexer cuts off a first link between the first memory and the target logic device based on the first strobe signal and connects a second link between the first memory and a baseboard management controller, and the baseboard management controller obtains the first firmware based on the second link and starts based on the first firmware; If the second firmware passes the verification, a second selection signal is sent to the second multiplexer, so that the second multiplexer cuts off the third link between the second memory and the target logic device based on the second selection signal, and connects the fourth link between the second memory and the central processing unit. The central processing unit obtains the second firmware based on the fourth link and starts the input and output system based on the second firmware.

2. The method according to claim 1, characterized in that Verifying the first firmware in the first memory includes: Obtain a first verification code; Parsing the first firmware to obtain a second verification code; Comparing the first verification code with the second verification code to obtain a first comparison result; If the first comparison result is that the first verification code is consistent with the second verification code, it is determined that the first firmware has passed verification.

3. The method according to claim 1, characterized in that Verifying the second firmware in the second memory includes: Obtain a first verification code; parsing the second firmware to obtain a third verification code; Comparing the first verification code with the third verification code to obtain a second comparison result; If the second comparison result is that the first verification code is consistent with the third verification code, it is determined that the second firmware passes verification.

4. The method according to claim 1, wherein The method further comprises: If the first firmware fails verification, ending the step of verifying the second firmware in the second memory; If the second firmware fails the verification, the step of verifying the first firmware in the first memory ends.

5. The method according to claim 1, wherein The method further comprises: Based on the verification status of the first firmware, sending a corresponding lighting signal to the first light-emitting diode to indicate the verification status of the first firmware; Based on the verification status of the second firmware, a corresponding lighting signal is sent to the second light emitting diode to indicate the verification status of the second firmware.

6. The method according to claim 5, characterized in that The step of sending a corresponding lighting signal to the first light emitting diode based on the verification status of the first firmware includes: When the verification state of the first firmware is that the first firmware is being verified, controlling the first lighting signal sent to the first light-emitting diode to flip the high and low levels at a first frequency, so that the state of the first light-emitting diode is a green flashing state, indicating that the first firmware is being verified; When the verification status of the first firmware is verified to be passed, controlling the first lighting signal sent to the first light-emitting diode to be low level, so that the state of the first light-emitting diode is a green and steady state, indicating that the first firmware verification has passed; When the verification status of the first firmware is verification failure, controlling the second lighting signal sent to the first light-emitting diode to be low level, so that the state of the first light-emitting diode is a red and steady light state, indicating that the first firmware verification has failed; The step of sending a corresponding lighting signal to the second light emitting diode based on the verification status of the second firmware includes: When the verification state of the second firmware is that the second firmware is being verified, controlling the third lighting signal sent to the second light-emitting diode to flip the high and low levels at the first frequency, so that the state of the second light-emitting diode is a green flashing state, indicating that the second firmware is being verified; When the verification status of the second firmware is passed, the third lighting signal sent to the second light-emitting diode is controlled to be low level, so that the state of the second light-emitting diode is a green and steady state, indicating that the second firmware has passed the verification; When the verification status of the second firmware is verification failure, the fourth lighting signal sent to the second light-emitting diode is controlled to be low level, so that the state of the second light-emitting diode is a long red state, indicating that the second firmware verification has failed.

7. The method according to claim 2 or claim 3, characterized in that The obtaining of the first verification code includes: Based on a plurality of lines correspondingly connected to a plurality of check code acquisition pins in the target logic device, obtaining a level corresponding to each line; A first check code is determined based on the level corresponding to each line.

8. A server startup device, characterized in that: The device comprises: a verification module, configured to verify, after the server is powered on, first firmware in a first memory and second firmware in a second memory, wherein the first firmware is firmware for a baseboard management controller and the second firmware is firmware for an input / output system; the target logic device obtains a first verification code through a verification code generation circuit, the verification code generation circuit is configured to generate a first verification code, and the first verification code is used to verify the first firmware and the second firmware; a first sending module, configured to send a first selection signal to a first multiplexer if the first firmware passes verification, so that the first multiplexer disconnects a first link between the first memory and the target logic device based on the first selection signal and connects a second link between the first memory and a baseboard management controller, so that the baseboard management controller obtains the first firmware based on the second link and starts based on the first firmware; The second sending module is used to send a second selection signal to the second multiplexer when the second firmware passes the verification, so that the second multiplexer cuts off the third link between the second memory and the target logic device based on the second selection signal, and connects the fourth link between the second memory and the central processing unit. The central processing unit obtains the second firmware based on the fourth link and starts the input and output system based on the second firmware.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the server startup method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the server startup method according to any one of claims 1 to 7.

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