Image display control method and device and chip

Abstract

The invention discloses an image display control method and device and a chip, and the method comprises the steps: reading a first image frame from an on-chip memory through employing a two-dimensional image processing unit under the condition that the target resolution of a display image is higher, combining a to-be-displayed image with the first image frame, generating a second image frame, writing the second image frame into the on-chip memory, and enabling the to-be-displayed image to be displayed in the on-chip memory; according to the image rendering method and device, the first image frame in the on-chip memory is replaced by the first image frame in the on-chip memory, so that the image rendering process is completed by storing one image frame in the on-chip memory and reading and writing the on-chip memory, multiple times of reading and writing of the off-chip memory are avoided, the bandwidth pressure is reduced while the image rendering effect is guaranteed, and the image display efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an image display control method, device and chip. Background Art

[0002] In the semiconductor field, memory is often set outside the chip. Memory bandwidth usage usually refers to the bandwidth occupied by the memory system during data transmission. Bandwidth usage can be expressed as the amount of data that the memory system can transmit in a specific time, usually measured in bits or bytes per second. Memory bandwidth usage is critical to system performance and throughput, especially in application scenarios that require processing large amounts of data, such as graphics processing, high-performance computing, and large-scale databases.

[0003] At present, for multi-hardware domain chips, there are multiple hardware domains that have image display requirements. The images to be displayed after being processed by these hardware domains will first be stored in the off-chip memory. When rendering the image, the image processing unit obtains the image to be displayed from the off-chip memory, processes it, and then writes it to the off-chip memory, and then displays it on the screen. It can be seen that this process will cause multiple read and write operations on the off-chip memory, which will bring a large amount of bandwidth occupation, and then cause the problem of slow frame rate due to bandwidth pressure. In order to optimize the bandwidth, there is a processing method that sets the frame buffer in the external memory to a smaller format, but this processing method will cause the output display data to lose color space. Summary of the invention

[0004] The embodiments of the present application provide an image display control method, device and chip, which store an image frame in an on-chip memory and complete the image rendering process by reading and writing the on-chip memory to reduce bandwidth pressure.

[0005] In a first aspect, an image display control method is provided, which is applied to a chip including an on-chip memory, comprising: using a two-dimensional image processing unit to read an image to be displayed from an off-chip memory independent of the chip; determining a target resolution of a display screen in a display, and when the target resolution reaches a resolution threshold, using the two-dimensional image processing unit to read a first image frame from the on-chip memory, the first image frame corresponding to the display screen; using the two-dimensional image processing unit to merge the image to be displayed and the first image frame to generate a second image frame; using the two-dimensional image processing unit to write the second image frame into the on-chip memory to replace the first image frame in the on-chip memory; and using the two-dimensional image processing unit to drive the display to display an image based on the second image frame in the on-chip memory.

[0006] In some embodiments, before using the two-dimensional image processing unit to read the first image frame from the on-chip memory, it also includes at least one of the following: reading image data corresponding to the display screen from the off-chip memory, generating the first image frame based on the image data, and writing the first image frame to the on-chip memory; reading a target image frame corresponding to the display screen from the off-chip memory, and writing the target image frame as the first image frame to the on-chip memory.

[0007] In some embodiments, the off-chip memory includes at least one frame buffer, and the target image frame corresponding to the display screen is read from the off-chip memory, including: if the off-chip memory includes one frame buffer, the target image frame is read from the one frame buffer; if the off-chip memory includes multiple frame buffers, the target image frame is read from a first target frame buffer, each of the frame buffers is used to store image frames written by the two-dimensional image processing unit in a preset writing order, and the first target frame buffer is the frame buffer in which the image frame is last written among the frame buffers.

[0008] In some embodiments, the two-dimensional image processing unit is used to drive the display to display images based on the second image frame in the on-chip memory, including: using the two-dimensional image processing unit to copy the second image frame in the on-chip memory to the off-chip memory through a fast copy technology; using a display control unit to read the second image frame from the off-chip memory, and sending the second image frame to the display for display.

[0009] In some embodiments, after determining the target resolution of the display screen in the display, it also includes: when the target resolution does not reach the resolution threshold, using the two-dimensional image processing unit to read a third image frame corresponding to the display screen from the off-chip memory; using the two-dimensional image processing unit to merge the image to be displayed and the third image frame to generate a fourth image frame; using the two-dimensional image processing unit to write the fourth image frame to the off-chip memory; using the two-dimensional image processing unit, based on the fourth image frame in the off-chip memory, driving the display to display an image.

[0010] In some embodiments, the off-chip memory includes at least one frame buffer, and the two-dimensional image processing unit is used to write the fourth image frame into the off-chip memory, including: if the off-chip memory includes one frame buffer, the two-dimensional image processing unit is used to write the fourth image frame into the one frame buffer; if the off-chip memory includes multiple frame buffers, the two-dimensional image processing unit is used to write the fourth image frame into a second target frame buffer, each of the frame buffers is used to store image frames written by the two-dimensional image processing unit in a preset writing order, and the second target frame buffer is the frame buffer in which the image frame is first written among each frame buffer.

[0011] In some embodiments, the two-dimensional image processing unit is used to merge the image to be displayed and the first image frame to generate a second image frame, including at least one of the following: using the two-dimensional image processing unit to determine a target area corresponding to the image to be displayed in the first image frame, updating the target area based on the image to be displayed, and generating the second image frame; using the two-dimensional image processing unit to determine a target layer corresponding to the image to be displayed in the first image frame, updating the target layer based on the image to be displayed, and generating the second image frame.

[0012] In a second aspect, an image display control device is provided, which is applied to a chip including an on-chip memory, and includes: a processor, used to determine a target resolution of a display screen in a display, and compare the target resolution area with a resolution threshold; a two-dimensional image processing unit, used to read an image to be displayed from an off-chip memory independent of the chip when the target resolution reaches the resolution threshold; read a first image frame from the on-chip memory, the first image frame corresponding to the display screen; merge the image to be displayed and the first image frame to generate a second image frame; write the second image frame into the on-chip memory to replace the first image frame in the on-chip memory; and drive the display to display an image based on the second image frame in the on-chip memory.

[0013] In some embodiments, the two-dimensional image processing unit is also used to copy the second image frame in the on-chip memory to the off-chip memory through a fast copy technology, and the image display control device also includes: a display control unit, used to read the second image frame from the off-chip memory and send the second image frame to the display for display.

[0014] According to a third aspect, a chip is provided, comprising the image display control device as described in the second aspect.

[0015] By applying the above technical solution, a two-dimensional image processing unit is used to read the image to be displayed from an off-chip memory independent of the chip; the target resolution of the display screen in the display is determined, and when the target resolution reaches the resolution threshold, the two-dimensional image processing unit is used to read the first image frame from the on-chip memory, and the first image frame corresponds to the display screen; the two-dimensional image processing unit is used to merge the image to be displayed and the first image frame to generate a second image frame; the two-dimensional image processing unit is used to write the second image frame into the on-chip memory to replace the first image frame in the on-chip memory; the two-dimensional image processing unit is used to drive the display to display the image based on the second image frame in the on-chip memory. In this way, an image frame is stored in the on-chip memory, and the image rendering process is completed by reading and writing the on-chip memory, thereby avoiding multiple reading and writing of the off-chip memory, thereby reducing the bandwidth pressure while ensuring the image rendering effect, thereby improving the image display efficiency and avoiding the problem of slow frame rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 A flowchart of an image display control method according to an embodiment of the present application;

[0018] Figure 2 A flowchart of driving a display to display an image according to an embodiment of the present application;

[0019] Figure 3 A flowchart of an image display control method according to another embodiment of the present application;

[0020] Figure 4 A system framework diagram corresponding to the image display control method of an embodiment of the present application;

[0021] Figure 5 A schematic diagram of the principle of the image display control method according to an embodiment of the present application;

[0022] Figure 6 A schematic diagram of an image rendering process without adopting the image display control method of the embodiment of the present application;

[0023] Figure 7 For Figure 6 Schematic diagram of bandwidth calculation for the corresponding image rendering process;

[0024] Figure 8 A schematic diagram of an image rendering process after adopting the image display control method according to an embodiment of the present application;

[0025] Fig. 9 For Figure 8 Schematic diagram of bandwidth calculation for the corresponding image rendering process;

[0026] Fig.10 is a structural block diagram of an image display control device according to an embodiment of the present application;

[0027] Fig.11 This is a structural block diagram of an image display control device according to another embodiment of the present application. DETAILED DESCRIPTION

[0028] Various aspects and features of the present application are described herein with reference to the accompanying drawings.

[0029] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0030] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0031] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0032] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to readily implement many other equivalent forms of the present application.

[0033] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.

[0034] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.

[0035] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.

[0036] Before describing the embodiments of the present application in detail, the technical names and terms involved in the embodiments of the present application are first described.

[0037] (1) On-chip memory, i.e. IRAM (internal RAM), is an internal random access memory that is usually integrated inside the chip. The processor can directly access the data in IRAM through the data bus and address bus, which makes the access speed of IRAM very fast and can meet the needs of high-performance computing.

[0038] (2) Off-chip memory: memory that is independent of the chip, which can be DDR or SDRAM. Its storage capacity is usually greater than the storage capacity of on-chip memory.

[0039] (3) Two-dimensional image processing unit, usually refers to the 2D graphics acceleration engine (2D Graphics Acceleration Engine) in the graphics processing unit (GPU). G2D is a component in the GPU that is specifically used to handle 2D graphics operations and rendering. It can be a part of the GPU, specifically responsible for the acceleration and rendering of 2D data such as images, text, and graphics. In the semiconductor field, it is widely used in embedded systems and mobile devices to provide high-performance graphics processing capabilities.

[0040] (4) Display control unit, namely DC (Display control), is the hardware that displays data.

[0041] (5) Framebuffer is a memory data cache used for display.

[0042] (6) Hardware domain: Multiple hardware components can be integrated into a chip, such as the central processing unit (CPU), memory controller, graphics processing unit (GPU), etc. These hardware resources are configured into multiple sets of different hardware components, called hardware domains.

[0043] An image display control method according to an embodiment of the present application, when the target resolution of the display screen is high, uses a two-dimensional image processing unit to read a first image frame from an on-chip memory, merges the image to be displayed and the first image frame to generate a second image frame, and writes the second image frame into the on-chip memory to replace the first image frame in the on-chip memory. In this way, an image frame is stored in the on-chip memory, and the image rendering process is completed by reading and writing the on-chip memory, thereby avoiding multiple reading and writing of off-chip memory, thereby reducing bandwidth pressure while ensuring image rendering effect, thereby improving image display efficiency.

[0044] The image display control method is applied to a chip including an on-chip memory, such as Figure 1 As shown, the following steps are included:

[0045] Step S101 : using a two-dimensional image processing unit, reading an image to be displayed from an off-chip memory independent of the chip.

[0046] In this embodiment, an on-chip memory is provided in the chip, and the chip may be, for example, a chip of the type of MCU (Microcontroller Unit), SoC (System on Chip), etc. The image to be displayed may be an image generated by the hardware domain of the chip, and the hardware domain stores the image to be displayed in an off-chip memory after generating the image to be displayed. The image to be displayed may correspond to a certain area in a display screen in a display, or may correspond to a certain layer in a display screen, and the image to be displayed may include one or more layers. The image to be displayed is read from an off-chip memory independent of the chip using a two-dimensional image processing unit, and then the two-dimensional image processing unit performs image rendering on the image to be displayed.

[0047] Step S102, determining a target resolution of a display screen in the display, and when the target resolution reaches a resolution threshold, using the two-dimensional image processing unit to read a first image frame from the on-chip memory, the first image frame corresponding to the display screen.

[0048] In this embodiment, the display screen of the display may adopt different target resolutions. The higher the target resolution, the larger the amount of data in the rendering process. If the target resolution reaches the resolution threshold, it means that the display screen adopts a higher target resolution. In this case, the image frames stored in the on-chip memory are used for image rendering to reduce the reading and writing of the off-chip memory and reduce the bandwidth pressure. Specifically, the two-dimensional image processing unit is used to read the first image frame from the on-chip memory, and the first image frame may be the image frame currently displayed in the display screen.

[0049] Step S103: Utilize the two-dimensional image processing unit to merge the image to be displayed and the first image frame to generate a second image frame.

[0050] After the image to be displayed and the first image frame are obtained, the image to be displayed and the first image frame are merged by using a two-dimensional image processing unit to update image data corresponding to the image to be displayed in the first image frame to generate a second image frame.

[0051] Step S104: Use the two-dimensional image processing unit to write the second image frame into the on-chip memory to replace the first image frame in the on-chip memory.

[0052] In this embodiment, the on-chip memory stores an image frame, and the two-dimensional image processing unit writes the second image frame into the on-chip memory, so that the first image frame in the on-chip memory becomes the second image frame, thereby completing the rendering operation of the image to be displayed. The second image frame stored in the on-chip memory is the next frame image of the display screen.

[0053] Step S105 , using the two-dimensional image processing unit to drive the display to display an image based on the second image frame in the on-chip memory.

[0054] In this embodiment, the two-dimensional image processing unit is used to drive the display to display the second image frame, thereby completing display of the image to be displayed.

[0055] The image display control method of the embodiment of the present application uses a two-dimensional image processing unit to read the image to be displayed from an off-chip memory independent of the chip; determines the target resolution of the display screen in the display, and when the target resolution reaches the resolution threshold, uses the two-dimensional image processing unit to read the first image frame from the on-chip memory, the first image frame corresponding to the display screen; uses the two-dimensional image processing unit to merge the image to be displayed and the first image frame to generate a second image frame; uses the two-dimensional image processing unit to write the second image frame into the on-chip memory to replace the first image frame in the on-chip memory; uses the two-dimensional image processing unit to drive the display to display the image based on the second image frame in the on-chip memory. In this way, by storing an image frame in the on-chip memory and completing the image rendering process by reading and writing the on-chip memory, multiple reading and writing of the off-chip memory is avoided, thereby reducing the bandwidth pressure while ensuring the image rendering effect, thereby improving the image display efficiency and avoiding the problem of slow frame rate.

[0056] In some embodiments of the present application, before using the two-dimensional image processing unit to read the first image frame from the on-chip memory, at least one of the following is further included:

[0057] Reading image data corresponding to the display screen from the off-chip memory, generating the first image frame according to the image data, and writing the first image frame into the on-chip memory;

[0058] A target image frame corresponding to the display picture is read from the off-chip memory, and the target image frame is written into the on-chip memory as the first image frame.

[0059] In this embodiment, in order to perform image rendering based on the on-chip memory, it is necessary to first write the first image frame into the on-chip memory. Specifically, as one method, the image data corresponding to the display screen (e.g., image data of different areas or image data of different layers in the display screen) can be read from the off-chip memory first, and then the first image frame is generated according to the image data, and then the first image frame is written into the on-chip memory, thereby ensuring that the first image frame is reliably read from the on-chip memory. As another method, the target image frame corresponding to the display screen already exists in the off-chip memory, and the target image frame is first read from the off-chip memory, and then the target image frame is written into the on-chip memory as the first image frame, thereby ensuring that the first image frame is reliably read from the on-chip memory.

[0060] Optionally, the first image frame may be written into the on-chip memory in any of two ways, or different ways may be selected to write the first image frame into the on-chip memory according to different situations. For example, if the target image frame does not exist in the off-chip memory, the first image frame is generated according to the image data in the off-chip memory, and then the first image frame is written into the on-chip memory. If the target image frame already exists in the off-chip memory, the target image frame is directly read from the off-chip memory and written into the on-chip memory.

[0061] In some embodiments of the present application, the off-chip memory includes at least one frame buffer, and reading a target image frame corresponding to the display screen from the off-chip memory includes:

[0062] If the off-chip memory includes a frame buffer, reading the target image frame from the frame buffer;

[0063] If the off-chip memory includes multiple frame buffers, the target image frame is read from a first target frame buffer, each of which is used to store image frames written by the two-dimensional image processing unit in a preset writing order, and the first target frame buffer is the frame buffer in which the image frame is last written among the frame buffers.

[0064] In this embodiment, the off-chip memory includes at least one frame buffer. If the off-chip memory includes a frame buffer, the target image frame is read from the frame buffer. In the case where the off-chip memory includes multiple frame buffers, the two-dimensional image processing unit writes image frames to each frame buffer in a preset writing order. The image frame is a rendered image frame, and in some cases, it is a second image frame read from the on-chip memory. Subsequently, the image frames stored in each frame buffer are used in turn to drive the display to display the image. The frame buffer in which the image frame is written last in each frame buffer is the first target frame buffer. It can be understood that the image frame in the first target frame buffer corresponds to the image frame currently displayed in the display screen, and the target image frame is read from the first target frame buffer, thereby ensuring efficient reading of the target image frame.

[0065] For example, if the off-chip memory includes frame buffer 1 and frame buffer 2, the image frame in frame buffer 1 corresponds to the current image frame of the display screen, and frame buffer 2 corresponds to the previous image frame of the display screen. At this time, frame buffer 1 is the first target frame buffer. Subsequently, the two-dimensional image processing unit writes the next image frame into frame buffer 2, and frame buffer 2 becomes the first target frame buffer. At this time, the image frame in frame buffer 2 corresponds to the current image frame of the display screen, and frame buffer 1 corresponds to the previous image frame of the display screen. Then, the two-dimensional image processing unit writes the next image frame into frame buffer 1, and frame buffer 1 becomes the first target frame buffer, and so on.

[0066] In some embodiments of the present application, the two-dimensional image processing unit is used to drive the display to display an image based on the second image frame in the on-chip memory, such as Figure 2 As shown, the following steps are included:

[0067] Step S1051: using the two-dimensional image processing unit, copying the second image frame in the on-chip memory to the off-chip memory by using a fast copy technology.

[0068] In this embodiment, Figure 4 FIG. 1 is a system framework diagram corresponding to the image display control method of an embodiment of the present application. Figure 5 FIG. 2 is a schematic diagram showing the principle of the image display control method according to an embodiment of the present application. Figure 4 As shown, an on-chip memory is provided inside the chip, an off-chip memory is provided outside the chip, and a cache is provided between the chip and the off-chip memory, which can improve the efficiency of the chip in reading the off-chip memory. When the target resolution reaches the resolution threshold, the two-dimensional image processing unit merges the image to be displayed read from the off-chip memory and the first image frame read from the on-chip memory, and writes the generated second image frame into the on-chip memory. After that, the two-dimensional image processing unit copies the second image frame in the on-chip memory to the off-chip memory through the fast copy technology. Figure 5 As shown, the image to be displayed may include multiple layers, and the off-chip memory includes frame buffer 1 and frame buffer 2.

[0069] The fast copy technology can be implemented based on the FastCopy tool. The process of the fast copy technology can be: first input the target path to be copied, which can be a pure file or a directory, and convert the input target path to be copied into multiple FastCopy requests; submit the FastCopy requests to a thread pool for execution; according to the node positions of the source block and the target block in the copy process, perform the ordinary DataCopy copy operation or the local LocalCopy copy operation respectively.

[0070] The two-dimensional image processing unit copies the second image frame in the on-chip memory to the off-chip memory through the fast copy technology, so that the second image frame can be copied to the off-chip memory more efficiently.

[0071] Step S1052: read the second image frame from the off-chip memory using a display control unit, and send the second image frame to the display for display.

[0072] In this embodiment, Figure 4 and Figure 5 As shown, the display control unit reads the second image frame from the off-chip memory. Specifically, if the off-chip memory includes a frame buffer, the display control unit reads the second image frame from the frame buffer. If the off-chip memory includes multiple frame buffers, the display control unit reads the second image frame from the frame buffer (i.e., the first target frame buffer) into which the image frame is last written. The display control unit then outputs the second image frame to the display for display, thereby ensuring that the display reliably displays the second image frame.

[0073] In some embodiments of the present application, after determining the target resolution of the displayed image on the display, such as Figure 3 As shown, the following steps are also included:

[0074] Step S106 : when the target resolution does not reach the resolution threshold, use the two-dimensional image processing unit to read a third image frame corresponding to the display picture from the off-chip memory.

[0075] In this embodiment, if the target resolution does not reach the resolution threshold, it means that the amount of data to be read and written is small, and the bandwidth occupied is also small, and the off-chip memory can be used for image rendering. First, the two-dimensional image processing unit is used to read the third image frame corresponding to the display screen from the off-chip memory. Specifically, if the off-chip memory includes a frame buffer, the display control unit reads the third image frame from the frame buffer. If the off-chip memory includes multiple frame buffers, the display control unit reads the third image frame from the frame buffer to which the image frame was last written (i.e., the first target frame buffer).

[0076] Step S107: Utilize the two-dimensional image processing unit to merge the image to be displayed and the third image frame to generate a fourth image frame.

[0077] After the image to be displayed and the third image frame are obtained, the image to be displayed and the third image frame are merged by using a two-dimensional image processing unit to update image data corresponding to the image to be displayed in the third image frame to generate a fourth image frame.

[0078] Step S108: Using the two-dimensional image processing unit to write the fourth image frame into the off-chip memory.

[0079] The fourth image frame is written into the off-chip memory by using the two-dimensional image processing unit, thereby completing the rendering operation of the image to be displayed. The fourth image frame stored in the off-chip memory is the next frame image of the display screen.

[0080] Step S109: utilizing the two-dimensional image processing unit to drive the display to display an image based on the fourth image frame in the off-chip memory.

[0081] In this embodiment, the two-dimensional image processing unit and the fourth image frame in the off-chip memory are used to drive the display to display the fourth image frame, thereby completing display of the image to be displayed.

[0082] By performing image rendering based on off-chip memory when the target resolution does not reach the resolution threshold, the amount of data read and written during the rendering process is not large and will not occupy a large bandwidth. At the same time, on-chip memory can be used to perform other tasks besides image rendering, thereby improving flexibility.

[0083] In some embodiments of the present application, the off-chip memory includes at least one frame buffer, and using the two-dimensional image processing unit to write the fourth image frame into the off-chip memory includes:

[0084] If the off-chip memory includes a frame buffer, using the two-dimensional image processing unit to write the fourth image frame into the frame buffer;

[0085] If the off-chip memory includes multiple frame buffers, the two-dimensional image processing unit is used to write the fourth image frame into a second target frame buffer, each of the frame buffers is used to store the image frames written by the two-dimensional image processing unit in a preset writing order, and the second target frame buffer is the frame buffer in which the image frame is written first among the frame buffers.

[0086] In this embodiment, the off-chip memory includes at least one frame buffer. If the off-chip memory includes a frame buffer, the two-dimensional image processing unit is used to write the fourth image frame into the frame buffer. In the case where the off-chip memory includes multiple frame buffers, the two-dimensional image processing unit writes image frames to each frame buffer in a preset writing order, and the image frames are rendered image frames. Subsequently, the image frames stored in each frame buffer are used in turn to drive the display to display images. The frame buffer in each frame buffer that first writes the image frame is the second target frame buffer, and the two-dimensional image processing unit is used to write the fourth image frame into the second target frame buffer, thereby ensuring that the fourth image frame is written into the off-chip memory efficiently and accurately.

[0087] For example, if the off-chip memory includes frame buffer 1 and frame buffer 2, the image frame in frame buffer 1 corresponds to the current image frame of the display screen, and frame buffer 2 corresponds to the previous image frame of the display screen. At this time, frame buffer 2 is the second target frame buffer. Subsequently, the two-dimensional image processing unit writes the next fourth image frame into frame buffer 2, and frame buffer 1 becomes the second target frame buffer. At this time, the image frame in frame buffer 2 corresponds to the current image frame of the display screen, and frame buffer 1 corresponds to the previous image frame of the display screen. Then, the two-dimensional image processing unit writes the next fourth image frame into frame buffer 1, and frame buffer 2 becomes the second target frame buffer, and so on.

[0088] It can be understood that, since image rendering can be performed through an on-chip memory or an off-chip memory, when the target resolution reaches the resolution threshold, the image frame stored in each frame buffer may be the second image frame written by the two-dimensional image processing unit. When the target resolution does not reach the resolution threshold, the image frame stored in each frame buffer may be the fourth image frame written by the two-dimensional image processing unit.

[0089] It should be noted that the “first” and “last” mentioned in the embodiments of the present application are not fixed, but change as the two-dimensional image processing unit writes each image frame into each frame buffer.

[0090] In some embodiments of the present application, using the two-dimensional image processing unit to merge the image to be displayed and the first image frame to generate a second image frame includes at least one of the following:

[0091] Determine a target area corresponding to the image to be displayed in the first image frame by using the two-dimensional image processing unit, update the target area based on the image to be displayed, and generate the second image frame;

[0092] The two-dimensional image processing unit is used to determine a target layer corresponding to the image to be displayed in the first image frame, and the layer is updated based on the image to be displayed to generate the second image frame.

[0093] In this embodiment, the image to be displayed may correspond to a target area in the first image frame. In this case, a two-dimensional image processing unit is used to determine the target area in the first image frame, and the target area is updated based on the image to be displayed, thereby achieving efficient generation of the second image frame.

[0094] The image to be displayed may also correspond to a target layer in the first image frame. In this case, a two-dimensional image processing unit is used to determine the target layer corresponding to the image to be displayed in the first image frame, and the target layer is updated based on the image to be displayed, thereby achieving an efficient second image frame.

[0095] Similarly, in some embodiments of the present application, using a two-dimensional image processing unit to merge the image to be displayed and the third image frame to generate a fourth image frame includes at least one of the following:

[0096] Determine, by using a two-dimensional image processing unit, an area corresponding to the image to be displayed in the third image frame, and update the area corresponding to the image to be displayed in the third image frame based on the image to be displayed to generate a fourth image frame;

[0097] The two-dimensional image processing unit is used to determine the layer corresponding to the image to be displayed in the third image frame, and the layer corresponding to the image to be displayed in the third image frame is updated based on the image to be displayed to generate a fourth image frame.

[0098] The following combination Figure 6-Figure 9 The technical effects of the image display control method of the embodiment of the present application are described. Figure 6-Figure 9 In the figure, SDRAM / DDR indicates off-chip memory, image or img indicates the image to be displayed read from the off-chip memory, the image format of the image to be displayed is RGBA8888 (one pixel occupies 4 bytes), fmt indicates the image format, framebuffer is the frame buffer in the off-chip memory, and iram is the on-chip memory.

[0099] like Figure 6 Schematic diagram of the image rendering process without using the image display control method of the embodiment of the present application, the image rendering process involves synthesizing the image with the target area in the framebuffer, the position of the target area is (0,0,400,400), and then writing the synthesized image frame into the framebuffer. Figure 7 Shown with Figure 6 The corresponding bandwidth calculation diagram of the image rendering process, Figure 7 The corresponding image rendering process includes reading img from the off-chip memory, reading the image frame before synthesis (such as the third image frame) from the framebuffer of the off-chip memory, and writing the synthesized image frame (such as the fourth image frame) to the framebuffer of the off-chip memory. The whole process involves two read operations and one write operation on the off-chip memory, and the bandwidth occupied by the off-chip memory is: 400*400*4*3*60=110M. Among them, 400*400 represents the number of pixels, 4 represents one pixel occupies 4 bytes, 3 represents two read operations plus one write operation, and 60 represents 60 frames.

[0100] like Figure 8 The image rendering process after adopting the image display control method of the embodiment of the present application is schematically shown. The image rendering process involves synthesizing the target area in image and iram, where the position of the target area is (0, 0, 400, 400), and then writing the synthesized image frame into iram. Fig. 9 Shown with Figure 8 The corresponding bandwidth calculation diagram of the image rendering process, Fig. 9 The corresponding image rendering process includes reading img from the off-chip memory, reading the image frame before synthesis (the first image frame) from iram, and writing the synthesized image frame (the second image frame) to iram. The whole process involves performing a read operation on the off-chip memory, a read operation and a write operation on iram, and the bandwidth occupied by the off-chip memory is: 400*400*4*60=36.6M. It can be seen that by adopting the image display control method of the embodiment of the present application, the bandwidth occupied by the off-chip memory is greatly reduced.

[0101] The present application also provides an image display control device, which is applied to a chip including an on-chip memory, such as Fig.10 As shown, including:

[0102] A processor, configured to determine a target resolution of a display image in the display, and compare the target resolution region with a resolution threshold;

[0103] A two-dimensional image processing unit is used to read the image to be displayed from an off-chip memory independent of the chip when the target resolution reaches a resolution threshold; read a first image frame from the on-chip memory, the first image frame corresponding to the display screen; merge the image to be displayed and the first image frame to generate a second image frame; write the second image frame into the on-chip memory to replace the first image frame in the on-chip memory; and drive the display to display an image based on the second image frame in the on-chip memory.

[0104] The image display control device of the embodiment of the present application, when the target resolution of the display screen is high, uses a two-dimensional image processing unit to read a first image frame from the on-chip memory, merges the image to be displayed and the first image frame to generate a second image frame, and writes the second image frame to the on-chip memory to replace the first image frame in the on-chip memory. In this way, an image frame is stored in the on-chip memory, and the image rendering process is completed by reading and writing the on-chip memory, thereby avoiding multiple reading and writing of the off-chip memory, thereby reducing the bandwidth pressure while ensuring the image rendering effect, thereby improving the image display efficiency.

[0105] In some embodiments of the present application, the two-dimensional image processing unit is further configured to copy the second image frame in the on-chip memory to the off-chip memory by using a fast copy technique, such as Fig.11 As shown, the image display control device also includes:

[0106] The display control unit is used to read the second image frame from the off-chip memory and send the second image frame to the display for display.

[0107] Optionally, the two-dimensional image processing unit and the display control unit may be arranged in the chip, or may be integrated in the chip as an IP module.

[0108] For other embodiments of an image display control device of the present application, reference may be made to the relevant embodiments of an image display control method of the present application.

[0109] The embodiments of the present application also provide a chip, including the image display control device as described in the embodiments of the present application.

[0110] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0111] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0112] The above embodiments are only exemplary embodiments of the present application and are not intended to limit the present application. The protection scope of the present application is defined by the claims. Those skilled in the art may make various modifications or equivalent substitutions to the present application within the essence and protection scope of the present application, and such modifications or equivalent substitutions shall also be deemed to fall within the protection scope of the present application.

Claims

1. An image display control method, characterized in that: Applicable to chips with on-chip memory, including: Using a two-dimensional image processing unit, reading an image to be displayed from an off-chip memory independent of the chip; Determine a target resolution of a display screen in the display, and when the target resolution reaches a resolution threshold, use the two-dimensional image processing unit to read a first image frame from the on-chip memory, where the first image frame corresponds to the display screen; Using the two-dimensional image processing unit to merge the image to be displayed and the first image frame to generate a second image frame; Using the two-dimensional image processing unit, writing the second image frame into the on-chip memory to replace the first image frame in the on-chip memory; The two-dimensional image processing unit is used to drive the display to display an image based on the second image frame in the on-chip memory.

2. The image display control method according to claim 1, characterized in that: Before using the two-dimensional image processing unit to read the first image frame from the on-chip memory, the method further includes at least one of the following: Reading image data corresponding to the display screen from the off-chip memory, generating the first image frame according to the image data, and writing the first image frame into the on-chip memory; A target image frame corresponding to the display picture is read from the off-chip memory, and the target image frame is written into the on-chip memory as the first image frame.

3. The image display control method according to claim 2, characterized in that: The off-chip memory includes at least one frame buffer, and reading a target image frame corresponding to the display screen from the off-chip memory includes: If the off-chip memory includes a frame buffer, reading the target image frame from the frame buffer; If the off-chip memory includes multiple frame buffers, the target image frame is read from a first target frame buffer, each of which is used to store image frames written by the two-dimensional image processing unit in a preset writing order, and the first target frame buffer is the frame buffer in which the image frame is last written among the frame buffers.

4. The image display control method according to claim 1, wherein: Using the two-dimensional image processing unit to drive the display to display an image based on the second image frame in the on-chip memory includes: Using the two-dimensional image processing unit, copying the second image frame in the on-chip memory to the off-chip memory by using a fast copy technology; The second image frame is read from the off-chip memory by using a display control unit, and the second image frame is sent to the display for display.

5. The image display control method according to claim 1, wherein: After determining the target resolution of the display screen, it also includes: When the target resolution does not reach the resolution threshold, using the two-dimensional image processing unit to read a third image frame corresponding to the display picture from the off-chip memory; Using the two-dimensional image processing unit to merge the image to be displayed and the third image frame to generate a fourth image frame; Using the two-dimensional image processing unit to write the fourth image frame into the off-chip memory; The two-dimensional image processing unit is used to drive the display to display an image based on the fourth image frame in the off-chip memory.

6. The image display control method according to claim 5, characterized in that: The off-chip memory includes at least one frame buffer, and using the two-dimensional image processing unit to write the fourth image frame into the off-chip memory includes: If the off-chip memory includes a frame buffer, using the two-dimensional image processing unit to write the fourth image frame into the frame buffer; If the off-chip memory includes multiple frame buffers, the two-dimensional image processing unit is used to write the fourth image frame into a second target frame buffer, each of the frame buffers is used to store the image frames written by the two-dimensional image processing unit in a preset writing order, and the second target frame buffer is the frame buffer in which the image frame is written first among the frame buffers.

7. The image display control method according to claim 1, characterized in that: Using the two-dimensional image processing unit to merge the image to be displayed and the first image frame to generate a second image frame includes at least one of the following: Determine a target area corresponding to the image to be displayed in the first image frame by using the two-dimensional image processing unit, update the target area based on the image to be displayed, and generate the second image frame; The two-dimensional image processing unit is used to determine a target layer corresponding to the image to be displayed in the first image frame, and the target layer is updated based on the image to be displayed to generate the second image frame.

8. An image display control device, characterized in that: Applicable to chips with on-chip memory, including: A processor, configured to determine a target resolution of a display image in the display, and compare the target resolution region with a resolution threshold; A two-dimensional image processing unit is used to read the image to be displayed from an off-chip memory independent of the chip when the target resolution reaches a resolution threshold; read a first image frame from the on-chip memory, the first image frame corresponding to the display screen; merge the image to be displayed and the first image frame to generate a second image frame; write the second image frame into the on-chip memory to replace the first image frame in the on-chip memory; and drive the display to display an image based on the second image frame in the on-chip memory.

9. The image display control device according to claim 8, wherein: The two-dimensional image processing unit is further used to copy the second image frame in the on-chip memory to the off-chip memory by using a fast copy technology, and the image display control device further includes: The display control unit is used to read the second image frame from the off-chip memory and send the second image frame to the display for display.

10. A chip, characterized in that: Includes the image display control device as described in claim 8 or 9.

Images