Region-aware memory management in memory subsystem

Abstract

The invention relates to region aware memory management in a memory subsystem. A system is disclosed that includes a memory device having a plurality of physical memory blocks and associated with a logical address space including a plurality of regions, where each region includes a plurality of logical block addresses (LBAs); and a processing device operatively coupled with the memory device to: receive a request to store data referenced by an LBA associated with a first region of the plurality of regions; obtaining a version identifier of the first area; obtaining erase values for a plurality of available physical memory blocks of the memory device; selecting a first physical memory block of the plurality of available physical memory blocks in view of the version identifier and the erase value of the first region; mapping a next available LBA within the first region to the first physical memory block; and storing the data in the first physical memory block.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with application date of June 18, 2021, application number 202110676084.0, and invention name “Region-aware memory management in memory subsystem”. Technical Field

[0003] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to locality-aware memory management in memory subsystems. Background Art

[0004] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0005] One aspect of the present application relates to a system comprising: a memory device comprising multiple physical memory blocks and associated with a logical address space comprising multiple regions, each region comprising multiple logical block addresses (LBAs); and a processing device operatively coupled to the memory device to perform operations comprising: receiving a request to store data referenced by an LBA associated with a first region among the multiple regions; obtaining a version identifier for the first region; obtaining erase values ​​for multiple available physical memory blocks of the memory device, each erase value representing the number of completed erase operations for a corresponding one of the multiple memory blocks; selecting a first physical memory block among multiple available physical memory blocks in view of the version identifier and the erase value of the first region; mapping a next available LBA associated with the first region to the first physical memory block; and storing the data in the first physical memory block.

[0006] Another aspect of the present application relates to a system comprising: a memory device comprising a plurality of physical memory blocks and associated with a logical address space comprising a plurality of regions, wherein each region comprises a plurality of logical block addresses (LBAs), and a processing device operatively coupled to the memory device to perform operations comprising: initiating a scan of the memory device; identifying a first region among the plurality of regions as a region having a lowest version identifier, wherein the version identifier of a region reflects a number of invalidation times for the region; starting from a first LBA of the first region, performing an error correction analysis to detect risky physical memory blocks of consecutive LBAs mapped to the first region; and determining whether to stop the scan of the memory device at the first region in view of the detected risky physical memory blocks of the LBAs mapped to the first region.

[0007] Another aspect of the present application relates to a method, which includes: receiving, by a processing device operatively coupled to a memory device, a request to store data referenced by a logical block address (LBA) associated with a first region among a plurality of regions, wherein each region includes a plurality of logical block addresses (LBAs) of a logical address space of the memory device, and the memory device has a plurality of physical memory blocks; obtaining, by the processing device, a version identifier of the first region; obtaining, by the processing device, erase values ​​of a plurality of available physical memory blocks of the memory device, wherein each erase value represents the number of completed erase operations of a corresponding one of the plurality of available memory blocks; selecting, by the processing device, a first physical memory block among the plurality of available physical memory blocks in view of the version identifier and the erase value of the first region; mapping, by the processing device, a next available LBA associated with the first region to the first physical memory block; and storing, by the processing device, the data in the first physical memory block. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0010] Figure 2A-2B A high-level description of locality-aware memory management in a memory subsystem is schematically shown.

[0011] Figure 3 The diagram schematically illustrates region-block matching in region-aware memory management according to some embodiments of the present disclosure.

[0012] Figure 4The diagram schematically illustrates distribution-based region-block matching in region-aware memory management according to some embodiments of the present disclosure.

[0013] Figure 5 A flow chart illustrating an example method of locality-aware memory management of a memory device according to some embodiments of the present disclosure.

[0014] Fig. 6A A flow chart illustrating an example method of performing region-aware background scanning in a memory device according to some embodiments of the present disclosure.

[0015] Figure 6B According to some embodiments of the present disclosure Fig. 6A A flow chart of one possible embodiment of the method is shown.

[0016] Figure 6C An example region-aware background scan performed according to some embodiments of the present disclosure is schematically illustrated.

[0017] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0018] Various aspects of the present disclosure relate to region-aware memory management using version numbers of memory regions in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system can utilize a memory subsystem that includes one or more memory components (e.g., memory devices) that store data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0019] The memory device may be a non-volatile memory device that can store data from a host system. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. Each of the memory devices may include one or more memory cell arrays. A memory cell ("cell") is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states related to the number of bits stored. The logical states may be represented by binary values ​​(e.g., "0" and "1") or combinations of such values.

[0020] Each access operation can be performed on a memory cell. Data can be written to, read from, and erased from a memory cell. Memory cells can be grouped into write units, such as pages. For some types of memory devices, a page is the smallest write unit. A page is a group of cells across the same word line. The page size represents the number of specific cells in a page. For some types of memory devices (e.g., NAND), memory cells can be grouped into erase units, such as physical blocks, which are a group of pages. A physical block is a 2-dimensional memory array of pages (cell rows) and strings (cell columns). Data can be written to blocks page by page. Data can be erased at the block level. However, parts of a block cannot be erased.

[0021] Pages in a block may contain valid data, invalid data, or no data. Invalid data is data that is marked as outdated because a new version of the data is stored on the memory device. Invalid data includes data that was previously written but is no longer associated with a valid logical address (e.g., a logical address referenced by the host system in a physical to logical (P2L) mapping table). Valid data is the latest version of such data stored on the memory device. The memory subsystem may mark data as invalid based on information received from the operating system, for example. Pages that do not contain data include pages that have been previously erased and have not yet been written.

[0022] The memory subsystem controller may perform operations for media management algorithms, such as wear leveling, refresh, garbage collection, scrubbing, etc., to help manage data on the memory subsystem. A block may have some pages with valid data and some pages with invalid data. To avoid waiting for all pages in a block to have invalid data in order to erase and reuse the block, an algorithm referred to below as "garbage collection" may be invoked so that the block can be erased and freed as a free block for subsequent write operations. Garbage collection is a set of media management operations that includes, for example, selecting blocks with valid and invalid data, selecting pages in a block with valid data, copying valid data to a new location (e.g., a free page in another block), marking data in previously selected pages as invalid, and erasing selected blocks.

[0023] Hereinafter, "garbage collection" refers to selecting a block, rewriting valid data from the selected block to another block, and erasing all invalid data and valid data stored at the selected block. Valid data from multiple selected blocks can be copied to a smaller number of other blocks, and then the selected block can be erased. Therefore, the number of blocks that have been erased can be increased, so that more blocks can be used to store subsequent data from the host system. However, effective memory management may be complicated by the following intrinsic memory subsystem design limitations: Typical transistor-based memory cells will wear out after a certain number of erase operations (from a few thousand times in a three-level cell to tens of thousands of times or more in a single-level cell), at which time the ability of the floating gate to continue to hold a charge will be significantly reduced.

[0024] Some memory management schemes may deploy zoned namespaces (ZNS), also referred to herein as "zones." A zone is a partition of the logical address space of a memory device that is configured in such a way that the logical block addresses (LBAs) of each zone are used sequentially starting from the low-end LBA in write operations. The LBA range belonging to a particular zone can be dedicated to a specific host application, and individual applications can only access zones dedicated to those applications. Because the LBAs of each zone are written sequentially, rewriting data already stored in a zone requires invalidating the entire zone (by, for example, moving the write pointer to the starting LBA of the zone). Using a zoned namespace allows for more efficient (faster) read, write, and erase operations, and reduces the need to over-provision memory blocks to various applications (by reducing the number of blocks that would otherwise store invalid data and must be taken into account when allocating memory to applications).

[0025] However, the ZNS architecture does not completely eliminate the need for efficient memory management. For example, different applications may store (and update) data at different rates. Therefore, some areas may only be overwritten a few times, while other areas are overwritten more frequently. If the LBA to physical memory block mapping remains static, it may cause significant differences in erase counts between physical memory blocks used by different applications. For example, an area used to store a relatively static database may be rarely overwritten, while an area used to store temporary calculation data or a short-term cache may be overwritten at a much higher rate.

[0026] Aspects of the present disclosure address the above and other deficiencies by describing region-aware memory management in a memory subsystem. In some embodiments, a memory controller of a memory subsystem may track the number of times a region is overwritten - the version number (VN) of the region - and the number of times individual physical blocks are erased. In some embodiments, when an application (e.g., running on a host system) requests to store data in association with a particular region, the application may specify an identifier of the region, which may be the starting (lowest) LBA of the region or any other pointer that specifies the region. In response to receiving the identifier, the memory controller may determine the VN of the region, and further obtain the erase counts (EC) of available physical memory blocks, which may be identified by their corresponding physical block addresses (PBAs). The memory controller may select blocks based on the VN of the region, such that a "cold" region with a low VN (indicating a low probability that the region will become invalid in the future) is associated with a high EC "hot" physical memory block (i.e., a block with fewer erase operations remaining in its life cycle than the average block of the memory subsystem). Conversely, the memory controller may associate "cold" physical memory blocks (blocks with low EC) with "hot" regions with high VNs (indicating a high probability that the region will often become invalid in the future). After selecting the appropriate physical block, the memory controller may match the next available LBA of the region with the PBA of the selected block, write the data to the selected block, and store the LBA-PBA association (e.g., in a memory lookup table) for subsequent read and erase operations that may be directed to the LBA by an application.

[0027] In some embodiments, a memory controller (or local media controller) may perform (e.g., during idle time or periodically) a background scan of the physical memory blocks of the memory subsystem to determine whether data in some blocks is at risk of corruption. For example, data that has been stored in a particular block for a long time may be damaged due to physical (electrostatic) interference from other (e.g., physically adjacent) blocks that are subjected to various read, write, and / or erase operations. The background scan may perform error correction code (ECC) analysis of at least some blocks and schedule those blocks whose bit error rate (BER) exceeds a certain threshold for folding, which refers to refreshing the data stored therein by moving the data to other blocks. In region-aware memory management, the background scan may only take a portion of the time required to check all blocks of the memory subsystem. More specifically, because a low VN indicates a long storage time (in the absence of erasure) of data stored in association with a region (and the LBA of the region), the background scan may start from the lowest VN region, because the physical memory blocks of such regions (which are overwritten the least number of times) are more likely to be at risk of data loss.

[0028] Furthermore, because high EC blocks are used to store data in (i.e., associated with) low VN regions as described above, such high EC blocks may be closer to their resource limits and, thus, have a higher risk of damage. Therefore, once the ECC operation determines that the blocks of a particular region (e.g., the region with the Nth low VN) are within a low-risk BER range, the background scan may stop. Additionally, because within each region, data is stored in (i.e., associated with) sequential LBAs, it is sufficient to scan only the physical memory blocks associated with the lower LBAs of each region, since these blocks have stored data for the longest time and therefore have the highest risk of damage. Once the ECC operation determines that a particular number of (e.g., consecutive) physical blocks of a region are within a low-risk BER range, the background scan of the particular region may stop (and the next region may be scanned if necessary). Therefore, only a small portion of the physical blocks associated with each region and a limited number of regions may need to be scanned.

[0029] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0030] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0032] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including electrical, optical, magnetic, etc.

[0033] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0034] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), and the like. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130) when the memory subsystem 110 is coupled to the host system 120 via a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. As an example, Figure 1 Memory subsystem 110 is shown. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. Non-volatile memory cross-point arrays can perform bit storage based on changes in body resistance in conjunction with stackable cross-grid data access arrays. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed if they have been previously erased. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of, for example, SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. In some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0038] Although non-volatile memory components such as a 3D cross-point non-volatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 (or, for simplicity, controller 115) may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses LBA, partition namespaces) and physical addresses (e.g., physical block addresses PBA) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0044] In some embodiments, the memory device 130 includes a local media controller 135 that is used in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0045] The memory subsystem 110 includes a zone-aware memory management component (ZMC) 113, which can access the version number (VN) of a particular zone in response to receiving a request to store data in the zone, obtain the EC of at least a subset of available physical memory blocks (e.g., blocks that currently do not store data or store invalid data), and select the PBA of the best block to store the data. The best block to store the data may be a block whose EC is negatively correlated with the zone VN, as described below with reference to Figure 3Described in more detail, thereby ensuring uniform wear across memory devices 130 and / or 140. ZMC 113 may further perform region-aware background scans of one or more memory devices 130, 140 by scanning regions in order of version numbers and by scanning physical blocks associated with the LBAs of each region starting with the lowest LBA (earliest written PBA). In some embodiments, ZMC 113 may stop scanning blocks within a given region once a first condition is met. For example, ZMC 113 may determine that a predetermined number of blocks (e.g., consecutive blocks) within the scanned region have a BER below a "risk" threshold. In some embodiments, ZMC 113 may similarly stop scanning a region when a second condition is met. For example, ZMC 113 may determine that the number of risk blocks in one or more regions does not exceed a second predetermined number of blocks. However, different first and second conditions may be used in various other embodiments, such as reference Figures 6A to 6C Explain in more detail. During operation of the memory subsystem 110, the VNs of various regions of the memory subsystem 110 may be stored in one of the memory devices 130 and / or 140, or in a separate data structure accessible to the memory controller 115 (or the local media controller 135). The memory device or separate data structure may be a volatile memory structure (e.g., DRAM). In some embodiments, when the memory subsystem 110 is powered on and the memory controller 115 (and / or the local media controller 135) is initialized, the VN may be extracted from a non-volatile memory (e.g., NAND memory) to the volatile memory structure. When a region is invalid, the VN of the region may be updated in the volatile memory structure and copied to the non-volatile memory so that the VN is maintained in the event of an unexpected power outage.

[0046] In some embodiments, ZMC 113 may perform background scans during idle time of the memory subsystem, such as when the number of write, erase and / or read requests per unit time falls below a certain set threshold. In some embodiments, ZMC 113 may perform background scans in response to the number (e.g., percentage) of the latest failed read or write operations. In some embodiments, ZMC 113 may perform background scans at fixed time intervals from the start (or end) time of an earlier scan. In some embodiments, ZMC 113 may perform background scans at specific times - hourly, daily, or every other time unit - as configured by memory subsystem 110 and / or host system 120 or a human operator (e.g., a production engineer or system administrator). In some embodiments, the monitoring schedule for the background scans may be stored in local memory 119 (e.g., embedded memory).

[0047] In some embodiments, the memory subsystem controller 115 includes at least a portion of the ZMC 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 to perform the operations described herein. In some embodiments, the ZMC 113 is part of the host system 120, application, or operating system. In some embodiments, the ZMC 113 may have configuration data, libraries, and other information stored in the memory device 130 (and / or the memory device 140).

[0048] Figure 2A-2B A high-level description of locality-aware memory management in a memory subsystem is schematically shown. Figure 2A One embodiment 200 of memory management is depicted. Figure 2B Another embodiment of memory management is depicted 202. Figure 2A As shown in , the host system 120 (e.g., its operating system or any application executing on the host system 120) may transmit a read, write, or erase request to the memory subsystem 110. The request may include an LBA 210 within the logical space of the memory subsystem 110 or within a portion of the logical space accessible to the request initiator. The LBA 210 may be used by the memory subsystem controller 115 to identify the physical memory partition (block, page, plane, etc.) associated with the received memory request. For example, the memory subsystem controller 115 may access the memory lookup table 212 to determine the PBA 216 corresponding to the LBA 210. The controller 115 may then execute the received memory request using the corresponding block identified by the determined PBA 216. For example, the controller 115 may read the data stored in the corresponding block (and provide the data to the processing device of the host system 120) or write the data to the corresponding block. In some cases, when data in a block is to be overwritten or if no block is currently assigned to LBA 210, controller 115 may first perform a dynamic garbage collection (GC) routine (214). For example, controller 115 may identify an appropriate block (via its PBA 216), which may be a block with a minimum number of erase counts, or more generally, a block that has been erased less than the average block in the memory device. Upon such identification, controller 115 may write the new data to the identified block. Controller 115 may also update memory lookup table 212 (as indicated by dashed lines connecting boxes 214 and 212) with the new memory translation LBA→PBA. In the event that the memory request is an overwrite request, controller 115 may also invalidate data already stored in the old block (previously identified by LBA 210) and update memory lookup table 212 with the new memory translation LBA→PBA.

[0049] After executing a memory request, for example, during downtime or scheduled GC time, the controller 115 may perform a static GC 218 and / or background scan 220. During the static GC 218, "cold" data that has only been overwritten a small number of times (e.g., less than the average block of the memory device) may be identified and moved to a block that has a higher than average erase count (EC) and is therefore closer to the end of its resource limit than other blocks. During the background scan 220, the memory subsystem controller 115 may identify blocks that have a higher risk of having too many bits damaged so that the error correction code (ECC) may eventually be unable to repair the data stored thereon. Such blocks may be folded (copied to a new location where the old location is erased or invalid, i.e., scheduled for erasure) to other blocks, such as blocks with lower ECs. After completing the static GC 218 and / or background scan 220 (or in some embodiments, during execution), the controller 115 may update the memory lookup table 212 with the new memory translation LBA→PBA (as indicated by the corresponding dotted line). In some embodiments, the dynamic GC 214 may include region-block matching 232, and the background scan 220 may include region-aware background scan 236, as described below with reference to Figure 2B Describe in more detail.

[0050] like Figure 2B As shown in FIG. 1 , according to some embodiments of the present disclosure, the host system 120 may generate a region write request 230 and transmit the request to the memory subsystem 110. Because write requests in the partition namespace architecture are performed using sequential LBAs assigned to the corresponding regions, the request 230 may identify the region but need not specify the LBA. The controller 115 may perform region-block matching 232, as described below with reference to FIG. Figure 3 Described in more detail. During region-block matching 232, the controller may identify physical memory blocks that will be used to store data referenced in write request 230 to obtain optimal performance of the memory device (e.g., to maximize its life and long-term capabilities). For example, it is expected that regions that were rarely invalid in the past are likely to retain data for a long time in the future without the data being overwritten, and the controller 115 may match regions with low version numbers (VNs) with blocks with high ECs. Conversely, the controller 115 may match regions with high VNs (expected to be often invalid in the future) with blocks with low ECs. The memory subsystem controller 115 may then update the memory lookup table 212 with an LBA→PBA conversion, where the LBA is the next available logical address of the region, and the PBA (234) is the physical address of the block identified during region-block matching 232 and used to perform the write request.

[0051] During downtime or scheduled GC time, the controller 115 may perform a region-aware background scan 236. Specifically, the memory subsystem controller 115 may identify blocks with a higher risk of data loss (e.g., blocks with too many bits damaged to be repaired via ECC operations). Such blocks may be folded into other blocks, such as blocks with lower ECs. The region-aware background scan 220 may start from the region with the lowest VN. Such regions are assigned physical memory blocks that have not been erased for the longest time and therefore have the highest risk of data loss. Within each region, the blocks with the highest risk of data loss are those associated with LBAs near the beginning of the region (because these blocks have not been overwritten / erased for the longest time among the blocks assigned to the region). Therefore, the controller 115 may start the block test from the beginning of the region LBA and stop the background scan of the particular region after a specific (e.g., predetermined) number of blocks successfully pass the block test criteria. Similarly, the controller 115 may test different regions in ascending order of VN and stop the background scan of the memory device after a predetermined number of regions successfully pass the region test criteria. Blocks identified as "risk" blocks may be folded into other blocks using a procedure similar to the region-block matching 232 described above. During the region-aware background scan 236 (or after the scan is completed), the controller 115 may update the memory lookup table 212 (as indicated by the dashed line) by replacing the folded block PBA with the new block PBA in the stored LBA→PBA translation.

[0052] Figure 3 Schematically illustrates region-block matching 300 in region-aware memory management according to some embodiments of the present disclosure. A schematic depiction of a set of regions 310 of a memory device sorted in ascending order of their VNs (from top to bottom) is shown on the left. Each region is denoted as "region (VN)", where VN1 is the current lowest VM among the regions of the memory device, and VN M is the current highest VM. There may be any number of regions with a given VN, as depicted, with multiple regions associated with some VNs (e.g., as depicted, there are three regions with VN33 and two regions with VN M As shown in the gray (indicating the filling of the region) schematic, region 310 can be written to consecutively, for example, from lower (high-level) LBAs to higher (low-level) LBAs. When the region is completely filled, any subsequent write operations associated with the region require the entire region to be invalidated. Similarly, once the entire region has become invalid, write or erase operations performed in association with LBAs belonging to the gray (written) portion of the region can be performed.

[0053] Figure 3A schematic depiction of a set of physical memory blocks 320 available for region 310 is shown on the right. Blocks 320 are sorted in ascending order of their EC (from bottom to top). Each block is denoted as "Block (EC)", where EC1 is the current lowest EC among the available blocks of the memory device, and EC N is the current highest EC. There may be any number of blocks, each with a particular EC, as depicted, where multiple blocks are associated with some erase counts (eg, as depicted, there are four blocks with EC5 and three blocks with EC1).

[0054] In some embodiments, the memory subsystem controller 115 performs region-block matching, with the ultimate goal of ensuring that the distribution of the physical memory blocks of the memory subsystem in their erase counts is as narrow as possible. For example, region-block matching may be performed so that the difference between the maximum erase count and the minimum erase count among the blocks of the memory subsystem (or a portion of the memory subsystem) is within a target count gap (which may be set by the memory controller or host system). In an ideal situation, all memory blocks will have the same EC, thereby ensuring uniform wear of the memory device. Therefore, region-block matching 300 may be performed so that the highest EC block is provided to execute write requests associated with the region with the lowest VN. Similarly, the lowest EC block is provided to execute write requests associated with the region with the highest VN. For example, in one embodiment, once the controller 115 determines that the region has the lowest VN (e.g., region (VN1)), the controller 115 may select the highest EC block (e.g., block (EC N-1 )) and uses the selected block to execute the write request directed to the lowest VN. Conversely, once the controller 115 determines that the region has the highest VN (e.g., region (VN M )), the controller 115 may select the lowest EC block (eg, block (EC1)) and use the selected block to execute the write request directed to the highest VN region.

[0055] In some embodiments, blocks can be grouped into groups, where each group contains blocks with similar (but not necessarily equal) ECs. For example, a group can contain blocks such that the difference between the maximum erase count and the minimum erase count among the blocks in the group is within a target range (which can be set by the memory controller or host system). For example, if Figure 3 As depicted in FIG. 1 , blocks with EC1 and EC2 may be included in Group 1, blocks with EC3 and EC4 may be included in Group 2, and blocks with EC N-1 and EC NThe blocks of group P(EC) can be included in group p, and so on. The controller 115 can use groups to speed up block matching. For example, because the blocks within each group have similar ECs, the controller 115 no longer needs to determine the distribution of available blocks on EC each time a write request is received, but can select a block in the corresponding block group (for example, a random block or the next block in the queue). The controller 115 can periodically (or at idle time, or both) determine the current distribution of blocks P(EC) on erase counts and reclassify the currently available blocks into groups. Similarly, the controller 115 can group regions into categories ( Figure 3 ). To speed up region-block matching, the controller 115 may periodically (or at idle time, or both) determine the current distribution of regions P(VN) in version numbers and reclassify the current regions into different categories. In some embodiments, the number of region categories may be equal to the number of block groups. Once the regions and groups are determined, the controller 115 may select blocks from block group j to match the selected blocks and write requests associated with regions belonging to region category j. Blocks in a given group may be selected by various algorithms. For example, in one embodiment, blocks may be randomly selected from a group. In some embodiments, blocks may be selected in the order of the ECs of the remaining blocks in the group (e.g., starting with the lowest or highest EC).

[0056] Figure 4 The diagram schematically illustrates distribution-based region-block matching 400 in region-aware memory management according to some embodiments of the present disclosure. Figure 4 An exemplary distribution P(EC) of physical memory blocks over their erase counts is depicted in the middle (top). The distribution P(EC) is dynamic (time-dependent) and gradually shifts to the right (towards higher EC) during the lifetime of the memory device. Figure 4 The depiction shown in should be understood as a snapshot in time of the distribution of blocks on the EC at some point during utilization of the memory device. Figure 4 An exemplary distribution of zones over their version numbers, P(VN), is depicted in the middle (bottom). The distribution, P(VN), is also dynamic and gradually shifts to the left (towards higher VNs) during the life of the memory device (at least until a zone reset occurs, when the controller 115 or host system 120 resets the zone allocations to the various applications supported by the memory device). Figure 4 The depiction shown in should be understood as a time snapshot of the distribution of regions on VN. The controller 115 may monitor the distribution P(EC) and P(VN) at periodic time intervals (e.g., quasi-continuously) or during downtime or upon receiving a write request or after a predetermined number of write requests have been received since the last distribution monitoring.

[0057] The distributions P(EC) and P(VN) can be separated into groups and categories, which are Figure 4 Indicated by numbers in the figure. In some embodiments, block groups may be padded to ensure that there is an equal or comparable number of blocks within each block group. Similarly, region categories may be padded to ensure that there is an equal or comparable number of regions within each region category. For example, in one non-limiting embodiment, the groups and categories are based on corresponding percentiles of the two distributions. More specifically, block group 1 may include blocks with EC within the last 20% of all available blocks, group 2 may include blocks with EC above the last 20% but below the last 40% of all available blocks, group 3 may include blocks with EC above the last 40% but below the first 40% of all available blocks, group 4 may include blocks with EC above the first 40% but below the first 20% of all available blocks, and group 5 may include blocks with EC within the first 20% of all available blocks. In some embodiments, "available" blocks do not include blocks that have been erased more than a certain number of times, such as blocks belonging to the "tail" of P(EC). Such blocks may be discarded (e.g., Figure 4 ) and are excluded by region-block matching. Region categories can be filled in the same way, where the boundaries between categories ( Figure 4 The dashed lines in the figure are set at the same percentage.

[0058] In some embodiments, the controller 115 may populate the block groups and region categories according to different schemes. For example, the groups and categories may be populated based on the standard deviation σ of the corresponding distributions. For example, if there are three groups for region-block matching, then Group 2 may include blocks whose EC is within ±0.5σ (±0.6σ, ±0.7σ, etc.) of the mean (or median, modulus, etc.) of the P(EC) distribution, Group 1 may include blocks (regions) whose EC is lower than -0.5σ (-0.6σ, -0.7σ, etc.), and Group 3 may include blocks (regions) whose EC is higher than +0.5σ (+0.6σ, +0.7σ, etc.). In some embodiments, the boundaries of the region categories may reflect the boundaries of the block groups. Specifically, in the previous example, category 1 may include areas where VN is higher than the mean (or median, modulus, etc.) of the regional distribution P(VN) by +0.5σ (+0.6σ, +0.7σ, etc.), while category 3 may include areas where VN is lower than -0.5σ (-0.6σ, -0.7σ, etc.). However, in other embodiments, the boundaries of the regional categories may be set differently from the boundaries of the corresponding block groups. For example, block group 2 may include blocks within the range of ±0.5σ, while the corresponding regional category 2 may include areas within the range of ±0.8σ.

[0059] In some embodiments, filling block groups and region categories may be performed according to different schemes. For example, block groups may be set using percentage points, while region categories may be set with reference to standard deviations (or any other parameter of the corresponding distributions), or vice versa. One skilled in the art will recognize that there are an almost infinite number of possibilities for associating several intervals (ranges) of the distribution P(EC) of available blocks with intervals (ranges) of the distribution P(VN) of existing regions, thereby achieving the goal of keeping the two distributions as narrow as possible during operation of the memory device.

[0060] Figure 5 6 respectively show method 500 and method 600. Methods 500 and 600 can be performed by processing logic, and the processing logic can include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, hardware of device, integrated circuit, etc.), software (e.g., instructions running or executing on processing device) or a combination thereof. Although shown in a specific order, unless otherwise specified, the order of operations can be modified. Therefore, the illustrated embodiments should be understood as just examples, and the illustrated operations can be performed in different orders, some of which can be performed in parallel. In addition, in various embodiments, one or more operations can be omitted. Therefore, not all operations of methods 500 and 600 are required in each embodiment. Other operation flows are possible. In some embodiments, different operations can be used. It can be noted that various aspects of the present disclosure can be used for any type of multi-bit memory cell.

[0061] Figure 5 A flow chart showing an example method 500 for locality-aware memory management of a memory device according to some embodiments of the present disclosure. In one embodiment, the controller 115 of the memory subsystem (more specifically, the ZMC 113 of the controller 115) may execute the example method 500 based on instructions stored in an embedded memory of the local memory 119. In some embodiments, firmware of the memory subsystem 110 (or memory device 130) may execute the example method 500. In some embodiments, an external processing device (e.g., a processing device of the host system 120) may execute the example method 500.

[0062] Method 500 may be implemented in a memory device including several physical memory blocks. The memory device may have a logical address space (e.g., a partition namespace) including multiple regions, each region having a continuous logical block address (LBA). Method 500 may involve receiving a request to store data (operation 510). The request may reference an LBA to which data will be stored in association. The LBA may belong to, for example, a first region of a memory device having multiple regions. (The terms "first", "second", etc. used in this specification should not be understood as always describing the actual order of corresponding entities (e.g., regions, blocks, categories, groups, etc.). Although such an order may be explicitly used or implied in some cases, in other cases, the terms "first", "second", etc. refer to arbitrarily selected entities, which do not have to be ordered in any way.) Each or some regions may be assigned to various applications being executed by a host system. A region may be configured to require that all LBAs of the region must be invalid if some information referenced by an LBA belonging to the region is to be overwritten. At operation 520, a processing device executing method 500 may obtain a version identifier (VI) of the first region. The VI of the region may depend on the number of invalidations of the region. For example, the VI of a region may be equal to the number of invalidation times of the region, or may be a function of the number of invalidation times N of the region, such as VI=f(N). In some embodiments, the function may be an increasing or decreasing function of the number of invalidation times of the region. For example, the first region may be the region with the lowest VI among the regions of the memory device (or a subset of the regions of the memory device). In some embodiments, where the function f(N) is a decreasing function of the number N, the first region may be the region with the highest VI among the regions of the memory device (or a subset of the regions). In some embodiments, f(N)=N, and the VI of the region is equal to the version number VN, as described above. In some embodiments, the version identifier may be a non-numerical representation of the version number (e.g., a letter or other symbolic mark).

[0063] At operation 530, the processing device executing method 500 may obtain the erase value of the available physical memory block of the memory device. The erase value may depend on the number of erases of the corresponding block (the number of erase counts completed). In some embodiments, the erase value may be the same as the erase count. In some embodiments, the erase value may be a numerical value, such as a mathematical function of the erase count. In some embodiments, the erase value may be a non-numerical representation of the erase count (e.g., a letter or other symbol mark). For example, the available block may be a block that currently does not store any information, a block that stores information that is already invalid, an erased block, etc. Some blocks of the memory device may be reserved for use by the memory controller 115 or the host system 120 (or any application running thereon), etc., and therefore may not be included in the multiple available blocks. At operation 540, method 500 may continue to select the first physical memory block in view of the first region version identifier and the erase value of the available block. In some embodiments, the first physical memory block has the highest erase value among the qualified subset of the available physical memory blocks. For example, the qualified subset may include a block whose erase value does not exceed the threshold erase value. In one embodiment, blocks having an erase value greater than (or equal to) a threshold erase value may be discarded and no longer used to store new information and may be excluded from the pool of available blocks.

[0064] In some embodiments, to select a first physical memory block, the processing device may obtain a distribution P(VN) of version identifiers of regions (a first distribution), and may further obtain a distribution P(EC) of erase values ​​or counts of available physical memory blocks (or qualified available blocks) (a second distribution). The processing device may then select the first physical memory block based on the first distribution and the second distribution. For example, in one embodiment, the processing device may identify a specified number of intervals of the first distribution and the specified number of intervals of the second distribution. The intervals may correspond to region categories and block groups, as described above with respect to Figure 3 and 4 The intervals may be identified based on a predetermined scheme for grouping regions and blocks, such as intervals corresponding to predetermined percentiles, intervals associated with standard deviations (or other parameters of a distribution), and the like. In some embodiments, the selection of the physical memory block may be performed by a negative correlation with the region version identifier and the block erase value. Specifically, the processing device may determine that the region version identifier belongs to the jth low version identifier interval of the first distribution, and select the first physical memory block from the jth high erase value interval of the second distribution.

[0065] In one illustrative, non-limiting example, once it is determined that the first region has the lowest number of failure operations among the regions (e.g., the lowest version identifier), the processing device may select the first physical memory block from the block with the highest erase value among the available blocks. In another illustrative, non-limiting example, once the processing device determines that the first region is not the region with the lowest number of failure operations among the regions (e.g., has a version identifier different from the lowest version identifier), the processing device may select the first physical memory block from the block with the lowest erase value among the available blocks.

[0066] At operation 550 , the processing device executing method 500 may map the next available LBA of the first area to the selected first physical memory block, and may store data in the first physical memory block at operation 560 .

[0067] Fig. 6A A flow chart showing an example method 600 for performing region-aware background scanning in a memory device according to some embodiments of the present disclosure is shown. In one embodiment, the controller 115 of the memory subsystem (more specifically, the ZMC 113 of the controller 115) may perform the example method 600 based on instructions stored in an embedded memory of the local memory 119. In some embodiments, firmware of the memory subsystem 110 (or memory device 130) may perform the example method 600. In some embodiments, an external processing device (e.g., a processing device of the host system 120) may perform the example method 600. Figure 6B is a flow chart of one possible embodiment 601 of a method 600 according to some embodiments of the present disclosure.

[0068] Method 600 may involve initiating a scan of the memory device (operation 610). In some embodiments, the scan may be initiated at regular time intervals, initiated during idle time, or initiated in response to the failure of a memory operation (e.g., a read or write operation or a particular number of such operations). In some embodiments, the scan may be initiated by the controller 115 based on instructions stored in the local memory 119 or based on instructions received from the host system 120. In some embodiments, the scan may be initiated and performed by the host system 120. At operation 620, the processing device executing method 600 may identify a first region as having the lowest version identifier among the regions of the memory device. In some embodiments, the physical memory blocks mapping the LBAs of the first region have the same first erase value. In some embodiments, in addition to identifying the first region, the processing device may also at least identify multiple regions in the memory device that must be scanned. The identified regions may be sorted according to their version identifiers. As indicated by Figure 6BAs indicated by block 620-1 in , in some embodiments, the processing device may set a region counter, starting with the region having the lowest version identifier (eg, the first region).

[0069] At operation 630, the method 600 may continue with the processing device performing an error correction code (ECC) analysis to detect risky physical memory blocks mapped to consecutive LBAs of the first region. Figure 6B In some embodiments, the processing device may set a block counter, start from the beginning of the region (i.e., from the block storing the oldest data), and scan consecutive blocks (step 630-2, as shown in FIG. Figure 6B ). For example, a processing device executing method 600 may select (e.g., randomly or according to a predetermined pattern) some pages in the current block and determine a bit error rate (BER) of the current block. If it is determined at decision step 630-3 that the BER of the current block is above a certain predetermined BER threshold, then the current block may be "folded." That is, data from the current block may be moved to an available physical memory block (which may be associated with the next available LBA of the region), and the current block may be marked as an invalid block.

[0070] In some embodiments, all blocks currently storing data may be scanned within the tested area (e.g., the first area). In other embodiments, a limited number of blocks may be tested, and the area scan may be stopped when a predetermined first condition is satisfied. For example, if it is determined (step 630-5, such as Figure 6B If the BER of n of the m physical memory blocks associated with the last m LBAs (as shown in ) is below the BER threshold, scanning of the current region may be stopped. Because in region-aware memory management, consecutive LBAs are used for write operations in chronological order, the untested LBAs are associated with data that is stored for a shorter time (shorter than the tested LBA) and are unlikely to be mapped to risk physical memory blocks. However, if the processing device determines that scanning of the current region is to continue, the processing device may increment the block counter (operation 630-6, as shown in ). Figure 6B ) and repeats loop 630-2-630-5 for the memory block mapped to the next LBA of the region.

[0071] Once the scanning of the first region is complete (all blocks have been tested) or stopped (a sufficient number of blocks in the region are found to be not at risk), the method 600 may continue at operation 640 to determine whether scanning of the memory device is to be stopped at the first region (conditional on some predetermined second condition being met) or whether the second region must be similarly scanned. In some embodiments, to stop scanning at the first (or any subsequent) region, the processing device needs to determine that the first (or any subsequent) region has no more than a certain predetermined p risk blocks, or no more than a certain predetermined percentage of risk blocks, or a certain number of blocks that are not at risk, or any other criteria in an almost infinite number of possibilities. In some embodiments, untested blocks of the region (if scanning of the region is stopped before all LBAs of the region have been tested) may be assumed to be not at risk. In some embodiments, some of the untested blocks may be assumed to be at risk in the same proportion as in the last m tested blocks of the region, or in the same proportion as in all tested blocks of the region, and so on. In some embodiments, more than one region must satisfy one of the aforementioned (or other) conditions.

[0072] If it is determined that the scanning of the memory device is to be stopped at the first region (the result of decision block 640-1 is "yes", such as Figure 6B ), the processing device may stop scanning. However, if it is determined that scanning of the memory device is not to be stopped at the first (or any subsequent) region, the method 600 may continue to identify a second (or any subsequent) region as having a second (or any subsequent) lower version identifier among the plurality of regions (operation 650). In some embodiments, the physical memory blocks of the LBAs mapped to the second region have the same second erase value, which is higher than (or at least equal to) the first erase value. Therefore, in one embodiment, the processing device may increment the region counter (block 650-1, as shown in FIG. 650-1). Figure 6B ) and repeat loop 630-1-640-1 for the second (or any subsequent) region. Specifically, at operation 660, the processing device may perform error correction analysis (starting at the first LBA of the second region) to detect risk physical memory blocks mapped to consecutive LBAs of the second region, and determine whether to stop scanning of the memory device at the second region in view of the detected risk physical memory blocks of the LBAs mapped to the second region at operation 670. The method 600 may continue until: 1) all regions are scanned, or 2) scanning is stopped after determining (e.g., at operation 640-1) that there are no more regions to test.

[0073] Figure 6CAn example region-aware background scan 602 performed in accordance with some embodiments of the present disclosure is schematically illustrated. The first six regions, sorted in ascending order by version identifier, are schematically depicted, each region having seven LBAs mapped to its corresponding physical memory blocks. The background scan is performed in the direction indicated by the arrows. Blocks with a BER above (or equal to) a threshold are marked as "failed", while blocks with a BER below the threshold are marked as "passed". Figure 6C In the illustrative example of , scanning of a given region stops once three of the last four blocks receive a "pass" label (the first condition). Untested blocks are indicated by shading. Figure 6C In the illustrative example of , if more than two-thirds of the blocks associated with each of the last two regions receive a "pass" tag (the second condition), where the untested blocks are assumed to have received a "pass" tag, then scanning of the memory device stops. Figure 6C , all blocks of the first and second regions are scanned, but the scan of the third region stops after testing the first six blocks (the third region satisfies the first condition). The scan of the fourth region stops after testing only three blocks, at which point the scan of the memory device stops (the fourth region satisfies the first condition). No other regions are tested because more than two-thirds (5 out of 7) of the blocks associated with the third region and more than two-thirds (7 out of 7) of the blocks associated with the fourth region receive a "pass" label (satisfying the second condition).

[0074] Figure 7 An example machine of a computer system 700 is shown, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or can be used to perform operations of the controller (for example, to execute an operating system to execute a corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0075] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0076] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0077] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 702 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 that communicates via a network 720.

[0078] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a non-transitory computer-readable storage medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methods or functions described herein. The instructions 726 may also reside completely or at least partially within the main memory 704 and / or within the processing device 702 during execution by the computer system 700, the main memory 704, and the processing device 702, which also constitute the machine-readable storage medium. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0079] In one embodiment, instruction 726 includes implementing a corresponding Figure 1The functional instructions of the ZMC 113 of the present invention. Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0080] Some portions of the previous detailed description have been presented with respect to operations and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the most effective means for those skilled in the art of data processing to communicate the content of their work to others skilled in the art. Here and in general, an algorithm or operation is conceived as a self-consistent sequence of operations that produce a desired result. The operations are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been demonstrated that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc., primarily for common reasons.

[0081] It should be borne in mind, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0082] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, which are respectively coupled to a computer system bus.

[0083] The algorithms, operations and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems can be used together with the programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures for various of these systems will be presented from the following description. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein can be implemented using a variety of programming languages.

[0084] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0085] The words "example" or "exemplary" are used herein to mean serving as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" should not necessarily be interpreted as being preferred or advantageous over other aspects or designs. On the contrary, the use of the words "example" or "exemplary" is intended to present concepts in a specific way. As used in this application, the term "or" means an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or obvious from the context, "X includes A or B" means any natural inclusive arrangement. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied in any of the foregoing situations. In addition, the article "one" as used in this application and the appended claims can be generally interpreted as meaning "one or more", unless otherwise specified or clearly visible from the context to represent a singular form. In addition, the use of the terms "embodiment" or "one embodiment" or "embodiment" or "one embodiment" etc. throughout the article is not intended to represent the same embodiment or embodiments, unless so described. One or more embodiments described herein may be combined in a particular embodiment. The terms “first,” “second,” “third,” “fourth,” etc. as used herein are intended as labels to distinguish different elements and may not necessarily have ordinal meanings consistent with their numerical names.

[0086] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A system comprising: a memory device comprising a plurality of physical memory blocks PMB and associated with a logical address space including the first region; as well as a processing device operatively coupled to the memory device to perform operations comprising: receiving a first request to store first data referenced by a first logical block address LBA associated with the first area; obtaining a version identifier of the first region, wherein the version identifier of the first region represents a number of times the first region has been invalidated, wherein invalidating the first region includes invalidating a plurality of LBAs of the first region; selecting a first PMB of the plurality of PMBs in view of the version identifier of the first region; mapping the first LBA associated with the first region to the first PMB; and The first data is stored in the first PMB.

2. The system of claim 1, wherein the first region is invalidated by moving a write pointer to a starting LBA of the first region.

3. The system of claim 1, wherein selecting the first PMB is further in view of an erase value of the first PMB, the erase value of the first PMB representing a number of completed erase operations of the first PMB. 4 . The system of claim 3 , wherein the first region has a lowest number of fail operations among a plurality of regions, and wherein the first PMB has a highest erase value among at least a subset of the plurality of PMBs.

5. The system of claim 4, wherein the erasure values ​​of the subset of the plurality of PMBs do not exceed a threshold erasure value.

6. The system of claim 3, wherein the operations further comprise: receiving a second request to store second data referenced by a second LBA associated with a second region of the logical address space of the memory device; obtaining a version identifier of the second region, wherein the version identifier of the second region represents a number of times the second region has been invalidated, wherein invalidating the second region includes invalidating a plurality of LBAs of the second region; selecting a second PMB from among the plurality of PMBs in view of the version identifier of the second region; mapping the second LBA associated with the second region to the second PMB, wherein the version identifier of the second region is less than the version identifier of the first region, wherein an erase value of the second PMB is greater than the erase value of the first PMB, and wherein the erase value of the second PMB represents a number of completed erase operations of the second PMB; and The second data is stored in the second PMB.

7. The system of claim 3, wherein selecting the first PMB comprises: obtaining a first distribution of version identifiers for a plurality of regions; obtaining a second distribution of erase values ​​for at least a subset of the plurality of PMBs, wherein the erase values ​​represent a number of completed erase operations for corresponding PMBs of the subset of the plurality of PMBs; as well as Based on the first distribution and the second distribution, the first PMB is selected.

8. The system of claim 7, wherein selecting the first PMB based on the first distribution and the second distribution comprises: dividing the first distribution into a first plurality of version identifier intervals; dividing the second distribution into a second plurality of erase value intervals; determining that the version identifier of the first region belongs to a j-th lower version identifier interval of the first distribution; and The first PMB is selected from a j-th high erasure value interval of the second distribution.

9. A method comprising: receiving, by a processing device operatively coupled to a memory device, a first request to store first data referenced by a first logical block address LBA associated with a first region of a logical address space of the memory device, the memory device comprising a plurality of physical memory blocks PMB; obtaining, by the processing device, a version identifier of the first region, wherein the version identifier of the first region represents a number of times the first region has been invalidated, wherein invalidating the first region includes invalidating a plurality of LBAs of the first region; Selecting, by the processing device, a first PMB from among the plurality of PMBs in view of the version identifier of the first region; Mapping, by the processing device, the first LBA associated with the first region to the first PMB; as well as The first data is stored in the first PMB by the processing device.

10. The method of claim 9, wherein selecting the first PMB is further in view of an erase value of the first PMB, the erase value of the first PMB representing a number of completed erase operations of the first PMB. 11 . The method of claim 10 , wherein the first region has a lowest number of fail operations among a plurality of regions, and wherein the first PMB has a highest erase value among at least a subset of the plurality of PMBs.

12. The method of claim 11, wherein the erasure values ​​of the subset of the plurality of PMBs do not exceed a threshold erasure value.

13. The method according to claim 10, further comprising: receiving a second request to store second data referenced by a second LBA associated with a second region of the logical address space of the memory device; obtaining a version identifier of the second region, wherein the version identifier of the second region represents a number of times the second region has been invalidated, wherein invalidating the second region includes invalidating a plurality of LBAs of the second region; selecting a second PMB from among the plurality of PMBs in view of the version identifier of the second region; mapping the second LBA associated with the second region to the second PMB, wherein the version identifier of the second region is less than the version identifier of the first region, wherein an erase value of the second PMB is greater than the erase value of the first PMB, and wherein the erase value of the second PMB represents a number of completed erase operations of the second PMB; and The second data is stored in the second PMB.

14. The method of claim 10, wherein selecting the first PMB comprises: obtaining a first distribution of version identifiers for a plurality of regions; obtaining a second distribution of erase values ​​for at least a subset of the plurality of PMBs, wherein the erase values ​​represent a number of completed erase operations for corresponding PMBs of the subset of the plurality of PMBs; as well as Based on the first distribution and the second distribution, the first PMB is selected.

15. The method of claim 14, wherein selecting the first PMB based on the first distribution and the second distribution comprises: dividing the first distribution into a first plurality of version identifier intervals; dividing the second distribution into a second plurality of erase value intervals; determining that the version identifier of the first region belongs to a j-th lower version identifier interval of the first distribution; and The first PMB is selected from a j-th high erasure value interval of the second distribution.

16. A non-transitory computer readable memory storing instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a first request to store first data referenced by a first logical block address LBA associated with a first region of a logical address space of a memory device, wherein the memory device comprises a plurality of physical memory blocks PMB; obtaining a version identifier of the first region, wherein the version identifier of the first region represents a number of times the first region has been invalidated, wherein invalidating the first region includes invalidating a plurality of LBAs of the first region; selecting a first PMB of the plurality of PMBs in view of the version identifier of the first region; mapping the first LBA associated with the first region to the first PMB; and The first data is stored in the first PMB by the processing device.

17. The non-transitory computer readable memory of claim 16, wherein selecting the first PMB is further in view of an erase value of the first PMB, the erase value of the first PMB representing a number of completed erase operations of the first PMB.

18. The non-transitory computer readable memory of claim 16, wherein the operations further comprise: receiving a second request to store second data referenced by a second LBA associated with a second region of the logical address space of the memory device; obtaining a version identifier of the second region, wherein the version identifier of the second region represents a number of times the second region has been invalidated, wherein invalidating the second region includes invalidating a plurality of LBAs of the second region; selecting a second PMB from among the plurality of PMBs in view of the version identifier of the second region; mapping the second LBA associated with the second region to the second PMB, wherein the version identifier of the second region is less than the version identifier of the first region, wherein an erase value of the second PMB is greater than the erase value of the first PMB, and wherein the erase value of the second PMB represents a number of completed erase operations of the second PMB; and The second data is stored in the second PMB.

19. The non-transitory computer readable memory of claim 16, wherein selecting the first PMB comprises: obtaining a first distribution of version identifiers for a plurality of regions; obtaining a second distribution of erase values ​​for at least a subset of the plurality of PMBs, wherein the erase values ​​represent a number of completed erase operations for corresponding PMBs of the subset of the plurality of PMBs; as well as Based on the first distribution and the second distribution, the first PMB is selected.

20. The non-transitory computer readable memory of claim 19, wherein selecting the first PMB based on the first distribution and the second distribution comprises: dividing the first distribution into a first plurality of version identifier intervals; dividing the second distribution into a second plurality of erase value intervals; determining that the version identifier of the first region belongs to a j-th lower version identifier interval of the first distribution; and The first PMB is selected from a j-th high erasure value interval of the second distribution.

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