Self-calibration in memory device

Abstract

The invention relates to self-calibration in a memory device. Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for retraining the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been satisfied, and in response, the semiconductor device retrains the equalizer without invoking retraining by a host device coupled to the semiconductor device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 507,951, filed on June 13, 2023, entitled “Self-Calibration in a Memory Device,” which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate generally to the field of semiconductor memory devices. More specifically, embodiments of the present disclosure relate to self-calibration and tracking in dynamic random access memory (DRAM) devices. Background Art

[0004] The operating rates of memory devices (including the data rates of the memory devices) continue to increase over time. As a side effect of the increased speed of memory devices, data errors due to distortion may increase. For example, inter-symbol interference between transmitted data may occur, whereby previously received data affects currently received data (e.g., previously received data affects and interferes with subsequently received data). One way to correct for such interference is by using a decision feedback equalizer (DFE) circuit, which can be programmed to counteract (i.e., eliminate, mitigate, or minimize) the effects of the channel on the transmitted data.

[0005] In addition, it is still important to correct distortion in the transmitted signal. One way to correct distortion may be to use link training and subsequent retraining, in which a host device (e.g., a processor) trains a link of a double data rate (DDR) interface between a DRAM device and the host device. Such link training / retraining includes the host device sending / receiving signals over the DDR interface while programming adjustments to interface-related parameters. However, the link training and subsequent retraining time of the DDR interface of these DRAM devices may be relatively lengthy and have a negative impact on the user experience. Summary of the invention

[0006] On the one hand, the present disclosure provides a method, which includes: using a semiconductor device to self-train an equalizer of the semiconductor device; receiving, at the semiconductor device, an indication of a condition for retraining the equalizer; operating the equalizer based on trained values ​​derived during the self-training; using the semiconductor device to determine that the condition has been met; and retraining the equalizer by the semiconductor device without invoking retraining by a host device coupled to the semiconductor device.

[0007] On the other hand, the present disclosure further provides a semiconductor device, comprising: a receiver, which is configured to receive data bits from another device and use a first reference voltage to latch at least some of the data bits in parallel in a first group of latches and use a second reference voltage to latch at least some of the data bits in parallel in a second group of latches; and a self-calibration circuit system, which comprises: an analysis circuit system, which is configured to compare corresponding parallel latched bits to determine whether to increment a bit counter; an averaging circuit system, which includes a bit counter configured to track the number of increments determined in the analysis circuit system, and the averaging circuit system is configured to track the number of bit comparisons performed in the analysis circuit system; an adder / subtractor circuit system, which is configured to add a value to a current setting or subtract the value from the current setting to generate a new setting based on the number of counted increments; and a reference voltage generator, which is used to convert the new setting to generate the first reference voltage.

[0008] In yet another aspect, the present disclosure further provides a self-calibration circuit system configured to perform self-training in a memory device, wherein the self-calibration circuit system includes: an input configured to receive first and second latched bits of a single bit capture received from the memory device; an analysis circuit system for comparing the first and second latched bits to determine an incremented first bit counter based on the comparison of the first and second latched bits; a digital averaging circuit system including: the first bit counter configured to track the number of increments determined in the analysis circuit system; and a second bit counter configured to track the number of bit comparisons performed in the analysis circuit system; an adder / subtractor circuit system configured to: receive a step signal indicating an increment value; receive an indication of a previous setting of an equalizer; and add the increment value to the previous setting or subtract the increment value from the previous setting to output a new setting based at least in part on the step signal, the indication of the previous setting, and the number of increments counted in the first bit counter; and a reference voltage generator for converting the new setting to generate a reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects of the present disclosure may be better understood after reading the following detailed description and referring to the drawings, in which:

[0010] Figure 1 is a simplified block diagram illustrating certain features of a memory device including an I / O interface having a data transceiver according to an embodiment of the present disclosure;

[0011] Figure 2 A method for implementing a DQ transceiver according to an embodiment of the present disclosure is described. Figure 1 Block diagram of a data transceiver;

[0012] Figure 3 A DQ receiver having a decision feedback equalizer (DFE) according to an embodiment of the present disclosure is described. Figure 1 A block diagram of an embodiment of a data transceiver;

[0013] Figure 4 Describe the embodiment according to the present disclosure Figure 3 A circuit diagram of a DFE distortion correction circuit of a DQ receiver;

[0014] Figure 5A and 5B A method for implementing a self-calibration circuit system with an error assessment subcircuit according to an embodiment of the present disclosure is described. Figure 3 A circuit diagram of a DFE distortion correction circuit of a DQ receiver;

[0015] Figure 6 A method for implementing a self-calibration circuit system with multiple error assessment subcircuits according to an embodiment of the present disclosure is described. Figure 3 A circuit diagram of a DFE distortion correction circuit of a DQ receiver;

[0016] Figure 7 A preamplifier having a plurality of error evaluation subcircuits driving the preamplifier and also including a self-calibration circuit system according to an embodiment of the present disclosure is described. Figure 3 A circuit diagram of a DFE distortion correction circuit of a DQ receiver;

[0017] Figure 8 A method for implementing a self-calibration circuit system according to an embodiment of the present disclosure is described. Figure 3 Circuit diagrams of different embodiments of a DFE distortion correction circuit of a DQ receiver;

[0018] Fig. 9 a block diagram illustrating the self-calibration circuitry of FIGS. 5 , 6 , 7 , and 8 according to an embodiment of the present disclosure; and

[0019] Fig.10 Describe the method for using the embodiment according to the present disclosure Fig. 9 Flow chart of a process for performing self-calibration by a self-calibration circuit system. DETAILED DESCRIPTION

[0020] One or more specific embodiments will be described below. In order to provide a concise description of these embodiments, not all features of the actual implementation are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve developer-specific goals that may vary from implementation to implementation, such as compliance with system-related and business-related constraints. In addition, it should be understood that such development work may be complex and time-consuming, but is still a routine task of design, fabrication, and manufacturing for a person of ordinary skill in the art who has the benefit of this disclosure.

[0021] As previously described, correction for bit distortion between a host device (e.g., a processor) and a memory device may be performed through link training / retraining. However, such link training / retraining may take a long time to complete and may have a negative impact on the use of the memory device. To at least partially mitigate the negative impact, the memory device may be used to autonomously train the memory interface and / or autonomously adjust circuit parameters after training to maintain interface margins during operation of the memory device. As discussed below, such autonomous training and / or adjustment may take into account memory environment-specific complexities, such as single-ended signaling, bursty data transfers (including associated rapid power-ups and / or power-downs), relatively poor transistor performance, bidirectional pins, and / or other situations that may not be suitable for non-memory device calibration / training.

[0022] Now turning to the graph, Figure 1 is a simplified block diagram illustrating certain features of memory device 10. Specifically, Figure 1 The block diagram of FIG. 1 is a functional block diagram illustrating certain functionality of the memory device 10. According to one embodiment, the memory device 10 may be a double data rate 5 synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of the DDR5 SDRAM allow for reduced power consumption, more bandwidth, and more storage capacity compared to previous generations of DDR SDRAM.

[0023] The memory device 10 may include several memory banks 12. For example, the memory banks 12 may be DDR5 SDRAM memory banks. The memory banks 12 may be disposed on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). As will be appreciated, each DIMM may include several SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having several memory banks 12. For DDR5, the memory banks 12 may be further arranged to form memory bank groups. For example, for an 8-gigabit (GB) DDR 5 SDRAM, the memory chip may include 16 memory banks 12 arranged in 8 memory bank groups, each memory bank group including 2 memory banks. For example, for a 16GB DDR5 SDRAM, the memory chip may include 32 memory banks 12 arranged in 8 memory bank groups, each memory bank group including 4 memory banks. Various other configurations, organizations, and sizes of memory banks 12 on memory device 10 may be utilized depending on the application and design of the overall system.

[0024] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16 configured to exchange (e.g., receive and transmit) signals with an external device. The command interface 14 is configured to provide a number of signals (e.g., signal 15) from an external device (not shown), such as a processor or controller. The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transmission and reception of data to be written to or read from the memory device 10.

[0025] As will be appreciated, for example, the command interface 14 may include several circuits to ensure that the signal 15 is properly handled, such as a clock input circuit 18 and a command address input circuit 20. The command interface 14 may receive one or more clock signals from an external device. Typically, double data rate (DDR) memories utilize a differential pair of system clock signals, referred to herein as a true clock signal (Clk_t) and a complementary clock signal (Clk_c). The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t intersects the falling complementary clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rise of the complementary clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal and data is transmitted or received on both the positive and negative clock edges.

[0026] The clock input circuit 18 receives the true clock signal (Clk_t) and the complementary clock signal (Clk_c) and generates an internal clock signal Clk. The internal clock signal CLK is supplied to an internal clock generator 30, such as a delay locked loop (DLL) circuit. The internal clock generator 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. For example, the phase-controlled internal clock signal LCLK is supplied to the I / O interface 16 and is used as a timing signal for determining the output timing of the read data.

[0027] The internal clock signal CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from a command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide the command signal to the internal clock generator 30 via a bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. For example, the phase-controlled internal clock signal LCLK may be used to clock data through the I / O interface 16.

[0028] In addition, the command decoder 32 can decode commands (e.g., read commands, write commands, mode register set commands, activate commands, etc.) and provide access to the specific memory bank 12 corresponding to the command via the bus path 40. As will be appreciated, the memory device 10 may include various other decoders to facilitate access to the memory banks 12, such as row decoders and column decoders. In one embodiment, each memory bank 12 includes a memory bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) and other features (e.g., timing control and data control) to facilitate execution of commands to and from the memory bank 12. The memory banks 12 and the memory bank control blocks 22 may be collectively referred to as a memory array 23.

[0029] The memory device 10 performs operations, such as read commands and write commands, based on command / address signals received from an external device, such as a processor. In one embodiment, the command / address bus may be a 14-bit bus to accommodate command / address signals (CA<13:0>). The command / address signals are clocked to the command interface 14 using clock signals (Clk_t and Clk_c). For example, the command interface may include a command address input circuit 20 configured to receive and transmit commands to provide access to the memory bank 12 through the command decoder 32. In addition, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands on the incoming CA<13:0> bus. Access to a specific memory bank 12 within the memory device 10 is encoded on the CA<13:0> bus with a command.

[0030] In addition, the command interface 14 may be configured to receive a number of other command signals. For example, an intra-die termination command / address (CA_ODT) signal may be provided to facilitate proper impedance matching within the memory device 10. For example, during power-on, a reset command (RESET_n) may be used to reset the command interface 14, the status register, the state machine, and the like. The command interface 14 may also receive a command / address inversion (CAI) signal, which may be provided to, for example, invert the state of the command / address signal CA<13:0> on the command / address bus depending on the command / address routing of the specific memory device 10. A mirror (MIR) signal may also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a specific application, the MIR signal may be used to multiplex signals so that they may be exchanged for implementing a specific routing of signals to the memory device 10. Various signals, such as a test enable (TEN) signal, may also be provided to facilitate testing of the memory device 10. For example, the TEN signal may be used to place the memory device 10 in a test mode for connectivity testing.

[0031] The command interface 14 may also be used to provide an alert signal (ALERT_n) to a system processor or controller for certain errors that may be detected. For example, if a cyclic redundancy check (CRC) error is detected, an alert signal (ALERT_n) may be transmitted from the memory device 10. Other alert signals may also be generated. In addition, the bus and pins used to transmit the alert signal (ALERT_n) from the memory device 10 may be used as input pins during certain operations, such as a connectivity test mode performed using the TEN signal, as described above.

[0032] Data may be sent to or from the memory device 10 by transmitting and receiving data signals 44 through the I / O interface 16 utilizing the command and timing signals discussed above. More specifically, data may be sent to or retrieved from the memory bank 12 through a data bus 46 that includes a plurality of bidirectional data connections. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data connections. For certain memory devices, such as DDR5 SDRAM memory devices, the I / O signals may be divided into high and low bytes. For example, for a x16 memory device, the I / O signals may be divided into high and low I / O signals (e.g., DQ<15:8> and DQ<7:0>), such as corresponding to the high and low bytes of the data signals.

[0033] To allow for higher data rates within the memory device 10, some memory devices (e.g., DDR memory devices) may utilize a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller that sends data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is actually an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal is used as a clock signal to capture the corresponding input data. Like the clock signal (Clk_t and Clk_c), the data strobe (DQS) signal may be provided as a differential pair (DQS_t and DQS_c) of data strobe signals to provide differential pair signaling during reading and writing. For certain memory devices (e.g., DDR5 SDRAM memory devices), the differential pair of DQS signals may be divided into high and low data select signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to the high and low bytes of data sent to and from the memory device 10.

[0034] An impedance (ZQ) calibration signal may also be provided to the memory device 10 through the I / O interface 16. The ZQ calibration signal may be provided to a reference pin and used to tune the output driver and ODT value by adjusting the pull-up and pull-down resistors of the memory device 10 across changes in process, voltage, and temperature (PVT) values. Because PVT characteristics may affect the ZQ resistor value, the ZQ calibration signal may be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor acts as a reference for adjusting the internal ODT and drive strength of the IO pin.

[0035] In addition, a loopback signal (LOOPBACK) may be provided to the memory device 10 through the I / O interface 16. The loopback signal may be used during a test or debug phase to set the memory device 10 into a mode in which a signal is looped back through the memory device 10 through the same pin. For example, the loopback signal may be used to set up the memory device 10 to test the data output of the memory device 10. The loopback may include both the data signal and the strobe signal, or may include only the data pin. This is generally intended to be used to monitor the data captured by the memory device 10 at the I / O interface 16.

[0036] As will be appreciated, various other components such as power supply circuits (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 10), etc. may also be incorporated into the memory device 10. Therefore, it should be understood that only the memory device 10 is provided. Figure 1 The block diagram is used to highlight certain functional features of the memory device 10 to assist in the subsequent detailed description.

[0037] In some embodiments, memory device 10 may be coupled to a host device 47. Host device 47 may include a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), another microprocessor, a programmable logic device, and / or any other suitable processor that controls system functions and processing of requests. In addition, any host device / processor may include multiple processing units.

[0038] The host device 47 is operable to transfer data to the memory device 10 for storage and can read data from the memory device 10 to perform various operations. Therefore, to facilitate these data transfers, in some embodiments, the I / O interface 16 may include a data transceiver 48 that operates to receive and transmit DQ signals from and to the I / O interface 16.

[0039] Figure 2The I / O interface 16 of the memory device 10 is generally illustrated and the data transceiver 48 is illustrated more specifically. As illustrated, the data transceiver 48 of the I / O interface 16 may include a DQ connector 50 (e.g., any of DQ<7:0> and / or DQ<15:8>), a DQ transceiver 52, and a serializer / deserializer 54. It should be noted that in some embodiments, multiple data transceivers 48 may be utilized such that each single data transceiver 48 may be utilized in conjunction with, for example, a respective one of each of the high and low I / O signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to the high and low bytes of the data signal. Thus, the I / O interface 16 may include multiple data transceivers 48, each data transceiver 48 corresponding to one or more I / O signals (e.g., including a respective DQ connector 50, a DQ transceiver 52, and a serializer / deserializer 54).

[0040] The DQ connector 50 may include pins, pads, lines, other types of interfaces, and / or combinations thereof that operate to receive DQ signals from the host device 47 as part of an operation (e.g., a data write operation). Additionally, the DQ connector 50 may be used to transmit DQ signals from the memory device 10 to the host device 47 as part of an operation (e.g., a data read operation). To facilitate these data reads / writes, the DQ transceiver 52 in the data transceiver 48 may determine the timing of the transmission via a received clock signal generated by the internal clock generator 30. The clock signal transmitted by the internal clock generator 30 may be based on one or more timing signals received by the memory device 10 from the host device 47 at the clock connector 56 and routed to the internal clock generator 30 via the clock input circuit 18.

[0041] Figure 2 The DQ transceiver 52 of the present invention may also receive one or more DQS signals to assist in capturing data in the DQ signals. The DQS signals may be received from the host device 47 at the DQS connector, which are routed to the DQ transceiver 52 via the DQS transceiver 60. The DQS transceiver 60 operates to control the selective transmission of the DQS signals to the DQ transceiver 52. Thus, the DQ transceiver 52 may receive the DQS signals to assist in data writing operations.

[0042] In addition, if Figure 24, the data transceiver 48 also includes a serializer / deserializer 54 that operates to convert serial data bits (e.g., a serial bit stream) into parallel data bits (e.g., a parallel bit stream) for transmission along the data bus 46 during a data write operation of the memory device 10. Likewise, the serializer / deserializer 54 operates to convert parallel data bits (e.g., a parallel bit stream) into serial data bits (e.g., a serial bit stream) during a read operation of the memory device 10. In this manner, the serializer / deserializer 54 operates to convert data received from the host device 47 in a serial format into a parallel format for transmission over the data bus 46. Likewise, the serializer / deserializer 54 operates to convert data received from the data bus 46 in a parallel format into a serial format suitable for transmission to the host device 47.

[0043] As can be appreciated, the serializer / deserializer 54 and the DQ transceiver 52 may contain different circuitry internally so that the DQ receiver may be coupled to the serializer and the DQ transmitter may be coupled to the deserializer (or deserializer). Figure 3 The data transceiver 48 is illustrated as including a DQ connector 50, a DQ receiver 62, a DQ transmitter 64, a deserializer 66, and a serializer 68. In operation, as part of an operation (e.g., a write), the host device 47 transmits data in serial form to the transceiver 48. This data is received at the DQ connector 50 and transmitted to the DQ receiver 62. The DQ receiver 62 may perform one or more operations on the data (e.g., amplify, drive a data signal, etc.) and / or may operate as a latch for the data until a corresponding DQS signal is received that operates to coordinate the transmission of the data to the deserializer 66. As part of the operation, the deserializer 66 converts the data from a serial format to a parallel format for transmission over the data bus 46.

[0044] Likewise, during another operation (e.g., reading), the serializer 68 may receive data in a parallel format from the data bus 46 and convert it to a serial format for transmission to the DQ transmitter 64. The DQ transmitter 64 may perform one or more operations on the data (e.g., amplify / de-amplify, drive the data signal, etc.). Additionally or alternatively, the DQ transmitter 64 may operate as a latch for the received data until a corresponding clock signal is received from the internal clock generator 30, which operates to coordinate (e.g., control) the transmission of data to the DQ connector 50 for transmission along the data transfer bus 51 to one or more components of the host.

[0045] In some embodiments, data received at DQ connector 50 may be distorted. For example, data received at DQ connector 50 may be affected by inter-symbol interference (ISI), where previously received data interferes with subsequently received data. For example, due to a higher transmission frequency across data transfer bus 51 to DQ connector 50, data received at DQ connector 50 may be distorted relative to data transmitted by host device 47. One technique to mitigate such distortion is to apply equalization to the data using an equalizer.

[0046] The data transceiver 48 includes a decision feedback equalizer (DFE) 70 as an equalizer, but may include other equalizers, such as a continuous time linear equalizer (CTLE), a feed forward equalizer (FFE), and / or any other suitable equalizer type. In addition, the training techniques discussed herein may be applied to any suitable equalizer, input offset training / calibration, output driver training, and the like. Output driver training may be based on information extracted from a received signal. For example, the information may include tuning drive strength, termination strength, feed forward (FFE) tap coefficients, pre / de-emphasis equalization settings, and the like. In addition, although the present discussion generally relates to the magnitude and sign of the tap coefficients, the temporal position of the taps may be determined for the DFE "slip time". The sliding tap timing may be synchronized with the bit unit interval or may be continuous. In some embodiments, the continuous property may be turned on and off (e.g., using a mode register value).

[0047] As illustrated, the DFE 70 is a multi-tap (e.g., four-tap) DFE 70. However, fewer or more than four taps may be utilized in the DFE 70. Likewise, the DFE 70 may be disposed separately from or internal to the deserializer 66 or DQ receiver 62. In operation, the binary output (e.g., from a latch or decision slicer) is captured in one or more data latches or data registers. In the present embodiment, these data latches or data registers may be disposed in the deserializer 66, with the latched values ​​transmitted back along paths 72, 74, 76, and 78 as taps of the DFE 70.

[0048] When a data bit is received at the DQ receiver 62, it may be recognized as being transmitted from the host as bit "n" and may be received at time t 0Received as distorted bit n (e.g., bit n has been distorted due to ISI). The currently received bit (N) may be preceded by bits N-4 (four bits ago), N-3 (three bits ago), N-2 (two bits ago), and N-1 (previous bit) from the previous cycle (and / or half cycle). Latched bits N-1, N-2, N-3, and N-4 are used by DFE 70 to mitigate distortion of transmitted bit N. These latched bits are fed back to DFE 70 along paths 72, 74, 76, and 78. DFE 70 applies the latched bits using weighted taps added to the input signal. Additionally or alternatively, the weighted taps (e.g., voltages) may be combined with an initial reference value to produce an offset that mitigates data distortion.

[0049] Figure 5A and 5B A distortion correction circuit 100 is illustrated that may be part of a DFE 70 and is configured to process and correct four bits. Additionally or alternatively, at least some of the functions and / or circuitry of the distortion correction circuit 100 may be located in a data buffer chip between the host device 47 and the memory device 10. As used herein, the distortion correction circuit 100 may also be referred to as error assessment circuitry, error detection circuitry, error correction circuitry, and the like. The distortion correction circuit 100 includes a first subcircuit 102, a second subcircuit 104, a third subcircuit 106, and a fourth subcircuit 108, each of which may be a latch circuitry including one or more latches configured to latch input data 110 of a corresponding clock phase. Furthermore, in some embodiments, the memory device 10 may divide the clock into different phases and use different phases for consecutive bits to control operations (e.g., writes). In such embodiments, the first subcircuit 102 may correspond to a first phase and may process the first bit and every fourth bit after the first bit (e.g., the 5th bit, the 9th bit, etc.) in operation. Likewise, the second subcircuit 104 may correspond to the second phase and may be in operation to process the second bit and every fourth bit after the second bit (e.g., the 6th bit, the 10th bit, etc.). Similarly, the third subcircuit 106 may correspond to the third phase and may be in operation to process the third bit and every fourth bit after the third bit (e.g., the 7th bit, the 11th bit, etc.), and the fourth subcircuit 108 may correspond to the fourth phase and may be in operation to process the fourth bit and every fourth bit after the fourth bit (e.g., the 8th bit, the 12th bit, etc.). The first subcircuit 102 may receive an input bit 110 (e.g., from the data transfer bus 51). Likewise, the second subcircuit 104 may receive an input bit 112. The third subcircuit 106 may receive an input bit 114, and the fourth subcircuit 108 may receive an input bit 116.

[0050] To further illustrate, the first subcircuit 102 may receive the input bit 110 and may begin processing it using the previous bits or weighted tap data transmitted along the paths 74, 76 and 78 to calculate the values ​​to be used by the latches (or equalizers) 118 and 120. The latches implement taps 2 to 4 by applying current subtraction using the values ​​carried along the paths 74, 76 and 78. The voltage reference signals 122 (VRHI) and 124 (VRLO) may represent modified DQ reference signals that have been adjusted for the contribution of the bit values ​​of N-1 to logic high and low, respectively. In other words, any possible value (e.g., 0 or 1) of the most recent bit value may be calculated (i.e., spread out) in parallel because the delay of the most recent bit propagating to the latches 118 and 120 may be too late to be properly equalized. The outputs 126 and 128 may be transmitted to the selection device 129 on the rising (or falling) edge of the DQS signal. The selection device 129 can use the actual N-1 bit value stored in the deserializer 66 to select between parallel operations assuming a high value or a low value for the N-1 bit to determine the correct value taken by the value of the corrected bit 130. In other words, the selection device 129 selects the value of the corrected bit 130 from either the output 126 or the output 128.

[0051] The inputs used to determine the corrected bits 130 for the second subcircuit 104 may be different than the inputs used for the first subcircuit 102, but the second subcircuit 104 may operate similarly to the first subcircuit 102. For example, the second subcircuit 104 may receive the input bits 112 and may begin processing the input bits 112 with the most recent bits being expanded. Thus, the voltage reference signal 132 operates as a logic high reference (VRHI) assuming the most recent bits for the second subcircuit are logic high, and the voltage reference signal 134 operates as a logic low reference (VRLO) assuming the most recent bits are logic low. The method described in conjunction with the first subcircuit 102 may be used to correct the input bits 112, except that the previous bits or weighted tap data transmitted along the paths 72, 74, and 76 are used to calculate the values ​​used to provide correction via the equalizers 136 and 138. The outputs 140 and 142 may be transmitted to the selection device 144 on the rising (or falling) edge of the DQS signal 145 (e.g., UDQS_t, UDQS_c, LDQS_t, and / or LDQS_c). The selection device 144 of the second sub-circuit 104 may use the bit value stored in the deserializer 66 for transmission along the path 78 to make a final decision on the value of the corrected bit 130 corresponding to the input bit 112.

[0052] The inputs used to determine the corrected bit 130 for the third subcircuit 106 may be different than the inputs used for the second subcircuit 104, but the third subcircuit 106 may operate similarly to the second subcircuit 104. For example, the third subcircuit 106 may receive the input bit 114 and may begin processing the input bit 114 with the previous bit (e.g., along path 76) being unfolded. For this purpose, the voltage reference signal 146 (VRHI) corresponds to a logic high and the voltage reference signal 148 (VRLO) corresponds to a logic low. The method described in conjunction with the first subcircuit 102 may be used to correct the input bit 114, except that the previous bit or weighted tap data transmitted along paths 72, 74, and 78 may be used to calculate the values ​​used to provide correction via equalizers 150 and 152. Outputs 154 and 156 may be transmitted to the selection device 158 on the rising (or falling) edge of the DQS signal 145. The selection device 158 of the third sub-circuit 106 may use the bit values ​​stored in the deserializer 66 for transmission along the path 76 to make a final decision on the value of the corrected bits 130 of the input bits 114 .

[0053] The inputs used to determine the corrected bits 130 for the fourth subcircuit 108 may be different from the inputs used for the third subcircuit 106, but it may operate similarly to the third subcircuit 106. The fourth subcircuit 108 may receive the input bits 116 and begin processing the input bits 116, wherein the bits (e.g., corresponding to path 74) are unfolded. For this purpose, the voltage reference signal 160 (VRHI) corresponds to a logic high, and the voltage reference signal 162 (VRLO) corresponds to a logic low. The method described in conjunction with the first subcircuit 102 may be used to correct the input bits 116, except that the previous bits or weighted tap data transmitted along paths 72, 76, and 78 may be used to calculate the values ​​used to provide correction via equalizers 164 and 166. Outputs 168 and 170 may be transmitted to the selection device 172 on the rising (or falling) edge of the DQS signal 145. The selection device 172 of the fourth subcircuit 108 may use the bit values ​​stored in the deserializer 66 for transmission along the path 74 to make a final decision on the value of the corrected bits 130 of the input bits 116 .

[0054] The outputs from the selection devices 129, 144, 158, and 172 are transmitted to the deserializer 66 at the end of each final decision on the corresponding corrected bit 130. In the deserializer 66, the latched value is updated according to the corrected bit 130 data. It can be noted that before receiving the fifth input bit, the corrected bit 130 may not have a completed transmission to the deserializer 66, nor an updated value stored for transmission along the path 72 to 78, so the method of delaying the final selection of the corrected bit 130 can continue. Therefore, the first subcircuit 102 can apply the weighted value from the fourth subcircuit 108 in parallel until the corrected bit 130 is determined from the fourth subcircuit 108 and used as the selection bit for the first subcircuit 102. Similarly, the second subcircuit 104 can apply the weighted value from the first subcircuit 102 in parallel until the corrected bit 130 is determined from the first subcircuit 102 and used as the selection bit for the second subcircuit 104. Likewise, the third subcircuit 106 may apply the weighted values ​​from the second subcircuit 104 in parallel until the corrected bit 130 is determined from the second subcircuit 104 and used as the select bit for the third subcircuit 106. The fourth subcircuit 108 may apply the weighted values ​​from the third subcircuit 106 in parallel until the corrected bit 130 is determined from the third subcircuit 106 and used as the select bit for the fourth subcircuit 108.

[0055] As previously described, memory device 10 may include self-training and / or circuitry adjustments to maintain link integrity without host device 47 interaction and / or with reduced host device 47 interaction. For example, Figure 5A and 5B Distortion correction circuit 190 is shown, which may be part of DFE 70 . Figure 5A and 5B The distortion correction circuit 190 can be used with Figure 4 100 operates similarly to the description of the distortion correction circuit 100 of 100, except that the distortion correction circuit 190 uses programmable reference voltages 194 and 196 in the error evaluation subcircuit 198. The programmable reference voltages 194 and 196 can both be based on a new programmable reference level ("dLev"), which is then expanded to programmable reference voltage 194 for a logic high and to programmable reference voltage 196 for a logic low, similar to the expansion of the reference levels of the voltage reference signals 122 and 124 for high and low values ​​as discussed above. For example, the programmable reference voltage 194 can be dLev after being adjusted by the tap adjustment assuming that the previous bit was high, and the programmable reference voltage 196 can be dLev after being adjusted by a different tap adjustment assuming that the previous bit was low.

[0056] The error assessment subcircuit 198 may be another instance of any of the subcircuits 102, 104, 106, or 108, except that the latches (e.g., latches 118 and 120) of the error assessment subcircuit 198 use programmable reference voltages 194 and 196 that are different from the programmable reference voltages used in the corresponding subcircuit (e.g., the first subcircuit 102). In the illustrated embodiment, the error assessment subcircuit 198 performs analysis of the input bits 110 in parallel with the first subcircuit 102 using another instance of latches 118 and 120 and using an additional copy of the latches, multiplexers, inputs, clocks, routing, and taps used in the first subcircuit 102. However, the error assessment subcircuit 198 may send its corrected bits 130 to the self-calibration circuitry 200 instead of the deserializer 66. The self-calibration circuit system 200 (or self-training circuit system) receives the corrected bits 130 from the error assessment subcircuit 198 and the corrected bits 130 from the first subcircuit 102 along with the tap adjustments via paths 72, 74, 76, and 78. These tap adjustments may be received from the deserializer 66 via a bus 202 originating from the serializer. In response to the corrected bits 130 from the error assessment subcircuit 198 and the corrected bits 130 from the first subcircuit 102, the self-calibration circuit system 200 may transmit an output 204 including a setting for dLev. The output 204 may also include a DFE setting used to control the DFE to maintain the link integrity between the host device 47 and the memory device 10. As described below with respect to Fig. 9 As discussed, the self-calibration circuitry 200 enables the memory device 10 to self-train / self-level the bias level of the DFE. The self-training / self-calibration may be performed without constant supervision by the host device 47. In some embodiments, the host device 47 may initiate the calibration / training and / or send a data pattern and (several) clock signals, but the memory device 10 may control the dLev and DFE bias settings according to the data pattern and (several) clock signals.

[0057] As illustrated, since the error assessment subcircuit 198 is another instance of the first subcircuit 102, the error assessment subcircuit 198 uses the same clock phase and tap adjustment at the corresponding latches and / or multiplexers. Additionally or alternatively, the error assessment subcircuit 198 may be an instance of any of the other subcircuits 104, 106, and 108 to route analysis of other corresponding bits using corresponding clocks and tap adjustments. In some embodiments, the error assessment subcircuit 198 may rotate between different tap points. The error assessment subcircuit 198 may be used to train the first bit during a first training period and may be used to train the second bit during a second training period. During the second training period, the error assessment subcircuit 198 may use different tap connections corresponding to the latch corresponding to the second bit. In other embodiments, the error assessment subcircuit 198 may be used to train using the first bit, but the resulting DFE settings may be applied to other taps (e.g., taps 1 to 4) in the group that includes the first bit.

[0058] Additionally or alternatively, in some embodiments, the distortion correction circuit 190 may include multiple error evaluation subcircuits. For example, Figure 6 1 is a simplified circuit diagram of an embodiment of a distortion correction circuit 190 that includes subcircuits 102, 104, 106, and 108 and error evaluation subcircuit 198 along with additional error evaluation subcircuits 210, 212, and 214. Since error evaluation subcircuit 198 corresponds to subcircuit 102, error evaluation subcircuits 210, 212, and 214 may correspond to respective subcircuits 104, 106, and 108. In other words, error evaluation subcircuit 210 may be another instance of subcircuit 104 and may use the same clock phase and tap adjustments at its respective latches and / or multiplexers as subcircuit 104. Similarly, error evaluation subcircuit 212 may be another instance of subcircuit 106 and may use the same clock phase and tap adjustments at its respective latches and / or multiplexers as subcircuit 106. Likewise, error evaluation subcircuit 214 may be another instance of subcircuit 108 and may use the same clock phase and tap adjustments at its corresponding latches and / or multiplexers as subcircuit 108. As can be appreciated, Figure 6 The distortion correction circuit 190 and Figure 5A and 5B The distortion correction circuit 190 can provide more parallel computation of the self-training output than the conventional one, but may consume more power.

[0059] In some embodiments of memory device 10, DQ receiver 62 may include a preamplifier for the DQ signal. For example, Figure 7An embodiment of a distortion correction circuit 190 is shown that includes preamplifiers 230 and 232 coupled to the DQ pads (rather than the DQ pads being coupled directly to the latches of the subcircuits 102, 104, 106, and 108). Even with the use of preamplifiers 230 and 232, tap 1 can still be developed, except that the voltage reference signals 122 and 124 have first passed through the respective preamplifiers 230 and 232. Preamplifier 230 receives a voltage reference high (VRHI) signal 234 corresponding to the previous bit being high and is used to generate the voltage reference signal 122 from the amplifier. Similarly, preamplifier 232 receives a voltage reference low (VRLO) signal 236 corresponding to the previous bit being low and is used to generate the voltage reference signal 124.

[0060] In addition, preamplifiers 230 and 232 may also be used on input bits 110. For example, preamplifiers 230 and 232 may include variable gain adjustment and / or continuous time linear equalization. Here, since preamplifiers 230 and 232 receive VRHI signal 234 and VRLO signal 236, the input bit 110 corresponding to the upper previous bit supplied to the latch (e.g., latch 118) may be different from the input bit 110 corresponding to the lower previous bit supplied to the latch (e.g., latch 120). Therefore, as illustrated, preamplifiers 230 and 232 may use different buses to transmit the respective input bits 110 to the respective latches. Figure 7 The remainder of the distortion correction circuit 190 operates similarly to the distortion correction circuit 190 of FIGS. 5 and 6 .

[0061] Although the foregoing discusses specific configurations of the DQ receivers 62 and their distortion correction circuits 190, any suitable configuration of the DQ receivers 62 may be used for self-training / self-calibration. Figure 8 An embodiment of the distortion correction circuit 190 is shown without expanding Tap 1 and using a separate equalizer 254 and latches 256, 258, 260, 262, 264, and 266. Latch 260 corresponds to latch 118, and latch 260 uses a first clock phase (and every fourth bit thereafter) based on reference voltage (Vref) 252 to capture the equalized data from equalizer 254 from preamplifier 250. Similarly, latch 262 uses a second clock phase (and every fourth bit thereafter), latch 264 uses a third clock phase (and every fourth bit thereafter), and latch 266 uses a fourth clock phase (and every fourth bit thereafter). Latches 260, 262, 264, and 266 also receive a preamplified version of reference voltage 252. Latches 256 and 258 are similar to corresponding latches 118 and 120 and use programmable reference voltages 194 and 196 to compare with the data from preamplifier 250, with tap 1 being expanded. Figure 8The remainder of the distortion correction circuit 190 operates similarly to the distortion correction circuit 190 of Figures 5 to 7 discussed previously. In addition, although the foregoing embodiments discuss a four-phase receiver, other implementations of the teachings herein may include any number of phases (e.g., 8 phases) and any number of suitable DFE taps.

[0062] Fig. 9 is a block diagram of an embodiment of the error assessment subcircuit 198. As previously described, the DQ receiver 62 (which includes the distortion correction circuit 190) transmits the current data bit state, the error bit state, and the feedback bit to the analysis circuit system 300. The analysis circuit system 300 may include digital logic circuit systems (e.g., NAND gates, inverters, OR gates, etc.). The analysis circuit system 300 receives the current data bit state, the error bit state, and the feedback bit and compares the received bits. Based on the comparison of the current data bit state, the error bit state, and / or the feedback bit, the analysis circuit system 300 may determine that the condition is met (e.g., the error bit state matches the current data bit state) and make an increment decision to increment the count. When the condition is not met, the analysis circuit system 300 may determine whether to decrement or not increment the count.

[0063] Analysis circuitry 300 may be coupled to averaging circuitry 302. Averaging circuitry 302 may be digital averaging circuitry because, in some embodiments, analog averaging circuitry may be unsuitable for this purpose due, at least in part, to the bursty nature of transmissions for at least some memory operations where analog averaging circuitry may typically require a continuous stream of data. Analysis circuitry 300 may increment bit counter 304 when any decision is made (increment or not) and may increment bit counter 306 when an increment decision is made. When a threshold number of bits (e.g., 1,024) has been counted in bit counter 304, it may output a stop signal to stop counting in bit counter 306. When counting is stopped via bit counter 304, bit counter 306 outputs an indication of whether a ratio threshold of the counted bits (e.g., greater than a certain ratio of the counted bits) corresponds to an increment counted in bit counter 306 due to the corresponding bit satisfying a condition. For example, when the total number of bits counted in bit counter 304 is 1,024, the proportional threshold may correspond to at least 512 increments greater than or equal to half the number of total bits counted. In some embodiments, there may be more than one single proportional threshold, each corresponding to a different output value, such that exceeding the highest (or lowest) threshold determines that output value. For example, the output value may correspond to an indication to add more voltage to dLev, to reduce the voltage level of dLev, and / or to leave dLev unchanged.

[0064] The number of bits to be counted before determining whether to make an addition or subtraction decision can be set by the host device 47 (e.g., via a setting mode register). This dynamic nature will enable the host device 47 to reduce the training time for less complex channel responses. Additionally or alternatively, the number of bits can be set by a fuse control configuration.

[0065] The output of the bit counter 306 is transmitted to the adder / subtractor circuit system 308. The adder / subtractor circuit system 308 also receives a step size signal 310, which may be one or more bits indicating a step size from a previous setting signal 312 for dLev. In other words, the previous setting signal 312 may indicate a previous voltage level of dLev (e.g., 50 mV), while the step size signal 310 indicates how much to change dLev in one direction (e.g., 5 mV) based on the output of the bit counter 306. In some embodiments, the step size signal 310 may be based on a proportional threshold determined in the bit counter 306. The output of the adder / subtractor circuit system 308 may indicate a new setting 314 for dLev. For example, if the output of the bit counter 306 indicates addition, the step size signal 310 indicates 5 mV, and the previous setting signal 312 indicates 50 mV, then the new setting 314 will indicate 55 mV. The new setting 314 may be stored in register 316 and / or latched as a dLev setting based on completing the counting of the threshold in bit counter 304. As illustrated, the output 204 (e.g., the dLev setting) is input to a dLev generator circuitry 318 that receives the new setting 314 as transmitted by register 316. The dLev generator circuitry 318 may decode and / or perform digital-to-analog conversion. For example, a digital code may be used to select a voltage level derived from a resistor ladder to generate a voltage level for dLev 320, which is then used directly or expanded as previously discussed for use in the DQ receiver 62.

[0066] In some embodiments, the die of the memory device 10 may include a self-calibration circuit system 200 shared among all DQs of the die. Alternatively, the die of the memory device 10 may include multiple self-calibration circuit systems 200. For example, in some embodiments, an instance of the self-calibration circuit system 200 may be added to each DQ, or at least one of the multiple instances of the self-calibration circuit system 200 may be shared between at least two DQs. The amount of the self-calibration circuit system 200 in the memory device 10 may vary accordingly based on how many self-calibration / training operations are to be performed in parallel by each of the self-calibration circuit systems 200. If the self-calibration circuit system 200 is to be shared between DQs, the memory device 10 may be supplemented with a multiplexer to the input / output of the self-calibration circuit system 200 to direct the signal to the appropriate location. In certain embodiments, one DFE and a set of registers 316 may be used for each DQ, regardless of the number of self-calibration circuit systems deployed on the die. However, the dLev generator circuit system 318 may be dedicated to a single DQ or shared between multiple DQs.

[0067] Target levels (e.g., programmable reference voltages 194 and 195) used to provide a reference in error calculations may also be set by the DQ receiver 62. In some embodiments, the target level may be determined based on a received logic low or a received logic high. In a fully linear time-invariant (LTI) system, determining a target level for a received logic low level will also produce accurate results for a received logic high case. In a nonlinear system, the results for the target level may be different for the high and low cases, but this difference may be predicted based on the input / output topology (e.g., channel termination to ground, etc.). In practice, the determination of the target level may be set for the worst case between the high case and the low case.

[0068] Alternatively, the target level may be calibrated based on both high and low values. These may be used sequentially / alternately or simultaneously / in parallel. Sequential training evaluations may take longer than parallel determinations and use switching (e.g., multiplexers) and control mechanisms to control when switching occurs. Simultaneous training may eliminate additional switching and control mechanisms, where the amount of time to find the target level is reduced in exchange for the inclusion of an additional error latch (e.g., latch 120). Furthermore, the target level may be selected as an offset relative to Vref based on one or another calculated target level, as an average offset relative to Vref based on the calculated target level, or as an independent offset (e.g., a high value relative to high and a low value relative to zero).

[0069] In addition, the step size signal 310 can be dynamic. Coarse granularity steps (e.g., 5 mV) versus fine granularity steps (e.g., 1 mV) can provide a tradeoff of the accuracy of fine granularity steps with the speed of low granularity steps. One mechanism can use both, where coarse granularity steps are used until the decision to add or subtract is changed in the adder / subtractor circuitry 308. After that, fine granularity steps can be used to more accurately determine the correct target level.

[0070] Other mechanisms used to shorten the duration of the process for determining levels may include estimating the starting point of the determination. For example, lookup table(s) may store information to estimate high and low target levels, where the estimated levels are estimated from known host drive strength and memory termination. Alternatively, these estimated levels may be calculated from the host drive strength and memory termination. By starting from an estimated endpoint, multiple iterations of search sweeps during training may be eliminated.

[0071] The received data pattern used in the self-calibration may be known or unknown. In addition, the data pattern may be continuous or bursty. How to analyze this data may change based on these conditions. For example, if n bits out of every m bits are evaluated, the memory device 10 / host device 47 may select a certain pattern to minimize the impact of inter-symbol interference (ISI) that has yet to be corrected. For example, for x number of bits, the used bit may not have a transition before or after the bit. Additionally or alternatively, the memory device 10 may skip x number of bits in a burst to avoid artifacts of channel / circuit settling time. Additionally or alternatively, if a high target (or low target) level is found, the host device 47 may send all 1s (or 0s) or long strings of 1s (or 0s) to speed up the process and reduce the impact of variations near true high and low signal levels. The long string may be at least as long as the number of DFE taps or the known channel response.

[0072] Similar to how the target level is determined, the tap coefficients may be trained. In some embodiments, the tap coefficients may be determined based on either a received logical low or a received logical high. However, signal asymmetry may make the determination solution suboptimal. Additionally or alternatively, the coefficients may be changed to an average of both high and low values. Such a solution may be more complex as the circuitry increases, but may at least partially mitigate the error of signal asymmetry. Additionally or alternatively, determining independent coefficients based on each high and low may include even more circuitry, but may more fully account for signal asymmetry.

[0073] In addition, the step size signal 310 can be dynamic. Coarse granularity steps (e.g., 5 mV) and fine granularity steps (e.g., 1 mV) can provide a tradeoff of the accuracy of fine granularity steps and the speed of low granularity steps. One mechanism can use both, where the coarse granularity steps are used until the decision to add or subtract is changed in the adder / subtractor circuit system 308. After that, the fine granularity steps can be used to more accurately determine the correct tap coefficients.

[0074] The "target level" determination discussed previously may set the target level to a pattern close to the high or low incoming signal level. Therefore, tuning the DFE tap coefficients based on these targets may leave excess margin that may be utilized more efficiently. One option is to train the DFE tap coefficients based on the initial target level, and then iteratively increase the spacing between the high and low target levels. Additionally or alternatively, the tap coefficients may be retrained at each step. Additionally or alternatively, the DFE tap coefficients are based on the initial target level and then the target level is retrained with equalization enabled. This methodology may produce smaller variations in the high and low received and equalized signal levels, pushing the high and low target levels toward their ideal positions. This iterative process may be looped until the target levels are no longer adjusted between iterations.

[0075] As previously mentioned, although DFE is generally discussed, other equalizers may be tuned as long as the cause-effect relationship between the error and the tuning knob can be identified. For example, the zero or peak frequency in a continuous time linear equalizer CTLE or the tap coefficients in a feed forward equalizer FFE may be manipulated similarly to the techniques discussed herein.

[0076] Because the electrical / thermal environment in which the memory device 10 is deployed may change over time, retraining may be used to guarantee target levels and / or DFE tap coefficients over time. Fig.10 A process 400 is shown that may be used when retraining a memory device 10 using self-training / self-calibration. As illustrated, the DFE of the memory device 10 is self-trained (block 402). This training may include self-training initiated by the host device 47 and performed without the host device 47's involvement, knowledge, and / or oversight of the self-training or retraining as previously discussed. Additionally or alternatively, self-training may be enabled as part of or after initialization of the memory device 10. Training may continue until a completion signal is returned to the host device 47, such as when the bit counter 304 has reached an end threshold. Additionally or alternatively, training may stop after a training duration has elapsed.

[0077] The host device 47 may also select from preset training conditions that define conditions for retraining (block 404). These conditions may be set and / or reset based on application specific power / performance tradeoffs that may be known to the host device 47. The condition may be that a specific event trigger has occurred, such as a monitored temperature exceeding a threshold, a voltage variation trend in a constant direction over a period of time, an external stimulus (e.g., spread spectrum clocking), and the like has occurred. In some embodiments, the condition may be that self-training has not been disabled, thereby enabling continuous testing (e.g., on non-enabled memory banks). Additionally or alternatively, the condition may be that a duration has passed since the last retraining occurred. For example, the memory device 10 may use an oscillator that is much slower than the speed of an internal clock used for memory operations in the memory device. When the oscillator causes a pulse, the memory device 10 may retrain regardless of other monitored conditions. In other words, retraining may be continuous, periodic, event-based, or a combination thereof.

[0078] The memory device 10 then operates the DFE based on the trained values ​​(block 406). The trained values ​​may include target levels and / or DFE tap coefficients. The memory device 10 may use monitoring circuitry / state machine to determine whether those conditions are met (block 408). For example, when the condition is that the monitored temperature has exceeded a threshold, the memory device 10 may use temperature monitoring circuitry. Additionally or alternatively, the memory device may use a counter that counts the number of cycles of an internal clock (or a slower clock) to determine whether enough time has elapsed since the last training to invoke a retrain operation. This counter may be reset after each retraining is completed. When the conditions are met, the memory device retrains the DFE (block 410).

[0079] As previously discussed, the memory interface of the memory device 10 may be bursty rather than continuous. Therefore, the memory device 10 may utilize digital averaging circuitry to account for the burstiness. The digital embodiment of the averaging circuitry 302 may be suitable for any circuitry that may use bursty data, such as DFE tap coefficient tuning, input offset calibration, and the like.

[0080] Another mechanism for handling bursty data may include introducing a data preamble to assist in stabilizing the data before proceeding with error evaluation. Typically, the preamble may be limited to a strobe pulse (e.g., WCK or DQS, depending on the standard). If there is no preamble, the error evaluation may be explicitly delayed by an "n" number of bits to mitigate skew due to start-up artifacts in the received signal. Thus, despite this, the dwell and non-dwell bits for the same value may be different. The number may be set by the host device 47 and / or via fusion. Furthermore, n may be related to the number of DFE taps to ensure that the taps are filled prior to training.

[0081] Since waiting for several cycles for the signal to stabilize may be inefficient, a unique "burst start" mode of DFE coefficients may be enabled after a data gap (e.g., a gap between write operations) that spans more than a certain number of bits. After that number of cycles (e.g., that number of taps), the DFE reverts to a set of real-time adaptive coefficients. In other words, the DFE taps may be set to an initial pattern (e.g., 0000, 0101, 1111, etc.) for use at the start of a burst.

[0082] To account for variable "midamble" or "burst gaps" between operations, the DQ receiver 62 may continue to modify the DFE history even when data is not being received. For example, an n-tap DFE may provide an internal trigger aligned with the strobe timing that continues even when there is no link activity to the host device 47. This internal trigger may maintain normal DFE functionality for up to n cycles when the number of midamble cycles exceeds the DFE tap count. After that, the DFE may be restarted to start a new burst. During this time, the internal strobe may be disabled to limit power usage during long gaps or periods of inactivity. Otherwise, the DFE coefficients are maintained as if the data were all set values ​​(e.g., 0 or 1) and ready for the next burst at any mid-cycle.

[0083] When the memory device 10 is symmetrical with two or more memory banks, at least some of the training may occur during normal operation. With balanced inter-bank layout, parasitics, and terminations, both enabled and disabled memory banks may see the same signal and may therefore continuously self-train. Such continuous self-training may take into account drift in signal margins due to changing temperature or voltage or any other parameter. In other words, the disabled bank may be trained using data sent to the enabled bank. Thus, the training portion may be run simultaneously for the disabled bank while performing memory operations for the enabled bank. In some embodiments, the memory device 10 may limit termination changes during training or for a duration after training.

[0084] As used herein, training of the DFE may be performed with or without accessing the memory array of the memory device 10. For example, training may be performed using incoming data that is not actually stored in the memory array. For example, non-target memory banks may use data that is not stored in the memory array. Additionally or alternatively, during self-training, the DFE may pull some data (e.g., data bits, configuration settings, thresholds, step sizes, etc.) from the memory array as part of training / calibration.

[0085] In some embodiments, the techniques disclosed herein may use independently adjustable timing in the DQS / WCK signal timing local to each data pin / DQ pad within the memory device 10 for sampling time optimization. As part of this adjustment, the host device 47 may distort the write data before initiation to compensate for data routing mismatches, DQS / WCK routing mismatches, and / or variations of the memory device 10. The host device 47 may also adjust the internal clock to optimize the sampling timing of the read data when receiving data from the memory device 10. In addition, in some embodiments, the training / calibration techniques discussed herein may assume that the host device 47 has trained the clock / strobe pulse relative to the data timing for the optimal sampling time at the data latch to obtain a starting point for training. This assumption enables the establishment of a fast first-order sampling timing based on the in-phase and out-of-phase effects of the aggressor on the victim row. This fast first-order timing may be achieved by applying a first pattern (e.g., 0101) to the victim row and a second pattern (e.g., 1010, 0101) to the aggressor row. These patterns may be received from the host device 47. Phase detection and signal averaging may be used to determine the resulting edge of the data eye and average signal level to initiate the training sequences discussed herein.In some embodiments, signal averaging may occur after target level determination has been performed.

[0086] As can be appreciated from the previous discussion, an equalizer (e.g., a DFE) may use a different number of taps than the number of phases. When the number of phases and taps is the same (e.g., 4), the correct number of bits used in the equalizer is inherently stored for use in the equalizer. However, if there are fewer phases than taps, the memory device 10 may buffer at least some bits to have sufficient bit history for use in the equalizer. In other words, the memory device 10 may store the number of bits necessary to store sufficient bit history to satisfy the number of taps used in the equalizer.

[0087] Additionally, although the present application discusses the use of single-ended signaling, memory device 10 may use differential signaling in place of and / or in addition to any of the single-ended signaling techniques discussed herein.

[0088] Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown in the drawings by way of example and described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. On the contrary, the present disclosure is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present disclosure as defined by the following claims.

[0089] Reference is made to the techniques presented and claimed herein and their application to material objects and specific examples of a practical nature that clearly improve the art and are therefore not abstract, intangible or purely theoretical. In addition, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [function] ..." or "steps for [performing] [function] ...", it is intended that such elements should be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements should not be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. A method comprising: using a semiconductor device to self-train an equalizer of the semiconductor device; receiving, at the semiconductor device, an indication of a condition for retraining the equalizer; operating the equalizer based on trained values ​​derived during the self-training; determining, using the semiconductor device, that the condition has been satisfied; and The equalizer is retrained by the semiconductor device without invoking retraining by a host device coupled to the semiconductor device. The method of claim 1 , wherein the semiconductor device comprises a memory device. The method of claim 1 , wherein the equalizer is a decision feedback equalizer.

4. The method of claim 1, wherein the conditions include a duration that has elapsed since the self-training, a monitored temperature that has exceeded a threshold, a voltage that has varied in one direction over a period of time, a monitored voltage that has exceeded a voltage threshold, or a combination thereof.

5. The method of claim 1, wherein retraining comprises determining a voltage or current level to be used in the equalizer. The method of claim 1 , wherein retraining comprises determining tap coefficients to be used in the equalizer.

7. The method of claim 1, wherein self-training includes the host device initiating the self-training, but the semiconductor device handling the remainder of the self-training and retraining without supervision by the host device.

8. The method of claim 1, wherein the condition comprises an indication that the retraining is to continue as long as the retraining is not disabled, and the retraining comprises continuous retraining.

9. The method of claim 8, wherein the continuous retraining comprises retraining disabled memory banks even when other memory banks are active.

10. A semiconductor device comprising: a receiver configured to receive data bits from another device and latch at least some of the data bits in parallel in a first set of latches using a first reference voltage and latch at least some of the data bits in parallel in a second set of latches using a second reference voltage; and A self-calibrating circuit system comprising: analysis circuitry configured to compare corresponding parallel latch bits to determine whether to increment a bit counter; averaging circuitry including a bit counter configured to track the number of increments determined in the analyzing circuitry, and the averaging circuitry configured to track the number of bit comparisons performed in the analyzing circuitry; adder / subtractor circuitry configured to add or subtract a value to or from a current setting to produce a new setting based on the number of counted increments; and A reference voltage generator is used for converting the new setting to generate the first reference voltage.

11. The semiconductor device of claim 10, wherein the semiconductor device comprises a memory device, the other device comprises a host device, and the self-calibration circuitry is configured to generate the first reference voltage without supervision from the host device. 12 . The semiconductor device of claim 10 , wherein determining whether to increment the bit counter comprises determining to increment the bit counter based at least in part on a comparison of logic values ​​of the parallel latch bits.

13. The semiconductor device of claim 10, wherein the adder / subtractor circuitry is configured to receive a step size signal indicative of the value to be added to or subtracted from the current setting to produce the new setting. 14 . The semiconductor device of claim 10 , wherein the semiconductor device comprises a memory device including a plurality of self-calibration circuit systems including the self-calibration circuit system. 15 . The semiconductor device according to claim 14 , comprising a plurality of data lines (DQ) each corresponding to a respective self-calibration circuit system among the plurality of self-calibration circuit systems.

16. The semiconductor device of claim 10, wherein the averaging circuitry comprises a second bit counter configured to track the number of bit comparisons performed and to output a stop signal when the number of bit comparisons reaches a threshold number. 17 . The semiconductor device according to claim 16 , wherein the threshold number is specified by the other device or indicated by one or more fuses of the semiconductor device.

18. A self-calibration circuit system configured to perform self-training in a memory device, wherein the self-calibration circuit system comprises: an input configured to receive first and second latched bits of a single bit capture received from the memory device; analyzing circuitry for comparing the first and second latched bits to determine to increment a first bit counter based on the comparison of the first and second latched bits; A digital averaging circuit system, comprising: the first bit counter configured to track a number of increments determined in the analysis circuitry; and a second bit counter configured to track a number of bit comparisons performed in the analysis circuitry; Adder / subtractor circuitry configured to: receiving a step size signal indicating an increment value; receiving an indication of a previous setting of the equalizer; and adding the increment value to or subtracting the increment value from the previous setting to output a new setting based at least in part on the step size signal, the indication of the previous setting, and the number of increments counted in the first bit counter; and A reference voltage generator is used to convert the new setting to generate a reference voltage.

19. The self-calibration circuit system of claim 18, wherein the new setting comprises a digital code that the reference voltage generator is configured to convert into an analog voltage, and the reference voltage generator comprises a resistance ladder configured to selectively output different voltage levels as the reference voltage based on the digital code.

20. The self-calibration circuitry of claim 19, wherein the self-calibration circuitry is configured to use the analysis circuitry, the digital averaging circuitry, and the adder / subtractor circuitry to determine tap settings for the equalizer using the new setting of the reference voltage.

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