Method for forming semiconductor device

Abstract

Embodiments of the present disclosure provide a method of selectively forming a seed layer on a semiconductor fin. Some embodiments provide a method for forming a selective seed layer using a monosilane at an elevated temperature. Some embodiments also provide a method of depositing a hetero-crystalline silicon cap layer over a bottom-to-top gap layer, thereby improving the filling of the gap and adjusting the profile of the fin structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly to a method for forming a semiconductor device. Background Art

[0002] As semiconductor devices continue to shrink, various process technologies have been developed to form devices with smaller sizes. As semiconductor devices continue to shrink, the spacing between components of the device (i.e., pitch) also shrinks. However, conventional technologies and / or process flows may hinder the reduction of pitch.

[0003] Therefore, there is a need to solve the above problems. Summary of the invention

[0004] The present disclosure provides a method for forming a semiconductor device, including: forming a first semiconductor fin structure and a second semiconductor fin structure; forming a dielectric fin structure between the first semiconductor fin structure and the second semiconductor fin structure; selectively forming a seed layer on the first semiconductor fin structure and the second semiconductor fin structure, wherein the sidewalls of the dielectric fin structure remain exposed after the seed layer is formed; depositing a sacrificial gate electrode layer on the seed layer and the dielectric fin structure; forming a sacrificial gate structure from the sacrificial gate electrode layer; forming a plurality of sidewall spacers on the sacrificial gate structure; etching the first semiconductor fin structure and the second semiconductor fin structure; forming a plurality of epitaxial source / drain regions; removing the sacrificial gate structure; and forming a replacement gate structure between the sidewall spacers.

[0005] Another embodiment of the present disclosure provides a method for forming a semiconductor device, including: forming a first semiconductor fin structure and a second semiconductor fin structure, wherein a first trench is formed between the first semiconductor fin structure and the second semiconductor fin structure; forming a first silicon layer on the first semiconductor fin and the second semiconductor fin structure, wherein the first silicon layer is arranged in the first trench in a bottom-up manner; depositing a first cap layer on the first silicon layer; depositing a second cap layer on the first cap layer, wherein the first cap layer and the second cap layer have different crystal structures; etching the first silicon layer, the first cap layer and the second cap layer to form a sacrificial gate structure; forming multiple sidewall spacers on the sacrificial gate structure; etching the first semiconductor fin structure and the second semiconductor fin structure; forming multiple epitaxial source / drain regions; removing the sacrificial gate structure; and forming a replacement gate structure between the sidewall spacers.

[0006] The disclosed embodiment further includes a method for forming a semiconductor device, comprising: forming two first fin structures, wherein a first trench is formed between the two first fin structures; forming two second fin structures, wherein a second trench is formed between the two second fin structures; forming a dielectric fin structure, wherein the dielectric fin structure is disposed between the first fin structures and the second fin structures, a third trench is formed between the dielectric fin structure and the first fin structures, and the third trench is narrower than the first trenches and the second trenches; selectively forming a seed layer on the first fin structure and the second fin structure, wherein the sidewalls of the dielectric fin structure remain exposed after the seed layer is formed; and forming a gap-fill silicon layer in the first trench, the second trench, and the third trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood with reference to the accompanying drawings and the detailed description below. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion.

[0008] Figure 1-Figure 3 , Figure 4A-4J , Figure 5A-5F , Figure 6A-6C , Figure 7A-7B , Figure 8-Figure 10 as well as Figure 11A-11B According to some embodiments of the present disclosure, side views of a semiconductor device are shown at various stages of forming the semiconductor device.

[0009] Fig.12 is a flow chart illustrating an exemplary method of forming a semiconductor device according to some embodiments of the present disclosure.

[0010] Fig.13 FIG. 4 is a flow chart illustrating an exemplary method for forming a selective seed layer according to some embodiments of the present disclosure.

[0011] The reference numerals are described as follows:

[0012] 100: Semiconductor devices

[0013] 102: Substrate

[0014] 104, 104a, 104b: Fin structure

[0015] 106a, 106b: well portion

[0016] 108a, 108b: Fin part

[0017] 110, 110a, 110b, 112, 112a, 112b: Grooves

[0018] 114: Isolation layer

[0019] 116: Lining

[0020] 118: Dielectric filling layer

[0021] 120: Dielectric fins

[0022] 120s: Sidewall

[0023] 122: Sacrificial gate dielectric layer

[0024] 124, 1240: Seed layer

[0025] 1241, 1243: continuous portion

[0026] 1242: discontinuous portion

[0027] 1244: agglomerate

[0028] 126, 1261, 1262, 126n: Silicon layer

[0029] 128: First silicon cap layer

[0030] 130: Second silicon cap layer

[0031] 132: Sacrificial gate electrode layer

[0032] 134: cushion

[0033] 136: Mask layer

[0034] 138: Sacrificial gate structure

[0035] 140: Sidewall spacer

[0036] 142: Source / drain groove

[0037] 144: Epitaxial source / drain region

[0038] 146: Contact etch stop layer (CESL)

[0039] 148: Interlayer dielectric layer (ILD layer)

[0040] 150: Replacement gate structure

[0041] 152: Gate dielectric layer

[0042] 154: Gate electrode layer

[0043] 156: Self-aligned contact layer (SAC layer)

[0044] 158: Source / drain contact parts

[0045] 160: Gate contact parts

[0046] 200, 300: Method

[0047] 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 302, 304, 306: Step 408, 410: Area

[0048] 402, 404, 406: Curve

[0049] AA, BB: Line

[0050] H1: Height

[0051] W1, W2, W1', W2', W3, W4: Width DETAILED DESCRIPTION

[0052] The following disclosure provides many embodiments or examples for implementing different elements of the present disclosure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, if the description mentions that a first element is formed on or above a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0053] Furthermore, spatially relative terms may be used, such as "below", "beneath", "below", "above", "above", "top", "upper", and the like, to facilitate describing the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0054] The following is a general description of some aspects of the embodiments described in the present disclosure. Although some of the embodiments described herein are based on nanosheet channel field-effect transistors (nanosheet channel FETs), the implementation of some aspects of the present disclosure may also be used in other processes and / or other devices, such as planer FETs, fin FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices. Those with ordinary knowledge in the art will readily understand that other modifications that may be made are also within the scope of the present disclosure. Furthermore, although the method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein. In the present disclosure, source / drain refers to source and / or drain. Source and drain may be used interchangeably.

[0055] The gap-filling process is used in various stages of FinFET manufacturing. For example, a sacrificial gate electrode layer is deposited in the trench between the fin structures. As the dimensions of semiconductor devices decrease, the aspect ratio of the trench in FinFET also increases, resulting in more challenges in gap filling through the trench. The aspect ratio is even higher in the trench between the semiconductor fin and the dielectric fin. An embodiment of the present disclosure provides a method for gap filling. In some embodiments, before performing the gap filling deposition process in a bottom-up manner, a seed layer can be deposited so that it is selectively formed on the sidewalls of the trench. Compared to a uniform seed layer, the selective seed layer of the present disclosure reduces the increase in the aspect ratio by virtue of the seed layer before the gap filling. In some embodiments, a heteroepitaxial cap layer is used on top of the bottom-up gap filling layer. For example, the cap layer according to the present disclosure may include an amorphous silicon (a-Si) layer and a crystalline silicon (c-Si) layer. The profile of the semiconductor fin may be adjusted by selecting a combination of heteroepitaxial cap layers. For example, a-Si may be selected to reduce the outward bending of the fin structure, and c-Si may be selected to achieve the outward bending of the fin structure.

[0056] Figure 1-Figure 3 , Figure 4A-4J , Figure 5A-5F , Figure 6A-6C , Figure 7A-7B , Figure 8-Figure 10 and Figure 11A-11B 1 is a diagram illustrating various stages of manufacturing a semiconductor device 100 according to a method of the present disclosure. In particular, Figure 1-Figure 3 , Figure 4A-4J , Figure 5A-5F , Figure 6A-6C , Figure 7A-7B , Figure 8-Figure 10 and Figure 11A-11B FIG. 1 is a schematic diagram illustrating a semiconductor device 100 during various stages of forming the semiconductor device according to some embodiments of the present disclosure. Fig.12 FIG. 2 is a flow chart illustrating an exemplary method 200 of forming a semiconductor device according to an embodiment of the present disclosure. As discussed below, the semiconductor device 100 may be manufactured using the method 200 .

[0057] like Figure 1 As shown, in step 202 of method 200 , the fin structure 104 is formed on the substrate 102 . Figure 1 2 is a side view of the semiconductor device 100 after step 202. The substrate 102 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Depending on the circuit design, the substrate 102 may include various doping configurations. For example, different doping profiles (e.g., n-well, p-well) may be formed in regions of the substrate 102 designed for different device types (e.g., n-type field effect transistor (NFET) and p-type field effect transistor (PFET)). In some embodiments, the substrate 102 may be a silicon-on-insulator (SOI) substrate including an insulating structure for enhancement.

[0058] In some embodiments, depending on the type of device to be formed, the fin structure 104 may be formed by depositing an epitaxial semiconductor layer on the substrate 102, followed by one or more patterned layers of lithography and etching processes. In some embodiments, the fin structure 104 may include a fin structure 104a for a first type of device, and a fin structure 104b for a second type of device.

[0059] Each fin structure 104a may include a well portion 106a formed in a first well region of the substrate 102, and a fin portion 108a formed from an epitaxially grown layer on the substrate 102. The fin portion 108a may include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon (Si), or other epitaxially grown semiconductor materials, such as germanium (Ge); compound semiconductors, such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. In some embodiments, the fin structure 104a serves as a channel region for an N-type device. The well portion 106a may include a p-type dopant. The fin portion 108a of the fin structure 104a may include epitaxially grown silicon.

[0060] Each fin structure 104b may include a well portion 106b formed in the second well region of the substrate 102, and a fin portion 108b formed from an epitaxially grown layer on the substrate 102. The fin portion 108b may include: epitaxially grown silicon (Si), epitaxially grown silicon germanium (SiGe), or other epitaxially grown semiconductor materials, such as germanium (Ge); compound semiconductors, such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. In some embodiments, the fin structure 104b is a channel region for a P-type device. The well portion 106b may be formed in an n-type well and include an n-type dopant. The fin portion 108b of the fin structure 104b may include epitaxially grown silicon germanium.

[0061] The fin structure 104 extends from the substrate 102 and forms a groove between adjacent fins. Figure 1 As shown, trench 110a is formed between adjacent fin structures 104a, trench 110b is formed between adjacent fin structures 104b, and trench 112 is formed between adjacent fin structures 104a and 104b. Trench 112 is wider than trench 110a and trench 110b. In some embodiments, dielectric fins may be subsequently formed in trench 112 to isolate transistors on opposite sides of trench 112.

[0062] In step 204, if Figure 2 As shown, isolation layers 114 are formed in the trenches 110 and 112 between the fin structures 104 , and dielectric fins 120 are formed in the trenches 112 between the fin structures 104 . Figure 2is a side view of the semiconductor device 100 after step 204 .

[0063] The isolation layer 114 may be formed in the trenches between the fin structures 104 by a suitable deposition process followed by an etch back process. As an example, the bottom profile of the isolation layer 114 is depicted as a curve. Depending on the pitch and / or height of the fin structures 104, the bottom profile of the isolation layer 114 may be different, such as a curve, substantially flat, or other shapes. The isolation layer 114 may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 114 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, or a combination thereof.

[0064] In some embodiments, the isolation layer 114 may be conformally formed. After the isolation layer 114 is deposited, the narrower trenches 110a and 110b may be completely filled, and the wider trench 112 may be partially filled, so that the dielectric fin 120 may be formed therein. In some embodiments, a liner 116 and a dielectric filling layer 118 may then be sequentially deposited on the isolation layer 114 to fill the trench 112. The liner 116 may be selected from a dielectric material having etching selectivity to allow the isolation layer 114 to be etched back. In some embodiments, the liner 116 and the dielectric filling layer 118 may include a low-k material, such as SiONC, SiCN, SiOC, or other dielectric materials, to provide etching resistance during the replacement gate process.

[0065] After the trenches 110 and 112 between the fin structures 104 are filled, a planarization process may be performed to expose the fin structures 104, and then an anisotropic etching process may be used to etch the grooves to remove a portion of the isolation layer 114. After etching the grooves, the fin portions 108a and 108b of the fin structures 104a and 104b are exposed and extended from the isolation layer 114. The dielectric fins 120 are formed in the trenches 112. Figure 2 In the example shown, the dielectric fin 120 extends from the isolation layer 114 . In some embodiments, the liner layer 116 may be etched out from the dielectric fill layer 118 , such that the sidewalls of the dielectric fin 120 include the dielectric fill layer 118 .

[0066] The dielectric fin 120, also referred to as a dummy fin or a hybrid fin, may include one or more layers of dielectric material sequentially deposited within the trench 112. For example, the dielectric fin 120 may include a high-k dielectric material layer, such as HfO2, ZrO2, HfAlO x 、HfSiO x , Al2O3, and the like; a low-k dielectric material layer, SiONC, SiCN, SiOC, or other dielectric material; or a double layer of dielectric material including a high-k upper portion and a low-k lower portion. As discussed below, in some embodiments, the outer layer of the dielectric fin 120 can be selected from a material that facilitates the selective formation of a seed layer. In some embodiments, the sidewall 120s of the dielectric fin 120 includes SiCN. In some embodiments, the sidewall 120s of the dielectric fin 120 includes SiCN, and its carbon molar concentration ranges from about 8% to about 16%, for example, about 12%.

[0067] After step 204, the fin structure 104 has a height H1 along the Z direction above the isolation layer 114. The height H1 may be changed according to the circuit design. In some embodiments, the height H1 ranges from about 20 nm to about 100 nm. The grooves 110a and 110b have a width W1 along the Y direction. In some embodiments, the width W1 ranges from about 3 nm to about 5 nm.

[0068] In some embodiments, the dielectric fin 120 may extend from the isolation layer 114 so that its height H1 is substantially the same as the fin structure 104. The trenches 112a and 112b are formed on opposite sides of the dielectric fin 120. In some embodiments, the trenches 112a and 112b have a width W2 along the Y direction. In some embodiments, the width W2 ranges from about 3 nm to about 50 nm. In some embodiments, the width W2 may be narrower than the width W1.

[0069] In step 206, if Figure 3 As shown, a sacrificial gate dielectric layer 122 is formed over the fin structure 104 . Figure 3 is a cross-sectional view of the semiconductor device 100 after step 206. A sacrificial gate dielectric layer 122 is formed over the fin structure 104. The sacrificial gate dielectric layer 122 may include an oxide of a semiconductor material. In some embodiments, the sacrificial gate dielectric layer 122 may be thermally grown from the fin structure 104 according to acceptable techniques, such as thermal CVD, CVD, atomic layer deposition (ALD), and other suitable methods.

[0070] In some embodiments, the sacrificial gate dielectric layer 122 may have a thickness ranging from about 1 nm to about 3 nm. Figure 3As shown, after the sacrificial gate dielectric layer 122 is formed, the widths of the trenches 110a, 110b, and 112a, 112b may be reduced to width W1' and width W2', respectively. The aspect ratio of the trenches 110a, 110b, and 112a, 112b (i.e., the ratio of the height H1 of the fin to the width W1' and the width W2') may increase. In some embodiments, the aspect ratio of the trenches 110a, 110b, and 112a, 112b may be greater than 5. A larger aspect ratio may make it difficult to fill the trenches 110a, 110b, and 112a, 112b with a sacrificial gate layer. For example, seams and / or voids may be formed in the sacrificial gate electrode layer. The seams and voids may cause the epitaxial source / drain or source / drain to contact and sip into the gate structure, thereby causing leakage. Steps 208 to 214 provide an improved gap-filling process to form a sacrificial gate electrode layer between the trenches 110a, 110b and the trenches 112a, 112b on the fin structure 104.

[0071] In step 208, if Figure 4A-4C As shown, the seed layer 124 is selectively formed on the fin structure 104. In particular, the seed layer 124 is formed on the sidewalls of the fin structure 104, but is not limited to being formed on the sidewalls 120s of the dielectric fin. By selectively forming the seed layer 124 on the semiconductor fin structure 104, the embodiments of the present disclosure avoid further increasing the aspect ratio of the trenches (e.g., trench 112a, trench 112b) between the semiconductor fin and the dielectric fin. Figure 4A-4C 1 and 2 are cross-sectional views of the semiconductor device 100 at various stages of forming the seed layer 124 .

[0072] In some embodiments, the seed layer 124 may be formed by a deposition process, an etching process, and a surface treatment. Fig.13 The illustrated method 300 proceeds to step 208 .

[0073] like Figure 4AAs shown, the method 300 includes step 302, which performs a non-uniform deposition process to deposit a seed layer 1240 on the semiconductor device 100. The seed layer 1240 includes a thicker continuous portion 1241 formed on the semiconductor fin structure 104, and a thinner discontinuous portion 1242 formed on the dielectric fin 120. In some embodiments, the seed layer 1240 is a silicon seed layer. In some embodiments, the seed layer 1240 can be a silicon layer without other elements, such as germanium, n-type impurities (such as phosphorus and arsenic), and p-type impurities (boron and indium). In some embodiments, the thicker and continuous portion 1241 of the seed layer 1240 can have a range of about to about The thinner and discontinuous portion 1242 of the seed layer 1240 may have a discontinuous silicon monoatomic layer.

[0074] The seed layer 1240 may be deposited using a suitable deposition process, such as atomic layer deposition (ALD). Depending on the surface composition of the fin structure 104 and the dielectric fin 120, non-uniform or selective deposition may be achieved by selecting suitable precursors and suitable process conditions. In some embodiments, the seed layer 1240 may be deposited using single crystal silicon containing precursors at an elevated temperature to reduce the deposition rate on the sidewalls 120s of the dielectric fin 120. In some embodiments, when the sidewalls 120s of the dielectric fin 120 include SiCN and the fin structure 104a and the fin structure 104b are Si and SiGe, the seed layer 1240 may be deposited using monosilane (SiH4). The above deposition may be performed at a temperature ranging from about 460°C to about 480°C (e.g., about 470°C).

[0075] The method 300 further includes a step 304 performed after the step 302. In the step 304, an etching process may be performed to remove a portion of the seed layer 1240. In some embodiments, as shown in FIG. 4B , an ex-situ dry etching process may be performed to substantially remove the thinner and discontinuous portion 1242 of the seed layer 1240.

[0076] In some embodiments, the dry etching process may be an isotropic etching process. In some embodiments, the etching gas may include a mixture of chlorine (Cl2) and nitrogen (N2), a mixture of fluorine (F2) and nitrogen (N2), or a mixture of NF3, H2 and helium (He), or HCl. In some embodiments, the etching may be performed using a reactive ion etch (RIE). In some embodiments, the etching process may be performed for a period of about 3 seconds to about 8 seconds, for example, about 5 seconds.

[0077] like Figure 4B As shown, after the etching process in step 304, the thinner and discontinuous portion 1242 of the seed layer 1240 can be substantially removed from the dielectric fin 120. The thicker and continuous portion 1241 of the seed layer 1240 is reduced to a continuous portion 1243 having a thickness in the range of about to about In some embodiments, agglomerates 1244 may be formed on the surface of the semiconductor device 100 , such as on the sidewalls 120 s of the dielectric fins 120 .

[0078] like Figure 4C As shown, the method 300 further includes step 306, which performs surface treatment to remove particles and accumulations 1244. In some embodiments, the surface treatment in step 306 can be a selective surface treatment to achieve highly selective surface property modification, such as selectively removing surface accumulations 1244. In some embodiments, the surface treatment can be performed by flowing inert atoms (such as argon) over the surface of the semiconductor device 100 into the process chamber to generate a very mild free radical plasma to remove the accumulations 1244. For example, the free radicals used during the surface treatment have an energy in the range of about 1% to about 10% of the plasma energy level during plasma etching. For example, the free radicals can be argon atoms with an energy level of about 11.7 eV. In some embodiments, the surface treatment can be performed using the Argos system of Lamb Technologies, Inc.

[0079] Figure 4C The semiconductor device 100 is shown after step 208. Figure 4C As shown, a seed layer 124 is selectively formed over the semiconductor fin structure 104 , but no seed layer is formed over the dielectric fin 120 .

[0080] It has been demonstrated that when forming a dielectric fin having a surface comprising SiCN and utilizing monosilane as a precursor to deposit a silicon seed layer, a silicon seed layer can be selectively deposited on the semiconductor fin. Figure 4D-4F is a dotted line graph of the surface composition using X-ray photoelectron spectroscopy (XPS) on a SiCN surface having 12% molar carbon under different deposition conditions. Figure 4D, curve 402 is a curve representing the standardized surface composition of SiCN using disilane (Si2H6) as a precursor; curve 404 is a curve representing the standardized surface composition of SiCN using monosilane as a precursor, and the deposition time is 18 minutes; curve 406 is a curve representing the standardized surface composition of SiCN using monosilane as a precursor, and the deposition time is 34 minutes. As shown in curve 402, using disilane as a precursor can form a silicon seed layer with an energy level Si0 represented as a peak. In contrast, there is no peak at the energy level Si0 along curves 404 and 406, indicating that if monosilane is used as a precursor, a silicon seed layer will not be formed on the SiCN surface, even if the deposition time is nearly twice as long. Figure 4E and Figure 4F It is an enlarged graph showing the concentration of curve 404 and curve 406 in Si0.

[0081] In some embodiments, the seed layer 124 may have a thickness ranging from about to about The seed layer 124 reduces the width of the trenches between the semiconductor fins (i.e., trenches 110a and 110b) from width W1 to width W3, and reduces the width of the trenches between the semiconductor fins and the dielectric fins (i.e., trenches 112a and 112b) from width W2 to width W4. The reduction from width W1 to width W3 is greater than the reduction from width W2 to width W4.

[0082] Figure 4G 1 is a cross-sectional view of a fin structure of an exemplary device having a selectively deposited silicon seed layer according to some embodiments of the present disclosure. The silicon seed layer 124 is formed on the sidewalls of the semiconductor fin structure 104a and the fin structure 104b. As shown in regions 408 and 410, the silicon seed layer 124 is not grown on the sidewalls 120s of the dielectric fin 120.

[0083] Figure 4H The top view of the fin structure before and after forming the seed layer 124 in step 208 is shown. Figure 4HAs shown, after forming the seed layer 124, the width of the semiconductor fin structure 104 will increase by twice the thickness of the seed layer 124, while the width of the dielectric fin 120 will not increase. In some embodiments, during the post-deposition etching of step 304 and the surface treatment of step 306, the dielectric fin 120 will shrink. Therefore, the width of the grooves 110a and 110b will be reduced by about two thicknesses of the seed layer 124, and the width of the grooves 112a and 112b adjacent to the dielectric fins will be reduced by at most one thickness of the seed layer 124. Since the dielectric fin 120 will lose some thickness, after step 208, the overall width W4 of the grooves 112a and 112b will increase by about 1 nm from the width W2. Therefore, compared to the deposition of a uniform seed layer, the embodiments of the present disclosure increase the spacing between the trenches 112a and 112b between the dielectric fin 120 and the semiconductor fin 104.

[0084] In some embodiments, when the semiconductor fin structure 104 includes Ge (e.g., SiGe), the deposition of the silicon seed layer according to the present disclosure can improve the abruptness of Ge, thereby preventing the diffusion of Ge and the oxidation of SiGe. Therefore, the silicon seed layer 124 according to the present disclosure can improve the interface trap density (Dit) of the germanium-containing channel.

[0085] Figure 4I-4J The normalized germanium steepness corresponding to silicon seed layers formed with disilane and monosilane at different temperatures is plotted. In particular, Figure 4I-4J Including: the Ge steepness of the silicon seed layer formed using disilane at 380°C, 405°C, and 415°C, and the Ge steepness of the silicon seed layer formed using monosilane at 450°C, 470°C, 485°C, and 500°C. Fig. 4I Showing the steepness of Ge deposited on amorphous silicon. Figure 4J The steepness of the Ge in the subsequent anneal is shown. Without wishing to be bound by theory, at low temperatures there is less segregation of Ge, while at high temperatures the material tends to complete the lattice structure before Ge segregation. Fig. 4I and Figure 4J As shown, the silicon seed layer formed using disilane at 405°C has a better Ge steepness during amorphous silicon deposition and annealing than the silicon seed layer formed using disilane at 380°C. The silicon seed layer formed using disilane at 415°C and the silicon seed layer formed using monosilane at 470°C have comparable Ge steepness during amorphous silicon deposition and better Ge steepness during annealing compared to the silicon seed layer formed using disilane at 380°C.

[0086] In step 210, if Figure 5A-5CAs shown, a bottom-up gap deposition may be performed to form a silicon layer 126 on the fin structure 104, the dielectric fin 120, and in the trenches 110 and 112. In some embodiments, the silicon layer 126 may be formed by one or more deposition-annealing-etching cycles to achieve bottom-up gap filling in the trenches 110 and 112. Figure 5A-5C The semiconductor devices are after the first, second and final deposition-annealing-etching cycles, respectively.

[0087] After forming the silicon seed layer 124, silicon may be grown on the silicon seed layer 124 using a silicon-containing precursor, such as disilane (Si2H6), monosilane (SiH4), or a mixture of disilane and monosilane. The temperature range for growing the silicon layer using disilane may be about 350°C to about 400°C. The temperature range for growing the silicon layer using monosilane may be about 400°C to about 500°C. Depending on the temperature, the growth rate of the silicon layer 126, and other process conditions, the silicon layer 126 may be an amorphous silicon layer or a polycrystalline silicon layer. During the deposition step of each deposition-annealing-etching cycle, the silicon layer 126 may be formed as a conformal layer.

[0088] After deposition, annealing may be performed. In some embodiments, annealing may be performed at a temperature ranging from about 450° C. to about 600° C. Depending on the temperature, annealing may last from about 2 minutes to about 2 hours, with higher temperatures corresponding to shorter annealing times and lower temperatures corresponding to longer annealing times. During annealing, process gases such as nitrogen (N2) and hydrogen (H2) may be introduced. Annealing causes silicon atoms to migrate. The migration of silicon atoms may involve annealing to break the bonds of hydrogen atoms (derived from precursors) from silicon atoms. Silicon atoms with dangling bonds on the surface tend to migrate to higher surface energies or lower potentials, and ultimately reduce the total system energy by filling trenches 110 and trenches 112. Silicon atoms with dangling bonds on the surface may then combine with other silicon atoms. The migration of silicon atoms from a higher location to a lower location is similar to the reflow of silicon, although the silicon at the annealing temperature is not molten or partially molten. The migration of silicon atoms creates a bottom-up effect, that is, more silicon migrates to the bottom of the trench, which is equivalent to growing silicon from the bottom up. In addition, the migration of silicon smoothes the sidewalls of the silicon layer 126 and reduces or eliminates the necking profile near the entrance of the trench 110 and the trench 112.

[0089] After the annealing process, an etch-back process may be performed on the silicon layer 126 to form an improved trench profile (i.e., more V-shaped) for a subsequent gap-filling process. In some embodiments, the etch-back process may be performed using an etching gas, such as one containing chlorine (Cl2), such as a mixture of chlorine (Cl2) and nitrogen (N2), a mixture of fluorine (F2) and nitrogen (N2), or a mixture of NF3, H2 and helium (He), or HCl. In some embodiments, the etch-back is an isotropic etch, such as one in which no bias power is applied in the etching chamber during the etch-back process.

[0090] like Figure 5A-5C As shown, in each deposition-annealing-etching cycle, silicon layer 1261, silicon layer 1262, silicon layer 126 n The profile of the trenches 110 and 112 is rounded and has a larger thickness at the bottom of the trenches 110 and 112. In the deposition-annealing-etching cycle of step 210, the profile of the silicon layer 126n in the trenches 110 and 112 is V-shaped and can be filled by bulk deposition.

[0091] It has been observed that during bottom-up deposition, the fin structure 104 may bend due to unbalanced forces on opposite sides of the fin structure 104 . Figure 5D 1 is a schematic diagram of a semiconductor device 100 having an outwardly curved fin structure 104 after a silicon layer 126 is deposited from bottom to top. Figure 5D As shown, the trench 112 between the fin structure 104 and the dielectric fin 120 is narrower than the trench 110 between the fin structures 104. The silicon layer 126 fills the narrower trench 112 faster than the wider trench 110. Therefore, the fin structure 104 bends outward from the trench 110 toward the dielectric fin 120.

[0092] Figure 5E It is a schematic diagram of a transmission electron microscope (TEM) image of a semiconductor device after the isolation layer is etched back. Fig. 5F FIG. 1 is a schematic diagram showing a TEM image of a semiconductor device after the silicon layer 126 is formed according to an embodiment of the present disclosure. Figure 5E and Fig. 5F , the silicon layer 126 causes the semiconductor fin structure 104 to bend outward from each other to the adjacent dielectric fin 120. According to an embodiment of the present disclosure, the bending of the semiconductor fin structure 104 can be reduced or controlled by selecting a suitable silicon cap layer or layers above the silicon layer 126. For example, an amorphous silicon cap layer can be deposited on the silicon layer 126 to reduce the outward bending of the fin structure 104.

[0093] like Fig. 6AAs shown, in step 212 , a first silicon capping layer 128 is deposited on the silicon layer 126 . Fig. 6A is a schematic cross-sectional view of the semiconductor device 100. The first silicon capping layer 128 may be formed by blanket deposition to fill the remaining areas in the trenches 110 and 112. In some embodiments, the first silicon capping layer 128 may have a thickness ranging from about 5 nm to about 20 nm, for example, about 10 nm.

[0094] In some embodiments, the first silicon capping layer 128 may be deposited using a silicon-containing precursor, such as disilane (Si2H6), monosilane (SiH4), or a mixture of disilane and monosilane. Depending on the temperature and other process conditions, the first silicon capping layer 128 may be an amorphous silicon layer or a crystalline silicon layer. In some embodiments, the temperature used to grow the first silicon capping layer 128 may be selected to produce a desired crystal structure.

[0095] In some embodiments, the first silicon capping layer 128 is an amorphous silicon layer to reduce the outward bowing of the fin structure 104. For example, the first silicon capping layer 128 may be deposited at a temperature ranging from about 450°C to about 500°C using monosilane as a precursor.

[0096] like Figure 6B As shown, in step 214 , a second silicon capping layer 130 may be deposited on the first silicon capping layer 128 . Figure 6B is a schematic cross-sectional view of the semiconductor device 100. The second silicon capping layer 130 may be formed by blanket deposition to achieve a target thickness for forming a sacrificial gate electrode. In some embodiments, the second silicon capping layer 130 may have a thickness ranging from about 150 nm to about 250 nm, for example, about 185 nm. In some embodiments, the second silicon capping layer 130 may be deposited using a silicon-containing precursor, such as disilane (Si2H6), monosilane (SiH4), or a mixture of disilane and monosilane. Depending on the temperature and other process conditions, the second silicon capping layer 130 may be an amorphous silicon layer or a crystalline silicon layer. In some embodiments, the temperature used to grow the second silicon capping layer 130 may be selected to produce a desired crystal structure.

[0097] In some embodiments, the second silicon capping layer 130 is a crystalline silicon layer, such as a polysilicon layer. The crystal structure in the second silicon capping layer 130 can interact with the first silicon capping layer 128 to remove any seams between the trench 110 and the trench 112. In some embodiments, the second silicon capping layer 130 can be deposited at a temperature greater than 500° C. (e.g., in a range of about 500° C. to about 700° C.) using monosilane as a precursor.

[0098] In some embodiments, the first silicon capping layer 128 and the second silicon capping layer 130 may be deposited in the same process chamber. For example, when the first silicon capping layer 128 is deposited to a target thickness, the process conditions may be changed, such as increasing the process temperature to greater than 500° C., to deposit the second silicon capping layer 130 .

[0099] like Figure 6B As shown, the first silicon capping layer 128 and the second silicon capping layer 130 according to the present disclosure have different crystal structures. The different crystal structure arrangements in the capping layers enable a void-free sacrificial gate layer to be deposited in a trench with a high aspect ratio.

[0100] Figure 6C Cartoons showing the gap-filling results using capping layers of different crystal structures. Figure 6C In, Figures (a) and (b) depict deposition in a bottom-up manner in a trench between two semiconductor fins. According to the present disclosure, step 210 can be used for bottom-up filling. As shown in Figure (b), the bottom-up deposition results in amorphous silicon in the trench. Figure (c) shows that if a silicon cap layer with amorphous silicon is deposited after the bottom-up deposition of Figure (b), a seam is formed in the trench. Figure (d) shows that if a silicon cap layer with crystalline silicon is deposited after the bottom-up deposition of Figure (b), a hole is formed in the trench. The hole may be caused by the outward bending effect of the fin of the crystalline silicon layer. Figure (e) shows that if a cap layer with heterogeneous crystals is deposited after the bottom-up deposition of Figure (b), a seam-free and hole-free silicon can be formed in the trench. In particular, depositing a cap layer including an amorphous sublayer and a crystalline sublayer can improve gap filling.

[0101] like Fig. 7A and Figure 7B As shown, a sacrificial gate structure 138 is formed in step 216 . Fig. 7A It is along Figure 7B 1 is a cross-sectional view of the semiconductor device 100 taken along line AA. Figure 7B It is along Fig. 7A 1 is a cross-sectional view of the semiconductor device 100 taken along line BB.

[0102] The seed layer 124, the silicon layer 126, the first silicon cap layer 128 and the second silicon cap layer 130 may be collectively referred to as a sacrificial gate electrode layer 132. In some embodiments, after the second silicon cap layer 130 is deposited, a planarization process may be performed, such as a chemical mechanical planarization (CMP) process, to form a Fig. 7AThe sacrificial gate electrode layer 132 is shown. In some embodiments, a pad layer 134 and a mask layer 136 may be sequentially deposited on the sacrificial gate electrode layer 132. The pad layer 134 may include silicon nitride. The mask layer 136 may include silicon oxide. A patterning step may be performed on the mask layer 136, the pad layer 134, the sacrificial gate electrode layer 132, and the sacrificial gate dielectric layer 122A using one or more etching processes (e.g., one or more plasma etching processes or one or more wet etching processes) to form a sacrificial gate structure 138. In some embodiments, the mask layer 136 and the pad layer 134 may be patterned using a patterning process, and then the sacrificial gate electrode layer 132 may be patterned using the patterned mask layer 136 and the pad layer 134 as etching masks. In some embodiments, the sacrificial gate electrode layer 132 may be etched by anisotropic etching (e.g., reactive ion etching (RIE) process). Anisotropic etching has a faster etching rate in the Z direction than in the X and Y directions. During the etching of the sacrificial gate electrode layer 132, the sacrificial gate dielectric layer 122 on the fin structure 104 can act as an etch stop layer to prevent the etchant from removing the fin structure 104. The sacrificial gate structure 138 covers a portion of the fin structure 104. The portion of the fin structure 104 covered by the sacrificial gate structure 138 will eventually form a channel region for the formed FinFET.

[0103] like Figure 8 As shown, in step 218 , sidewall spacers 140 are formed on the sacrificial gate structure 138 . Figure 8 It is along Figure 7B A schematic cross-sectional view of the semiconductor device 100 taken along line AA.

[0104] The sidewall spacers 140 may be formed by depositing one or more dielectric layers by ALD, CVD, or other suitable methods. The dielectric layer may include a suitable dielectric material, such as silicon oxide, silicon oxynitride, or a combination thereof. The dielectric layer may be formed by sequentially performing blanket deposition. In some embodiments, an anisotropic etch may be performed to remove the dielectric layer from the horizontal plane so that the sidewall spacers 140 are located on the sidewalls of the sacrificial gate structure 138.

[0105] like Figure 8 As shown, in step 220, the fin structure 104 in the source / drain region or the region not covered by the sacrificial gate structure 138 and the sidewall spacer 140 is recessed. In some embodiments, suitable dry etching and / or wet etching may be used to remove the semiconductor material in the fin structure 104. In some embodiments, the fin structure 104a and the fin structure 104b may be recessed to below the isolation layer 114. Figure 8 As shown, source / drain recesses 142 are formed on both sides of the sacrificial gate structure 138 .

[0106] like Fig. 9 As shown, in step 222 , epitaxial source / drain regions 144 are formed in the source / drain recesses 142 . Fig. 9 It is along Figure 7B Schematic diagram of a cross-section of the semiconductor device 100 taken along line AA. The epitaxial source / drain regions 144 may be formed by any suitable method, such as CVD, CVD epitaxy, molecular beam epitaxy (MBE), or other suitable deposition techniques. The epitaxial source / drain regions 144 may include one or more layers of Si, SiP, SiC, and SiCP for n-type devices, or one or more layers of Si, SiGe, Ge for p-type devices. The epitaxial source / drain regions 144 for n-type devices may also include n-type dopants, such as phosphorus (P), arsenic (As), etc. The epitaxial source / drain regions 144 for p-type devices may include p-type dopants, such as boron (B).

[0107] The epitaxial source / drain region 144 may be grown in the epitaxial chamber by a suitable process. For example, the epitaxial source / drain region 144 may be formed by a selective etching and growth process, wherein a thin film is deposited by introducing a reaction gas including both a deposition agent and an etching agent. In some embodiments, an optional etching process may be performed to achieve a desired shape and / or thickness of the epitaxial layer to be formed.

[0108] like Fig.10 As shown, in step 224 , a contact etch stop layer (CESL) 146 and an interlayer dielectric layer (ILD layer) 148 are formed on the semiconductor device 100 . Fig.10 It is along Figure 7B Schematic diagram of a cross-section of the semiconductor device 100 taken along line AA. A contact etch stop layer 146 is conformally formed on the exposed surface of the semiconductor device 100. The contact etch stop layer 146 is formed on the exposed epitaxial source / drain regions 144, the sidewall spacers 140, and the isolation layer 114. The contact etch stop layer 146 may include SiN, SiON, SiCN, or any other suitable material, and may be formed by CVD, PVD, or ALD.

[0109] An interlayer dielectric layer 148 is formed on the contact etch stop layer 146. The material of the interlayer dielectric layer 148 includes a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials (such as polymers) can be used for the interlayer dielectric layer 148. In some embodiments, the interlayer dielectric layer 148 can be formed by FCVD. The interlayer dielectric layer 148 protects the epitaxial source / drain region 144 during the removal of the sacrificial gate structure 138.

[0110] like Fig.11A and Fig. 11B As shown, a replacement gate structure 150 is formed in step 226 . Fig.11A It is along Fig. 11B A cross-sectional view of the semiconductor device 100 taken along line AA. Fig. 11B It is along Fig.11A A cross-sectional view of the semiconductor device 100 taken along line BB. The sacrificial gate dielectric layer 122 and the sacrificial gate electrode layer 132 may be removed by one or more suitable processes, such as dry etching, wet etching, or a combination thereof, to expose the fin structure 104. In some embodiments, a wet etchant such as tetramethylammonium hydroxide (TMAH) may be used. The replacement gate structure 150 may include a gate dielectric layer 152 and a gate electrode layer 154. Optionally, the replacement gate structure may include a self-aligned contact layer (SAC layer) 156.

[0111] A gate dielectric layer 152 may be conformally deposited on the surface exposed in the gate cavity. The gate dielectric layer 152 may have different compositions and dimensions for n-type devices and p-type devices, and may be formed using patterned mask layers and different deposition recipes, respectively. The gate dielectric layer 152 may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k materials, other suitable dielectric materials, and / or combinations thereof. Example high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 152 may be formed by CVD, ALD, or other suitable methods.

[0112] The gate electrode layer 154 is then formed on the gate dielectric layer 152 to fill the gate cavity. The gate electrode layer 154 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 154 may be formed by CVD, ALD, electroplating, or other suitable methods. After the gate electrode layer 154 is formed, a planarization process (e.g., CMP) may be performed to remove excess gate electrode material deposition and expose the top surface of the interlayer dielectric layer 148.

[0113] In some embodiments, a metal gate etching back (MGEB) process may be performed to form a self-aligned contact layer 156. One or more etching processes may be performed to remove a portion of the gate dielectric layer 152 and the gate electrode layer 154 to form a trench in the remaining area above the gate electrode layer 154. The MGEB process may be a plasma etching process using one or more etchants, such as a chlorine-containing gas, a bromine-containing gas, and / or a fluorine-containing gas. The etching process selectively etches the gate dielectric layer 152 and the gate electrode layer 154 from the interlayer dielectric layer 148 and the contact etch stop layer 146.

[0114] After the trench is filled with the self-aligned contact layer 156, a planarization process (eg, a CMP process) may be performed to remove excess self-aligned contact layer 156 deposition to expose the top surface of the interlayer dielectric layer 148. Fig.11A and Fig. 11B As shown, source / drain contact features 158 and gate contact features 160 are formed.

[0115] Reference Fig.11A The profile of the fin structure 104 in the replacement gate structure 150 may reflect the following: Fig. 5F For example, the fin structures 104 may bend outward from each other toward the adjacent dielectric fins 120 .

[0116] The various embodiments or examples discussed herein provide multiple advantages over the prior art. Embodiments of the present disclosure provide methods for selectively forming a seed layer over a semiconductor fin, thereby reducing the aspect ratio and enhancing and improving the quality of the gap fill. By forming a selective seed layer using monosilane at an elevated temperature, the embodiments of the present disclosure also improve the germanium steepness, prevent germanium diffusion or oxidation in the channel region, and ultimately improve the trap density in the channel region. During the formation of the sacrificial gate electrode, the embodiments of the present disclosure further improve the gap fill by depositing a heterogeneous crystalline silicon cap layer over the gap layer formed from the bottom up. The heterogeneous crystalline silicon cap layer can also adjust the profile of the semiconductor fin.

[0117] It should be understood that not all advantages of the present disclosure need to be discussed herein, nor are specific advantages necessary for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0118] Some embodiments of the present disclosure are related to a method for forming a semiconductor device, including: forming a first semiconductor fin structure and a second semiconductor fin structure; forming a dielectric fin structure between the first semiconductor fin structure and the second semiconductor fin structure; selectively forming a seed layer on the first semiconductor fin structure and the second semiconductor fin structure, wherein the sidewalls of the dielectric fin structure remain exposed after the seed layer is formed; depositing a sacrificial gate electrode layer on the seed layer and the dielectric fin structure; forming a sacrificial gate structure from the sacrificial gate electrode layer; forming a plurality of sidewall spacers on the sacrificial gate structure; etching the first semiconductor fin structure and the second semiconductor fin structure; forming a plurality of epitaxial source / drain regions; removing the sacrificial gate structure; and forming a replacement gate structure between the sidewall spacers. In some embodiments, it further includes: depositing a silicon layer on the first semiconductor fin structure, the second semiconductor fin structure, and the dielectric fin structure, wherein the silicon layer has a first growth rate on the first semiconductor fin structure and the second semiconductor fin structure and a second growth rate on the dielectric fin structure, and the first growth rate is different from the second growth rate. In some embodiments, the sidewalls of the dielectric fin structure include SiCN. In some embodiments, the step of depositing the silicon layer includes: flowing a precursor including monosilane at a temperature of about 460°C to about 480°C. In some embodiments, further including etching the silicon layer. In some embodiments, further including performing a surface treatment after etching. In some embodiments, the step of forming a sacrificial gate electrode layer on the seed layer and the dielectric fin structure includes: depositing a first silicon layer in a bottom-up manner; and depositing a cap layer on the first silicon layer. In some embodiments, the step of depositing the cap layer includes: depositing a first sublayer on the first silicon layer, wherein the first sublayer has a first crystal structure; and depositing a second sublayer on the first sublayer, wherein the second sublayer has a second crystal structure different from the first crystal structure. In some embodiments, the first sublayer is an amorphous silicon layer and the second sublayer is a crystalline silicon layer.

[0119] Other embodiments of the present disclosure are related to a method for forming a semiconductor device, including: forming a first semiconductor fin structure and a second semiconductor fin structure, wherein a first trench is formed between the first semiconductor fin structure and the second semiconductor fin structure; forming a first silicon layer on the first semiconductor fin and the second semiconductor fin structure, wherein the first silicon layer is disposed in the first trench in a bottom-up manner; depositing a first cap layer on the first silicon layer; depositing a second cap layer on the first cap layer, wherein the first cap layer and the second cap layer have different crystal structures; etching the first silicon layer, the first cap layer, and the second cap layer to form a sacrificial gate structure; forming a plurality of sidewall spacers on the sacrificial gate structure; etching the first semiconductor fin structure and the second semiconductor fin structure; forming a plurality of epitaxial source / drain regions; removing the sacrificial gate structure; and forming a replacement gate structure between the sidewall spacers. In some embodiments, the first cap layer is an amorphous silicon layer and the second cap layer is a crystalline silicon layer. In some embodiments, it further includes: before forming the first silicon layer, depositing a seed layer on the first semiconductor fin structure and the second semiconductor fin structure. In some embodiments, the first semiconductor fin structure and the second semiconductor fin structure include germanium, and the step of depositing the seed layer includes: depositing a silicon layer using a precursor including monosilane at a temperature range of about 460° C. to about 480° C. In some embodiments, further comprising: forming a dielectric fin structure adjacent to the first semiconductor fin structure, wherein a second trench is formed between the first semiconductor fin structure and the dielectric fin structure, and the seed layer is selectively formed on the first semiconductor fin structure and the second semiconductor fin structure. In some embodiments, the step of depositing the first cap layer includes: applying a first precursor at a first temperature; and the step of depositing the second cap layer includes: applying the first precursor at a second temperature, the second temperature being higher than the first temperature.

[0120] Still other embodiments of the present disclosure relate to a method for forming a semiconductor device, comprising: forming two first fin structures, wherein a first trench is formed between the two first fin structures; forming two second fin structures, wherein a second trench is formed between the two second fin structures; forming a dielectric fin structure, wherein the dielectric fin structure is disposed between the first fin structures and the second fin structures, a third trench is formed between the dielectric fin structure and the first fin structures, and the third trench is narrower than the first trenches and the second trenches; selectively forming a seed layer on the first fin structure and the second fin structure, wherein the sidewalls of the dielectric fin structure remain exposed after the seed layer is formed; and forming a gap-filling silicon layer in the first trench, the second trench, and the third trench. In some embodiments, the step of selectively forming a seed layer includes: depositing a silicon layer, wherein the silicon layer has a first growth rate on the first fin structure and the second fin structure and a second growth rate on the dielectric fin structure, and the first growth rate is greater than the second growth rate; and etching back the silicon layer to remove the deposition from the dielectric fin structure. In some embodiments, the step of selectively forming a seed layer further includes performing a surface treatment. In some embodiments, it further includes depositing a heterogeneous crystal cap layer on the gap-filling silicon layer. In some embodiments, the step of forming a gap-filling silicon layer includes cyclically performing a deposition process, an annealing process, and an etching process.

[0121] The above summarizes the components of several embodiments so that those with ordinary knowledge in the technical field to which the present disclosure belongs can more easily understand the concepts of the embodiments of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a first semiconductor fin structure and a second semiconductor fin structure; forming a dielectric fin structure between the first semiconductor fin structure and the second semiconductor fin structure; selectively forming a seed layer on the first semiconductor fin structure and the second semiconductor fin structure, wherein the sidewalls of the dielectric fin structure remain exposed after the seed layer is formed; depositing a sacrificial gate electrode layer on the seed layer and the dielectric fin structure; forming a sacrificial gate structure from the sacrificial gate electrode layer; forming a plurality of sidewall spacers on the sacrificial gate structure; etching the first semiconductor fin structure and the second semiconductor fin structure; forming a plurality of epitaxial source / drain regions; removing the sacrificial gate structure; as well as A replacement gate structure is formed between the plurality of sidewall spacers.

2. The method for forming a semiconductor device as claimed in claim 1, wherein the step of selectively forming the seed layer comprises: A silicon layer is deposited on the first semiconductor fin structure, the second semiconductor fin structure and the dielectric fin structure, wherein the silicon layer has a first growth rate on the first semiconductor fin structure and the second semiconductor fin structure and a second growth rate on the dielectric fin structure, and the first growth rate is different from the second growth rate.

3. The method for forming a semiconductor device according to claim 1 , wherein the step of forming the sacrificial gate electrode layer on the seed layer and the dielectric fin structure comprises: Depositing a first silicon layer in a bottom-up manner; as well as A capping layer is deposited on the first silicon layer.

4. A method for forming a semiconductor device, comprising: Forming a first semiconductor fin structure and a second semiconductor fin structure, wherein a first trench is formed between the first semiconductor fin structure and the second semiconductor fin structure; Forming a first silicon layer on the first semiconductor fin and the second semiconductor fin structure, wherein the first silicon layer is disposed in the first trench from bottom to top; Depositing a first capping layer on the first silicon layer; Depositing a second capping layer on the first capping layer, wherein the first capping layer and the second capping layer have different crystal structures; Etching the first silicon layer, the first cap layer and the second cap layer to form a sacrificial gate structure; forming a plurality of sidewall spacers on the sacrificial gate structure; etching the first semiconductor fin structure and the second semiconductor fin structure; forming a plurality of epitaxial source / drain regions; removing the sacrificial gate structure; as well as A replacement gate structure is formed between the plurality of sidewall spacers. 5 . The method for forming a semiconductor device as claimed in claim 4 , wherein the first cap layer is an amorphous silicon layer and the second cap layer is a crystalline silicon layer.

6. The method for forming a semiconductor device according to claim 4, further comprising: Before forming the first silicon layer, a seed layer is deposited on the first semiconductor fin structure and the second semiconductor fin structure.

7. The method for forming a semiconductor device according to claim 6, wherein the first semiconductor fin structure and the second semiconductor fin structure comprise germanium, and the step of depositing the seed layer comprises: A silicon layer is deposited using a precursor including monosilane at a temperature ranging from about 460° C. to about 480° C.

8. The method for forming a semiconductor device as claimed in claim 4, wherein the step of depositing the first cap layer comprises: applying a first precursor at a first temperature; And the step of depositing the second capping layer includes: applying the first precursor at a second temperature, the second temperature being higher than the first temperature.

9. A method for forming a semiconductor device, comprising: forming two first fin structures, wherein a first trench is formed between the two first fin structures; forming two second fin structures, wherein a second trench is formed between the two second fin structures; forming a dielectric fin structure, wherein the dielectric fin structure is disposed between the first fin structure and the second fin structure, a third trench is formed between the dielectric fin structure and the first fin structure, and the third trench is narrower than the first trench and the second trench; selectively forming a seed layer on the first fin structure and the second fin structure, wherein the sidewall of the dielectric fin structure remains exposed after the seed layer is formed; as well as A gap-filling silicon layer is formed in the first trench, the second trench and the third trench. 10 . The method for forming a semiconductor device as claimed in claim 9 , further comprising depositing a heterogeneous crystal cap layer on the gap-filling silicon layer.

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