Chip processing auxiliary detection system

Abstract

The invention relates to the technical field of chip processing, in particular to an auxiliary detection system for chip processing, which comprises the following steps of: carrying out spot check on chips produced by processing, and judging whether defective chips exist or not; when a defective chip is received, determining a to-be-detected range of the defective chip; based on the chip time detection range, obtaining time data of corresponding maintenance of the chip processing equipment in the chip time detection range, performing analysis to obtain a maintenance capability evaluation value, and then performing judgment with a threshold value to obtain a chip production maintenance capability signal; obtaining a fault performance value of chip processing in a sampling inspection process, and comparing the fault performance value with a fault performance threshold value to obtain a chip processing fault cycle frequency signal; according to the invention, the chip processing quality condition can be detected from two aspects of time and specific parameters at the same time, the maintenance capability of chip processing equipment and the timeliness of recovery work can be detected and evaluated, and the fault time and the cycle repeatability of fault factors during chip processing can be detected.

Description

Technical Field

[0001] The present invention relates to the technical field of chip processing, and in particular to a chip processing auxiliary detection system. Background Art

[0002] Chinese patent CN117038494B discloses an auxiliary intelligent detection system for the chip processing industry, which belongs to the field of intelligent detection technology, including a pin installation defect detection module, etc. The slope of the line segment formed by connecting the midpoints of the two short sides of the detection frame of each pin contact portion is calculated, and then the pins that are not parallel to other pins are identified according to the difference between the slope of each line segment and the average slope, thereby achieving accurate detection of the parallelism of the pins, and the horizontality of the pins is judged by the pixel value in the depth image, thereby accurately identifying the non-horizontal pins, achieving accurate detection of the horizontality of the pins, and then obtaining a more accurate pin installation quality score; and can accurately obtain the package shell installation defect data, thereby obtaining a more accurate package shell installation quality score; finally, according to the pin installation quality score and the package shell installation quality score, the installation quality of the current chip can be accurately scored;

[0003] In the prior art, chip detection is more focused on the chip structure to evaluate the chip quality. However, it is not possible to simply and effectively detect abnormal time and quality of chip processing, nor is it possible to detect the supporting auxiliary maintenance capabilities during the processing. As a result, the current chip processing detection system has problems such as one-sidedness. Summary of the invention

[0004] The purpose of the present invention is to provide a chip processing auxiliary detection system. The technical problem solved by the present invention is: in the prior art, the detection of chips is more focused on the chip structure, etc., to evaluate the chip quality, but now it is not possible to simply and effectively detect the abnormal time, quality, etc. of chip processing, and it is also impossible to detect the supporting auxiliary maintenance capabilities during the processing. Therefore, the current chip processing detection system has problems such as one-sidedness.

[0005] The purpose of the present invention can be achieved through the following technical solutions:

[0006] A chip processing auxiliary detection system, comprising:

[0007] The performance sampling module performs sampling inspection on the chips produced by processing to determine whether there are defective chips;

[0008] A detection range determination module, when receiving a defective chip, determines a range of defective chips to be detected;

[0009] The maintenance capability evaluation module obtains the time data of the maintenance of the chip processing equipment within the chip time detection range based on the chip time detection range, analyzes it to obtain the maintenance capability evaluation value, and then judges it with the threshold to obtain the chip production maintenance capability signal;

[0010] The chip production and maintenance capability signal includes a chip production and maintenance capability high signal or a chip production and maintenance capability low signal;

[0011] Processing energy efficiency detection module: obtains the fault performance value of chip processing during the sampling process, and compares it with the fault performance threshold to obtain the chip processing fault cycle frequency signal.

[0012] As a further solution of the present invention: the performance sampling module includes:

[0013] If the performance parameters obtained from the test are not within the standard process parameter range, the sampled chip will be marked as a defective chip.

[0014] As a further solution of the present invention: detection range determination module:

[0015] When a defective chip is generated during the sampling process, the production time corresponding to the defective chip is obtained and marked as the analysis time T1. The defective chip is used as the initial sequence, and the chips at the corresponding production time nodes are collected and tested in the order of the production time before and after the initial sequence, and the performance parameters of the chips in the previous and next sequences are obtained and compared with the standard process parameter range to determine whether it is a defective chip; until the chips in the previous and next sequences are qualified chips, the chip collection work is stopped;

[0016] The qualified chips collected above and the defective chips in the previous sequence of the qualified chips are obtained and marked as the qualified chips terminated by preliminary collection and the defective chips terminated by preliminary collection respectively;

[0017] Obtain the production time between the qualified chips terminated by preliminary collection and the defective chips terminated by preliminary collection, mark it as the first to-be-determined period, obtain the chip at the midpoint of the first to-be-determined period for testing, and determine whether it is a defective chip;

[0018] According to the above-mentioned method of the period to be determined, the chips are tested cyclically to determine whether they are defective chips, until it is determined that the chip obtained at the i-th time is a defective chip and the chip at the next production time is a qualified chip;

[0019] The production time of the defective chip obtained by the i-th time determined before and after the initial sequence is obtained, and is marked as the chip time detection range.

[0020] As a further solution of the present invention: the method of sequentially collecting along the production time of the initial sequence is: Tn = T1 + q n-1, n represents the number of sequences collected in sequence from the production time of the initial sequence forward, q is the common ratio of the geometric sequence, q is a positive integer greater than 1, q is preferably 2 or 3, Tn is the production time corresponding to the nth sequence collected in sequence from the production time of the initial sequence forward;

[0021] The method of sequentially collecting data from the production time of the initial sequence backward is: Tm = T1 + q m-1 , m represents the number of sequences collected backward along the production time of the initial sequence, Tm is the common ratio of the geometric sequence, q is a positive integer greater than 1, q is preferably 2 or 3, and Tm is the production time corresponding to the mth sequence collected backward along the production time of the initial sequence.

[0022] As a further solution of the present invention: the maintenance capability evaluation module includes:

[0023] The difference between the start and end time of the inspection is marked as CTk and CTj respectively, and the formula is used to The maintenance capability evaluation value ZPX is calculated; where a1 and a2 are both proportional coefficients;

[0024] Compare the maintenance capability evaluation value ZPX with the maintenance capability evaluation threshold;

[0025] If the maintenance capability evaluation value ZPX is greater than or equal to the maintenance capability evaluation threshold, a chip production maintenance capability high signal is generated;

[0026] If the maintenance capability evaluation value ZPX is less than the maintenance capability evaluation threshold, a low chip production maintenance capability signal is generated.

[0027] As a further solution of the present invention: when the chip time detection range is obtained, the start time and the end time of the chip time detection range are marked as the defective product generation start time and the defective product generation end time respectively;

[0028] Then obtain the start time and end time of the chip processing equipment maintenance within the chip time detection range, and mark them as the equipment maintenance start time and the equipment maintenance end time respectively;

[0029] The difference between the equipment maintenance start time and the defective product generation start time is calculated to obtain the inspection start time difference.

[0030] As a further solution of the present invention: the difference between the defective product generation end time and the equipment maintenance end time is calculated to obtain the inspection end time difference.

[0031] As a further solution of the present invention: the processing energy efficiency detection module includes:

[0032] Obtaining the time detection range of each chip and the performance parameters corresponding to the chip time detection range during the sampling process, analyzing to obtain the fault time detection value and the fault parameter detection value, adding the fault time detection value and the fault parameter detection value to obtain the fault performance value, comparing the fault performance value with the fault performance threshold, and generating a chip processing fault cycle frequency signal;

[0033] If the fault performance value is greater than or equal to the fault performance threshold, a chip processing fault cycle low frequency signal is generated;

[0034] If the fault performance value is less than the fault performance threshold, a chip processing fault cycle high frequency signal is generated.

[0035] As a further solution of the present invention: the analysis process of the fault time detection value is:

[0036] The interval between the time detection ranges of two adjacent chips is obtained and marked as the defective generation interval time. The variance of all defective generation interval times during the sampling process is calculated to obtain the fault time detection value.

[0037] As a further solution of the present invention: the analysis process of the fault parameter detection value is:

[0038] Obtain chip performance parameters detected within the chip time detection range, and perform mean calculation to obtain the mean value of the chip performance parameters;

[0039] The variance of all chip performance parameter means during the sampling process is calculated to obtain the fault parameter detection value.

[0040] Beneficial effects of the present invention:

[0041] (1) The present invention performs random inspection on the chips produced by the processing to determine whether there are defective chips; when receiving defective chips, determine the range of defective chips to be detected; based on the obtained chip time detection range, obtain the time data of the chip processing equipment corresponding to the maintenance within the chip time detection range, analyze and obtain the maintenance capability evaluation value, and then judge with the threshold to obtain the chip production and maintenance capability signal; the present invention performs random inspection on the chips prepared in the chip processing process to check the quality of the staged preparation, and then uses the geometric progression method and the time compromise method each time (if there is a vacancy error in the time midpoint obtained in the compromise process, the closest time can be selected The chip production time is taken as the midpoint of time), the processing time of defective chips can be quickly determined, as well as the quality of defective chips produced, and the chip processing quality can be effectively detected from both time and specific parameters. Based on the chip time detection range, the chip repair capability and timeliness of recovery work are detected and evaluated when batches of continuous defective products appear during the production process. Therefore, the present invention not only detects the chip processing quality from both time and specific parameters during the chip processing process, but also detects and evaluates the repair capability and timeliness of recovery work of chip processing equipment during the chip processing process.

[0042] (2) The present invention obtains the fault performance value of chip processing during the random inspection process, and compares it with the fault performance threshold to obtain a chip processing fault cycle frequency signal; the present invention performs further data analysis and detection based on the time and performance parameter data of defective chip processing obtained by the above detection to determine the cyclic repeatability of fault time and fault factors during chip processing. The present invention realizes the detection of the cyclic repeatability of fault time and fault factors during chip processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention will be further described below in conjunction with the accompanying drawings.

[0044] Figure 1 is a schematic diagram of the structure of Embodiment 1 of the present invention;

[0045] Figure 2 It is a structural diagram of embodiment 2 of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] Example 1

[0048] See also Figure 1 As shown, the present invention is a chip processing auxiliary detection system, comprising:

[0049] The performance sampling module performs sampling inspection on the chips produced by processing to determine whether there are defective chips;

[0050] In some embodiments, all chips produced by chip processing equipment within a period of time (the length of time can be set by the technician according to the production schedule, for example, the period of time can be 1 hour, 2 hours or 4 hours) are obtained, sampling rules are set, performance tests are performed on the selected chips, and the performance parameters obtained by the test are compared with the standard process parameter range;

[0051] If the performance parameters obtained by the test are within the standard process parameter range, the sampled chip will be marked as a qualified chip;

[0052] If the performance parameters obtained from the test are not within the standard process parameter range, the sampled chip will be marked as a defective chip;

[0053] Among them, the sampling inspection rule may be in accordance with the chip production time interval sequence;

[0054] Performance tests include: appearance inspection, electrical performance test, etc.

[0055] A detection range determination module, when receiving a defective chip, determines a range of defective chips to be detected;

[0056] In some embodiments, when a defective chip is generated during the sampling process, the production time corresponding to the defective chip is obtained and marked as the analysis time T1. The defective chip is used as the initial sequence, and the chips at the corresponding production time nodes are collected and tested in the order of the production time before and after the initial sequence, and the performance parameters of the chips in the previous and next sequences are obtained and compared with the standard process parameter range to determine (the determination method is the same as the determination method of the above-mentioned performance sampling module whether there is a defective chip) whether it is a defective chip; until the chips in the previous and next sequences are qualified chips, the chip collection work is stopped;

[0057] The method of sequentially collecting data along the production time of the initial sequence is: Tn = T1 + q n-1 , n represents the number of sequences collected in sequence from the production time of the initial sequence forward, q is the common ratio of the geometric sequence, q is a positive integer greater than 1, q is preferably 2 or 3, Tn is the production time corresponding to the nth sequence collected in sequence from the production time of the initial sequence forward;

[0058] The method of sequentially collecting data from the production time of the initial sequence backward is: Tm = T1 + q m-1, m represents the number of sequences collected in sequence from the production time of the initial sequence, Tm is the common ratio of the geometric sequence, q is a positive integer greater than 1, q is preferably 2 or 3, and Tm is the production time corresponding to the mth sequence collected in sequence from the production time of the initial sequence;

[0059] Further, the above collected qualified chips and the defective chips in the previous sequence of the qualified chips are obtained, and are marked as preliminary collection terminated qualified chips and preliminary collection terminated defective chips respectively;

[0060] The production time between the qualified chips terminated by the preliminary collection and the defective chips terminated by the preliminary collection is obtained, and marked as the first period to be determined. The chip at the midpoint of the first period to be determined is obtained for testing to determine whether it is a defective chip (the determination method is the same as the determination method of whether there is a defective chip in the above-mentioned performance sampling module).

[0061] If the chip detected in the first period to be determined is a defective chip, obtain the production time of the defective chip in the first period to be determined and the qualified chip terminated by the preliminary collection, mark it as the second period to be determined, obtain the chip at the midpoint of the second period to be determined for testing, and judge (the judgment method is the same as the judgment method of the above-mentioned performance sampling module whether there is a defective chip) whether it is a defective chip;

[0062] If the chip detected in the first period to be determined is a qualified chip, obtain the production time of the qualified chips in the first period to be determined and the preliminary collection of the defective chips, mark it as the second period to be determined, obtain the chip at the midpoint of the second period to be determined for testing, and judge (the judgment method is the same as the judgment method of the above-mentioned performance sampling module whether there is a defective chip) whether it is a defective chip;

[0063] Perform chip testing at the midpoint of each of the above-mentioned time periods until it is determined that the chip obtained at the i-th time is a defective chip and the chip produced at the next production time is a qualified chip;

[0064] Obtain the production time of the defective chip obtained by the i-th time before and after the initial sequence, and mark it as the chip time detection range;

[0065] The maintenance capability evaluation module obtains the time data of the maintenance of the chip processing equipment within the chip time detection range based on the chip time detection range, analyzes it to obtain the maintenance capability evaluation value, and then judges it with the threshold to obtain the chip production maintenance capability signal;

[0066] The chip production and maintenance capability signal includes a chip production and maintenance capability high signal or a chip production and maintenance capability low signal;

[0067] Among them, the time data includes the start time of maintenance and the end time of maintenance;

[0068] In some embodiments, when the chip time detection range is obtained, the start time and the end time of the chip time detection range are marked as the defective product generation start time and the defective product generation end time, respectively;

[0069] Then obtain the start time and end time of the chip processing equipment maintenance within the chip time detection range, and mark them as the equipment maintenance start time and the equipment maintenance end time respectively;

[0070] Calculate the difference between the equipment maintenance start time and the defective product generation start time to obtain the inspection start time difference;

[0071] Calculate the difference between the defective product generation end time and the equipment maintenance end time to obtain the inspection end time difference;

[0072] The difference between the start and end time of the inspection is marked as CTk and CTj respectively, and the formula is used to The maintenance capability evaluation value ZPX is calculated; wherein a1 and a2 are both proportional coefficients, a1+a2=1, a1 is 0.61, a2 is 0.39, and the values ​​of a1 and a2 represent the influence of the difference in the start time of the inspection and the difference in the end time of the inspection on the maintenance capability evaluation value ZPX;

[0073] Compare the maintenance capability evaluation value ZPX with the maintenance capability evaluation threshold;

[0074] If the maintenance capability evaluation value ZPX is greater than or equal to the maintenance capability evaluation threshold, it means that when batches of continuous defective products appear in the chip production process, the maintenance capability matched with its generation can promptly repair the chip processing equipment in the event of defective products, and the chip processing equipment can also resume normal operation in a timely manner after the repair, then a high chip production maintenance capability signal is generated;

[0075] If the maintenance capability evaluation value ZPX is less than the maintenance capability evaluation threshold, it means that when batches of continuous defective products appear in the chip production process, the maintenance capability matched with the chip production can fail to promptly repair the chip processing equipment when defective products appear, and the chip processing equipment fails to resume normal operation in a timely manner after repair, thus generating a low chip production maintenance capability signal;

[0076] It needs to be explained that the difference in the start time of inspection reflects whether the chip processing equipment can be repaired in time when defective products appear during the chip production process. That is, the smaller the difference in the start time of inspection, the more timely the chip processing equipment can be repaired, which corresponds to a greater maintenance capacity of the chip processing technology.

[0077] The difference in inspection end time reflects whether the chip processing equipment can resume normal operation in a timely manner after a period of maintenance in the event of defective products during the chip production process. That is, the smaller the difference in inspection end time, the more timely the chip processing equipment can resume normal operation after maintenance, which corresponds to a greater maintenance capability of the chip processing technology.

[0078] The technical solution of the embodiment of the present invention is as follows: sampling the chips produced by processing to determine whether there are defective chips; when receiving defective chips, determining the range of defective chips to be detected; based on the obtained chip time detection range, obtaining the time data of the corresponding maintenance of the chip processing equipment within the chip time detection range, analyzing to obtain the maintenance capability evaluation value, and then judging with the threshold to obtain the chip production and maintenance capability signal; the present invention performs sampling on the chips prepared in the chip processing process to check the quality of the staged preparation, and then uses the method of geometric progression and the method of time compromise each time (if there is a vacancy error in the time midpoint obtained in the compromise process, the closest time can be selected The chip production time is taken as the midpoint of time), so the time when the probability of abnormal processing of defective chips is relatively high can be quickly determined, as well as the quality of the defective chips produced, so that the chip processing quality can be effectively detected from both the time and specific parameters at the same time; based on the chip time detection range, the chip maintenance capability and the timeliness of recovery work can be detected and evaluated when batches of continuous defective products appear in the chip production process; therefore, the present invention not only realizes the simultaneous detection of chip processing quality from both the time and specific parameters during the chip processing process, but also can detect and evaluate the maintenance capability and timeliness of recovery work of chip processing equipment during the chip processing process.

[0079] Example 2

[0080] See also Figure 2 As shown, the present invention is a chip processing auxiliary detection system, which also includes:

[0081] Processing energy efficiency detection module: obtains the fault performance value of chip processing during the sampling process, and compares it with the fault performance threshold to obtain the chip processing fault cycle frequency signal;

[0082] Wherein, the chip processing fault cycle frequency signal includes a chip processing fault cycle frequency low signal or a chip processing fault cycle frequency high signal;

[0083] In some implementation schemes, each chip time detection range and the performance parameter corresponding to the chip time detection range are obtained during the sampling process, and the fault time detection value and the fault parameter detection value are analyzed to obtain the fault performance value, and the fault performance value is compared with the fault performance threshold value to generate a chip processing fault cycle frequency signal;

[0084] If the fault performance value is greater than or equal to the fault performance threshold, a chip processing fault cycle low frequency signal is generated;

[0085] If the fault performance value is less than the fault performance threshold, a chip processing fault cycle high frequency signal is generated;

[0086] First, specifically, the analysis process of the fault time detection value is:

[0087] Get the interval between the time detection ranges of two adjacent chips, mark it as the defective generation interval time, calculate the variance of all defective generation interval times during the sampling process, and get the fault time detection value;

[0088] The analysis process of the fault parameter detection value is:

[0089] Obtain chip performance parameters detected within the chip time detection range, and perform mean calculation to obtain the mean value of the chip performance parameters;

[0090] The variance of all chip performance parameter means during the sampling process is calculated to obtain the fault parameter detection value;

[0091] It should be explained that: the high chip processing fault cycle frequency signal indicates that during the sampling period of chip processing, the frequency of a certain fault of the processing equipment cyclically occurs at a high frequency, and the low chip processing fault cycle frequency signal indicates that during the sampling period of chip processing, the frequency of a certain fault of the processing equipment cyclically occurs at a low frequency;

[0092] The fault time detection value indicates whether there are defective chips with cyclic intermittent failures in the chip processing cycle corresponding to the random inspection, so as to infer whether the chip processing equipment has cyclic intermittent failures. That is, the smaller the fault time detection value, the greater the probability of cyclic intermittent failures in the chip processing equipment.

[0093] The fault parameter detection value indicates the fluctuation of performance parameters during the production time of each defective chip in the chip processing cycle corresponding to the sampling inspection. The smaller the fault parameter detection value, the greater the probability that a specific fault of the processing equipment is caused during the production time of each defective chip.

[0094] The technical solution of an embodiment of the present invention is as follows: the fault performance value of chip processing is obtained during the random inspection, and compared with the fault performance threshold value to obtain a chip processing fault cycle frequency signal; the present invention performs further data analysis and detection based on the time and performance parameter data of defective chip processing obtained from the above detection to determine the cyclic repeatability of fault time and fault factors during chip processing. The present invention realizes the detection of the cyclic repeatability of fault time and fault factors during chip processing.

[0095] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0096] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A chip processing auxiliary detection system, characterized in that: include: The performance sampling module performs sampling inspection on the chips produced by processing to determine whether there are defective chips; A detection range determination module, when receiving a defective chip, determines a range of defective chips to be detected; When a defective chip is generated during the sampling process, the production time corresponding to the defective chip is obtained and marked as the analysis time T1. The defective chip is used as the initial sequence, and the chips at the corresponding production time nodes are collected and tested in the order of the production time of the initial sequence. The performance parameters of the chips in the previous and next sequences are obtained and compared with the standard process parameter range to determine whether it is a defective chip. The chip collection work is stopped until the chips in the previous and next sequences are qualified chips. The maintenance capability evaluation module obtains the time data of the maintenance of the chip processing equipment within the chip time detection range based on the chip time detection range, analyzes it to obtain the maintenance capability evaluation value, and then judges it with the threshold to obtain the chip production maintenance capability signal; The chip production and maintenance capability signal includes a chip production and maintenance capability high signal or a chip production and maintenance capability low signal; Processing energy efficiency detection module: obtains the fault performance value of chip processing during the sampling process, compares it with the fault performance threshold, and detects the chip processing fault cycle frequency signal.

2. A chip processing auxiliary detection system according to claim 1, characterized in that: The performance sampling module includes: If the performance parameters obtained from the test are not within the standard process parameter range, the sampled chip will be marked as a defective chip.

3. A chip processing auxiliary detection system according to claim 1, characterized in that: The detection range determination module also includes: Obtain the qualified chips collected above, and the defective chips in the previous sequence of the qualified chips, and mark them as preliminary collection terminated qualified chips and preliminary collection terminated defective chips respectively; Obtain the production time between the qualified chips terminated by preliminary collection and the defective chips terminated by preliminary collection, mark it as the first to-be-determined period, obtain the chip at the midpoint of the first to-be-determined period for testing, and determine whether it is a defective chip; According to the above-mentioned method of the period to be determined, the chips are tested cyclically to determine whether they are defective chips, until it is determined that the chip obtained at the i-th time is a defective chip and the chip at the next production time is a qualified chip; The production time of the defective chip obtained by the i-th time determined before and after the initial sequence is obtained, and is marked as the chip time detection range.

4. A chip processing auxiliary detection system according to claim 3, characterized in that: The method of sequentially collecting along the production time of the initial sequence is: Tn = T1 + q n-1 , n represents the number of sequences collected in sequence from the production time of the initial sequence forward; q is the common ratio of the geometric sequence, q is a positive integer greater than 1, q is preferably 2 or 3, Tn is the production time corresponding to the nth sequence collected in sequence from the production time of the initial sequence forward; The method of sequentially collecting data from the production time of the initial sequence backward is: Tm = T1 + q m-1 , m represents the number of sequences collected backward along the production time of the initial sequence; Tm is the common ratio of the geometric sequence, q is a positive integer greater than 1, q is preferably 2 or 3, and Tm is the production time corresponding to the mth sequence collected backward along the production time of the initial sequence.

5. A chip processing auxiliary detection system according to claim 1, characterized in that: The maintenance capability assessment modules include: The difference between the start and end time of the inspection is marked as CTk and CTj respectively, and the formula is used to calculate The maintenance capability evaluation value ZPX is calculated; where a1 and a2 are both proportional coefficients; Compare the maintenance capability evaluation value ZPX with the maintenance capability evaluation threshold; If the maintenance capability evaluation value ZPX is greater than or equal to the maintenance capability evaluation threshold, a chip production maintenance capability high signal is generated; If the maintenance capability evaluation value ZPX is less than the maintenance capability evaluation threshold, a low chip production maintenance capability signal is generated.

6. A chip processing auxiliary detection system according to claim 5, characterized in that: When the chip time detection range is obtained, the start time and the end time of the chip time detection range are marked as the defective product generation start time and the defective product generation end time respectively; Then obtain the start time and end time of the chip processing equipment maintenance within the chip time detection range, and mark them as the equipment maintenance start time and the equipment maintenance end time respectively; The difference between the equipment maintenance start time and the defective product generation start time is calculated to obtain the inspection start time difference.

7. A chip processing auxiliary detection system according to claim 6, characterized in that: The difference between the defective product generation end time and the equipment maintenance end time is calculated to obtain the inspection end time difference.

8. A chip processing auxiliary detection system according to claim 1, characterized in that: The processing energy efficiency detection module includes: Obtain the time detection range and corresponding performance parameters of each chip during the sampling process, analyze and obtain the fault time detection value and the fault parameter detection value, add the fault time detection value and the fault parameter detection value to obtain the fault performance value, compare the fault performance value with the fault performance threshold, and generate a chip processing fault cycle frequency signal; If the fault performance value is greater than or equal to the fault performance threshold, a chip processing fault cycle low frequency signal is generated; If the fault performance value is less than the fault performance threshold, a chip processing fault cycle high frequency signal is generated.

9. A chip processing auxiliary detection system according to claim 8, characterized in that: The analysis process of the fault time detection value is: The interval between the time detection ranges of two adjacent chips is obtained and marked as the defective generation interval time. The variance of all defective generation interval times during the sampling process is calculated to obtain the fault time detection value.

10. A chip processing auxiliary detection system according to claim 9, characterized in that: The analysis process of the fault parameter detection value is: Obtain chip performance parameters detected within the chip time detection range, and perform mean calculation to obtain the mean value of the chip performance parameters; The variance of all chip performance parameter means during the sampling process is calculated to obtain the fault parameter detection value.

Images