Wafer structure and method of manufacturing the same

Abstract

The application belongs to the technical field of semiconductor manufacturing, and provides a wafer structure, which comprises a chip region and a positioning region. The positioning region comprises a fine positioning region. The fine positioning region comprises M material layers stacked along a first direction, and is denoted as the first to M material layers. The fine positioning region is divided into N mark regions along a second direction, and is denoted as the first to N mark regions. At least one material layer of each mark region is provided with a fine positioning pattern, and the first material layer is a positioning layer, wherein the fine positioning pattern in the positioning layer is an alignment mark. When exposure positioning is performed, the mark region with the best positioning effect can be determined according to the intensity of the positioning signal of each mark region, and effective alignment positioning of the wafer is realized. The application further provides a preparation method of the wafer structure, which is used for manufacturing the wafer structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a wafer structure and a preparation method thereof. BACKGROUND

[0002] Surface passivation technology is an important part of the semiconductor device manufacturing process. By using surface passivation technology, a passivation layer can be formed on the surface of the device to prevent the device from being eroded by the external environment, and to reduce the generation of surface states and improve the electrical performance and reliability of the device. In existing semiconductor devices, a PI (polyimide) passivation layer is often provided. In order to further improve the withstand voltage, a CB passivation layer is introduced before the PI passivation layer is formed in the semiconductor manufacturing process, and the CB passivation layer and the PI passivation layer together form a composite passivation layer.

[0003] In the semiconductor manufacturing process, the layer above the CB passivation layer is a thick aluminum layer. Since the solubility of aluminum in silicon is very low, and the solubility of silicon in aluminum is very high, it will cause cracks when silicon is dissolved in aluminum during the deposition of aluminum on the silicon wafer. After the aluminum atoms enter the cracks, a sharp wedge is formed, which will cause the PN junction to fail. In order to solve the problem of the sharp wedge, the material of the thick aluminum layer is often silicon-aluminum alloy.

[0004] Since the alignment mark of the semiconductor device is covered by the thick aluminum layer, the outline of the alignment mark will become blurred, which will make the photolithography alignment very difficult. Therefore, during the semiconductor design stage, the thick aluminum layer on the alignment mark needs to be removed. However, after the thick aluminum layer is exposed and etched, the silicon in the thick aluminum layer will be precipitated and gathered on the surface to form silicon chips. The magnification effect of the CB layer on the silicon chips is very prominent, which will make the reflected light of the alignment mark more chaotic, causing serious interference with the positioning signal during exposure positioning, resulting in distortion of the reflected signal, and further causing signal recognition errors or frequent exposure interruption. Therefore, how to enhance the identification of the alignment mark of the semiconductor device by the photolithography machine, reduce the probability of exposure failure and the risk of positioning deviation, and ensure product quality, is a problem that needs to be solved at present. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a wafer structure and a preparation method thereof, in order to solve the problems of poor identification and positioning effect of the alignment mark of the wafer in the prior art, and to improve the strength of the alignment signal during exposure positioning of the photolithography machine and improve the effect of alignment positioning.

[0006] To achieve the above object and other related objects, the present application provides a wafer structure, comprising a chip region and a positioning region located at the periphery of the chip region, the positioning region comprising a fine positioning region, the fine positioning region comprising M material layers stacked in sequence along a first direction and denoted as the 1st to Mth material layers along the first direction respectively; wherein the first direction is the thickness direction of the wafer structure, and M is a positive integer greater than 5;

[0007] Viewing the wafer structure along the first direction, the fine positioning region has a strip structure, and the extension direction of the strip structure of the fine positioning region is a second direction, the fine positioning region is divided into N mark regions along the second direction and denoted as the 1st to Nth mark regions along the second direction in sequence respectively, wherein N is a positive integer greater than 3, at least one material layer of each mark region is provided with a fine positioning pattern, and the 1st material layer is a positioning layer, and the fine positioning pattern in the 1st material layer is an alignment mark.

[0008] Optionally, M is 8, the fine positioning region comprises the 1st to 8th material layers stacked in sequence along the first direction, wherein the 2nd to 4th material layers are material injection layers, the 5th material layer is a polysilicon layer, the 6th material layer is a thick aluminum layer, and the 7th and 8th material layers are passivation layers.

[0009] Optionally, the fine positioning pattern has a cross structure, comprising a first type of pattern and a second type of pattern, the first type of pattern is an upper convex cross structure, and the second type of pattern is a groove-shaped cross structure.

[0010] Optionally, the cross structure of the fine positioning pattern has four rectangular protrusions, the width of the rectangular protrusions is denoted as a mark width, and the value of the mark width is 1.5 μm to 6 μm.

[0011] Optionally, M is 8, and there is a K-1th mark region in the N mark regions; the K-1th mark region comprises the 1st to 8th material layers, and the 3rd material layer and the 5th to 8th material layers of the K-1th mark region are provided with the second type of pattern; wherein K is a positive integer less than N.

[0012] Optionally, the second type of pattern in the 3rd material layer and the second type of pattern in the 5th to 8th material layers are aligned along the first direction.

[0013] Optionally, there are a Kth mark region and a K+1th mark region in the N mark regions; and,

[0014] The Kth marking area includes the first to fourth material layers, the sixth material layer, and the eighth material layer, and the first material layer of the Kth marking area is provided with the first type of pattern or the second type of pattern;

[0015] The K+1th marking region includes the first to second material layers, the fourth material layer and the eighth material layer, and the first type of pattern or the second type of pattern is provided in the first material layer of the K+1th region.

[0016] Optionally, in the first material layer of the Kth mark area, the mark width of the precise alignment pattern is a first width;

[0017] In the third material layer and the fifth to eighth material layers of the K-1th region, the mark width of the second type of graphics is the second width.

[0018] Optionally, the first width is 2.5 μm or 5 μm, and the second width is 3 μm.

[0019] The present application also provides a method for preparing a wafer structure, which is used to manufacture any of the wafer structures described in the aforementioned embodiments, comprising the following steps:

[0020] Providing a wafer test piece having a first material layer, wherein the first material layer is provided with a precise alignment pattern;

[0021] forming a second material layer on the first material layer;

[0022] coating a photoresist on the second material layer and performing development and exposure;

[0023] Etching and cleaning the exposed second material layer to form a second material layer having a precisely aligned pattern;

[0024] The third to Mth material layers having precise alignment patterns are sequentially formed on the second material layer.

[0025] The wafer structure and preparation method provided by this application have at least the following beneficial effects:

[0026] First, in the wafer structure of this embodiment, the fine alignment area is divided into N marking areas, and the marking area has multiple material layers. A fine alignment pattern is provided in at least one material layer in each marking area. The marking area with the best positioning effect can be judged according to the scanning intensity of the positioning signal of each marking area, thereby realizing effective alignment and positioning of the wafer; the N marking areas have the K-1th marking area to the Kth marking area with a specific structure, and the thick aluminum layer of the Kth marking area is retained during the exposure and etching process, which effectively reduces the precipitation of silicon chips and thus reduces the interference with the positioning signal. The third material layer and the fifth material layer to the eighth material layer of the K-1th marking area are provided with a fine alignment pattern aligned along the first direction, and the third material layer and the fifth material layer to the seventh material layer are removed from the K+1th marking area, which reduces the intensity of the clutter signal and increases the intensity of the positioning signal, thereby significantly reducing the risk of position deviation during wafer alignment, ensuring the accuracy and reliability of wafer alignment, effectively reducing the rework rate and raw material consumption during the exposure process, saving production costs, ensuring product quality, and having extremely high practical and promotion value.

[0027] On the second aspect, the method for preparing the wafer structure provided in the present application is used to manufacture the above-mentioned wafer structure, and therefore also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 Shown is a structural schematic diagram of the wafer structure provided in Example 1 of the present application.

[0030] Figure 2 Shown is a schematic diagram of a partial cross-sectional structure of a precision alignment pattern along the second direction provided in an optional embodiment of the first embodiment of the present application.

[0031] Figure 3 Shown is a structural schematic diagram of silicon chips deposited on the surface of the wafer structure provided in Example 1 of the present application.

[0032] Figure 4 Shown is a schematic diagram of the surface structure with silicon chips in the prior art provided in Example 1 of the present application.

[0033] Figure 5 Shown is a schematic diagram of scanning of positioning signals during exposure positioning in the prior art provided in the first embodiment of the present application.

[0034] Figure 6 Shown is a schematic structural diagram of spot etching of silicon chips in the prior art provided in Example 1 of the present application.

[0035] Figure 7 Shown is a schematic diagram of a partial cross-sectional structure of a precision alignment pattern along the second direction provided by another optional embodiment in the first embodiment of the present application.

[0036] Figure 8 Shown is a schematic diagram of the position of the precise alignment pattern provided in an optional embodiment of the first embodiment of the present application.

[0037] Figure 9 Shown is a schematic diagram of a top view of a portion of the precise alignment area along the first direction provided in an optional embodiment of the first embodiment of the present application.

[0038] Figure 10 Display as Figure 9 A partially enlarged view of the precision alignment pattern within the elliptical coil in the precision alignment area shown.

[0039] Figure 11 Shown is a scanning schematic diagram of the positioning signal during exposure positioning provided by an optional embodiment in the first embodiment of the present application.

[0040] Figure 12 Shown is a flow chart of a method for preparing a wafer structure provided in the second embodiment of the present application.

[0041] Reference numerals:

[0042] 1. Wafer structure; 11. Chip area; 12. Positioning area; 121. Fine alignment area; 1211. 1st material layer; 1212. 2nd material layer; 1213. 3rd material layer; 1214. 4th material layer; 1215. 5th material layer; 1216. 6th material layer; 1217. 7th material layer; 1218. 8th material layer; 1201. K-2nd mark area; 1202. K-1st mark area; 1203. Kth mark area; 12 04, K+1th marking area; 1205, K+2th marking area; 1206, K+3th marking area; 1207, K+4th marking area; 1208, K+5th marking area; 1209, K+6th marking area; 122, first positioning pattern; 1221, fine alignment pattern; 1222, coarse alignment pattern; 123, coarse alignment area; 2, mask; 21, second positioning pattern; 31, lens group; 32, mask; 321, third positioning pattern. DETAILED DESCRIPTION

[0043] To make the technical objectives, technical solutions, and technical effects of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with embodiments. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Generally, the components of the embodiments of this application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in this application without creative effort are within the scope of protection of this application. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance.

[0045] In the description of this application, it should be noted that the reference terms "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate scheme in any one or more embodiments or examples.

[0046] Example 1

[0047] This embodiment provides a wafer structure 1 for solving the problem in the prior art that, when a lithography machine positions a wafer, positioning signal interference is severe, resulting in poor positioning effect or frequent exposure interruptions.

[0048] In this embodiment, refer to Figure 1 and Figure 2 The wafer structure 1 includes a chip area 11 and a positioning area 12. The chip area 11 is the chip setting area. The positioning area 12 is located on the periphery of the chip area. A first positioning pattern 122 is provided in the positioning area 12 for aligning and positioning the wafer. The positioning area 12 includes a fine alignment area 121. The first positioning pattern 122 includes a fine alignment pattern 1221. The fine alignment pattern is provided in the fine alignment area 121 for fine alignment of the wafer. It should be noted that Figure 2 The fine alignment pattern 1221 shown in the figure does not represent actual size and is drawn for ease of understanding only. The fine alignment region 121 includes M material layers stacked sequentially along a first direction. The M material layers are sequentially denoted as the 1st to the Mth material layers along the first direction. The first direction is the thickness direction of the wafer structure 1, and M is a positive integer greater than 5.

[0049] In an optional embodiment, the positioning area further includes a coarse alignment area 123 , and the first positioning pattern 122 further includes a coarse alignment pattern 1222 . The coarse alignment pattern 1222 is disposed in the coarse alignment area 123 , and the coarse alignment pattern 1222 is used for coarse alignment of the wafer.

[0050] In an optional embodiment, the value of M can be, for example, 8, and the fine alignment region 121 includes a first material layer 1211 to an eighth material layer 1218 stacked sequentially along the first direction. Optionally, among the eight material layers, the first material layer 1211 is an alignment layer, and the fine alignment pattern 1221 in the first material layer 1211 is an alignment mark, which can reflect incident light to form reflected light. The second material layer 1212 to the fourth material layer 1214 are material injection layers, for example, the second material layer 1211 is an alignment mark. The material layer 1212 and the fourth material layer 1214 can be P-type material injection layers, the third material layer 1213 can be, for example, an N-type material injection layer, the fifth material layer 1215 is a polysilicon layer, the sixth material layer 1216 is a metal layer, for example, the sixth material layer 1216 can be a thick aluminum layer, the seventh material layer 1217 and the eighth material layer 1218 are passivation layers, for example, the seventh material layer 1217 can be a CB passivation layer, and the eighth material layer 1218 can be, for example, a PI passivation layer.

[0051] In an optional embodiment, the M value can be 5, for example, and the fine alignment area 121 includes the first material layer 1211 to the fifth material layer 1215 stacked in sequence along the first direction, wherein the first material layer 1211 is an alignment layer, the fine alignment pattern 1221 in the first material layer 1211 is an alignment mark, the second material layer 1212 is a material injection layer, the third material layer 1213 is a polysilicon layer, the fourth material layer 1214 is a metal layer such as a thick aluminum layer, and the fifth material layer 1215 is a passivation layer.

[0052] In the prior art, referring to Figure 3 and Figure 4 Since the thick aluminum layer covers the alignment mark, the outline of the alignment mark will be blurred. Therefore, the thick aluminum layer above the alignment mark is removed. After the thick aluminum layer is exposed and etched, the silicon in it precipitates and aggregates on the surface to form silicon chips. At this time, refer to Figure 5 When the wafer is exposed and positioned, the silicon chips are magnified by the passivation layer, making the reflected light of the alignment mark more chaotic, disrupting the positioning signal, causing serious interference in the signal scanning, and increasing the risk of positioning deviation and exposure termination. To solve the above problems caused by silicon chips, refer to Figure 6 Currently, the freckle etching process is often used to remove silicon chips. However, the pits produced after the silicon chips fall off will undergo electrochemical reactions, causing pad contamination problems on the chip surface, thereby affecting chip performance.

[0053] Based on the above technical issues, refer toFigure 2 In this embodiment, when viewing the wafer structure 1 from a first direction, the fine alignment region 121 is in a strip-shaped structure. With the extension direction of the strip-shaped structure of the fine alignment region 121 serving as a second direction, the fine alignment region 121 is divided into N marking regions along the second direction. These N marking regions are sequentially referenced as the first to Nth marking regions along the second direction, where N is a positive integer greater than 3. Furthermore, a fine alignment pattern 1221 is provided in at least one material layer of each marking region. By providing multiple marking regions and arranging the fine alignment patterns within the marking regions, the marking region with the best positioning effect can be determined based on the scanning intensity of the positioning signals from each marking region during use, thereby achieving effective alignment and positioning of the wafer.

[0054] In an optional embodiment, the precision alignment pattern 1221 in the first material layer 1211 is an alignment mark, and the precision alignment pattern 1221 in the second material layer 1212 to the Nth material layer penetrates the material layer in which it is located, thereby enabling it to form a window in the material layer in which it is located, so as to improve the transmission effect of reflected light, enhance the strength of the positioning signal, and improve the accuracy and reliability of wafer positioning. Optionally, the precision alignment pattern is a cross-shaped structure.

[0055] Reference Figure 1 The wafer structure 1 is placed on the machine, and the light generated by the photolithography machine is irradiated onto the surface of the wafer structure 1 through the lens group 31 and the mask 2. The photolithography machine is provided with a mask 32, and the mask 32 has a third positioning pattern 321. The mask 2 is provided with a second positioning pattern 21. The incident light is irradiated onto the surface of the wafer and forms reflected light through the first material layer 1211. The reflected light passes through the second positioning pattern 21 and the third positioning pattern 321 to reach the optical fiber detector. When the first positioning pattern 122, the second positioning pattern 21 and the third positioning pattern 321 are located in the same straight line, the reflected light is detected by the optical fiber detector, and the current position of the wafer structure 1 is recorded by the machine, thereby realizing the positioning of the wafer structure 1. When in use, the rough alignment pattern 1222, the second positioning pattern 21 and the third positioning pattern 321 are used to perform rough alignment on the wafer structure 1. After completing the rough alignment, the fine alignment pattern, the second positioning pattern 21 and the third positioning pattern 321 are used to perform fine alignment on the wafer structure 1, thereby achieving alignment and positioning of the wafer structure 1.

[0056] In an optional embodiment, the number of precision alignment areas 121 in the wafer structure 1 can be one or more. For example, two precision alignment areas 121 are provided in the wafer structure 1, and the two precision alignment areas 121 are spaced apart from each other to achieve precise alignment and positioning of the wafer. Other appropriate numbers of precision alignment areas 121 can also be provided and distributed in an appropriate manner. This embodiment is not limited to the order.

[0057] In an optional embodiment, the fine alignment pattern 1221 is in a cross structure, and the fine alignment pattern 1221 includes a first type of pattern and a second type of pattern, wherein the first type of pattern is an upper convex cross structure, and the second type of pattern is a groove cross structure. The cross structure of the fine alignment pattern has four rectangular protrusions. Optionally, the width of the rectangular protrusion is referred to as a mark width, and the value of the mark width is 1.5 μm to 6 μm.

[0058] In this embodiment, with reference to Figure 2 When M is 8, in each of the N mark regions, there is a K-1th mark region 1202, the K-1th mark region 1202 includes the first material layer 1211 to the eighth material layer 1218, and the third material layer 1213, the fifth material layer 1215, the sixth material layer 1216, the seventh material layer 1217, and the eighth material layer 1218 of the K-1th mark region 1202 are provided with the second type of pattern, wherein K is a positive integer less than N.

[0059] In an optional embodiment, the second type of pattern in the third material layer 1213 and the fifth material layer 1215 to the eighth material layer 1218 are aligned along the first direction, and the second type of pattern penetrates the material layer in which it is located, so that the third material layer 1213 and the fifth material layer 1215 to the eighth material layer 1218 form a window at the corresponding position along the first direction, improving the transmission effect of reflected light and enhancing the strength of the positioning signal. Optionally, in the third material layer 1213 and the fifth material layer 1215 to the eighth material layer 1218 of the K-1th mark region 1202, the mark width of the second type of pattern is a second width, and further, the second width is 3 μm.

[0060] In this embodiment, in the N mark regions, there are also a Kth mark region 1203 and a K+1th mark region 1204. The Kth mark region 1203 includes the first material layer 1211 to the fourth material layer 1214, and the sixth material layer 1216 and the eighth material layer 1218, and the first material layer 1211 of the Kth mark region 1203 is provided with the first type of pattern or the second type of pattern. The K+1th mark region 1204 includes the first material layer 1211, the second material layer 1212, the fourth material layer 1214, and the eighth material layer 1218, and the first material layer 1211 of the K+1th mark region 1204 is provided with the first type of pattern or the second type of pattern. Optionally, in the first material layer 1211 of the Kth mark region 1203, the mark width of the fine alignment pattern 1221 is a first width, and further, the first width is 2.5 μm or 5 μm.

[0061] In an optional embodiment, with reference to Figure 2, K is a positive integer greater than 3, N is a positive integer greater than 10, and the N marking areas include a K-2th marking area 1201 to a K+6th marking area 1209. Specifically, the K-2th marking area 1201 includes the first and second material layers 1212, the fourth material layer 1214, and the eighth material layer 1218. The first material layer 1211 is provided with a first type of pattern. The K+1th marking area 1204 and the K+4th marking area 1207 have the same structure as the K-2th marking area 1201. Optionally, the mark widths of the first type of pattern in the K-2th marking area 1201, the K+1th marking area 1204, and the K+4th marking area 1207 are 3.5 μm, 4.5 μm, and 5.5 μm, respectively. The K-1 marking area 1202 includes the 1st material layer 1211 to the 8th material layer 1218, and the second type of graphics are arranged in the 3rd material layer 1213 and the 5th material layer 1215 to the 8th material layer 1218 of the K-1 marking area 1202. The K+2 marking area 1205 and the K+5 marking area 1208 have the same structure as the K-1 marking area 1202. Optionally, the marking width of the second type of graphics in the above material layers is 3μm. The Kth marking area 1203 includes the 1st material layer 1211 to the 4th material layer 1214, the 6th material layer 1216, and the 8th material layer 1218. The first material layer 1211 of the Kth marking area 1203 is provided with a first type of graphic. The K+3th marking area 1206 has the same structure as the Kth marking area 1203. Optionally, the marking widths of the first type of graphic in the Kth marking area 1203 and the K+3th marking area 1206 are 2.5μm and 5μm, respectively. The K+1th marking region 1204 includes a first material layer 1211, a second material layer 1212, a fourth material layer 1214, and an eighth material layer 1218. A first type of pattern is provided in the first material layer 1211 of the K+1th marking region 1204. The K+4th marking region 1207 has the same structure as the K+1th marking region 1204. Optionally, the mark widths of the first type of pattern in the K+1th marking region 1204 and the K+4th marking region 1207 are 4.5 μm and 5.5 μm, respectively. The K+6th marking region 1209 includes the first material layer 1211 to the fourth material layer 1214, and the eighth material layer 1218. A first type of pattern is provided in the first material layer 1211 of the K+1th marking region 1204. Optionally, the mark width of the first type of pattern in the K+6th marking region 1209 is 6 μm.

[0062] In an alternative embodiment, reference Figure 7 , K is a positive integer greater than 3, N is a positive integer greater than 10, and among the N marking areas, there are the K-2 marking area 1201 to the K+6 marking area 1209, and the K-2 marking area 1201 to the K+6 marking area 1209 and Figure 2The structure shown is similar, except that: the first material layer 1211 of the K-2 marking area 1201, the K marking area 1203, the K+1 marking area 1204, the K+3 marking area 1206, the K+4 marking area 1207 and the K+6 marking area 1209 is provided with a precision alignment pattern 1221 of the second type of pattern.

[0063] In this embodiment, when etching the 6th material layer 1216, the photoresist on the 6th material layer 1216 of the K mark area 1203 is retained to retain the thick aluminum layer, thereby reducing the precipitation of silicon chips to reduce interference with the positioning signal, and the mark width of the alignment mark of the K mark area 1203 is set to a specific value. At the same time, a precise alignment pattern aligned along the first direction is provided in the 3rd material layer 1213 and the 5th material layer 1215 to the 8th material layer 1218 of the K-1 mark area 1202, and the 3rd material layer 1213 and the 5th material layer 1215 to the 7th material layer 1217 are removed from the K+1 mark area 1204, effectively improving the signal strength of the detection of the K mark area 1203 during exposure alignment, so that the signal strength of the positioning signal is increased and the noise is not obvious, thereby significantly reducing the risk of position deviation during wafer alignment, and ensuring the accuracy and reliability of wafer alignment.

[0064] In an optional embodiment, a UT1500 lithography machine is used in the manufacturing process of a 1700V FRD chip. In the wafer structure 1, N is 33, and the fine alignment area 121 includes 33 mark areas, wherein the K value is 9. Specifically, the material layer structure of the 7th mark area to the 30th mark area is as follows: Figure 8 As shown. In the figure, the numbers in the table on the lower right side indicate the mark width of the current layer precision alignment pattern 1221; the gray area with numbers indicates that the layer is a dark field area during exposure and has a groove-shaped cross structure; the white area with numbers indicates that the layer is a bright field area during exposure and has an upward convex cross structure; the gray area without numbers indicates that the current layer is a dark field area during exposure and the layer is retained; the white area without numbers indicates that the current layer is a bright field area during exposure and the layer is etched. Figures 9 to 11 After testing the above-mentioned wafer structure, it was found that compared with the existing technology, the amount of silicon chips was effectively curbed, the positioning signal strength of the alignment mark detection was significantly increased, and the intensity of the clutter signal was effectively reduced, which reduced the full inspection rate of the wafer structure from 39.58% in the existing technology to 5.23%, and the overlay rework rate during exposure positioning was reduced from 3.44% to 0.43%.

[0065] In the wafer structure 1 provided in this embodiment, the fine alignment area 121 is divided into N marking areas, the marking area has multiple material layers, and a fine alignment pattern is provided in at least one material layer in each marking area. The fine alignment pattern in the first material layer 1211 forms an alignment mark. When in use, the marking area with the best positioning effect can be judged according to the scanning intensity of the positioning signal of each marking area, thereby realizing effective alignment and positioning of the wafer. The K-1 marking area 1202 to the K-th marking area 1203 have specific structures among the N marking areas, and the thick aluminum layer of the K-th marking area 1203 is retained during the exposure and etching process, which effectively reduces the precipitation of silicon chips and thus reduces the interference with the positioning signal. The 3rd material layer 1213 and the 5th material layer 1215 to the 8th material layer 1218 of the K-1 marking area 1202 are provided with precise alignment patterns aligned along the first direction. The 3rd material layer 1213 and the 5th material layer 1215 to the 7th material layer 1217 are removed from the K+1 marking area 1204, which reduces the intensity of the clutter signal and increases the intensity of the positioning signal, thereby significantly reducing the risk of position deviation during wafer alignment, ensuring the accuracy and reliability of wafer alignment, effectively reducing the rework rate and raw material consumption during the exposure process, saving production costs, ensuring product quality, and having extremely high practical and promotion value.

[0066] Example 2

[0067] This embodiment provides a method for preparing a wafer structure 1, which is used to manufacture any of the wafer structures 1 in the first embodiment. Figure 12 The method for preparing the wafer structure 1 of this embodiment includes steps S1 to S5.

[0068] Step S1: Providing a wafer test piece having a first material layer. Specifically, the first material layer 1211 of the wafer test piece is provided with a fine alignment pattern, and the first material layer 1211 is an alignment layer, wherein the fine alignment pattern is an alignment mark. Optionally, the wafer test piece also has N mark areas divided along the second direction.

[0069] Step S2: forming a second material layer on the first material layer.

[0070] Step S3: coating photoresist on the second material layer and performing development and exposure. Specifically, a suitable mask can be provided according to the specific structure of the wafer structure 1 in the first embodiment to perform development and exposure so as to form a corresponding precisely aligned pattern in the current material layer.

[0071] Step S4: etching and cleaning the exposed second material layer to form a second material layer with a precisely aligned pattern.

[0072] Step S5: Third to Mth material layers having precisely aligned patterns are sequentially formed on the second material layer 1212. Specifically, referring to steps S2 to S4, a third material layer 1213 is formed on the second material layer 1212. Development, exposure, and etching are performed to form the third material layer 1213 having precisely aligned patterns. Similarly, referring to the above steps, the fourth to Mth material layers are formed. Optionally, M is set to 8, and the third to eighth material layers 1218 having precisely aligned patterns are sequentially formed on the second material layer 1212.

[0073] In an optional embodiment, the value of M is 8, and the N marking areas formed also include the K-1th marking area 1202 to the K+1th marking area 1204 in the first embodiment. Among them, the K-1 marking area 1202 includes the 1st material layer 1211 to the 8th material layer 1218, and the second type of graphics are arranged in the 3rd material layer 1213 and the 5th material layer 1215 to the 8th material layer 1218 of the K-1 marking area 1202; the K marking area 1203 includes the 1st material layer 1211 to the 4th material layer 1214, the 6th material layer 1216, and the 8th material layer 1218, and the first type of graphics or the second type of graphics are arranged in the 1st material layer 1211 of the K marking area 1203; the K+1 marking area 1204 includes the 1st material layer 1211 to the 2nd material layer 1212, the 4th material layer 1214 and the 8th material layer 1218, and the first type of graphics or the second type of graphics are arranged in the 1st material layer 1211 of the K+1 area.

[0074] In an optional embodiment, the sixth material layer 1216 is a thick aluminum layer, which can be deposited on the surface of the wafer specimen by a magnetron sputtering process. Optionally, the material of the thick aluminum layer is a silicon-aluminum alloy containing 1% or about 1% silicon, and the thickness of the thick aluminum layer is 4μm or other suitable thickness.

[0075] The method for preparing the wafer structure 1 provided in this embodiment is used to manufacture the wafer structure 1 in the first embodiment, and therefore also has the beneficial effects of the first embodiment.

[0076] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify, alter, or combine the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or variations accomplished by a person of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A wafer structure, characterized in that: The wafer structure includes a chip region and a positioning region located outside the chip region, wherein the positioning region includes a fine alignment region, and the fine alignment region includes eight material layers stacked sequentially along a first direction, and are respectively recorded as the first to eighth material layers along the first direction; wherein the first direction is the thickness direction of the wafer structure; When the wafer structure is viewed from above along the first direction, the fine alignment region is in a strip-shaped structure. The extension direction of the strip-shaped structure of the fine alignment region is a second direction. The fine alignment region is divided into N marking regions along the second direction, which are sequentially recorded as first to Nth marking regions along the second direction, wherein N is a positive integer greater than 3. A fine alignment pattern is provided in at least one material layer of each marking region, and the first material layer is an alignment layer. The fine alignment pattern in the first material layer is an alignment mark. In which, the precise alignment pattern is a cross-shaped structure, including a second type of pattern in a groove-shaped cross structure; among the 1st to 8th material layers in the precise alignment area, the 6th material layer is a thick aluminum layer, and there are K-1th to K+1th marking areas in the N marking areas, the K-1th marking area includes the 1st to 8th material layers, and the second type of pattern is arranged in the 3rd material layer and the 5th to 8th material layers of the K-1th marking area, the Kth marking area includes the 1st to 4th material layers, the 6th material layer and the 8th material layer, the K+1th marking area includes the 1st to 2nd material layers, the 4th material layer and the 8th material layer, and does not contain the 3rd material layer and the 5th to 7th material layers, and K is a positive integer less than N.

2. The wafer structure according to claim 1, wherein: The second material layer to the fourth material layer are material injection layers, the fifth material layer is a polysilicon layer, and the seventh material layer and the eighth material layer are passivation layers.

3. The wafer structure according to claim 1, wherein: The precise alignment pattern also includes a first type of pattern, which is an upward convex cross structure.

4. The wafer structure according to claim 3, characterized in that: The cross-shaped structure of the precise alignment pattern has four rectangular protrusions. The width of each rectangular protrusion is recorded as a mark width, and the value of the mark width is 1.5 μm to 6 μm.

5. The wafer structure according to claim 3, wherein: In the K-1th marking area, the second type of patterns in the third material layer and the second type of patterns in the fifth to eighth material layers are aligned along the first direction.

6. The wafer structure according to claim 3, characterized in that: The first material layer of the Kth marking area is provided with the first type of graphics or the second type of graphics; The first type of pattern or the second type of pattern is provided in the first material layer of the K+1th region.

7. The wafer structure according to claim 6, characterized in that: In the first material layer of the Kth mark area, the mark width of the fine alignment pattern is a first width; In the third material layer and the fifth to eighth material layers of the K-1th region, the mark width of the second type of graphics is the second width.

8. The wafer structure according to claim 7, wherein: The first width is 2.5 μm or 5 μm, and the second width is 3 μm.

9. A method for preparing a wafer structure, for manufacturing the wafer structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: Providing a wafer test piece having a first material layer, wherein the first material layer is provided with a precise alignment pattern; forming a second material layer on the first material layer; coating a photoresist on the second material layer and performing development and exposure; Etching and cleaning the exposed second material layer to form a second material layer having a precisely aligned pattern; The third to eighth material layers having precise alignment patterns are sequentially formed on the second material layer.

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