Semiconductor device

Abstract

The invention provides a semiconductor device which comprises an MIM capacitor and a capacitance enhancement structure, the capacitance enhancement structure is located above the MIM capacitor, the MIM capacitor comprises a lower metal layer, an upper metal layer and a first dielectric layer arranged between the lower metal layer and the upper metal layer, the capacitance enhancement structure comprises a signal line and a first ground wire which are parallel to each other and arranged at an interval, and the first dielectric layer is located above the signal line. A second dielectric layer is arranged between the signal wire and the first ground wire, the signal wire is located on the side, close to the MIM capacitor, of the first ground wire, the signal wire is connected with the upper metal layer, the length of the signal wire is 58-65 microns, and the width of the signal wire is 0.25-0.37 microns. The capacitance enhancement structure is formed by arranging the signal line and the first ground wire which are parallel to each other and arranging the second dielectric layer between the signal line and the first ground wire, and the signal line is arranged to be connected with the upper metal layer, so that a parasitic coupling MIM capacitor is generated between the signal line and the first ground wire, and the capacitance value of the MIM capacitor is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] In the integrated circuit of semiconductor device, usually capacitor and transistor integrated design are in the same chip or circuit, wherein, capacitor mainly includes metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitor and metal-oxide-metal (Metal-Oxide-Metal, MOM) capacitor two kinds.But the capacitance per unit area of ​​MOM capacitor is higher, about 3 times of MIM capacitor, and the capacitance density of MOM capacitor can gradually increase with the increase of frequency, while the capacitance density of MIM capacitor under the same area is more stable.Therefore, how to improve the capacitance value of MIM capacitor without increasing the MIM capacitor area is a problem that urgently needs to be solved at present. Summary of the invention

[0003] In view of this, the present application provides a semiconductor device to increase the capacitance value of a MIM capacitor.

[0004] The present application provides a semiconductor device, including a MIM capacitor and a capacitor enhancement structure, wherein the capacitor enhancement structure is located above the MIM capacitor, the MIM capacitor includes a lower metal layer, an upper metal layer, and a first dielectric layer arranged between the lower metal layer and the upper metal layer, the capacitor enhancement structure includes a signal line and a first ground line that are parallel to each other and arranged at intervals, a second dielectric layer is arranged between the signal line and the first ground line, the signal line is located on a side of the first ground line close to the MIM capacitor, the signal line is connected to the upper metal layer, the length of the signal line is 58-65μm, and the width of the signal line is 0.25-0.37μm.

[0005] In some embodiments, the semiconductor device further includes a second ground line located on a side of the MIM capacitor away from the first ground line, and the second ground line is connected to the lower metal layer.

[0006] In some embodiments, the second ground line is arranged in parallel with the first ground line and the signal line.

[0007] In some embodiments, the first dielectric layer has a first via and a second via that penetrate the first dielectric layer to expose the upper metal layer and the lower metal layer, the first via and the second via are spaced apart, and the first via and the second via are both filled with a first conductive connection portion to connect the upper metal layer with the lower metal layer.

[0008] In some embodiments, a third dielectric layer is arranged between the signal line and the upper metal layer, and the third dielectric layer has a third via hole that penetrates the third dielectric layer to expose the upper metal layer and the signal line, and the third via hole is filled with a second conductive connection portion to connect the upper metal layer with the signal line.

[0009] In some embodiments, a fourth dielectric layer is arranged between the lower metal layer and the second ground line, and the fourth dielectric layer has a fourth via hole that penetrates the fourth dielectric layer to expose the lower metal layer and the second ground line, and the fourth via hole is filled with a third conductive connection portion to connect the lower metal layer to the second ground line.

[0010] In some embodiments, both the first dielectric layer and the second dielectric layer are silicon oxide layers.

[0011] In some embodiments, the length of the first ground line is 58-65 μm, and the width of the first ground line is 0.25-0.37 μm.

[0012] In some embodiments, the upper metal layer and the lower metal layer are both arranged in parallel with the signal line.

[0013] In some embodiments, in a direction from the lower metal layer toward the signal line, the orthographic projection of the upper metal layer is located within the orthographic projection of the lower metal layer.

[0014] The present application provides a semiconductor device, including a MIM capacitor and a capacitance enhancement structure, the capacitance enhancement structure is located above the MIM capacitor, the MIM capacitor includes a lower metal layer, an upper metal layer and a first dielectric layer arranged between the lower metal layer and the upper metal layer, the capacitance enhancement structure includes a signal line and a first ground line that are parallel to each other and spaced apart, a second dielectric layer is arranged between the signal line and the first ground line, the signal line is located on the side of the first ground line close to the MIM capacitor, the signal line is connected to the upper metal layer, the length of the signal line is 58-65μm, and the width of the signal line is 0.25-0.37μm. By setting a capacitance enhancement structure composed of a signal line and a first ground line that are parallel to each other and a second dielectric layer is arranged between the signal line and the first ground line, and the signal line is set to be connected to the upper metal layer, so that when a voltage is applied to the signal line, the signal line and the first ground line adjacent thereto are respectively charged with opposite charges, thereby generating a parasitic coupling MIM capacitor, thereby increasing the capacitance value of the MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 It is a schematic diagram of the cross-sectional structure of the semiconductor device provided by the present application.

[0017] Reference numerals:

[0018] 10. Semiconductor device; 100. MIM capacitor; 110. Lower metal layer; 120. Upper metal layer; 130. First via; 140. Second via; 150. First conductive connection; 200. Capacitor enhancement structure; 210. Signal line; 220. First ground line; 300. Second ground line; 400. Third via; 500. Second conductive connection; 600. Fourth via; 700. Third conductive connection. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by a person skilled in the art to which this application belongs. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more related listed items. The terms "connection", "electrical connection", and "electrical connection" used herein include any direct and indirect electrical or structural connection means. Therefore, if the text describes a first device coupled / connected / electrically connected to a second device, it means that the first device can be directly electrically / structurally connected to the second device, or indirectly electrically / structurally connected to the second device through other devices or connection means.

[0022] The present application provides a semiconductor device, including a MIM capacitor and a capacitor enhancement structure, wherein the capacitor enhancement structure is located above the MIM capacitor, the MIM capacitor includes a lower metal layer, an upper metal layer, and a first dielectric layer arranged between the lower metal layer and the upper metal layer, the capacitor enhancement structure includes a signal line and a first ground line that are parallel to each other and spaced apart, a second dielectric layer is arranged between the signal line and the first ground line, the signal line is located on a side of the first ground line close to the MIM capacitor, the signal line is connected to the upper metal layer, the length of the signal line is 58-65μm, and the width of the signal line is 0.25-0.37μm.

[0023] In the present application, a capacitance enhancement structure is formed by setting a signal line and a first ground line that are parallel to each other and setting a second dielectric layer between the signal line and the first ground line, and the signal line is set to be connected to the upper metal layer, so that when a voltage is applied to the signal line, the signal line and the first ground line adjacent to it carry opposite charges respectively, thereby generating a parasitic coupled MIM capacitor, thereby increasing the capacitance value of the MIM capacitor.

[0024] See also Figure 1 , Figure 1: is a schematic diagram of the cross-sectional structure of a semiconductor device provided by the present application. The present application provides a semiconductor device 10, including a MIM capacitor 100 and a capacitance enhancement structure 200, the capacitance enhancement structure 200 is located above the MIM capacitor 100, the MIM capacitor 100 includes a lower metal layer 110, an upper metal layer 120 and a first dielectric layer arranged between the lower metal layer 110 and the upper metal layer 120, the capacitance enhancement structure 200 includes a signal line 210 and a first ground line 220 that are parallel to each other and arranged at intervals, a second dielectric layer is arranged between the signal line 210 and the first ground line 220, the signal line 210 is located on the side of the first ground line 220 close to the MIM capacitor 100, the signal line 210 is connected to the upper metal layer 120, the length L1 of the signal line 210 is 58-65μm, and the width W1 of the signal line 210 is 0.25-0.37μm. Specifically, the lower metal layer 110, the first dielectric layer and the upper metal layer 120 are stacked in sequence from bottom to top, and the capacitance enhancement structure 200 is located above the MIM capacitor 100, wherein the signal line 210 is arranged on the side of the upper metal layer 120 away from the lower metal layer 110, the signal line 210 is arranged in parallel with the first ground line 220, the side of the signal line 210 away from the upper metal layer 120 is arranged on the second dielectric layer, and the side of the second dielectric layer away from the signal line 210 is arranged with the first ground line 220; the upper metal layer 120 is connected to the lower metal layer 110, the signal line 210 is connected to the upper metal layer 120, and the lower metal layer 110 and The upper metal layer 120 can be composed of at least one of titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), titanium nitride (TiN) and tantalum nitride (TaN), that is, the lower metal layer 110 and the upper metal layer 120 can be titanium, tantalum layer, tungsten layer, aluminum layer, titanium nitride layer or tantalum nitride layer, etc., respectively. The length L1 of the signal line 210 can be 58μm, 59μm, 60μm, 62.3μm, 64.7μm or 65μm, etc., and the width W1 of the signal line 210 can be 0.25μm, 0.27μm, 0.30μm, 0.32μm, 0.36μm or 0.37μm, etc.

[0025] In the present application, a capacitance enhancement structure 200 is formed by arranging a signal line 210 and a first ground line 220 which are parallel to each other and a second dielectric layer is arranged between the signal line 210 and the first ground line 220, and the signal line 210 is arranged to be connected to the upper metal layer 120, that is, the signal line 210 is used as the upper plate of the capacitance enhancement structure 200, and the first ground line 220 is used as the lower plate of the capacitance enhancement structure 200, so that when a voltage is applied to the signal line 210, the signal line 210 and the first ground line 220 adjacent thereto are respectively charged with opposite charges, thereby generating a parasitic coupling MIM capacitor 100, that is, the signal line 210 and the first ground line 220 are used to generate a parasitic coupling capacitor, so as to increase the capacitance value of the MIM capacitor 100 without increasing the capacitance value. The area of ​​the MIM capacitor 100 is increased to increase the capacitance of the MIM capacitor 100, and test data show that by using the signal line 210 and the first ground line 220 to generate parasitic coupling capacitance, the capacitance of the MIM capacitor 100 can reach 197% of the original capacitance, which is equivalent to saving nearly half of the area of ​​the MIM capacitor 100, thereby reducing the area of ​​the entire semiconductor device 10; the length L1 of the signal line 210 is set in the range of 58-65μm, and the width W1 of the signal line 210 is set in the range of 0.25-0.37μm to further ensure that the electric field is evenly distributed in the second dielectric layer, reduce electric field concentration and edge effects, thereby improving the capacitance stability of the MIM capacitor 100, thereby further improving the performance of the semiconductor device 10.

[0026] In the present application, the signal line 210 is arranged in parallel with the first ground line 220 to ensure that the electric field is evenly distributed in the second dielectric layer, reduce electric field concentration and edge effects, thereby improving the stability of the MIM capacitor 100 value, and at the same time, reducing the interference of the parasitic coupling capacitor on other components in the semiconductor device 10. Especially in high-frequency circuits, the parasitic coupling capacitor may introduce unnecessary signal coupling and noise, affecting the overall performance of the semiconductor device 10. In addition, it can also maintain the integrity and accuracy of the signal, reduce signal distortion and attenuation, and thus ensure the performance of the semiconductor device 10.

[0027] In one embodiment, the length L2 of the first ground line 220 is 58-65 μm, and the width W2 of the first ground line 220 is 0.25-0.37 μm. Specifically, the length L2 of the first ground line 220 can be 58 μm, 59 μm, 60 μm, 62.3 μm, 64.7 μm or 65 μm, etc., and the width W2 of the first ground line 220 can be 0.25 μm, 0.27 μm, 0.30 μm, 0.32 μm, 0.36 μm or 0.37 μm, etc. The length L2 of the first ground line 220 and the width W2 of the first ground line 220 are set in this interval to further ensure that the electric field is evenly distributed in the second dielectric layer, reduce electric field concentration and edge effects, thereby improving the capacitance stability of the MIM capacitor 100, and further improving the performance of the semiconductor device 10.

[0028] In one embodiment, the semiconductor device 10 further includes a second ground line 300 located on the side of the MIM capacitor 100 away from the first ground line 220, and the second ground line 300 is connected to the lower metal layer 110. In the present application, by setting the MIM capacitor 100 to be connected to the second ground line 300, when an overvoltage occurs in the circuit, part of the overvoltage can be introduced into the ground, thereby protecting other components in the semiconductor device 10 from damage. At the same time, during the charging or discharging process of the MIM capacitor 100, the connection with the second ground line can allow the charge to be safely discharged, preventing the charge from accumulating too much inside the MIM capacitor 100 and causing safety hazards, thereby ensuring the performance of the semiconductor device 10.

[0029] In one embodiment, the second ground line 300 is arranged in parallel with the first ground line 220 and the signal line 210 to optimize the circuit layout in the semiconductor device 10, reduce unnecessary space occupation and wiring complexity, and improve circuit integration and performance.

[0030] In one embodiment, the first dielectric layer has a first via hole 130 and a second via hole 140 penetrating the first dielectric layer to expose the upper metal layer 120 and the lower metal layer 110. The first via hole 130 and the second via hole 140 are arranged at intervals. The first via hole 130 and the second via hole 140 are filled with a first conductive connection part 150 to connect the upper metal layer 120 with the lower metal layer 110. The first conductive connection part 150 is made of titanium (Ti), tungsten (W) or aluminum (Al). The first via hole 130 and the second via hole 140 are connected between the upper metal layer 120 and the lower metal layer 110 to ensure the performance of the MIM capacitor 100, thereby ensuring the performance of the semiconductor device 10.

[0031] In one embodiment, a third dielectric layer is provided between the signal line 210 and the upper metal layer 120, and the third dielectric layer has a third via 400 penetrating the third dielectric layer to expose the upper metal layer 120 and the signal line 210, and the third via 400 is filled with a second conductive connection 500 to connect the upper metal layer 120 with the signal line 210. Further, the third dielectric layer is a silicon oxide layer, that is, the third dielectric layer is composed of silicon oxide, and the second conductive connection 500 is composed of titanium (Ti), tungsten (W) or aluminum (Al). The third dielectric layer and the second conductive connection are provided between the signal line 210 and the upper metal layer 120 to ensure the performance of the MIM capacitor 100, thereby ensuring the performance of the semiconductor device 10.

[0032] In one embodiment, a fourth dielectric layer is provided between the lower metal layer 110 and the second ground line 300, and the fourth dielectric layer has a fourth via 600 penetrating the fourth dielectric layer to expose the lower metal layer 110 and the second ground line 300, and the fourth via 600 is filled with a third conductive connection portion 700 to connect the lower metal layer 110 to the second ground line 300. Further, the fourth dielectric layer is a silicon oxide layer, that is, the fourth dielectric layer is composed of silicon oxide, and the third conductive connection portion 700 is composed of titanium (Ti), tungsten (W) or aluminum (Al). By providing the fourth dielectric layer and the third conductive connection portion 700 between the lower metal layer 110 and the second ground line 300, the performance of the MIM capacitor 100 is ensured, thereby ensuring the performance of the semiconductor device 10.

[0033] In one embodiment, the first dielectric layer and the second dielectric layer are both silicon oxide layers, that is, the first dielectric layer and the second dielectric layer are both made of silicon oxide material. Since the first dielectric layer and the second dielectric layer are both silicon oxide layers, the capacitance value of the MIM capacitor 100 is further increased.

[0034] In one embodiment, in a direction from the lower metal layer 110 toward the signal line 210 , the orthographic projection of the MIM capacitor 100 is located within the orthographic projection of the capacitance enhancement structure 200 to further enhance the capacitance of the MIM capacitor 100 , thereby ensuring the performance of the semiconductor device 10 .

[0035] In one embodiment, the upper metal layer 120 and the lower metal layer 110 are both disposed in parallel with the signal line 210 to further increase the capacitance of the MIM capacitor 100 , thereby ensuring the performance of the semiconductor device 10 .

[0036] In one embodiment, in a direction from the lower metal layer 110 toward the signal line 210 , the orthographic projection of the upper metal layer 120 is located within the orthographic projection of the lower metal layer 110 to further enhance the capacitance of the MIM capacitor 100 , thereby ensuring the performance of the semiconductor device 10 .

[0037] In one embodiment, the length L3 of the second ground line 300 is 58-65 μm, and the width W3 of the second ground line 300 is 0.25-0.37 μm. Specifically, the length L3 of the second ground line 300 can be 58 μm, 59 μm, 60 μm, 62.3 μm, 64.7 μm or 65 μm, etc., and the width W3 of the second ground line 300 can be 0.25 μm, 0.27 μm, 0.30 μm, 0.32 μm, 0.36 μm or 0.37 μm, etc. The length L3 of the second ground line 300 and the width W3 of the second ground line 300 are set in this interval to further ensure that the electric field is evenly distributed in the second dielectric layer, reduce electric field concentration and edge effects, thereby improving the capacitance stability of the MIM capacitor 100, and further improving the performance of the semiconductor device 10.

[0038] In one embodiment, the length L4 of the lower metal layer 110 and the upper metal layer 120 is 58-65 μm, and the width W4 of the lower metal layer 110 and the upper metal layer 120 is 0.25-0.37 μm. Specifically, the length L4 of the lower metal layer 110 and the upper metal layer 120 can be 58 μm, 59 μm, 60 μm, 62.3 μm, 64.7 μm or 65 μm, etc., and the width W4 of the lower metal layer 110 and the upper metal layer 120 can be 0.25 μm, 0.27 μm, 0.30 μm, 0.32 μm, 0.36 μm or 0.37 μm, etc. The length L4 and the width W4 of the lower metal layer 110 and the upper metal layer 120 are set in this range to further ensure that the electric field is evenly distributed in the first dielectric layer, reduce electric field concentration and edge effects, thereby improving the capacitance stability of the MIM capacitor 100, thereby further improving the performance of the semiconductor device 10.

[0039] In another embodiment, the second ground line 220 is spaced apart from the signal line 210 and is not arranged in parallel to optimize the circuit layout in the semiconductor device 10, reduce unnecessary space occupation and wiring complexity, and improve the integration and performance of the circuit.

[0040] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: It includes a MIM capacitor and a capacitor enhancement structure, wherein the capacitor enhancement structure is located above the MIM capacitor, the MIM capacitor includes a lower metal layer, an upper metal layer and a first dielectric layer arranged between the lower metal layer and the upper metal layer, the capacitor enhancement structure includes a signal line and a first ground line that are parallel to each other and arranged at intervals, a second dielectric layer is arranged between the signal line and the first ground line, the signal line is located on a side of the first ground line close to the MIM capacitor, the signal line is connected to the upper metal layer, the length of the signal line is 58-65μm, and the width of the signal line is 0.25-0.37μm.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a second ground line located at a side of the MIM capacitor away from the first ground line, and the second ground line is connected to the lower metal layer.

3. The semiconductor device according to claim 2, characterized in that The second ground line is arranged in parallel with the first ground line and the signal line.

4. The semiconductor device according to claim 1, wherein: The first dielectric layer has a first via and a second via that penetrate the first dielectric layer to expose the upper metal layer and the lower metal layer. The first via and the second via are spaced apart. The first via and the second via are both filled with a first conductive connection portion to connect the upper metal layer with the lower metal layer.

5. The semiconductor device according to claim 1, wherein: A third dielectric layer is arranged between the signal line and the upper metal layer. The third dielectric layer has a third via hole penetrating the third dielectric layer to expose the upper metal layer and the signal line. The third via hole is filled with a second conductive connection part to connect the upper metal layer with the signal line.

6. The semiconductor device according to claim 3, characterized in that A fourth dielectric layer is arranged between the lower metal layer and the second ground line. The fourth dielectric layer has a fourth via hole that penetrates the fourth dielectric layer to expose the lower metal layer and the second ground line. The fourth via hole is filled with a third conductive connection part to connect the lower metal layer to the second ground line.

7. The semiconductor device according to claim 1, wherein: The first dielectric layer and the second dielectric layer are both silicon oxide layers.

8. The semiconductor device according to claim 1, wherein: The length of the first ground line is 58-65 μm, and the width of the first ground line is 0.25-0.37 μm.

9. The semiconductor device according to claim 1, wherein: The upper metal layer and the lower metal layer are both arranged in parallel with the signal line.

10. The semiconductor device according to claim 1, wherein: In a direction from the lower metal layer toward the signal line, the orthographic projection of the upper metal layer is located within the orthographic projection of the lower metal layer.

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