Chip special for power optimizer and application circuit thereof

Abstract

The invention discloses a chip special for a power optimizer and an application circuit thereof, the chip special for the power optimizer comprises a packaging body, and an MCU chip, driving chips and power devices which are packaged in the packaging body, the MCU chip is correspondingly connected with at least one driving chip through at least one PWM pin, each driving chip drives two power devices, and the power devices are connected with the power optimizer. Functional pins of the power device serve as a power node pin, a power ground pin and a drain electrode pin of the special chip and are directly led out of the packaging body; the MCU chip is integrated with an MMPT algorithm module and a power loop control algorithm module, so that research and development engineers can directly call the algorithm module in the development process conveniently, the development process is simplified, the research and development cycle can be shortened, and the product investment on the market can be accelerated; according to the power optimizer, digital control, PWM driving and power devices are integrated, a solution which is low in cost, small in size and high in efficiency is provided for power optimizers of power generation assemblies such as photovoltaic assemblies, and the power optimizer has very high popularization value.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and electronic circuits, and in particular relates to a power optimizer dedicated chip and an application circuit thereof. Background Art

[0002] Taking photovoltaic power generation as an example, the output of a single photovoltaic module is often insufficient to provide the actual power demand, so the photovoltaic module array must be formed in series and parallel to meet the design requirements. When selecting photovoltaic modules to form an array, the following situation is usually encountered: due to the inconsistency of the electrical parameters of the photovoltaic modules in series and parallel, or when the strings are partially or intermittently shaded or aged, the output power after series and parallel connection will be less than the sum of the output power of the individual modules. This situation is professionally called "mismatch loss". As the operating life of the photovoltaic power station increases, it will affect the actual power generation of the entire power station to varying degrees.

[0003] In order to eliminate the impact of the above situation and increase photovoltaic power generation, the current common solution in the industry is to add a photovoltaic power optimizer. That is, in a photovoltaic module containing multiple series and parallel connections, each photovoltaic module is connected to a power optimizer with an independent maximum power point tracking function, and the output of each photovoltaic module is connected to the input of the power optimizer module. In this way, each photovoltaic module is an independent entity relative to the photovoltaic array, and its output power will not be affected by any other components, and it always outputs the maximum power value under the current environmental conditions.

[0004] However, the key components of photovoltaic optimizers currently used in the market, such as power devices, driver chips, controllers, etc., are usually built using discrete devices, with low integration, large size, long R&D cycle, high cost, and are not easy to install and use. Summary of the invention

[0005] In order to solve the above technical problems, the present invention proposes a power optimizer dedicated chip and its application circuit. The present invention is implemented by the following technical solutions:

[0006] According to a first aspect of the present invention, a power optimizer dedicated chip is provided, characterized in that it comprises a package body and an MCU chip, a first driver chip, a first power device, and a second power device encapsulated in the package body; the MCU chip integrates an MMPT algorithm module and a power loop control algorithm module; the MCU chip has a first PWM output pin, and the first PWM output pin is connected to the PWM input pin of the first driver chip in the package body; the first driver output terminal and the second driver output terminal of the first driver chip are respectively connected to the gate of the first power device and the gate of the second power device in the package body; the drain of the first power device serves as the first drain pin of the dedicated chip and is led out of the package body, the source of the second power device serves as the power ground pin of the dedicated chip and is led out of the package body, and the source of the first power device and the drain of the second power device jointly serve as the first power node pin of the dedicated chip and are led out of the package body.

[0007] As a preferred technical solution, the first driver chip has a group of high-side driver power supply pins and a group of low-side driver power supply pins that are led out of the dedicated chip and are respectively led out of the package body.

[0008] As a preferred technical solution, the power optimizer dedicated chip also includes a second driver chip, a third power device and a fourth power device; the MCU chip has a second PWM output pin, and the second PWM output pin is connected to the PWM input pin of the second driver chip in the package; the first driver output terminal and the second driver output terminal of the second driver chip are respectively connected to the gate of the third power device and the gate of the fourth power device in the package; the drain of the fourth power device serves as the second drain pin of the dedicated chip and is led out of the package, the source of the third power device is connected to the power ground pin, and the drain of the third power device and the source of the fourth power device jointly serve as the second power node pin of the dedicated chip and are led out of the package.

[0009] As a preferred technical solution, the second driver chip has a group of high-side driver power supply pins and a group of low-side driver power supply pins that are led out of the dedicated chip and are respectively led out of the package body.

[0010] As a preferred technical solution, the first power device, the second power device, the third power device and the fourth power device are GAN power devices.

[0011] As a preferred technical solution, the MCU chip has a sampling signal processing module and a sampling signal input pin directly led out of the package body.

[0012] As a preferred technical solution, the MCU chip has a signal comparison module and a comparison signal input pin directly led out of the package body.

[0013] As a preferred technical solution, the MCU chip has a HRPWM signal processing module and a HRPWM signal pin directly led out of the package body.

[0014] As a preferred technical solution, the MCU chip has an I / O module and I / O pins directly led out of the package body.

[0015] As a preferred technical solution, the MCU chip has a data storage control module and data storage pins directly led out of the package body.

[0016] As a preferred technical solution, the MCU chip has a communication control module and communication control pins directly led out of the package body.

[0017] According to a second aspect of the present invention, a power optimizer dedicated chip application circuit is provided, characterized in that it includes: the power optimizer dedicated chip with a dual drive chip as described above; and also includes a capacitor C1, a capacitor C2, a resistor RCS1, a resistor RCS2, and an inductor L1; the positive electrode of the capacitor C1 is connected to the first drain pin and is connected to the positive output end of the power generation component; the negative electrode of the capacitor C1 is connected to the power ground pin and is connected to the negative output end of the power generation component through the resistor RCS1; the positive electrode of the capacitor C2 is connected to the second drain pin and serves as the positive output end of the application circuit; the negative electrode of the capacitor C2 is connected to the power ground pin and serves as the negative output end of the application circuit after passing through the resistor RCS1; the inductor L1 is connected in series between the first power node pin and the second power node pin.

[0018] The third aspect of the present invention provides another power optimizer dedicated chip application circuit, characterized in that it includes: the power optimizer dedicated chip with dual drive chip mentioned above; also includes capacitor C1, capacitor C2, resistor RCS1, resistor RCS2, inductor L1, inductor L2; the positive electrode of capacitor C1 is connected to the voltage bus VBUS and the first drain pin, and the negative electrode is connected to the power ground pin; the positive electrode of capacitor C2 is connected to the voltage bus VBUS and the second drain pin, and the negative electrode is connected to the power ground pin; the power ground pin is connected to the negative output end of the power generation component and the negative output end of the application circuit through resistors RCS1 and RCS2 respectively; the first power node pin and the second power node pin are connected to the positive output end of the power generation component and the positive output end of the application circuit respectively.

[0019] The power optimizer dedicated chip provided by the above technical solution of the present invention integrates digital control, PWM drive, and power devices in one, providing a low-cost, small-volume, and high-efficiency solution for power optimizers of power generation components such as photovoltaic components, which can shorten the R&D cycle and production assembly time of the entire power optimizer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the internal structure of a first power optimizer dedicated chip provided for a specific implementation of the present invention.

[0021] Figure 2 This is an example diagram of an application scenario of the first power optimizer dedicated chip provided in a specific embodiment of the present invention.

[0022] Figure 3 A schematic diagram of the internal structure of a second power optimizer dedicated chip provided for a specific implementation of the present invention.

[0023] Figure 4 A pin function diagram of a second power optimizer dedicated chip provided for a specific implementation of the present invention.

[0024] Figure 5 A schematic diagram of an application circuit of a second power optimizer dedicated chip provided for a specific implementation of the present invention.

[0025] Figure 6 Another application circuit schematic diagram of the second power optimizer dedicated chip provided for the specific implementation mode of the present invention. DETAILED DESCRIPTION

[0026] The technical solutions of the embodiments of the present invention are explained and described below in conjunction with the drawings of the embodiments of the present invention, but the following embodiments are only preferred embodiments of the present invention, not all. Based on the embodiments in the implementation mode, other embodiments obtained by those skilled in the art without creative work are all within the protection scope of the present invention.

[0027] like Figure 1 As shown, the first power optimizer dedicated chip provided by the embodiment of the present invention can be applied to photovoltaic power optimizers or other similar power optimizers of power generation components. The power optimizer dedicated chip includes a package body and an MCU chip encapsulated in the package body, a first driver chip Driver1, a first power device GAN_H1, and a second power device GAN_L1.

[0028] The MCU chip integrates an MMPT algorithm module and a power loop control algorithm module for realizing power optimization control; the MCU chip has a first PWM output pin, which is connected to the PWM input pin of the first driver chip Driver1 in the package; the first driver output terminal and the second driver output terminal of the first driver chip Driver1 are respectively connected to the gate (G pole) of the first power device GAN_H1 and the gate (G pole) of the second power device GAN_L1 in the package; the drain (D pole) of the first power device GAN_H1 serves as the first drain pin D1 of the dedicated chip and is led out of the package, the source (S pole) of the second power device GAN_L1 serves as the power ground pin PGND of the dedicated chip and is led out of the package, and the source (S pole) of the first power device GAN_H1 and the drain (D pole) of the second power device GAN_L1 serve together as the first power node pin SW1 of the dedicated chip and are led out of the package.

[0029] Among them, the first driver chip Driver1 has a group of high-side driver power supply pins HB1 and HS1 led out of the dedicated chip, and also has a group of low-side driver power supply pins COM1 and VDD1. The high-side driver power supply pins HB1 and HS1 and the low-side driver power supply pins COM1 and VDD1 are respectively led out of the package body.

[0030] The power optimizer dedicated chip adopts a single drive chip and a dual power device structure. In specific applications, the power optimizer 100 using the dedicated chip can be connected in series to the string group of power generation components by using the first drain pin D1 and the first power node pin SW1. Figure 2 shown.

[0031] like Figure 3 and Figure 4 As shown, the second power optimizer dedicated chip provided by the embodiment of the present invention is Figure 1On the basis of the dedicated chip shown, it also includes a second driver chip Driver2, a third power device GAN_H2 and a fourth power device GAN_L2; the MCU chip also has a second PWM output pin, and the second PWM output pin is connected to the PWM input pin of the second driver chip Driver2 in the package; the first driver output end and the second driver output end of the second driver chip Driver2 are respectively connected to the gate (G pole) of the third power device GAN_H2 and the gate (G pole) of the fourth power device GAN_L2 in the package; the drain (D pole) of the fourth power device GAN_L2 serves as the second drain pin D2 of the dedicated chip and is led out of the package, the source (S pole) of the third power device GAN_H2 is connected to the power ground pin PGND, and the drain (D pole) of the third power device GAN_H2 and the source (S pole) of the fourth power device GAN_L2 jointly serve as the second power node pin SW2 of the dedicated chip and are led out of the package.

[0032] Similarly, the second driver chip Driver2 has a group of high-side driver power supply pins HB2 and HS2 led out of the dedicated chip, and also has a group of low-side driver power supply pins COM2 and VDD2. The high-side driver power supply pins HB2 and HS2 and the low-side driver power supply pins COM2 and VDD2 are respectively led out of the package body.

[0033] In the second power optimizer dedicated chip provided in the above embodiment, the MCU chip provides external communication, signal sampling, power supply control, IO control and other functions of the photovoltaic optimizer; the two integrated isolated or non-isolated half-bridge driver chips Driver1 and Driver2 play a connecting role; the driver chips Driver1 and Driver2 are controlled by the MCU chip and directly control the on and off of the corresponding power devices at the same time; the four integrated power devices are all GAN ​​power devices, GAN_H1 and GAN_L1 form the upper and lower tube power circuit nodes SW1, and GAN_H2 and GAN_L2 form the upper and lower tube power circuit nodes SW2; because the GAN power device has small parasitic parameters, it can provide higher working efficiency and switching frequency for the photovoltaic power optimizer, and can reduce the volume and cost of the photovoltaic power optimizer.

[0034] In addition, the driver chips Driver1 and Driver2 are directly connected to the gate of the MCU chip and the power device inside the package, reducing the parasitic parameters of the circuit; at the same time, the two driver chips respectively lead out the lower tube driver power supply pins VDD and COM, and the upper tube driver power supply pins HB and HS. The upper tube driver power supply can use a power supply independent of the lower tube or a bootstrap drive power supply method.

[0035] Continue to see Figure 3 and Figure 4In the dedicated chip provided in the above embodiment, the MCU chip has a sampling signal processing module and a sampling signal input pin directly led out of the package body, and the MCU chip also has a signal comparison module and a comparison signal input pin directly led out of the package body; for example, the MCU chip leads out ADC1 / COMP1-ADC6 / COMP6 to provide signal sampling and internal comparator protection functions for the photovoltaic power optimizer. The MCU chip has an HRPWM signal processing module and an HRPWM signal pin directly led out of the package body; for example, the MCU chip leads out HRPWM1 and HRPWM2 pins to reserve the PWM control requirements of the photovoltaic power optimizer. The MCU chip has an I / O module and an I / O pin directly led out of the package body; for example, the PA1-PA6 led out of the MCU chip can provide I / O control requirements for the photovoltaic power optimizer. The MCU chip has a data storage control module and a data storage pin directly led out of the package body; for example, the MCU chip leads out SDA and SCL pins to provide external storage connection for the photovoltaic power optimizer. The MCU chip also has a communication control module and communication control pins directly led out of the package body; for example, the MCU chip leads out UART0_RX / GAN_RX and UART0_TX / GAN_TX to provide a link for the photovoltaic power optimizer to communicate with the outside.

[0036] In the dedicated chip provided in the above embodiment, the names and functions of the pins are as follows:

[0037]

[0038]

[0039] In the above embodiments, the MCU chip can adopt the existing MCU chip with PWM control, and can integrate the MMPT algorithm and the power loop control algorithm, such as: the MCU chips of TAE32F5300 and TAE32G5800 of Zhuhai Taiwei Electronics Co., Ltd. The first driver chip Driver1 and the first driver chip Driver2 can adopt the existing power device driver chip, such as: the NSD2621X series driver chip of Nanochip Microelectronics. In addition, all power devices use GAN (gallium nitride) power devices, which can provide higher power generation efficiency and switching frequency, which can further reduce the volume and cost of the product.

[0040] The dedicated chip provided in the above embodiment integrates digital control, PWM drive, and GAN power devices in one; since the three key devices are sealed together, the volume is smaller, and it is more convenient to use and assemble. At the same time, its integrated GAN power device can provide higher power generation efficiency and switching frequency, which can further reduce the volume and cost of the product; in addition, the dedicated chip of the present invention solidifies the MMPT algorithm and the power loop control algorithm, which can be convenient for R&D engineers to directly call during the development process, simplify the development process, shorten the R&D cycle, and accelerate the product to the market. Therefore, the present invention provides a low-cost, small-volume, high-efficiency, and R&D cycle-shortening solution for photovoltaic optimizers, which has great promotion value and economic benefits.

[0041] like Figure 5 As shown, an embodiment of the present invention also provides a power optimizer dedicated chip application circuit, including: the power optimizer dedicated chip with dual drive chip mentioned above; also including capacitor C1, capacitor C2, resistor RCS1, resistor RCS2, inductor L1; the positive electrode of capacitor C1 is connected to the first drain pin, and is connected to the positive output end of the power generation component; the negative electrode of capacitor C1 is connected to the power ground pin, and is connected to the negative output end of the power generation component through resistor RCS1; the positive electrode of capacitor C2 is connected to the second drain pin, and serves as the positive output end of the application circuit; the negative electrode of capacitor C2 is connected to the power ground pin, and serves as the negative output end of the application circuit after passing through resistor RCS1; inductor L1 is connected in series between the first power node pin and the second power node pin.

[0042] like Figure 6 As shown, an embodiment of the present invention also provides another power optimizer dedicated chip application circuit, including: the power optimizer dedicated chip with dual drive chip mentioned above; also including capacitor C1, capacitor C2, resistor RCS1, resistor RCS2, inductor L1, inductor L2; the positive electrode of capacitor C1 is connected to the voltage bus VBUS and the first drain pin, and the negative electrode is connected to the power ground pin; the positive electrode of capacitor C2 is connected to the voltage bus VBUS and the second drain pin, and the negative electrode is connected to the power ground pin; the power ground pin is connected to the negative output end of the power generation component and the negative output end of the application circuit through resistors RCS1 and RCS2 respectively; the first power node pin and the second power node pin are connected to the positive output end of the power generation component and the positive output end of the application circuit respectively.

[0043] The above embodiments are only preferred embodiments that fully disclose but do not limit the present invention. Any replacement of equivalent technical features based on the creative purpose of the present invention and without creative labor should be regarded as the scope of disclosure of this application. For example, the functions, names, quantities, and sequences of the pinouts are not limited to the legends of the present invention, and other applications based on the ideas and structures of the present invention are within the protection scope of the present invention; the present invention is not limited to the photovoltaic power optimizer application proposed by the present invention, but can also be applied to other application scenarios based on the present invention, such as battery charging and discharging application scenarios.

Claims

1. A power optimizer dedicated chip, It is characterized in that It includes a package body and an MCU chip, a first driver chip, a first power device, and a second power device packaged in the package body; the MCU chip integrates an MMPT algorithm module and a power loop control algorithm module; the MCU chip has a first PWM output pin, and the first PWM output pin is connected to the PWM input pin of the first driver chip in the package body; the first driver output terminal and the second driver output terminal of the first driver chip are respectively connected to the gate of the first power device and the gate of the second power device in the package body; the drain of the first power device serves as the first drain pin of the dedicated chip and is led out of the package body, the source of the second power device serves as the power ground pin of the dedicated chip and is led out of the package body, and the source of the first power device and the drain of the second power device jointly serve as the first power node pin of the dedicated chip and are led out of the package body.

2. The power optimizer dedicated chip according to claim 1, It is characterized in that The first driver chip has a group of high-side driver power supply pins and a group of low-side driver power supply pins that are led out of the dedicated chip and are respectively led out of the package body.

3. The power optimizer dedicated chip according to claim 2, It is characterized in that The power optimizer dedicated chip also includes a second driver chip, a third power device and a fourth power device; the MCU chip has a second PWM output pin, and the second PWM output pin is connected to the PWM input pin of the second driver chip in the package; the first driver output terminal and the second driver output terminal of the second driver chip are respectively connected to the gate of the third power device and the gate of the fourth power device in the package; the drain of the fourth power device serves as the second drain pin of the dedicated chip and is led out of the package, the source of the third power device is connected to the power ground pin, and the drain of the third power device and the source of the fourth power device jointly serve as the second power node pin of the dedicated chip and are led out of the package.

4. The power optimizer dedicated chip according to claim 3, It is characterized in that The second driver chip has a group of high-side driver power supply pins and a group of low-side driver power supply pins that are led out of the dedicated chip and are respectively led out of the package body.

5. The power optimizer dedicated chip according to any one of claims 1 to 4, It is characterized in that The first power device, the second power device, the third power device and the fourth power device are GAN power devices.

6. The power optimizer dedicated chip according to any one of claims 1 to 4, It is characterized in that The MCU chip has a sampling signal processing module and a sampling signal input pin directly led out of the package body.

7. The power optimizer dedicated chip according to any one of claims 1 to 4, It is characterized in that The MCU chip has a signal comparison module and a comparison signal input pin directly led out of the package body.

8. The power optimizer dedicated chip according to any one of claims 1 to 4, It is characterized in that The MCU chip has an HRPWM signal processing module and an HRPWM signal pin directly led out of the package body.

9. The power optimizer dedicated chip according to any one of claims 1 to 4, It is characterized in that The MCU chip has an I / O module and I / O pins directly led out of the package body.

10. The power optimizer dedicated chip according to any one of claims 1 to 4, It is characterized in that The MCU chip has a data storage control module and data storage pins directly led out of the package body.

11. The power optimizer dedicated chip according to any one of claims 1 to 4, It is characterized in that The MCU chip has a communication control module and communication control pins directly led out of the package body.

12. A power optimizer dedicated chip application circuit, It is characterized in that include: The power optimizer dedicated chip as described in any one of claims 1-11; also includes capacitor C1, capacitor C2, resistor RCS1, resistor RCS2, and inductor L1; the positive electrode of capacitor C1 is connected to the first drain pin and connected to the positive output end of the power generation component; the negative electrode of capacitor C1 is connected to the power ground pin and connected to the negative output end of the power generation component through resistor RCS1; the positive electrode of capacitor C2 is connected to the second drain pin and serves as the positive output end of the application circuit; the negative electrode of capacitor C2 is connected to the power ground pin and serves as the negative output end of the application circuit after passing through resistor RCS1; inductor L1 is connected in series between the first power node pin and the second power node pin.

13. A power optimizer dedicated chip application circuit, It is characterized in that include: The power optimizer dedicated chip as described in any one of claims 1-11; also includes capacitor C1, capacitor C2, resistor RCS1, resistor RCS2, inductor L1, inductor L2; the positive electrode of capacitor C1 is connected to the voltage bus VBUS and the first drain pin, and the negative electrode is connected to the power ground pin; the positive electrode of capacitor C2 is connected to the voltage bus VBUS and the second drain pin, and the negative electrode is connected to the power ground pin; the power ground pin is connected to the negative output end of the power generation component and the negative output end of the application circuit through resistors RCS1 and RCS2 respectively; the first power node pin and the second power node pin are respectively connected to the positive output end of the power generation component and the positive output end of the application circuit.

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