Method for manufacturing semiconductor device

Abstract

A semiconductor manufacturing method includes: forming an epitaxial stack on a substrate, the epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a fin in the epitaxial stack; forming a sacrificial gate stack on the plurality of channel regions of the fin; forming a plurality of gate sidewall spacers on a plurality of sidewalls of the sacrificial gate stack; performing a plurality of pretreatment operations to remove a plurality of impurities from the at least one sacrificial epitaxial layer; recessing the at least one sacrificial epitaxial layer to form a cavity; forming an internal spacer material in the cavity; forming a plurality of source / gate features; removing the sacrificial gate stack and the at least one sacrificial epitaxial layer in the fins; and forming a metal gate to replace the sacrificial gate stack and the at least one sacrificial epitaxial layer, wherein the internal spacer material has a thickness sufficient to resist epitaxial damage.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. Background Art

[0002] Semiconductor devices have been used in a variety of electrical appliances, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are usually made by sequentially configuring insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning each material layer through photolithography technology to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the packing density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more electronic components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that must be addressed. Summary of the invention

[0004] A technical aspect of the present disclosure is a method for manufacturing a semiconductor device, comprising: forming an epitaxial stack on a substrate, the epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming fins in the epitaxial stack; forming a sacrificial gate stack on multiple channel regions of the fins; forming multiple gate sidewall spacers on multiple sidewalls of the sacrificial gate stack; performing multiple pre-processing operations to remove multiple impurities from at least one sacrificial epitaxial layer; recessing at least one sacrificial epitaxial layer to form a cavity; forming an internal spacing material in the cavity; forming multiple source / gate features; removing the sacrificial gate stack and at least one sacrificial epitaxial layer in the fins; and forming a metal gate to replace the sacrificial gate stack and at least one sacrificial epitaxial layer, wherein the internal spacing material has a thickness sufficient to resist epitaxial damage.

[0005] A technical aspect of the present disclosure is a method for manufacturing a semiconductor device, comprising: forming an epitaxial stack on a substrate, the epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming fins in the epitaxial stack; forming a sacrificial gate stack on multiple channel regions of the fins; forming multiple gate sidewall spacers on the sidewalls of the sacrificial gate stack; performing multiple pre-treatment operations to remove multiple impurities from at least one sacrificial epitaxial layer, wherein the multiple pre-treatment operations include: applying hydrogen radicals and nitrogen radicals to at least one sacrificial epitaxial layer and at least one channel epitaxial layer; and applying hydrogen fluoride rinsing to remove byproducts of applying hydrogen radicals and oxygen radicals; recessing at least one sacrificial epitaxial layer to form a cavity; and forming an internal spacing material in the cavity, wherein the internal spacing material has a thickness sufficient to resist epitaxial damage.

[0006] A technical aspect of the present disclosure is a method for manufacturing a semiconductor device, comprising: forming an epitaxial stack on a substrate, the epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming fins in the epitaxial stack; forming a sacrificial gate stack on multiple channel regions of the fins; forming multiple gate sidewall spacers on multiple sidewalls of the sacrificial gate stack; performing multiple pre-processing operations to remove multiple impurities from at least one sacrificial epitaxial layer, wherein the multiple pre-processing operations include multiple nitridation operations, multiple carbon removal operations, and multiple oxide layer removal operations; recessing at least one sacrificial epitaxial layer to form a cavity; and forming an internal spacing material in the cavity, wherein the internal spacing material has a thickness sufficient to resist epitaxial damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read together with the accompanying drawings, the aspects of the present disclosure can be best understood from the following embodiments. Note that according to standard practice in this industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flowchart depicting an example method for fabricating a semiconductor device including a multi-gate device according to some embodiments;

[0009] Figures 2 to 11 and Figure 13 to Figure 22 Schematic diagrams for depicting semiconductor devices or structures at various stages of fabrication according to some embodiments;

[0010] Fig. 12A and Fig. 12B A block diagram of an example of pre-processing operations according to some embodiments.

[0011]

Explanation of symbols

[0012] 100: Method

[0013] 102~132: Block

[0014] 200: Installation

[0015] 202:Substrate

[0016] 212: Epitaxial stacking

[0017] 214: Sacrificial epitaxial layer

[0018] 216: channel epitaxial layer

[0019] 220: Fins

[0020] 222: Isolation Features

[0021] 224: Sacrificial gate structure

[0022] 226: Sacrificial gate dielectric layer

[0023] 228: Sacrificial gate electrode layer

[0024] 232: Gate sidewall spacer

[0025] 233: Impurities

[0026] 234: concave part

[0027] 236: Cavity

[0028] 238: Internal spacer material layer

[0029] 240: Source / Drain Characteristics

[0030] 242: Contact etching stop layer

[0031] 244: Interlayer dielectric layer

[0032] 254: Gate groove

[0033] 260: Gate structure

[0034] 262: Interface layer

[0035] 264: High dielectric constant dielectric layer

[0036] 300: Pre-processing operation

[0037] 302: Nitriding operation

[0038] 304: Carbon Removal Operation

[0039] 306: Oxide Removal Operation

[0040] 310~320: Size DETAILED DESCRIPTION

[0041] The following disclosure provides many different implementations or examples for implementing the different features of the described subject matter. Specific examples of components and configurations are described below to simplify this specification. Of course, these are merely examples and are not restrictive.

[0042] For the sake of brevity, conventional techniques associated with conventional semiconductor device manufacturing may not be described in detail herein. Furthermore, the various operations and procedures described herein may be integrated into a more complete process or procedure having additional functions not described in detail herein. Specifically, there are a variety of processes for the manufacture of semiconductor devices that are well known, and therefore, for the sake of brevity, many conventional procedures will only be briefly mentioned or omitted entirely in this article without providing those well-known details. It will be apparent to those skilled in the art after reading this disclosure in its entirety that the structures disclosed herein can be used in a variety of technological fields and can be integrated into a wide variety of semiconductor devices and products. In addition, it should be noted that the semiconductor device structure includes an indefinite number of components, and a single component illustrated in the accompanying drawings may represent multiple components.

[0043] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers, parts and / or sections in this article, these elements, components, regions, layers, parts and / or sections should not be limited by these terms. These terms are only used to separate one element, component, region, layer, part or section from another element, component, region, layer, part or section. Therefore, the first "element", "component", "region", "layer", "part" or "section" discussed below can be referred to as a second element, component, region, layer, part or section without departing from the teachings of this article.

[0044] Spatially relative terms such as "on", "above", "over", "upper", "top", "below", "below", "under", "lower", "bottom", etc. may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. When a spatially relative descriptor, such as those listed above, is used to describe the relationship of a first element to a second element, the first element may be directly on the second element, or there may be other separating elements or layers.

[0045] In addition, the disclosure may repeat reference numerals and / or reference letters in multiple examples. Such repetition is for the purpose of brevity and clarity, and does not in itself indicate the relationship between the multiple embodiments and / or configurations discussed.

[0046] Note that in this specification, references to "one embodiment", "an embodiment", "an example", "exemplary", "example", etc. indicate that the embodiment may have a specific feature, structure or property, but not every embodiment may have the specific feature, structure or property. In addition, such statements do not necessarily refer to the same embodiment. Moreover, when describing a specific feature, structure or property related to an embodiment, whether or not it is explicitly described, a person skilled in the art should understand whether the specific feature, structure or property is related to other embodiments.

[0047] In certain embodiments herein, a "material layer" is a layer containing at least 50% by weight of a known material, such as at least 60% by weight of a known material, at least 75% by weight of a known material, at least 90% by weight of a known material, at least 95% by weight of a known material, or at least 99% by weight of a known material. And a layer of "material" is a layer containing at least 50% by weight of a known material, such as at least 60% by weight of a known material, at least 75% by weight of a known material, at least 90% by weight of a known material, at least 95% by weight of a known material, or at least 99% by weight of a known material. For example, in certain embodiments, a layer of aluminum and a layer of aluminum are each at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of aluminum.

[0048] It is to be understood that the words and terms herein are used for the purpose of description rather than limitation, so that the words and terms of the specification can be interpreted by those familiar with the relevant art in view of the teachings of this document.

[0049] The following disclosure provides many different embodiments or examples for implementing different features of the described subject matter. Specific examples of components and configurations are described below to simplify this specification. Of course, these are merely examples and are not restrictive. For example, in the subsequent description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, in the description herein, unless otherwise stated, the same reference numerals in different figures refer to the same or similar parts formed using the same or similar materials and the same or similar methods.

[0050] Herein, various embodiments are discussed in a specific context, namely, regarding the formation of a semiconductor structure including a fin field effect transistor (FinFET) device. The semiconductor structure, for example, can be a complementary metal oxide semiconductor (CMOS) FinFET device including a P-type metal oxide semiconductor (PMOS) FinFET device and an N-type metal oxide semiconductor (NMOS) FinFET device. Now, the embodiments will be discussed with a specific example of a manufacturing process including a FinFET. However, the embodiments are not limited to the examples provided herein, and the same concepts can be practiced in a wide variety of embodiments. Therefore, various embodiments can be applied in other semiconductor devices / processes, such as planar transistors, etc. In addition, some embodiments herein are discussed in the context of devices formed using a gate-last process. In other embodiments, a gate-first process may be used.

[0051] Even though various embodiments of semiconductor devices are depicted in the drawings, additional features may be added to the semiconductor devices depicted in the drawings, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.

[0052] Additional operations may be added before, during and / or after each stage described in these embodiments. In different embodiments, some stages may be replaced or removed.

[0053] As used herein, a "layer" is a region, such as a block, that includes arbitrary boundaries and does not necessarily include a constant thickness. For example, a layer can be a region that includes at least some thickness variation.

[0054] The present disclosure generally relates to semiconductor devices and their fabrication, and more particularly to multi-gate devices. Multi-gate devices include transistors where gate structures are formed on at least two sides of a channel region. These multi-gate devices may include N-type metal oxide semiconductor devices or P-type metal oxide semiconductor multi-gate devices. Certain examples herein may be presented and referred to herein as a multi-gate transistor referred to as a gate-all-around (GAA) device. A gate-all-around includes any device where a gate structure or a portion of a gate structure is formed on four sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include channel regions disposed in nanosheet channels, nanowire channels, rod-shaped channels, and / or other suitable channel configurations. Embodiments of devices presented herein also include one or more channel regions (e.g., nanosheets) with a single continuous gate structure. However, one of ordinary skill in the art will appreciate that the present teachings may be applied to a single channel or any number of channels, such as a FinFET, due to its fin-like structure. One of ordinary skill in the art can recognize other examples of semiconductor devices that can benefit from aspects of the present disclosure.

[0055] The gate-all-around silicon nanosheet structure is considered to be an excellent candidate for achieving better power performance and area scaling compared to other fin field effect transistor technologies. Specifically, the gate-all-around structure can provide high drive current due to the wide effective channel width while maintaining short channel control. Multiple disclosed embodiments can provide a method for controlling the critical dimension of silicon germanium and a method for controlling the critical dimension of a metal gate to improve device performance.

[0056] Figure 1 To describe various aspects according to the present disclosure, a flow chart of an exemplary method 100 for manufacturing a semiconductor including a multi-gate device is provided. As used herein, the term "multi-gate device" is used to describe a semiconductor device (a semiconductor device such as a semiconductor transistor) having at least some gate material disposed on multiple sides of at least one channel thereof. In some examples, a multi-gate device having gate material disposed on four sides of at least one channel member is referred to as a wrap-around gate device. The channel member may be referred to as a nanostructure or nanosheet, and these two terms are used herein to indicate any material portion that is located at the nanoscale or even the microscale and has an elongated shape. Therefore, as used herein, the terms "nanostructure" or "nanoflake" are used to indicate both circular and elongated material portions that have a substantially circular cross-section, and beam-shaped or rod-shaped material portions, including, for example, cylindrical or substantially rectangular material portions in cross-section.

[0057] Figure 1 It is a combination Figures 2 to 11 as well as Figure 13 to Figure 22and is described, Figures 2 to 11 as well as Figure 13 to Figure 22 A semiconductor device or structure 200 is depicted at various stages of fabrication according to some embodiments. The method 100 is merely an example and is not intended to limit the present disclosure beyond what is expressly recited within the scope of the patent. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 100. Additional features may be added to the semiconductor device 200 depicted in the figures, and some of the features described below may be replaced, modified, or eliminated in other embodiments.

[0058] As with other device examples and method implementations discussed herein, it should be understood that components of a semiconductor device can be manufactured by a semiconductor technology process flow. Therefore, some of the processes herein will only be briefly described. In addition, this exemplary semiconductor device may include a variety of other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, turntables, fuses and / or other logic devices, etc., but in order to better understand the concepts of the present disclosure, we will simplify the above. In some embodiments, this exemplary device includes a plurality of semiconductor devices (such as transistors) that can be interconnected, including P-channel field effect transistors, N-channel field effect transistors, etc. In addition, it is noted that the process steps of method 100, including any description referring to the accompanying drawings, are merely exemplary, as are other methods and exemplary diagrams in the present disclosure, and are not intended to further limit the present disclosure beyond the content explicitly described in the scope of the patent later in this article.

[0059] Figures 2 to 6 , Figure 8 , Fig.10 and Figure 13 to Figure 22 is a cross-sectional side view of an embodiment of an example semiconductor device 200 at various stages of fabrication in an example process according to some embodiments. Fig.11 2 is a three-dimensional schematic diagram of a portion of an example semiconductor device 200 at multiple stages of manufacture in an example process according to some embodiments. In some of the drawings, reference numbers for some of the components depicted therein may be omitted to avoid obstructing other components or features. This is for the convenience of drawing the drawings.

[0060] At block 102, the example method 100 includes providing a substrate. Figure 2In one embodiment of block 102, a substrate 202 is provided to form a multi-gate device 200. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, substrate 202 includes a single crystal semiconductor layer at least on a surface portion thereof. Substrate 202 may include a single crystal semiconductor material, such as but not limited to silicon, germanium, silicon germanium, potassium arsenide, indium antimonide, gallium phosphide, gallium antimonide, InAlAs, InGaAs, GaSbP, GaAsSb, and indium phosphide. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Substrate 202 may include multiple layers, including conductive or insulating layers formed on a semiconductor substrate. Substrate 202 may include multiple doping configurations according to design requirements. For example, regions designed as different device types (such as N-type field effect transistors and P-type field effect transistors) on substrate 202 may have different doping concentrations (such as N-wells or P-wells). Suitable doping methods may include ion implantation and / or diffusion processes of dopants. The substrate 202 has isolation features (eg, shallow trench isolation features) between regions providing different device types. In addition, the substrate 202 may be strained to enhance performance, may include a silicon-on-insulator structure, and / or have other suitable enhancement features.

[0061] At block 104, the example method 100 then includes forming one or more epitaxial layers on the substrate. Figure 3 In one embodiment of block 104, an epitaxial stack 212 is formed on a substrate 202. The epitaxial stack 212 includes a plurality of sacrificial epitaxial layers 214 including a first component and a channel epitaxial layer 216 including a second component. The first component and the second component may be different. In one embodiment, the sacrificial epitaxial layer 214 is composed of silicon germanium and the channel epitaxial layer is composed of silicon. However, other embodiments may include a first component and a second component having different oxidation rates and etching selectivities. In some embodiments, the sacrificial epitaxial layer 214 includes silicon germanium and the channel epitaxial layer 216 includes silicon, and the silicon oxidation rate of the channel epitaxial layer 216 is less than the silicon germanium oxidation rate of the sacrificial epitaxial layer 214. Note that Figure 3 3 layers of sacrificial epitaxial layer 214 and channel epitaxial layer 216 are shown in the figure for illustration purposes only and are not intended to further limit the scope of the patent beyond the explicit description. In various embodiments, any number of epitaxial layers can be formed in the epitaxial stack 212, and the number of layers is determined by the number of channel regions required by the device 200. In some embodiments, the number of channel epitaxial layers 216 is between 2 and 10, such as 3, 4 or 5.

[0062] In some embodiments, the sacrificial epitaxial layer 214 has a thickness of about 4 nanometers to about 12 nanometers. The thickness of the sacrificial epitaxial layer 214 can be substantially uniform. In some embodiments, the channel epitaxial layer 216 has a thickness of about 3 nanometers to about 6 nanometers. The thickness of the channel epitaxial layer 216 can be substantially uniform.

[0063] As described in detail below, the channel epitaxial layer 216 can be used as the channel region of the multi-gate device to be formed later, and its thickness is selected based on device performance considerations. The sacrificial epitaxial layer 214 can be used to reserve a gap (or trench) between the channel regions of the multi-gate device to be formed later, and its thickness is selected based on device performance considerations.

[0064] For example, the epitaxial growth of the epitaxial stack 212 can be performed by a molecular beam growth process, a metal organic chemical vapor deposition process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers, such as the channel epitaxial layer 216, contain the same material as the substrate 202, such as silicon. In some embodiments, the epitaxially grown sacrificial epitaxial layer 214 and the channel epitaxial layer 216 contain a different material from the substrate 202. As described below, in at least some examples, the sacrificial epitaxial layer 214 includes an epitaxially grown Si 1-x Ge x layer (for example, x is approximately 25% to 55%), and the channel epitaxial layer 216 includes a silicon layer grown epitaxially. Alternatively, in some embodiments, both the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 may include other materials, such as germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP, or combinations thereof. As previously discussed, the materials of the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 may be selected based on differences in oxidation and etching selectivity properties provided by the materials. In various embodiments, the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 are substantially free of dopants (i.e., have a thickness of approximately 0 cm -3 Up to 10 17 cm -3 of the concentration of foreign dopants), for example, without any deliberate doping during the epitaxial growth process.

[0065] At block 106, the example method 100 includes patterning the epitaxial stack to form semiconductor fins (or fins). Figure 4In one embodiment of block 106 , a plurality of fins 220 extending from the substrate 202 are formed. In various embodiments, the fins 220 include an upper portion interlaced with the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 and a bottom portion protruding from the substrate 202 .

[0066] The fins 220 may be formed by suitable procedures, including photolithography and etching procedures. The photolithography procedure may include forming a photoresist layer on the substrate 202 (e.g., formed on the epitaxial stack 212), exposing a pattern to the photoresist, performing a post-exposure baking procedure, and forming the photoresist into a photoresist-containing shielding layer. In some embodiments, patterning the photoresist to form a shielding layer includes using an electron beam lithography procedure. This shielding layer can be used to protect areas on the substrate 202 and the epitaxial stack 212 formed thereon, while an etching procedure masks grooves that were formed in unprotected areas, thereby leaving a plurality of fins extending therefrom. The etching of the grooves may use dry etching (e.g., reactive ion etching), wet etching, and / or other suitable procedures. These grooves may be filled with dielectric material to form, for example, shallow groove isolation features between the fins.

[0067] At block 108, the exemplary method 100 includes forming a shallow recess isolation feature on the substrate. In various embodiments, the shallow recess isolation feature is formed by filling a recess between fins with a dielectric material to form an isolation feature. Figure 5 In one embodiment of block 108, a plurality of fins 220 and alternating sacrificial epitaxial layers 214 and channel epitaxial layers 216 extend from substrate 202. Isolation features 222, such as shallow groove isolation features 222, have been formed in grooves between adjacent fins 220. The sidewalls of the sacrificial epitaxial layer 214 expand due to the thermal effect during the formation of the shallow groove isolation. In this example, because the sacrificial epitaxial layer 214 is etched before the heating process of the shallow groove isolation formation, the sacrificial epitaxial layer 214 expands to the same width as the channel epitaxial layer 216.

[0068] The isolation feature 222 may include one or more dielectric layers. Suitable dielectric materials for the isolation feature 222 include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass, low dielectric constant materials and / or other suitable dielectric materials. The dielectric material may be deposited by suitable techniques, including thermal growth, chemical vapor deposition, high density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition and / or spin coating techniques. The deposited isolation feature 222 is then recessed to form a shallow recessed isolation feature (also labeled as shallow recessed isolation feature 222). In the embodiment depicted in the accompanying drawings, the shallow recessed isolation feature 222 is deposited on the sidewall of the protrusion of the substrate 202. The top surface of the shallow recessed isolation feature 222 may be coplanar with the bottom surface of the epitaxial stack 212, or about 1 nanometer to about 10 nanometers below the bottom surface of the epitaxial stack 212. Any suitable etching technique may be used to recess the isolation features 212 , including dry etching, wet etching, reactive ion etching and / or other etching methods, and in one embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation features 222 without etching the fins 220 .

[0069] At block 110, the example method 100 includes forming a sacrificial layer / feature on a substrate. Figure 6 and Figure 7 In one embodiment of forming a sacrificial layer / feature on a substrate, a sacrificial gate dielectric layer 226 is blanket deposited on the fin 220. A sacrificial gate electrode layer 228 is blanket deposited on the sacrificial gate dielectric layer 226 and the fin 220. The sacrificial gate electrode layer 228 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer 226 is in a range of about 1 nanometer to about 5 nanometers. In some embodiments, the thickness of the sacrificial gate electrode layer 228 is in a range of about 100 nanometers to about 200 nanometers. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer 226 and the sacrificial gate electrode layer 228 are deposited using chemical vapor deposition including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable techniques.

[0070] At block 112, the example method 100 includes patterning a sacrificial layer / feature to form a dummy gate structure on a channel region of the fin. Figure 8 and Fig. 9As an example, in one embodiment of block 112, a sacrificial gate structure 224 is formed on a portion of the fin 220 that will become a channel region. The sacrificial gate structure 224 defines the channel region of the wrap-around gate device. The sacrificial gate structure includes a sacrificial gate dielectric layer 226 and a sacrificial gate electrode layer 228. The sacrificial gate structure 224 is formed by forming a shielding layer on the sacrificial gate electrode layer 228. The shielding layer may include a silicon oxide pad layer and a silicon nitride shielding layer. Then, the shielding layer, the sacrificial gate dielectric layer 226, and the sacrificial gate electrode layer 228 are patterned. By patterning the sacrificial gate structure 224, the fin 220 is exposed on the opposite side of the sacrificial gate structure 224, thereby defining a source / drain region. In the present disclosure, the source and drain are interchangeable in use, and the structures of the source and drain are substantially the same.

[0071] As described in block 126 of the method 100, the sacrificial gate structure 224 is subsequently removed and replaced with a final gate stack in a subsequent processing stage of the device 200. More specifically, as discussed below, in a subsequent processing stage, the sacrificial gate structure 224 is replaced with a high-k dielectric layer and a metal gate electrode.

[0072] At block 114, the example method 100 includes forming gate sidewall spacers on sidewalls of the dummy gate stack. Fig.10 In one embodiment of block 114, a gate sidewall spacer 232 is formed on the sidewall of the sacrificial gate structure 224. The gate sidewall spacer 232 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film and / or combinations thereof. In some embodiments, the gate sidewall spacer 232 includes a plurality of layers, such as a main spacer and a liner, etc. For example, the gate sidewall spacer 232 may be formed by depositing a dielectric material layer on the sacrificial gate structure 224 using a chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other suitable process. In some embodiments, the deposition of the dielectric material layer is followed by an etch back process (e.g., an anisotropic etch back process) to expose a portion of the fin 220 adjacent to and not covered by the sacrificial gate structure (e.g., a source / drain region). The dielectric material layer may remain on the sidewalls of the sacrificial gate structure 224 to form a gate sidewall spacer 232. In some embodiments, the etch-back process may include a dry etch process, a wet etch process, a multi-step etch process, and / or a combination thereof. The gate sidewall spacer 232 may have a thickness of 5 nm to 20 nm.

[0073] At block 116, the example method 100 includes recessing the fins in the source / drain regions. Fig.10In one embodiment of block 116, the stacked sacrificial epitaxial layer 214 and the channel epitaxial layer 216 are etched away in the source / drain region to form a recess 234. The top of the substrate 202 is also etched. In various embodiments, the recess is performed by a suitable etching process, such as a dry etching process, a wet etching process, or a reactive ion etching process. The dry etching process can be performed by an etchant including a bromine-containing gas (such as HBr and / or CHBr3), a fluorine-containing gas (such as CF4, SF6, CH2F2, CHF3 and / or C2F6), other suitable gases, or a combination thereof.

[0074] At block 118, the example method 100 includes performing a pre-treatment operation on the sacrificial epitaxial layer 214 to remove impurities in the sacrificial epitaxial layer 214. Fig.11 In one embodiment prior to block 116, the sacrificial epitaxial layer 214 includes silicon germanium and the impurity 233 may include SiO x (For example, x is equal to about 1 to about 3), SiO2, carbon, GeO x (For example, x is equal to about 1 to about 3), GeO2 and / or other impurities. The impurities may interfere with the subsequent formation of inner spacers around the sacrificial epitaxial layer 214. In various embodiments, the pre-treatment operation may include applying hydrogen radicals (H*) and nitrogen radicals (N*) (e.g., SiOC+H*+N*: SiON+SiOH+CH4+HCN) to the sacrificial epitaxial layer 214 and the channel epitaxial layer 216, and then applying hydrogen fluoride (HF) to remove byproducts of the application of hydrogen radicals and nitrogen radicals (e.g., SiON+SiOH+HF: SiF4+H2O+NH3).

[0075] The impurities may cause the LWR of the subsequent recessed sacrificial epitaxial layer 214 to increase, which may further cause the inner spacers formed around the sacrificial epitaxial layer 214 to have less than ideal thickness in many places, resulting in epitaxial damage and metal gate to metal drain short circuits, thereby reducing the yield. In order to reduce the possibility of increased LWR, epitaxial damage and metal gate to metal drain short circuits, a pre-treatment operation is applied to the sacrificial epitaxial layer 214 to remove impurities in the sacrificial epitaxial layer 214.

[0076] Reference Fig. 12A and Fig. 12BIn one embodiment of block 116, a pre-treatment operation 300 is applied to the sacrificial epitaxial layer 214 to remove impurities in the sacrificial epitaxial layer 214. In this example, the pre-treatment operation includes a nitridation operation 302, a carbon removal operation 304, and an oxide removal operation 306. The desalination operation 302 includes applying N2 radicals to the sacrificial epitaxial layer 214 and the channel epitaxial layer 216. The carbon removal operation 304 includes applying N2 radicals and H2 radicals to the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 to remove carbon elements. The oxide removal operation 306 includes applying a hydrogen fluoride rinse to the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 to remove oxides.

[0077] At block 120, the example method 100 includes forming inner spacers. Forming the inner spacers includes recessing a sacrificial epitaxial layer (eg, silicon germanium), depositing an inner spacer material, and etching back the inner spacer material. Fig.13 An embodiment is provided after recessing the sacrificial epitaxial layer 214 to form a cavity 216. The sacrificial epitaxial layer 214 can be selectively etched using a wet etchant such as (but not limited to) ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP) or potassium hydroxide (KOH) solution. Alternatively, at block 120, the exposed side of the sacrificial epitaxial layer 120 in the recess 234 can be selectively oxidized to increase the etch selectivity between the sacrificial epitaxial layer 214 and the channel epitaxial layer 216. In some examples, the oxidation process is performed by exposing the device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof.

[0078] Due to the pre-treatment, the line width roughness of the sacrificial epitaxial layer 214 can be reduced. In various embodiments, the line width roughness can be 4.4 nanometers when the pre-treatment operation is applied, while the line width roughness is 6.4 nanometers when the pre-treatment operation is not applied. In various embodiments, the pre-treatment operation can result in an improvement in line width roughness of about 31.2%.

[0079] Fig.14 Another embodiment is provided after recessing the sacrificial epitaxial layer 214 (e.g., silicon germanium). In this example, the silicon germanium critical dimension 310 is in the range of 5 nanometers to 20 nanometers, which is equal to the critical dimension of the metal gate at the end of the line, the silicon germanium critical dimension 312 (e.g., the metal gate critical dimension at the end of the line) is in the range of 5 nanometers to 20 nanometers, and the silicon germanium critical dimension 314 (e.g., the metal gate critical dimension at the end of the line) is in the range of 5 nanometers to 20 nanometers. In this example, the recess dimensions 316a, 316b, 316c, 317a, 317b, 317c, 318a, 318b, and 318c are in the range of less than 6 nanometers. In this example, the channel epitaxial layer 216 has a thickness 319 in the range of 3 nanometers to 10 nanometers.

[0080] Fig.15 An embodiment after depositing the internal spacer material is provided. An internal spacer material layer 238 is formed on the side of the sacrificial epitaxial layer 214 in the cavity 236 and the channel epitaxial layer 216 in the recess 234. The internal spacer material layer 238 can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbonitride oxide, and / or other suitable dielectric materials. In some embodiments, the internal spacer material layer 238 is deposited as a conformal layer. The internal spacer material layer 238 can be formed by atomic layer deposition or any suitable method. By conformally forming the internal spacer material layer 238, the size of the cavity 236 will be reduced or completely filled.

[0081] Fig.16 An embodiment of the inner spacer material layer 238 after etching back is provided. After the inner spacer material layer 238 is formed, an etching operation is performed to remove a portion of the inner spacer material layer 238. Through this etching, the inner spacer material layer 238 generally remains in the cavity 236 due to the small volume of the cavity 236. Generally speaking, the plasma dry etching will etch the layer located in the flat wide area faster than the layer located in the recessed part (e.g., hole, groove or gap). Therefore, the inner spacer material layer 238 may remain in the cavity 236. The remaining portion of the inner spacer material layer 238 will be recorded as the inner spacer 238.

[0082] Fig.17 Another embodiment is provided after etching back the inner spacer material layer 238. In this example, the variance (ie, the range of the critical dimension) of the SiGe CD 320 is less than 3 nm.

[0083] At block 122, the example method 100 includes forming source / drain features. Fig.18 In one embodiment of block 122, epitaxial source / gate features 240 are formed in cavity 234. In some embodiments, the epitaxial source / drain features 240 of N-type metal oxide semiconductors include silicon, and the epitaxial source / drain features 240 of P-type metal oxide semiconductors include silicon germanium. In some embodiments, the epitaxial source / drain features 240 are formed by an epitaxial growth method using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. The epitaxial source / drain features 240 are formed in contact with the channel epitaxial layer 216 and are separated from the sacrificial epitaxial layer 214 by an internal spacer 238.

[0084] At block 124, the example method 100 includes forming a contact etch stop layer and an interlayer dielectric layer. Fig.19In one embodiment of block 124, a contact etch stop layer 242 is formed on the epitaxial source / drain features 240, and an interlayer dielectric layer 244 is formed on the contact etch stop layer 242. The contact etch stop layer 242 may include silicon nitride, silicon oxynitride, silicon nitride containing carbon and oxygen, and / or other materials, and may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods. The interlayer dielectric layer 244 may include tetraethyl silicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG),

[0085] Phosphorus silicate glass (PSG), borosilicate glass and / or other suitable dielectric materials. The interlayer dielectric layer 244 can be formed by plasma enhanced chemical vapor deposition, flowable chemical vapor deposition or other suitable methods. In some embodiments, forming the interlayer dielectric layer 244 further includes performing a chemical mechanical polishing process to flatten the top surface of the device 200 so that the top surface of the sacrificial gate structure 224 is exposed.

[0086] At block 126, the example method 100 includes removing the dummy gate stack to form a gate recess. Fig. 20 In one embodiment of block 126, the sacrificial gate structure 224 is removed to form a gate recess 254. The gate recess 254 exposes the fin 220 in the channel region, and the interlayer dielectric layer 244 and the contact etch stop layer 242 protect the epitaxial source / drain features 240 when the sacrificial gate structure 224 is removed. The sacrificial gate structure 224 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer is polysilicon and the interlayer dielectric layer is oxide, a wet etchant such as tetramethylammonium hydroxide can be used to selectively remove the sacrificial gate electrode layer. The sacrificial gate dielectric layer can then be removed using plasma dry etching or wet etching.

[0087] At block 128, the example method 100 includes removing the sacrificial epitaxial layer to form nanosheets. Fig.21 In one embodiment of block 128, the sacrificial epitaxial layer is removed to release the channel member from the channel region of the wrap-around gate device. In the illustrated embodiment, the channel member is a channel epitaxial layer 216 in the form of a nanosheet, and in various embodiments, the channel epitaxial layer 216 comprises silicon and the sacrificial epitaxial layer comprises silicon germanium. In various embodiments, the plurality of sacrificial epitaxial layers 214 are selectively removed by a selective removal process comprising oxidizing the plurality of sacrificial epitaxial layers 214 using a suitable oxidant, such as ozone. Subsequently, the oxidized sacrificial epitaxial layers 214 are selectively removed by a dry etching process, for example, by applying hydrogen chloride gas at a temperature of about 500 degrees Celsius to about 700 degrees Celsius, or a mixture of CF4, SF6, and CHF3.

[0088] At block 130, the example method 100 includes forming a high-k metal gate structure. Fig. 12A and Fig. 12B In one embodiment of block 130, a gate structure 260 is formed. In various embodiments, the gate structure is a gate of a multi-gate transistor. In various embodiments, the gate structure is a high-k metal gate stack, although other compositions are possible. In various embodiments, the high-k metal gate stack includes a gate dielectric layer including an interfacial layer 262 and a high-k dielectric layer 264. The high-k dielectric layer 264 covers each nanosheet 216, and the interfacial layer 262 is interposed between the high-k dielectric layer and the nanosheet 216. The interfacial layer 262 may include a dielectric material such as silicon oxide or silicon oxynitride, and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The high-k dielectric layer may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), other suitable high-k dielectric materials, or combinations thereof. The high-k dielectric material may be further selected from metal oxides, metal nitrides, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloys, other suitable materials, and / or combinations thereof. The high-k dielectric layer may be formed by any suitable process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, remote plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, metal organic chemical vapor deposition, sputtering, electroplating, other suitable processes and / or combinations thereof. In one embodiment, the gate dielectric layer is formed by using a highly conformal deposition process, such as atomic layer deposition, to ensure that the gate dielectric layer has a uniform thickness around each channel layer. The high-k metal gate structure may include additional material layers.

[0089] At block 132, the example method 100 includes performing further fabrication. The semiconductor device may be further processed to form various features and regions as is well known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts / vias / lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectric layers) on the substrate, configured to connect the various features to form a functional circuit including one or more multi-gate devices. Taking this example further, the multi-layer interconnect features may include vertical interconnect features, such as contacts and vias, and horizontal interconnect features, such as metal lines. The various interconnect features may use a variety of conductive materials, including copper, tungsten and / or silicide. In one example, damascene and / or dual damascene processes are used to form a copper-related multi-layer interconnect structure. In addition, according to various embodiments of the method 100, additional process steps may be performed before, during, or after the method 100, and the process steps described above may be replaced or eliminated.

[0090] Improved systems, methods of manufacture, techniques and products of manufacture have been described. The systems, methods, techniques and products described can be used in a wide variety of semiconductor devices, including wrap-around gate field effect transistors / forked-fins / complementary field effect transistors / vertical field effect transistors / metal oxide semiconductor field effect transistors. The systems, methods, techniques and products described can be used to manufacture semiconductor devices including semiconductor devices with nano-sheet structures. The systems, methods, techniques and products described can be used to precisely control metal gate critical dimension profiles, thereby improving device properties and integrated circuit performance.

[0091] One form of the technology described in this article is related to a method for manufacturing a semiconductor device, comprising: forming an epitaxial stack on a substrate, the epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming fins in the epitaxial stack; forming a sacrificial gate stack on multiple channel regions of the fins; forming multiple gate sidewall spacers on multiple sidewalls of the sacrificial gate stack; performing multiple pre-processing operations to remove multiple impurities from at least one sacrificial epitaxial layer; recessing at least one sacrificial epitaxial layer to form a cavity; forming internal spacing material in the cavity; forming multiple source / gate features; removing the sacrificial gate stack and at least one sacrificial epitaxial layer in the fins; and forming a metal gate to replace the sacrificial gate stack and at least one sacrificial epitaxial layer, wherein the internal spacing material has a thickness sufficient to resist epitaxial damage.

[0092] One aspect of the technology described herein is related to a method for fabricating a semiconductor device, wherein after recessing at least one sacrificial epitaxial layer, the at least one sacrificial epitaxial layer has a line width roughness less than 3 nanometers.

[0093] One aspect of the technology described herein relates to a method for fabricating a semiconductor device, wherein at least one sacrificial epitaxial layer has a critical dimension in the range of 5 nm to 20 nm, and the cavity has a recess dimension less than 6 nm.

[0094] One aspect of the technology described herein relates to a method for fabricating a semiconductor device, wherein a plurality of pre-processing operations are performed including subjecting at least one sacrificial epitaxial layer and at least one channel epitaxial layer to hydrogen radicals (H*) and nitrogen radicals (N*).

[0095] One aspect of the technology described herein relates to a method for fabricating a semiconductor device wherein a plurality of pre-processing operations are performed and further comprises applying a hydrogen fluoride rinse to remove byproducts resulting from the application of hydrogen radicals and oxygen radicals.

[0096] One aspect of the technology described herein is related to a method for manufacturing a semiconductor device, wherein a plurality of pre-processing operations are performed, further comprising a nitridation operation, a carbon removal operation, and an oxide removal operation.

[0097] One aspect of the technology described herein relates to a method of fabricating a semiconductor device wherein at least one sacrificial epitaxial layer comprises silicon germanium and at least one channel epitaxial layer comprises silicon.

[0098] One aspect of the technology described herein is related to a method for manufacturing a semiconductor device, wherein the plurality of impurities include one or more SiO x , where x is a value from 1 to 3, carbon, and one or more GeO x , where x is a value from 1 to 3.

[0099] One aspect of the technology described in this article is related to a method for manufacturing a semiconductor device, including: forming an epitaxial stack on a substrate, the epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming fins in the epitaxial stack; forming a sacrificial gate stack on multiple channel regions of the fins; forming multiple gate sidewall spacers on the sidewalls of the sacrificial gate stack; performing multiple pre-treatment operations to remove multiple impurities from at least one sacrificial epitaxial layer, wherein the multiple pre-treatment operations include: applying hydrogen radicals and nitrogen radicals to at least one sacrificial epitaxial layer and at least one channel epitaxial layer; and applying hydrogen fluoride rinsing to remove byproducts of applying hydrogen radicals and oxygen radicals; recessing at least one sacrificial epitaxial layer to form a cavity; and forming an internal spacing material in the cavity, wherein the internal spacing material has a thickness sufficient to resist epitaxial damage.

[0100] One aspect of the technology described herein is related to a method for fabricating a semiconductor device, wherein after recessing at least one sacrificial epitaxial layer, the at least one sacrificial epitaxial layer has a line width roughness less than 3 nanometers.

[0101] One aspect of the technology described herein relates to a method for fabricating a semiconductor device, wherein at least one sacrificial epitaxial layer has a critical dimension in the range of 5 nm to 20 nm, and the cavity has a recess dimension less than 6 nm.

[0102] One aspect of the technology described herein relates to a method of fabricating a semiconductor device wherein at least one sacrificial epitaxial layer comprises silicon germanium and at least one channel epitaxial layer comprises silicon.

[0103] One aspect of the technology described herein is related to a method for manufacturing a semiconductor device, wherein the plurality of impurities include one or more SiO x , where x is a value from 1 to 3, carbon, and one or more GeO x , where x is a value from 1 to 3.

[0104] One form of the technology described in this article is related to a method for manufacturing a semiconductor device, including: forming an epitaxial stack on a substrate, the epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming fins in the epitaxial stack; forming a sacrificial gate stack on multiple channel regions of the fins; forming multiple gate sidewall spacers on multiple sidewalls of the sacrificial gate stack; performing multiple pre-processing operations to remove multiple impurities from at least one sacrificial epitaxial layer, wherein the multiple pre-processing operations include multiple nitridation operations, multiple carbon removal operations, and multiple oxide layer removal operations; recessing at least one sacrificial epitaxial layer to form a cavity; and forming an internal spacer material in the cavity, wherein the internal spacer material has a thickness sufficient to resist epitaxial damage.

[0105] One aspect of the technology described herein is related to a method for fabricating a semiconductor device, wherein after recessing at least one sacrificial epitaxial layer, the at least one sacrificial epitaxial layer has a line width roughness less than 3 nanometers.

[0106] One aspect of the technology described herein relates to a method for fabricating a semiconductor device, wherein at least one sacrificial epitaxial layer has a critical dimension in the range of 5 nm to 20 nm, and the cavity has a recess dimension less than 6 nm.

[0107] One aspect of the technology described herein is related to a method for manufacturing a semiconductor device, wherein the plurality of impurities include one or more SiO x , where x is a value from 1 to 3, carbon, and one or more GeO x , where x is a value from 1 to 3.

[0108] One aspect of the technology described herein relates to a method for fabricating a semiconductor device, wherein a plurality of nitridation operations include applying N2 radicals to at least one sacrificial epitaxial layer and at least one channel epitaxial layer.

[0109] One aspect of the technology described herein is related to a method for manufacturing a semiconductor device, wherein multiple carbon removal operations include applying N2 radicals and H2 radicals to at least one sacrificial epitaxial layer and at least one channel epitaxial layer to remove carbon elements.

[0110] One aspect of the technology described herein is related to a method for fabricating a semiconductor device, wherein a plurality of oxide layer removal operations include performing a hydrogen fluoride rinse on at least one sacrificial epitaxial layer and at least one channel epitaxial layer to remove oxide.

[0111] Even though at least one embodiment has been presented in the foregoing detailed description of the present disclosure, it should be recognized that many variations exist. It should also be recognized that the embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. Instead, the foregoing detailed description will provide a convenient guide for those skilled in the art to practice the embodiments of the present disclosure. It should be understood that many changes may be made to the functions and configurations of the elements described in the embodiments without exceeding the scope of the present disclosure set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming an epitaxial stack on a substrate, the epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a fin in the epitaxial stack; forming a sacrificial gate stack on a plurality of channel regions of the fin; forming a plurality of gate sidewall spacers on a plurality of sidewalls of the sacrificial gate stack; performing a plurality of pre-processing operations to remove a plurality of impurities from the at least one sacrificial epitaxial layer; recessing the at least one sacrificial epitaxial layer to form a cavity; forming an inner spacer material in the cavity; forming a plurality of source / gate features; removing the sacrificial gate stack and the at least one sacrificial epitaxial layer in the fin; as well as A metal gate is formed to replace the sacrificial gate stack and the at least one sacrificial epitaxial layer, wherein the inner spacer material has a thickness sufficient to resist epitaxial damage.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: After the at least one sacrificial epitaxial layer is recessed, the at least one sacrificial epitaxial layer has a line width roughness less than 3 nanometers.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The at least one sacrificial epitaxial layer has a critical dimension in the range of 5 nanometers to 20 nanometers, and the cavity has a recess dimension less than 6 nanometers.

4. A method for manufacturing a semiconductor device, characterized in that: include: forming an epitaxial stack on a substrate, the epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a fin in the epitaxial stack; forming a sacrificial gate stack on a plurality of channel regions of the fin; forming a plurality of gate sidewall spacers on a plurality of sidewalls of the sacrificial gate stack; Performing a plurality of pre-processing operations to remove a plurality of impurities from the at least one sacrificial epitaxial layer, wherein performing the plurality of pre-processing operations comprises: Applying hydrogen radicals and nitrogen radicals to the at least one sacrificial epitaxial layer and the at least one channel epitaxial layer; and Flushing with hydrogen fluoride to remove byproducts of hydrogen and oxygen radicals; recessing the at least one sacrificial epitaxial layer to form a cavity; as well as An inner spacer material is formed in the cavity, wherein the inner spacer material has a thickness sufficient to resist epitaxial damage.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: After the at least one sacrificial epitaxial layer is recessed, the at least one sacrificial epitaxial layer has a line width roughness less than 3 nanometers.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The at least one sacrificial epitaxial layer has a critical dimension in the range of 5 nanometers to 20 nanometers, and the cavity has a recess dimension less than 6 nanometers.

7. A method for manufacturing a semiconductor device, characterized in that: include: An epitaxial stack is formed on a substrate, the epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a fin in the epitaxial stack; forming a sacrificial gate stack on a plurality of channel regions of the fin; forming a plurality of gate sidewall spacers on a plurality of sidewalls of the sacrificial gate stack; Performing a plurality of pre-treatment operations to remove a plurality of impurities from the at least one sacrificial epitaxial layer, wherein the plurality of pre-treatment operations include a plurality of nitridation operations, a plurality of carbon removal operations, and a plurality of oxide layer removal operations; recessing the at least one sacrificial epitaxial layer to form a cavity; as well as An inner spacer material is formed in the cavity, wherein the inner spacer material has a thickness sufficient to resist epitaxial damage.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The plurality of nitridation operations include applying N2 radicals to the at least one sacrificial epitaxial layer and the at least one channel epitaxial layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The plurality of carbon removal operations include applying N2 radicals and H2 radicals to the at least one sacrificial epitaxial layer and the at least one channel epitaxial layer to remove carbon elements.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The oxide layer removal operations include washing the at least one sacrificial epitaxial layer and the at least one channel epitaxial layer with hydrogen fluoride to remove oxides.

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