Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate; an epitaxial layer disposed on the substrate; a plurality of trenches formed in the epitaxial layer; a shielding insulating layer formed inside the plurality of grooves; a shield electrode surrounded by the shield insulating layer and disposed inside the plurality of trenches; an inter-electrode insulating layer formed on top of the shield insulating layer and the shield electrode; a gate insulating layer disposed on the inter-electrode insulating layer; a gate electrode disposed on the gate insulating layer; a body region formed on an upper portion of the epitaxial layer between the plurality of trenches; a source region formed on the body region; an interlayer insulating layer formed on the gate electrode and the source region; and a body contact region in contact with the source region and the body region.

Description

Technical Field

[0001] The following description relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device having a trench MOSFET structure and a method for manufacturing the same, in which a shield electrode or a source electrode is formed at the lower portion of the trench and a gate electrode is formed at the upper portion of the trench by applying a split-gate trench structure. Background Art

[0002] More and more electronic and electrical products require complex circuits and high-performance technology. In order to reduce the power consumption of products and maximize the efficiency of products, high-performance electrical semiconductor devices are required, and in particular, the demand for power discrete trench MOSFET devices is rapidly increasing.

[0003] In a semiconductor device having a power trench MOSFET structure, breakdown voltage and switching characteristics are important factors that determine the performance of the MOSFET device. In addition, reducing high breakdown voltage and on-resistance is necessary to improve the characteristics of the semiconductor device.

[0004] As an example of related art, a power MOSFET using a triple polysilicon structure allows a shielding polysilicon electrode to be formed in a trench and allows a gate polysilicon electrode to be formed on both sides of an upper portion of the shielding polysilicon electrode. In this related art, it is not easy to simultaneously ensure a stable breakdown voltage and an on-off switch.

[0005] In a power MOSFET structure using a triple polysilicon structure, since the gate electrode must be formed on both sides of the upper portion of the shielding polysilicon electrode, parasitic capacitance is generated between the shielding polysilicon electrode and the gate polysilicon electrode, so that the structure has a high parasitic capacitance value between the gate electrode and the source electrode. In order to reduce the parasitic capacitance value, the area of ​​the gate electrode must be reduced, or the thickness of the oxide formed between the gate electrode and the shielding electrode must be ensured. If the area of ​​the gate electrode is reduced, it is difficult to ensure that the breakdown voltage is higher than a certain level.

[0006] In addition, in order to increase the parasitic capacitance, the thickness of the insulating layer (oxide) provided between the gate polysilicon electrode and the shield polysilicon electrode must be increased, and in this case, since the thickness of the insulating layer must be increased, it is difficult to ensure a small cell pitch because the trench width increases. That is, it is difficult to ensure that there are many cells in the power trench MOSFET device, and therefore it is difficult to increase the cell density of the MOSFET device.

[0007] In addition, in the related art triple polysilicon structure, since two gate polysilicon electrodes must be formed on both sides of the top of the shield electrode, the input capacitance (Ciss) value will also increase. Here, the input capacitance refers to the capacitance that is charged when the device is turned on. As the input capacitance becomes smaller, the input switching speed becomes faster when the device is turned on. The input capacitance value is expressed as C iss =C gs +C gd , but there is an increase in C by having two gate polysilicon electrodes gs (capacitance between gate electrode and source electrode) problem.

[0008] Therefore, the total amount of gate charge (Qg) required to charge the input capacitance (Ciss) increases, resulting in switching loss. When the gate charge amount is large, it takes time to charge the power MOSFET to the required capacity to turn on the power MOSFET, so the switching loss increases. Therefore, it is necessary to improve the switching characteristics. Summary of the invention

[0009] This summary is provided to introduce a series of concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0010] In a general aspect, a semiconductor device includes: a semiconductor substrate of a first conductivity type; an epitaxial layer of the first conductivity type disposed on the substrate; a plurality of trenches formed in the epitaxial layer; a shielding insulating layer formed inside the plurality of trenches; a shielding electrode surrounded by the shielding insulating layer at the lower portion of the plurality of trenches; an inter-electrode insulating layer formed on top of the shielding insulating layer and the shielding electrode; a gate insulating layer disposed on the inter-electrode insulating layer; a gate electrode disposed on the gate insulating layer; a body region of a second conductivity type formed on the upper portion of the epitaxial layer located between the plurality of trenches; a source region formed on the body region; an inter-layer insulating layer formed on the gate electrode and the source region; and a body contact region in contact with the source region and the body region. The position and thickness of the gate electrode may be determined by the position and thickness of the inter-layer insulating layer.

[0011] The position and thickness of the interlayer insulating layer may be determined by the depth to which the shielding electrode is etched.

[0012] A ratio between a thickness of the inter-electrode insulating layer and a thickness of the gate electrode may be in a range of 1:1 to 1:10.

[0013] A ratio between a thickness of the inter-electrode insulating layer and a thickness of the shielding electrode may be in a range of 1:3 to 1:15.

[0014] An upper surface of the body region may be disposed lower than an upper surface of the gate electrode.

[0015] A ratio between a thickness of the shield electrode and a thickness of the gate electrode may be in a range of 1:1 to 15:1.

[0016] The plurality of grooves may be formed to have an inclination angle of a side surface of the groove with respect to an upper inner surface of the plurality of grooves between 85° and 90°.

[0017] The shield insulating layer may be formed by primary thermal oxidation or by performing secondary chemical vapor deposition (CVD) after performing primary thermal oxidation.

[0018] The semiconductor device may further include: a metal layer formed over the body region, the source region, and the interlayer insulating layer.

[0019] A ratio between a thickness of the inter-electrode insulating layer formed in the trench and a thickness of the gate electrode is in a range of 1:1.2 to 1:3.

[0020] In another general aspect, a method for manufacturing a semiconductor device includes: forming an epitaxial layer of a first conductivity type on a substrate of a first conductivity type; forming a plurality of trenches in the epitaxial layer; forming a shielding insulating layer inside the plurality of trenches; forming a shielding electrode surrounded by the shielding insulating layer at the lower portion of the plurality of trenches; forming an inter-electrode insulating layer on the shielding insulating layer and the shielding electrode inside the plurality of trenches; forming a gate insulating layer on the inter-electrode insulating layer disposed inside the plurality of trenches; forming a gate electrode on the gate insulating layer; forming a body region of a second conductivity type on the upper portion of the epitaxial layer between the plurality of trenches; forming a source region on the body region; forming an interlayer insulating layer on the gate electrode and the source region; and forming a body contact region in the body region. The position and thickness of the gate electrode may be determined by the position and thickness of the interlayer insulating layer.

[0021] The forming of the inter-electrode insulating layer may include determining the position and thickness of the inter-layer insulating layer by the depth to which the shield electrode is etched.

[0022] The forming of the epitaxial layer may include: forming a lower epitaxial layer on the substrate, and forming an upper epitaxial layer on the lower epitaxial layer. The dopant concentration of the lower epitaxial layer is higher than the dopant concentration of the upper epitaxial layer.

[0023] The forming of the plurality of trenches may further include forming an epitaxial layer, forming a mask on the epitaxial layer, and performing trench etching on the epitaxial layer to form trenches, and forming the sides of the trenches at an inclination angle between 85° and 90° relative to the upper inner surface of the trenches.

[0024] The forming of the plurality of trenches may further include forming a sacrificial oxide layer to restore damage on a sidewall or uneven regions of the epitaxial layer that occurs during etching to form the plurality of trenches.

[0025] The forming of the shield insulating layer may further include forming the shield insulating layer by primary thermal oxidation or by performing secondary chemical vapor deposition (CVD) after performing the primary thermal oxidation.

[0026] The formation of the shielding electrode may also include: forming the shielding electrode by depositing shielding polysilicon inside the shielding insulating layer on the upper surface of the shielding insulating layer, etching the shielding polysilicon deposited on the upper surface of the shielding insulating layer to the height of the upper surface of the groove via chemical mechanical polishing (CMP), or etching the shielding polysilicon deposited on the upper surface of the shielding insulating layer to the height of the upper surface of the epitaxial layer via blanket etching, and etching the shielding polysilicon etched to the height of the upper surface of the trench or to the height of the upper surface of the epitaxial layer to form an inter-electrode insulating layer.

[0027] The forming of the shield electrode may further include etching a portion of a side surface of the shield insulating layer to increase a width of an opening in the shield insulating layer disposed on a side of the shield electrode.

[0028] The formation of the inter-electrode insulating layer may also include: depositing polysilicon oxide on the upper surface of the shielding insulating layer by performing CVD on the shielding electrode, etching the upper surface of the epitaxial layer by performing CMP, blanket etching, or a combination of CMP and blanket etching, and performing dry etching, wet etching, or a combination of dry etching and wet etching on the upper surface and side walls of the inter-electrode insulating layer, so that the inter-electrode insulating layer etched to the upper surface of the epitaxial layer is formed in the groove.

[0029] The formation of the gate electrode may also include: depositing gate polysilicon on the shielding insulating layer and on the gate insulating layer formed on the upper surface of the epitaxial layer, performing CMP on the gate polysilicon deposited on the upper surface of the epitaxial layer to the upper surface of the epitaxial layer, and performing recess etching on the gate polysilicon subjected to CMP so that the height of the gate polysilicon is lower than the height of the upper surface of the epitaxial layer.

[0030] The recess etch may include etching the gate polysilicon from the upper surface of the epitaxial layer to to Etching thickness.

[0031] The forming of the body region may further include forming the body region to have a maximum thickness on the upper surface of the epitaxial layer equal to a depth of a gate electrode formed on the upper surface of the inter-electrode insulating layer.

[0032] The method for manufacturing a semiconductor device may further include forming a metal layer over the body region, the source region, and the interlayer insulating layer.

[0033] According to an example of the present disclosure, a power trench MOSFET device can achieve a small cell pitch by forming a shield electrode in a lower portion of a trench and a gate electrode in an upper portion of the trench using a split gate trench structure, thereby obtaining improved density of the MOSFET device.

[0034] Furthermore, by optimizing the thickness of the gate electrode, fast switching characteristics can be achieved by reducing input capacitance characteristics and the total amount of gate charge (Qg).

[0035] Furthermore, by obtaining an inter-electrode insulating layer (inter-poly oxide) having an optimized thickness formed between the shield polysilicon electrode and the gate electrode, the switching characteristics of the device including input capacitance and parasitic capacitance can be improved without reducing the breakdown voltage.

[0036] Furthermore, by applying a method for manufacturing a device that adjusts the thickness of an inter-electrode insulating layer, the depth of a body junction, and the thickness of gate polysilicon, desired input capacitance (Ciss) values, feedback capacitance (Crss) values, and breakdown voltage values ​​can be ensured.

[0037] Furthermore, desired input capacitance (Ciss) values, feedback capacitance (Crss) values, and breakdown voltage values ​​can be ensured by optimizing the thickness ratio of the shield electrode, the gate electrode, and the inter-electrode insulating layer.

[0038] The effects that can be obtained by the present disclosure are not limited to the above-mentioned effects described above, and other technical effects not described above will be obvious to ordinary technicians in the field to which the present disclosure belongs according to the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1A is a diagram illustrating a structure of a semiconductor device according to an example of the present disclosure.

[0040] Figure 1B Thicknesses of components of a semiconductor device according to an example of the present disclosure are shown.

[0041] Figure 2 The structure of a trench formed inside an epitaxial layer according to an example of the present disclosure is shown.

[0042] Figure 3 The structure of a shielding insulating layer according to an example of the present disclosure is shown.

[0043] FIG. 4A to FIG. 4E A process for forming a shield electrode according to an example of the present disclosure is shown.

[0044] FIG. 5A to FIG. 5C A process for forming an inter-electrode insulating layer according to an example of the present disclosure is shown.

[0045] Figure 6 The structure of a gate insulating layer according to an example of the present disclosure is shown.

[0046] 7A to 7C A process for forming a gate electrode according to an example of the present disclosure is shown.

[0047] Figure 8 A process of forming a body region, a source region, and an interlayer insulating layer according to an example of the present disclosure is shown.

[0048] Fig. 9 The structure of a metal layer according to an example of the present disclosure is shown.

[0049] Other features and aspects will be apparent from the following detailed description, drawings, and claims. DETAILED DESCRIPTION

[0050] By referring to the detailed examples described below and the accompanying drawings, the features, advantages and methods of implementing the present disclosure will become more apparent. However, the present disclosure is not limited to the examples to be disclosed below, but is implemented in different and various forms. These embodiments achieve a complete disclosure of the present disclosure, and these embodiments are provided to enable those skilled in the art to fully understand the scope of the present invention. The present disclosure is limited only by the scope of the appended claims. The same or similar reference numerals throughout the present disclosure may be used for the same or similar parts.

[0051] When a component is referred to as being “connected to” or “coupled to” another component, it includes both the case where the component is directly connected to or coupled to the other component and the case where the other component is inserted between the two components. Meanwhile, when a component is referred to as being “directly connected to” or “directly coupled to” another component, it indicates that no other component is inserted between the two components. The term “and / or” includes each of the mentioned items and all combinations of one or more thereof.

[0052] The terms used in this specification are only used to describe specific examples of the present disclosure and are not intended to be limiting. In this specification, if not specifically stated, expressions in the singular include expressions in the plural. The terms "comprising" and / or "consisting of" used in this specification are intended to specify the features, numbers, steps, operations, components, parts, or any combination thereof mentioned in this specification, and are not intended to exclude the presence or addition of at least one other feature, number, step, operation, component, part, or any combination thereof.

[0053] Although terms such as first and second, etc. may be used to describe various components, these components are not limited by the above-mentioned terms. These terms are only used to distinguish between one component and other components.

[0054] Therefore, within the spirit of the present invention, the first component to be described below may be the second component. Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meanings as those generally understood by those of ordinary skill in the art to which the present invention belongs. In addition, common terms defined in dictionaries should not be interpreted ideally or excessively as long as these terms are not clearly and specifically defined in this application.

[0055] The term "part" or "module" used in the example may refer to a software component or a hardware component, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC). A "part" or "module" performs certain functions. However, a "part" or "module" is not meant to be limited to software or hardware. A "part" or "module" may be configured to be placed in an addressable storage medium, or to restore one or more processors. Therefore, for example, a "part" or "module" may include components such as software components, object-oriented software components, class components, and task components, and may include processes, functions, attributes, methods, subroutines, program code segments, drivers, firmware, microcodes, circuits, data, databases, data structures, tables, arrays, and variables. The components and functions provided in a "part" or "module" may be combined with a smaller number of components and "parts" or "modules", or may also be divided into additional components and "parts" or "modules".

[0056] The method or algorithm steps described with respect to some examples of the present invention can be directly implemented by hardware modules and software modules executed by a processor, or can be directly implemented by their combination. The software module can reside on a RAM, a flash memory, a ROM, an EPROM, an EEPROM, a resistor, a hard disk, a removable disk, a CD-ROM, or any other type of recording medium known to those skilled in the art. An exemplary recording medium is coupled to the processor, and the processor can read information from the recording medium, and can record the information in a storage medium. In another way, the recording medium can be formed integrally with the processor. The processor and the recording medium can reside in an application specific integrated circuit (ASIC). The ASIC can reside in a user's terminal.

[0057] Hereinafter, examples of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. However, the present invention allows variations and modifications and is not limited to the examples described herein.

[0058] Hereinafter, the structure of a semiconductor device according to an example of the present disclosure will be described with reference to the accompanying drawings.

[0059] Figure 1A The structure of a semiconductor device according to an example of the present disclosure is shown.

[0060] Reference Figure 1A The semiconductor substrate 100 of the semiconductor device according to the example of the present disclosure may have a first conductivity type. An epitaxial layer 110 may be formed on the semiconductor substrate 100 .

[0061] The first conductivity type of the substrate 100 may have a doping concentration higher than that of the epitaxial layer 110 .

[0062] The epitaxial layer 110 may have the same first conductivity type as the semiconductor substrate 100 having the first conductivity type. The epitaxial layer 110 may include at least two or more layers by performing multiple epitaxial formation processes, wherein a lower epitaxial layer (not shown) may be formed on the substrate 100, and an upper epitaxial layer (not shown) may be formed on the lower epitaxial layer.

[0063] In the lower epitaxial layer, the dopant of the first conductivity type in the substrate 100 can be dispersed to the lower epitaxial layer by heat treatment performed in a subsequent process, so that the doping concentration of the lower epitaxial layer is increased and the resistivity value is reduced. In the upper epitaxial layer, since the dispersion of the dopant of the first conductivity type is relatively small, the concentration of the dopant of the first conductivity type can be lower than the concentration of the dopant of the first conductivity type in the lower epitaxial layer, and thus the resistivity of the upper epitaxial layer can be relatively high.

[0064] In this way, the resistivity formed in the epitaxial layer 110 of the drift layer is reduced as a whole, and a low on-resistance (Rdson) between the drain and the source can be achieved. The epitaxial layer 110 may have a thickness of 2 μm to 15 μm, and may be formed to have a thickness less than three times the depth of the trench 120 described later.

[0065] The shielding insulating layer 130 may be formed inside the plurality of trenches 120. The shielding insulating layer 130 may be formed through a primary thermal oxidation process and a secondary deposition process.

[0066] The shielding electrode 140 may be formed in a lower portion of the plurality of trenches 120 surrounded by the shielding insulating layer 130. The shielding electrode 140 may be formed by performing a shielding polysilicon deposition process on the shielding insulating layer 130.

[0067] The inter-electrode insulating layer 150 may be formed on the shield insulating layer 130 and the shield electrode 140 in the plurality of trenches 120. The input capacitance value and the total amount of gate charge (Qq) required to drive the input capacitance value may be adjusted by adjusting the area of ​​the inter-electrode insulating layer 150. The inter-electrode insulating layer 150 may be referred to as an inter-polysilicon dielectric layer, an inter-polysilicon oxide layer, or an inter-electrode insulating layer made of oxide, etc.

[0068] The gate insulating layer 160 may be formed and disposed on the inter-electrode insulating layer inside the plurality of trenches. The gate insulating layer 160 may be formed on the upper surface of the etched inter-electrode insulating layer 150 inside the trenches, on the inner wall of the trench 120, and on a portion of the upper surface of the epitaxial layer 110 via a deposition process.

[0069] The gate electrode 170 may be formed and disposed on the gate insulating layer 160 .

[0070] The gate electrode 170 may be formed by recess etching the gate polysilicon from the upper surface of the epitaxial layer 110 into the interior of the trench 120. By adjusting the thickness A of the gate electrode 170 through the recess etching process, the input capacitance value and the total amount of gate charge (Qq) required to drive the input capacitance value may be adjusted.

[0071] The gate electrode 170 disposed inside the trench 120 may be referred to as an upper electrode, and the shielding electrode 140 may be referred to as a lower electrode.

[0072] The body region 210 may be formed to include a surface on an upper portion of the epitaxial layer 110 between the plurality of trenches 120 .

[0073] Depending on the depth at which the body region 210 is formed, on-resistance (Ron) and capacitance values ​​may be adjusted, such that the depth of the body region 210 may vary depending on the intended use of the device.

[0074] The source region 220 may be formed on the body region 210 .

[0075] An interlayer insulating layer 230 may be formed on an upper surface of the gate electrode 170 and a portion of an upper surface of the source region 220 .

[0076] The body contact region 215 may be in contact with the source region 220 and the body region 210. The body contact region 215 may be formed within the body region 210 formed between the plurality of trenches 120.

[0077] The metal layer 240 may be formed on the body region 210, the source region 220, and the interlayer insulating layer 230. The metal layer 240 may be referred to as a source electrode electrically connected to the source region 220.

[0078] Figure 1B Thicknesses of components of a semiconductor device according to an example of the present disclosure are shown.

[0079] Reference Figure 1B 'A' shown in the figure represents the thickness of the gate electrode 170 , 'B' represents the thickness of the shield electrode 140 , and 'C' represents the thickness of the inter-electrode insulating layer 150 .

[0080] In addition, a ratio between the thickness 'B' of the shield electrode 140 and the thickness 'A' of the gate electrode may be expressed as 1:1 to 15:1.

[0081] By adjusting the thickness of the gate electrode 170, the area of ​​the interlayer insulating layer 230 formed on the gate electrode 170 can be adjusted. In addition, by adjusting the thickness of the gate electrode 170, the area of ​​the interlayer insulating layer 230 formed on the gate electrode 170 can be adjusted, and the capacitance value can be changed accordingly. In addition, by adjusting the thickness of the gate electrode 170 and the shielding electrode 140, the MOSFET voltage (guaranteed withstand voltage) can be adjusted. As the thickness of the shielding electrode 140 increases relative to the thickness of the gate electrode 170, a power MOSFET device with a high guaranteed withstand voltage can be realized.

[0082] A ratio between the thickness ('C') of the inter-electrode insulating layer 150 and the thickness ('A') of the gate electrode 170 may be expressed as 1:1 to 1:10.

[0083] In addition, a ratio between the thickness ('C') of the inter-electrode insulating layer 150 and the thickness ('B') of the shielding electrode 140 may be expressed as 1:3 to 1:15.

[0084] The present disclosure may have a characteristic that a capacitance value suitable for device characteristics may be adjusted by adjusting the thickness described above.

[0085] Hereinafter, a method of manufacturing a semiconductor device according to an example of the present disclosure will be described.

[0086] Figure 2 shows the structure of a trench formed inside an epitaxial layer according to an example of the present disclosure, Figure 3 shows the structure of a shielding insulating layer according to an example of the present disclosure, FIG. 4A to FIG. 4E is a diagram showing a process for forming a shield electrode according to an example of the present disclosure, FIG. 5A to FIG. 5C A process for forming an inter-electrode insulating layer according to an example of the present disclosure is shown. Figure 6 shows a structure of a gate insulating layer according to an example of the present disclosure, 7A to 7C shows a process for forming a gate electrode according to an example of the present disclosure, Figure 8 A process of forming a body region, a source region, and an interlayer insulating layer according to an example of the present disclosure is shown, and Fig. 9 The structure of a metal layer according to an example of the present disclosure is shown.

[0087] Reference Figure 2, an epitaxial layer 110 may be formed on a substrate 100. The semiconductor substrate 100 may be formed of a first conductivity type. The epitaxial layer 110 may be formed of the same first conductivity type as the substrate 100. The epitaxial layer 110 may be configured to have at least two layers or more, that is, may include a plurality of epitaxial layers. A lower epitaxial layer (not shown) may be formed on the substrate 100, and an upper epitaxial layer (not shown) may be formed on the lower epitaxial layer. In the lower epitaxial layer, since the dopant of the first conductivity type inside the substrate 100 is dispersed to the lower epitaxial layer by a heat treatment to be performed in a subsequent process, its resistivity value may be reduced by an increase in the concentration of the dopant of the lower epitaxial layer.

[0088] In the upper epitaxial layer, the resistivity value of the epitaxial layer may be higher because the dispersion of the first conductive type dopant in the upper epitaxial layer is relatively reduced and the concentration of the first conductive type dopant is relatively low. In this way, the resistivity of the epitaxial layer 100 of the drift layer can be reduced, and a low on-resistance (Rdson) between the drain and the source can be achieved. The epitaxial layer 110 can have a thickness of 2 μm to 15 μm, and can have a thickness not exceeding three times the depth of the trench 120.

[0089] Reference Figure 2 , a plurality of grooves 120 may be formed inside the epitaxial layer 110. The plurality of grooves 120 may be formed by performing a mask process and an etching process after forming the epitaxial layer 110. The plurality of grooves 120 may be formed such that the side of the groove has an inclination angle of 85° to 90° relative to the upper inner surface of the groove when etching, and the groove may be formed in a downward direction from the upper surface of the groove when etching. In addition, the plurality of grooves 120 may be formed to have an inclination angle of 90° to 95° of the groove sidewall relative to the upper outer surface of the groove, that is, the width of the lower surface of the groove may be formed to be narrower than or equal to the width of the upper surface of the groove.

[0090] This is to optimize the characteristics of the gate electrode 170 and the polysilicon shield formed inside the trench 120 , such as step coverage, cell pitch, breakdown voltage, and the like.

[0091] When etched, the trench 120 may be formed to have a U-shape or a V-shape, depending on the angle at which the trench 120 is etched.

[0092] The substrate 100 and the epitaxial layer 110 may be formed of silicon and silicon carbide.

[0093] After etching the trench, a step of forming a sacrificial oxide layer (not shown) on the sidewall of the trench 120 may be further included. The sacrificial oxide layer may be formed on the sidewall of the trench 120 etched on the upper portion of the inside of the epitaxial layer 110. The sacrificial oxide layer may be used to repair damage or uneven areas formed on the sidewall of the epitaxial layer 110 during etching of the trench 120. The sacrificial oxide layer may be thinly formed to have a thickness of 1000 to 10000 ℃ by performing a heat treatment at a temperature between 900° C. and 1200° C. to After repairing damage or irregularities in the sidewalls formed during etching of the trench 120 , the sacrificial oxide layer may be removed from the epitaxial layer 110 .

[0094] Reference Figure 3 , a shielding insulating layer 130 may be formed inside the plurality of trenches 120. The shielding insulating layer 130 may be formed by deposition through a primary thermal oxidation process. The shielding insulating layer 130 may be deposited through a primary thermal oxidation process to to In another example, the shielding insulation layer 130 may be formed by further performing a secondary chemical vapor deposition (CVD) process after the primary thermal oxidation layer process.

[0095] The secondary chemical vapor deposition (CVD) process can deposit a thickness of to In this case, the primary thermal oxide layer may be used as a buffer layer. The shielding insulating layer 130 may be formed by depositing only the primary thermal oxide layer or by a combination of a primary insulating layer deposition process and a secondary insulating layer deposition process.

[0096] The secondary CVD process may be performed by sub-atmospheric pressure CVD (SACVD), plasma enhanced CVD (PECVD), high density plasma CVD (HDPCVD), or the like.

[0097] According to other examples, the shielding insulating layer 130 may be formed as a silicon oxide layer through a primary thermal oxidation process and may be formed as an oxide layer or a nitride layer through a secondary process, or may be formed as a deposition structure in which an oxide layer and a nitride layer are deposited.

[0098] Reference FIG. 4A to FIG. 4D , the shielding electrode 140 may be formed by depositing and etching shielding polysilicon 140 a to 140 d .

[0099] Reference Figure 4AAfter forming the shielding insulating layer 130, a shielding polysilicon 140a deposition process may be performed on the shielding insulating layer 130. The shielding polysilicon 140a deposited on the shielding insulating layer 130 may have a thickness of 0.3 μm to 8 μm.

[0100] Reference Figure 4B , the portion of the shielding polysilicon deposited on the shielding insulating layer 130 can be removed by etching. After the portion of the shielding polysilicon is removed from the upper surface of the trench 120 by the CMP process, the blanket etching process can remove the shielding polysilicon so that only the portion of the shielding polysilicon 140b remains on the upper surface of the epitaxial layer 110.

[0101] Reference Figure 4C , the portion of the shielding polysilicon 140 inside the trench can be removed by further etching the shielding polysilicon 140c etched on the upper surface of the epitaxial layer 110. The depth to which the portion of the shielding polysilicon 140c is etched away in the trench 120 determines the thickness of the inter-electrode insulating layer 150 to be described later. The etched shielding polysilicon 140c serves as the shielding electrode 140.

[0102] Reference Figure 4D , a portion of the shielding insulating layer 130 formed on the sidewall of the trench in the upper portion of the shielding polysilicon 140d can be etched. By etching a portion of the shielding insulating layer 130, the opening 131 in the shielding insulating layer can be widened. In this way, the inter-electrode insulating layer 150 to be described later can be easily deposited on the inside of the trench 120 and the shielding insulating layer 130. Here, the etching process may be referred to as a partial etching process.

[0103] Reference Figure 4E , according to and with reference to Figure 4D In another example of a different process from that described above, the entire upper surface of the shield insulating layer 130 formed on the sidewall of the trench in the upper portion of the shield polysilicon 140d may be etched. By etching the entire upper surface of the shield insulating layer 130, the opening 132 in the shield insulating layer 130 may be larger than Figure 4D The width of the opening 131 formed in the shielding layer 130 is wider. The shielding insulating layer 130 can be etched deeper than the upper surface of the shielding polysilicon 140c. In this way, the inter-electrode insulating layer 150 of the layer to be described can be easily deposited on the inside of the trench 120 and the shielding insulating layer 130.

[0104] When etching is performed, etching may be performed by a wet etching method or a dry etching method.

[0105] The etching process may be performed by a dry etching method, a wet etching method, or a combination thereof.

[0106] Reference FIG. 5A to FIG. 5CThe inter-electrode insulating layer 150 may be formed by depositing inter-electrode insulating layers 150 a to 150 c on the shield insulating layer 130 and the shield electrode 140 inside the plurality of trenches 120 and then performing etching.

[0107] Reference Figure 5A , in execution Figure 4D After the partial etching of the electrode 130, the inter-electrode insulating layer 150a may be deposited on the shielding insulating layer 130 and the shielding electrode 140. The inter-electrode insulating layer 150a may be deposited by a CVD process. Alternatively, the inter-electrode insulating layer 150a may be deposited by a sub-atmospheric pressure CVD in a CVD process. The inter-electrode insulating layer 150a may be deposited to a thickness of to on the upper surface of the shielding insulation layer 130 .

[0108] In addition, the deposition of CVD may be performed by a plasma enhanced CVD process, a high density plasma CVD (HDPCVD) process, or the like.

[0109] Each of the shield insulating layer 130 and the inter-electrode insulating layer 150 may be formed of an insulating layer made of the same material or insulating layers made of different materials.

[0110] Reference Figure 5B , a CMP process and a blanket etching process can be performed on a portion of the shielding insulating layer 130 and a portion of the inter-electrode insulating layer 150 b deposited on the upper surface of the epitaxial layer 110, so that a portion of the shielding insulating layer 130 and a portion of the inter-electrode insulating layer 150 b remain on the upper surface of the epitaxial layer 110.

[0111] Reference Figure 5C By further etching the remaining shielding insulating layer 130 and the inter-electrode insulating layer 150c, the thickness (C) of the inter-electrode insulating layer 150 inside the groove can be adjusted. The portion of the shielding insulating layer 130 inside the groove 120 formed by the further etching process and the upper portion of the inter-electrode insulating layer 150c can be removed by a dry etching method, a wet etching method, or a combination of these methods. By removing the upper portion of the shielding insulating layer 130 and the inter-electrode insulating layer 150c, the inter-electrode insulating layer 150 can be formed inside the groove 120.

[0112] The inter-electrode insulating layer 150 formed on the upper surface of the shield electrode 140 inside the trench 120 may have to By adjusting the thickness C of the inter-electrode insulating layer 150 through the etching process, the area of ​​the inter-electrode insulating layer 150 can be adjusted. By adjusting the area of ​​the inter-electrode insulating layer 150, the target input capacitance value and the total amount of gate charge (Qq) required to drive the input capacitance value can be adjusted.

[0113] Reference Figure 6 , a gate insulating layer 160 may be formed on the inter-electrode insulating layer 150 disposed inside the plurality of trenches 120. The gate insulating layer 160 may be formed on the upper surface of the inter-electrode insulating layer 150 inside the trenches 120, the inner wall of the trenches 120, and the upper surface of the epitaxial layer 110 through a deposition process. The thickness of the gate insulating layer 160 may be formed to be about to within the range.

[0114] Reference 7A to 7C , gate polysilicon 170 a to 170 c may be deposited and etched on the gate insulating layer 160 .

[0115] Reference Fig. 7A , the gate polysilicon 170 a may be deposited on the gate insulating layer 160 . The gate polysilicon 170 a may be deposited from the inside of the trench 120 onto the upper surface of the epitaxial layer 110 .

[0116] Reference Figure 7B , the gate polysilicon 170b deposited on the upper surface of the epitaxial layer 110 may be removed to the upper surface of the epitaxial layer 110. A portion of the gate insulating layer 160 deposited on the upper surface of the epitaxial layer 110 may remain.

[0117] Reference Figure 7C , the gate polysilicon 170c can be recessed and etched from the upper surface of the epitaxial layer 110 into the trench 120. By recessing and etching the gate polysilicon into the gate electrode 170, the thickness A of the gate electrode 170 can be adjusted. The thickness of the gate polysilicon 170c recessed and etched to the upper surface of the epitaxial layer 110 can be to After the recess etching, the gate electrode 170 may have a thickness of 0.3 μm to 1 μm. By adjusting the thickness A of the gate electrode 170 through the above process, the target input capacitance value and the total amount of gate charge (Qq) required to drive the input capacitance value may be adjusted.

[0118] Reference Figure 8 , the body region 210 may be formed on the upper surface of the epitaxial layer 110 between the plurality of trenches 120. Here, the substrate 100 and the epitaxial layer 110 may have a first conductivity type, and the body region 210 may have an opposite second conductivity type. The body region 210 may be formed by a single implantation or multiple implantations. During multiple implantations, the process may be performed by dividing it into a first body region formation and a second body region formation, and the concentration of each may be adjusted differently.

[0119] In addition, an upper surface of the body region 210 may be disposed lower than an upper surface of the gate electrode 170 .

[0120] When ions are implanted in the body region 210 , impurities such as boron (B), boron difluoride (BF 2 ), etc. may be used for the ion implantation.

[0121] The depth of the body region 210 may be formed at various depths according to the application of the power semiconductor device, because the on-resistance (Ron), input capacitance (Ciss) value, and feedback capacitance (Crss) value may be adjusted according to the depth at which the body region is formed.

[0122] After forming the body region 210, a source pattern process may be performed to form the source region 220. In order to prevent the source region 220 from being formed on a termination region or the like other than an active region in which the source region 220 is to be formed within the body region 210, a source patterning process may be performed. After performing the source patterning process, the source region 220 may be formed. The source region 220 may be formed on the body region 210. The source region 220 may have a first conductivity type opposite to that of the body region 210. After forming the source region 220, the source pattern mask used in the source patterning process may be removed.

[0123] When forming the source region 220, impurities such as arsenic, phosphorus, etc. may be used. After forming the source region 220, an interlayer insulating layer 230 may be formed. The interlayer insulating layer 230 may be an interlayer dielectric (ILD) layer. The interlayer insulating layer 230 may be formed on the upper surface of the gate electrode 170 and the upper surface of the source region 220. The interlayer insulating layer 230 may be formed by a process of forming a layer of tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), etc. When the interlayer insulating layer 230 is formed as a TEOS layer, the thickness may be about 1000 Å. to Alternatively, when the interlayer insulating layer 230 is formed as a BPSG layer, the thickness may be approximately to

[0124] A body contact region 215 may be formed. The body contact region 215 may be formed in the body region 210 formed between the plurality of trenches 120. The body contact region 215 may be formed by etching the interlayer insulating layer 230. The body contact region 215 may be formed via a contact recess etching process. A metal layer 240 may be deposited to be disposed in the body contact region 215 formed between the interlayer insulating layers 230.

[0125] The body contact region 215 is ion implanted with high-concentration impurity ions of the second conductivity type that is higher than the concentration in the body region 210 .

[0126] Reference Fig. 9, a metal layer 240 may be formed. The metal layer 240 may be formed on the body region 210, the source region 220, and the interlayer insulating layer 230. The metal layer 240 may be formed by covering the body region 210, the source region 220, and the interlayer insulating layer 230. In addition, the metal layer 240 may be deposited to be disposed on the body contact region 215 formed between the interlayer insulating layers 230 described above. The metal layer 240 may be formed via a CMP process after performing a deposition process having a uniform thickness.

[0127] The metal layer 240 may be formed of a metal such as aluminum (Al), tungsten (W), or copper (Cu).

[0128] A passivation layer (not shown) may be formed on the metal layer 240 to protect the device.

[0129] The metal layer 240 may be referred to as a source electrode.

[0130] As described above, the manufacturing method of the semiconductor device according to the example of the present disclosure can achieve a small cell pitch by applying a split gate trench structure to form a shielding electrode 140 in the lower portion of the trench 120 and a gate electrode 170 above the shielding electrode 140, and can achieve fast switching characteristics by minimizing the thickness of the gate electrode 170 to reduce the input capacitance value and the total amount of gate charge (Qq) required to drive the input capacitance (Ciss) value.

[0131] Furthermore, the present disclosure aims to obtain a low input capacitance (Ciss) value by forming an inter-electrode insulating layer 150 having a thickness suitable for device characteristics between a shield electrode and a gate electrode through a shield polysilicon recess process and an oxide formation process.

[0132] Although the present disclosure has been described with reference to the examples shown in the accompanying drawings, this is exemplary only. It will be appreciated by those skilled in the art that various modifications and equivalent examples thereof may be implemented. Therefore, the true technical protection scope of the present disclosure should be determined by the creative conception of the appended claims.

Claims

1. A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; an epitaxial layer of the first conductivity type disposed on the substrate; forming a plurality of trenches in the epitaxial layer; a shielding insulating layer formed inside the plurality of trenches; a shielding electrode surrounded by the shielding insulating layer at a lower portion of the plurality of trenches; an inter-electrode insulating layer formed on top of the shield insulating layer and the shield electrode; a gate insulating layer disposed on the inter-electrode insulating layer; a gate electrode disposed on the gate insulating layer; forming a body region of a second conductivity type on an upper portion of the epitaxial layer between the plurality of trenches; a source region formed on the body region; an interlayer insulating layer formed on the gate electrode and the source region; as well as a body contact region in contact with the body region and the source region, The position and thickness of the gate electrode are determined by the position and thickness of the interlayer insulating layer.

2. The semiconductor device according to claim 1, wherein The position and thickness of the interlayer insulating layer are determined by the depth to which the shielding electrode is etched.

3. The semiconductor device according to claim 1, wherein A ratio between a thickness of the inter-electrode insulating layer and a thickness of the gate electrode is in a range of 1:1 to 1:

10.

4. The semiconductor device according to claim 1, wherein: A ratio between a thickness of the inter-electrode insulating layer and a thickness of the shielding electrode is in a range of 1:3 to 1:

15.

5. The semiconductor device according to claim 1, wherein An upper surface of the body region is disposed lower than an upper surface of the gate electrode.

6. The semiconductor device according to claim 1, wherein A ratio between a thickness of the shield electrode and a thickness of the gate electrode is in a range of 1:1 to 15:

1.

7. The semiconductor device according to claim 1, wherein The plurality of grooves are formed to have an inclination angle of a side surface of the groove with respect to an upper inner surface of the plurality of grooves between 85° and 90°.

8. The semiconductor device according to claim 1, wherein The shield insulating layer is formed by primary thermal oxidation or by performing secondary chemical vapor deposition after performing the primary thermal oxidation.

9. The semiconductor device according to claim 1, further comprising: A metal layer is formed over the body region, the source region, and the interlayer insulating layer.

10. The semiconductor device according to claim 1, wherein A ratio between a thickness of the inter-electrode insulating layer formed in the trench and a thickness of the gate electrode is in a range of 1:1.2 to 1:

3.

11. A method for manufacturing a semiconductor device, the method comprising: forming an epitaxial layer of the first conductivity type on a substrate of the first conductivity type; forming a plurality of trenches in the epitaxial layer; forming a shielding insulating layer inside the plurality of trenches; forming a shielding electrode surrounded by the shielding insulating layer at a lower portion of the plurality of trenches; forming an inter-electrode insulating layer on the shield insulating layer and the shield electrode inside the plurality of trenches; forming a gate insulating layer on the inter-electrode insulating layer disposed inside the plurality of trenches; forming a gate electrode on the gate insulating layer; forming a body region of a second conductivity type on an upper portion of the epitaxial layer between the plurality of trenches; forming a source region on the body region; forming an interlayer insulating layer on the gate electrode and the source region; as well as forming a body contact region in the body region, The position and thickness of the gate electrode are determined by the position and thickness of the interlayer insulating layer.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The formation of the inter-electrode insulating layer comprises: The position and thickness of the interlayer insulating layer are determined by the depth to which the shielding electrode is etched.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the epitaxial layer further comprises: forming a lower epitaxial layer on the substrate; and forming an upper epitaxial layer on the lower epitaxial layer, and Wherein, the dopant concentration of the lower epitaxial layer is higher than the dopant concentration of the upper epitaxial layer.

14. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the plurality of grooves further comprises: An epitaxial layer is formed, a mask is formed on the epitaxial layer, and trench etching is performed on the epitaxial layer to form a trench, and a side surface of the trench is formed to have an inclination angle between 85° and 90° with respect to an upper inner surface of the trench.

15. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the plurality of grooves further comprises: A sacrificial oxide layer is formed to restore damage on a sidewall or uneven region of the epitaxial layer that occurs during etching to form the plurality of trenches.

16. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the shielding insulating layer further comprises: The shield insulating layer is formed by primary thermal oxidation or by performing secondary chemical vapor deposition (CVD) after performing the primary thermal oxidation.

17. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the shielding electrode further comprises: forming a shield electrode by depositing shield polysilicon inside the shield insulating layer on an upper surface of the shield insulating layer; Etching the shielding polysilicon deposited on the upper surface of the shielding insulating layer to the height of the upper surface of the trench by chemical mechanical polishing (CMP), or etching the shielding polysilicon deposited on the upper surface of the shielding insulating layer to the height of the upper surface of the epitaxial layer by blanket etching; and The shield polysilicon etched to a height of an upper surface of the trench or to a height of an upper surface of the epitaxial layer is etched to a height at which the inter-electrode insulating layer is formed.

18. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the shielding electrode further comprises: Portions of side surfaces of the shield insulating layer are etched to increase a width of an opening in the shield insulating layer disposed on a side of the shield electrode.

19. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the inter-electrode insulating layer further comprises: depositing polysilicon oxide on the upper surface of the shield insulating layer by performing chemical vapor deposition on the shield electrode; etching the upper surface of the epitaxial layer by performing chemical mechanical polishing, blanket etching, or a combination of the chemical mechanical polishing and the blanket etching; and Dry etching, wet etching, or a combination of the dry etching and the wet etching is performed on the upper surface and the sidewall of the inter-electrode insulating layer, so that the inter-electrode insulating layer etched to the upper surface of the epitaxial layer is formed in the trench.

20. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the gate electrode further comprises: depositing gate polysilicon on the shield insulating layer and the gate insulating layer formed on the upper surface of the epitaxial layer; performing chemical mechanical polishing of gate polysilicon deposited on an upper surface of the epitaxial layer to an upper surface of the epitaxial layer; and Recess etching is performed on the gate polysilicon subjected to the chemical mechanical polishing, so that a height of the gate polysilicon is lower than a height of an upper surface of the epitaxial layer.

21. The method for manufacturing a semiconductor device according to claim 20, wherein: The recess etching includes etching the gate polysilicon from the upper surface of the epitaxial layer to to Etching thickness.

22. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the body region further comprises: The body region is formed to have a maximum thickness on an upper surface of the epitaxial layer equal to a depth of the gate electrode formed on an upper surface of the inter-electrode insulating layer.

23. The method for manufacturing a semiconductor device according to claim 11, further comprising: A metal layer is formed over the body region, the source region, and the interlayer insulating layer.

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