Semiconductor device structure and manufacturing method thereof

Abstract

The invention provides a semiconductor device structure and a manufacturing method thereof. The semiconductor device structure includes a source / drain (S / D) feature disposed in a recess between two adjacent channel regions, where the S / D feature includes an epitaxial layer conformally deposited on an exposed surface of the recess. The structure also includes a silicide layer conformally disposed on the S / D feature and an S / D contact disposed on the silicide layer, where the S / D contact has a first portion extending into the recess and the first portion has at least three surfaces surrounded by the silicide layer and the S / D feature.

Description

Technical Field

[0001] The present disclosure relates to semiconductor device structures and methods for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down presents new challenges. For example, reducing parasitic capacitance between source / drain features and gates while maintaining the desired K value of the device has become an increasing challenge. Improved structures and methods for manufacturing the same are needed. Summary of the invention

[0003] In one aspect, the present application provides a semiconductor device structure, comprising: a source / drain (S / D) feature disposed on a substrate and between two adjacent semiconductor layers; a support layer disposed between the S / D feature and the substrate; and a dielectric spacer disposed between the semiconductor layer and the substrate and in contact with the semiconductor layer and the substrate, wherein the dielectric spacer, the substrate, the support layer, and the S / D feature define an air gap therebetween.

[0004] On the other hand, the present application provides a semiconductor device structure, comprising: a plurality of semiconductor layers vertically stacked on a substrate; a gate electrode layer surrounding a portion of each semiconductor layer; a first dielectric spacer disposed between and in contact with two adjacent semiconductor layers; a source / drain (S / D) feature in contact with each of the plurality of semiconductor layers; and a supporting layer disposed between the substrate and the S / D feature, wherein the S / D feature has a curved bottom surface that is in contact with a portion of a top surface of the supporting layer.

[0005] On the other hand, the present application provides a method for forming a semiconductor device structure, comprising: depositing a sacrificial gate structure over a portion of a first fin structure and a portion of a second fin structure formed from a substrate, wherein the first fin structure and the second fin structure each include a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; removing portions of the first fin structure and the second fin structure not covered by the sacrificial gate structure to form recesses on opposite sides of the sacrificial gate structure; forming a base layer on a portion of the top surface of the substrate exposed by the recess, wherein the base layer includes a first material; converting the base layer into a supporting layer by treating the base layer with plasma or free radicals of a substance generated from a second material; forming a source / drain (S / D) layer on the supporting layer, wherein the S / D layer covers the top of the supporting layer so that an air gap is formed between the bottom surface of the S / D layer and the top surface of the substrate; removing the plurality of second semiconductor layers to expose a portion of each first semiconductor layer of the first fin structure and the second fin structure; and forming a gate electrode layer to at least surround the exposed portion of a first semiconductor layer among the plurality of first semiconductor layers of the first fin structure and the second fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood from the following specific implementations. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1 to 8 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0008] 9A to 10A as well as FIG. 22A to FIG. 27A According to some embodiments, Figure 8 The cross-sectional side views of various stages of manufacturing a semiconductor device structure are taken at section AA.

[0009] FIG. 9B to FIG. 10B as well as FIG. 22B to FIG. 27B According to some embodiments, Figure 8 Section BB is a cross-sectional side view of various stages of manufacturing a semiconductor device structure.

[0010] FIG. 9C to FIG. 10C as well as FIG. 22C to FIG. 27C According to some embodiments, Figure 8 Section CC is a cross-sectional side view of various stages of manufacturing a semiconductor device structure.

[0011] Figures 11 to 19 According to some embodiments, Figure 8 The cross-sectional side views of various stages of manufacturing a semiconductor device structure are taken at section AA.

[0012] Figure 14-1 is an enlarged view of a portion of a semiconductor device structure according to some embodiments.

[0013] Figure 20-1A and Figure 20-1B is a cross-sectional side view of a semiconductor device structure according to some embodiments.

[0014] Figure 21-1A to Figure 21-1D Cross-sectional side views of various stages in the fabrication of a semiconductor device structure are shown in accordance with some alternative embodiments.

[0015] Figure 21-2 According to some alternative embodiments Figure 21-1D An enlarged view of a portion of a semiconductor device structure in FIG.

[0016] Figure 22A-1 Shows Fig.22A An enlarged view of a portion of a semiconductor device structure is shown.

[0017] FIG. 22D to FIG. 27D According to some embodiments, Fig.22A Section DD is a cross-sectional side view of various stages of manufacturing a semiconductor device structure.

[0018] Figure 28 to Figure 31 An enlarged view of a portion of a semiconductor device structure is shown in accordance with some embodiments.

[0019] Fig.32A and Fig.32B is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, spatially relative terms (e.g., "below," "lower," "above," "over," "above," "top," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0022] The present disclosure relates generally to semiconductor devices, and more specifically to field effect transistors (FETs), such as planar FETs, three-dimensional fin-line FETs (FinFETs), gate-all-around (GAA) devices (e.g., horizontal gate-all-around (HGAA) FETs, vertical gate-all-around (VGAA) FETs), vertical FETs, forksheet FETs, or complementary FETs (CFETs). Although embodiments of the present disclosure are discussed with respect to GAA devices, implementations of some aspects of the present disclosure may be used in other processes and / or other devices. Those of ordinary skill in the art will readily appreciate that other modifications that may be made are contemplated within the scope of the present disclosure.

[0023] Figures 1 to 32B FIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that Figures 1 to 32B Additional operations are provided before, during, and after the illustrated processes, and some of the operations described below may be replaced or eliminated for additional embodiments of the methods. The order of the operations / processes is not limiting and may be interchangeable.

[0024] Figures 1 to 8 is a perspective view of various stages in fabricating a semiconductor device structure 100 in accordance with some embodiments. Fig.32A and Fig.32B FIG. 9 is a flow chart of a method 1000 for manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Fig.31 Semiconductor device 100 is schematically shown at various stages of fabrication according to method 1000. It should be understood that additional steps may be provided before, during, and / or after method 1000, and that some of the steps described may be replaced, eliminated, or moved for further embodiments of method 1000.

[0025] At block 1002, a semiconductor device structure 100 is provided, which includes a semiconductor layer stack 104 formed on a substrate 101, such as Figure 1As shown. Substrate 101 can be a semiconductor substrate. Substrate 101 may include crystalline semiconductor materials, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In one embodiment, substrate 101 is made of silicon. In some embodiments, substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer.

[0026] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type impurities). Depending on the circuit design, the dopant may be, for example, boron for a p-type field effect transistor (p-type FET) and phosphorus for an n-type field effect transistor (n-type FET).

[0027] The semiconductor layer stack 104 includes semiconductor layers made of different materials to facilitate the formation of a nanosheet channel in a multi-gate device (e.g., a nanosheet FET). In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first and second semiconductor layers 106, 108, and the first and second semiconductor layers 106, 108 are arranged parallel to each other. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some instances, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. In some embodiments, the first semiconductor layer 106 may be made of SiGe having a first Ge concentration range, and the second semiconductor layer 108 may be made of SiGe having a second Ge concentration range lower than or higher than the first Ge concentration range. In any case, the second semiconductor layer 108 may have a Ge concentration in a range between about 20 at. % (atomic percent) and 30 at. %.

[0028] The thickness of the first semiconductor layer 106 and the second semiconductor layer 108 can vary, depending on the application and / or device performance considerations. In some embodiments, each first semiconductor layer 106 and each second semiconductor layer 108 can have a thickness in a range between about 5 nm and about 30 nm. Each second semiconductor layer 108 can have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each first semiconductor layer 106 has a thickness in a range between about 10 nm and about 30 nm, and each second semiconductor layer 108 has a thickness in a range between about 5 nm and about 20 nm. The second semiconductor layer 108 can eventually be removed and used to define the vertical distance between adjacent channels of the semiconductor device structure 100.

[0029] The first semiconductor layer 106 or a portion thereof may form (one or more) nanosheet channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanosheet is used herein to represent any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term refers to an elongated material portion having a circular and substantially circular cross-section, and a beam-shaped or strip-shaped material portion including, for example, a cylindrical or substantially rectangular cross-section. The (one or more) nanosheet channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanosheet transistor. The nanosheet transistor may be referred to as a nanosheet transistor, a nanowire transistor, a fully surrounding gate (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define the channel of the semiconductor device structure 100 is further discussed below.

[0030] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of each layer of the semiconductor layer stack 104 may be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. Figure 1 The arrangement is shown as alternating, but it is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, depending on the predetermined number of nanosheet channels per FET. For example, the number of first semiconductor layers 106 (i.e., the number of channels) can be between 2 and 8.

[0031] At block 1004, a fin structure 112 is formed from the semiconductor layer stack 104, such as Figure 2As shown. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed from the substrate 101. Before forming the fin structure 112, a mask structure 110 is formed on the semiconductor layer stack 104. The mask structure 110 may include a liner layer 110a and a hard mask 110b. The liner layer 110a may be an oxygen-containing layer, such as SiO 2 The hard mask 110b may be a nitrogen-containing layer, such as Si 3 N 4 The mask structure 110 may be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process.

[0032] The fin structure 112 may be formed by patterning the mask structure 110 using one or more photolithography processes and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include a double patterning process or a multi-patterning process. Typically, the double patterning process or the multi-patterning process combines the photolithography process with the self-alignment process, thereby allowing the created pattern to have a pitch that is, for example, smaller than that obtainable using a single direct photolithography process. As an example of a multi-patterning process, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure 112. In any case, one or more etching processes form trenches 114 through the mask structure 110, through the semiconductor layer stack 104, and into the substrate 101 in an unprotected area, thereby leaving a plurality of extended fin structures 112. The width W1 of the fin structure 112 along the Y direction may be in a range between about 1.5 nm and about 44 nm (e.g., about 2 nm to about 6 nm). The trench 114 may be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof. Although two fin structures 112 are shown, the number of fin structures is not limited to two.

[0033] Figure 2 It is also shown that the fin structure 112 has substantially vertical sidewalls, so that the widths of the fin structures 112 are substantially similar, and each first semiconductor layer 106 and each second semiconductor layer 108 in the fin structure 112 are rectangular. In some embodiments, the fin structure 112 may have tapered sidewalls, so that the width of each fin structure 112 continuously increases in a direction toward the substrate 101. In this case, each first semiconductor layer 106 and each second semiconductor layer 108 in the fin structure 112 may have different widths and be trapezoidal.

[0034] At block 1006 , after forming the fin structures 112 , an insulating material 118 is formed in the trenches 114 between the fin structures 112 , such as Figure 3 As shown. The insulating material 118 fills the trench 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation (e.g., a chemical mechanical polishing (CMP) process and / or an etch back process) is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0035] Thereafter, the insulating material 118 is recessed to form the insulating region 120. After the recess, portions of the fin structure 112 (e.g., the semiconductor layer stack 104) may protrude from between adjacent insulating regions 120. The insulating region 120 may have a top surface that is flat, convex, concave, or a combination of the foregoing as shown. The recessing of the insulating material 118 exposes the trench 114 between adjacent fin structures 112. The insulating material 118 may be recessed using a suitable process (e.g., a dry etching process, a wet etching process, or a combination thereof). When the recess is completed, the top surface of the insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 in contact with the well portion 116 formed from the substrate 101.

[0036] At block 1008, a cladding layer 117 is formed on the exposed portion of the fin structure 112 by an epitaxial process, such as Figure 4 As shown. In some embodiments, a semiconductor liner (not shown) may be first formed on the fin structure 112, and then a cladding layer 117 may be formed on the semiconductor liner. During the formation of the cladding layer 117, the semiconductor liner may diffuse into the cladding 117. In either case, the cladding layer 117 is in contact with the semiconductor layer stack 104. In some embodiments, the cladding layer 117 and the second semiconductor layer 108 include the same material with the same etching selectivity. For example, the cladding layer 117 and the second semiconductor layer 108 may be or include SiGe. The cladding layer 117 and the second semiconductor layer 108 may be subsequently removed to create space for a subsequently formed gate electrode layer.

[0037] At block 1010, a liner 119 is formed on the cladding layer 117 and on the top surface of the insulating material 118, such as Figure 5 The liner 119 may include a material having a k value lower than 7, such as SiO 2, SiN, SiCN, SiOC, or SiOCN. The liner 119 may be formed by a conformal process, such as an ALD process. Then, in the trench 114 ( Figure 4 ) and a dielectric material 121 is formed on the liner 119. The dielectric material 121 may be an oxygen-containing material, such as an oxide, formed by FCVD. The oxygen-containing material may have a k value of less than about 7 (e.g., less than about 3). A planarization process (e.g., a CMP process) may be performed to remove portions of the liner 119 and the dielectric material 121 formed on the fin structure 112. After the planarization process, a portion of the cladding layer 117 disposed on the hard mask 110 b is exposed.

[0038] Next, the liner 119 and the dielectric material 121 are recessed to the level of the topmost first semiconductor layer 106. For example, in some embodiments, after the recessing process, the top surface of the liner 119 and the dielectric material 121 may be flush with the top surface of the topmost first semiconductor layer 106. The recessing process may be a selective etching process that does not substantially affect the semiconductor material of the cladding layer 117. As a result of the recessing process, trenches 123 are formed between the fin structures 112.

[0039] At block 1012, in the groove 123 ( Figure 5 ) and forming a dielectric material 125 on the dielectric material 121 and the liner 119, such as Figure 6 As shown. The dielectric material 125 may include SiO, SiN, SiC, SiCN, SiON, SiOCN, AlO, AlN, AlON, ZrO, ZrN, ZrAlO, HfO, or other suitable dielectric materials. In some embodiments, the dielectric material 125 includes a high-k dielectric material (e.g., a material having a k value greater than 7). The dielectric material 125 may be formed by any suitable process, such as a CVD, PECVD, FCVD, or ALD process. A planarization process (e.g., a CMP process) is performed until the hard mask 110b of the mask structure 110 is exposed. The planarization process removes the portion of the dielectric material 125 and the cladding layer 117 disposed above the mask structure 110. The liner 119, the dielectric material 121, and the dielectric material 125 may be collectively referred to as a dielectric feature 127 or a hybrid fin. The dielectric feature 127 is used to separate the subsequently formed source / drain (S / D) epitaxial features and the adjacent gate electrode layer.

[0040] At block 1014, the cladding layer 117 is recessed and the mask structure 110 is removed, as shown. Figure 7As shown. The recessing of the cladding layer 117 can be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. The recessing process can be controlled so that the remaining cladding layer 117 is substantially at the same level as the top surface of the uppermost first semiconductor layer 106 in the semiconductor layer stack 104. The etching process can be a selective etching process that does not substantially affect the dielectric material 125. The removal of the mask structure 110 can be performed by any suitable process, such as dry etching, wet etching, or a combination thereof.

[0041] At block 1016 , one or more sacrificial gate structures 130 (only two are shown) are formed over the semiconductor device structure 100 , such as Figure 8 As shown. A sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, followed by a patterning process and an etching process. For example, the patterning process includes a photolithography process (e.g., photolithography or electron beam (e-beam) lithography), and the photolithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations of the foregoing. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations of the foregoing.

[0042] By patterning the sacrificial gate structure 130, the semiconductor layer stack 104 of the fin structure 112 is partially exposed to the opposite side of the sacrificial gate structure 130. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 is used as the channel region of the semiconductor device structure 100. The portion of the fin structure 112 exposed to the opposite side of the sacrificial gate structure 130 defines the source / drain (S / D) region of the semiconductor device structure 100. In some cases, some S / D regions can be shared between various transistors. For example, each of these S / D regions can be connected together and implemented as a plurality of functional transistors. Although two sacrificial gate structures 130 are shown, more or fewer sacrificial gate structures 130 can be arranged along the X direction in some embodiments.

[0043] Next, a gate spacer 138 is formed on the sidewall of the sacrificial gate structure 130. The gate spacer 138 can be formed by first depositing a conformal layer and then etching back the conformal layer to form a sidewall gate spacer 138. For example, a spacer material layer can be conformally disposed on the exposed surface of the semiconductor device structure 100. The conformal spacer material layer can be formed by an ALD process. Subsequently, an anisotropic etch is performed on the spacer material layer using, for example, RIE. During the anisotropic etching process, most of the spacer material layer is removed from the horizontal surface (e.g., the top of the fin structure 112, the cladding layer 117, the dielectric material 125), thereby leaving the gate spacer 138 on the vertical surface (e.g., the sidewall of the sacrificial gate structure 130). The gate spacer 138 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or a combination of the foregoing.

[0044] In some embodiments where the capping layer 117 and the dielectric features 127 are not present, portions of the sacrificial gate structure 130 and the gate spacers 138 are formed on the insulating material 118 and gaps are formed between exposed portions of the fin structure 112 .

[0045] 9A to 10A as well as FIG. 22A to FIG. 27A According to some embodiments, Figure 8 1 and 2 are cross-sectional side views of various stages of fabricating the semiconductor device structure 100 , taken at section AA. FIG. 9B to FIG. 10B as well as FIG. 22B to FIG. 27B According to some embodiments, Figure 8 1 and 2 are cross-sectional side views of various stages of fabricating the semiconductor device structure 100 , taken at section BB. FIG. 9C to FIG. 10C as well as FIG. 22C to FIG. 27C According to some embodiments, Figure 8 1 and 2 are cross-sectional side views of various stages of fabricating the semiconductor device structure 100 , taken at section CC. Figures 11 to 19 According to some embodiments, Figure 8 1 and 1. The cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 are taken from the cross-sectional view AA. The cross-sectional view AA is in the plane of the fin structure 112 along the X direction. The cross-sectional view BB is in the plane perpendicular to the cross-sectional view AA and in the sacrificial gate structure 130. The cross-sectional view CC is in the plane perpendicular to the cross-sectional view AA and in the S / D epitaxial feature 146 ( Fig.22A )middle. FIG. 22D to FIG. 27D According to some embodiments, Fig.22A DD is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100.

[0046] At block 1018, the exposed portion of the semiconductor layer stack 104 of the fin structure 112, the exposed portion of the cladding layer 117, and the portion of the exposed dielectric material 125 not covered by the sacrificial gate structure 130 and the gate spacer 138 are removed to form a recess 139 for the S / D feature, as shown in FIG. Fig. 9A and Fig. 9C As shown. The removal of each layer can be accomplished by using one or more suitable etching processes (e.g., dry etching, wet etching, or a combination thereof). The one or more etching processes can be performed until the well portion 116 is exposed. The exposed portion of the fin structure 112 can be recessed to the level of the bottom surface of the second semiconductor layer 108 that contacts the well portion 116 of the substrate 101.

[0047] At block 1020, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally along the X direction. The removal of the edge portions of the second semiconductor layers 108 forms a cavity. In some embodiments, these portions of the second semiconductor layers 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon and / or SiGe having a lower germanium concentration than the second semiconductor layer 108, a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH) may be used. 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediaminecatechol (EDP), or potassium hydroxide (KOH) solution) to selectively etch the second semiconductor layer 108.

[0048] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer (or so-called inner spacer) 144, such as Fig. 10A As shown. The dielectric spacer 144 may be made of SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacer 144 may be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), and then removing the portion of the conformal dielectric layer except the dielectric spacer 144 by anisotropic etching. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between the dielectric spacers 144 along the X direction.

[0049] At block 1022 , a base layer 107 is formed on the exposed surfaces of the sacrificial gate structure 130 and the semiconductor layer stack 104 and a portion of the exposed surface of the substrate 101 . Fig.11As shown. The base layer 107 may be conformally formed on the top surface and the sidewall surface of the sacrificial gate structure 130. In some embodiments, the base layer 107 is deposited so that the base layer 107 on the horizontal surface of the semiconductor device structure 100 (e.g., the top surface of the sacrificial gate structure 130 and the top surface of the substrate 101) has a rounded head or a curved (e.g., convex) profile. As will be described in more detail below, the base layer 107 is deposited so that it does not completely cover the top surface of the substrate 101 between adjacent sacrificial gate structures 130, thereby exposing the top surface of the substrate 101 at and / or near the corners of the substrate 101 and the sidewall surface of the semiconductor layer stack 104 (e.g., the sidewall of the bottommost dielectric spacer 144) to air. The base layer 107 on the top surface of the sacrificial gate structure 130 may have a thickness H0, the base layer 107 on the sidewall surfaces of the sacrificial gate structure 130 and the semiconductor layer stack 104 may have a thickness H1 less than the thickness H0, and the base layer 107 on the top surface of the substrate 101 has a thickness H2 greater than the thickness H0.

[0050] In some embodiments, base layer 107 is deposited such that the highest point (e.g., center point) of base layer 107 on the top surface of substrate 101 is at a height above interface 109 defined by bottommost first semiconductor layer 106 and dielectric spacer 144. In some embodiments, the highest point of base layer 107 on the top surface of substrate 101 is at a height between the top surface and the bottom surface of bottommost first semiconductor layer 106.

[0051] In some embodiments, base layer 107 is deposited such that the highest point (eg, center point) of base layer 107 on the top surface of substrate 101 is at substantially the same height as interface 109 defined by bottommost first semiconductor layer 106 and dielectric spacer 144 .

[0052] The base layer 107 may include silicon or be formed of silicon. In some embodiments, the base layer 107 is pure silicon (e.g., intrinsic or undoped) or substantially pure silicon (e.g., substantially free of impurities, e.g., having an impurity percentage of less than about 1%). In some embodiments, the base layer 107 is formed of doped silicon. In the case where the base layer 107 is doped silicon, a dopant of a group III element, such as boron, may be used. In an exemplary embodiment, the base layer 107 is undoped silicon.

[0053] The base layer 107 may be deposited using any suitable deposition process, such as CVD, a cyclic deposition etch (CDE) epitaxial process, a selective etch growth (SEG) process, ALD, PEALD, molecular beam epitaxy (MBE), or any combination of the foregoing. In some embodiments, the base layer 107 is deposited by a plasma-assisted CVD process using a bottom-up growth technique. The bottom-up growth technique may be an epitaxial growth process (e.g., a deposition etch process) combined with an etching component. In this case, the semiconductor device structure 100 may be exposed to deposition chemicals and etching chemicals simultaneously during the epitaxial growth process. In the case where the base layer 107 is formed of undoped silicon, the bottom-up growth process may be performed by exposing the semiconductor device structure 100 to a plasma substance formed by a silicon-containing precursor and an etching gas. The silicon-containing precursor deposits silicon on the exposed surfaces of the sacrificial gate structure 130 and the semiconductor layer stack 104 and a portion of the exposed surface of the substrate 101, while the etching gas etches away a portion of the deposited silicon. Suitable silicon-containing precursors may include, but are not limited to, monosilane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), butadienesilane (Si 4 H 10 ), dimethylsilane ((CH 3 ) 2 S H 2 ), methylsilane (SiH(CH 3 ) 3 ), dichlorosilane (SiH 2 Cl 2 , DCS), trichlorosilane (SiHCl 3 , TCS), etc. Suitable etching gases may include, but are not limited to, hydrogen, hydrogen chloride (HCl), chlorine (Cl 2 )wait.

[0054] In any case, the final result of the deposition-etching process forms a conformal layer of base layer 107 on the exposed surfaces of sacrificial gate structure 130 and semiconductor layer stack 104 and a portion of the exposed surface of substrate 101. Since the ion flux at the horizontal surfaces of semiconductor device structure 100 (e.g., the top surfaces of sacrificial gate structure 130 and substrate 101) is generally higher than the ion flux at the vertical surfaces of semiconductor device structure 100 (e.g., the sidewall surfaces of sacrificial gate structure 130 and semiconductor layer stack 104), base layer 107 is deposited to have a greater thickness on the horizontal surfaces than on the vertical surfaces of semiconductor device structure 100. In addition, the difference in ion flux between the horizontal and vertical surfaces produces a deposition rate that is greater than the etching rate at the horizontal surfaces of semiconductor device structure 100, thereby depositing base layer 107 in a bottom-up manner to have a thickness difference from bottom to sidewall.

[0055] In various embodiments, the base layer 107 on the horizontal surface of the semiconductor device structure 100 (e.g., the top surface of the sacrificial gate structure 130 and the substrate 101) is deposited to have a rounded head or top. The rounded head or curved (e.g., convex) profile of the top of the base layer 107 may be due to the ion flux at and / or near the sidewall surface of the semiconductor layer stack 104 being lower than the ion flux at the central area of ​​the horizontal surface of the semiconductor device structure 100. It has been observed that an increased deposition rate of the base layer 107 may promote the rounded or curved profile of the top of the base layer 107. The deposition rate may be increased, for example, by increasing the power of the RF generator (for plasma generation), reducing the chamber pressure, providing bias power to the substrate holder on which the semiconductor device structure 100 is disposed, and / or other process parameters (e.g., temperature, deposition gas flow rate, etching gas flow rate, carrier gas flow rate, and combinations of the foregoing) may be adjusted to increase the deposition rate and, therefore, increase the shape / height of the base layer 107. In some embodiments, the process parameters of the bottom-up growth process are controlled to provide a lower ion flux at the corner region between the sidewall surface of the semiconductor layer stack 104 and the top surface of the substrate 101. Therefore, there is little or no coverage of the base layer 107 in the corner region of the top surface of the substrate 101 between adjacent sacrificial gate structures 130. In this case, a gap 113 may be formed at the corner between the base layer 107 on the sidewall surface of the semiconductor layer stack 104 and the base layer 107 on the substrate 101, exposing a portion of the top surface of the substrate 101 to the air.

[0056] At block 1024, the semiconductor device structure 100 is subjected to a trimming process 175 to remove a portion of the base layer 107, such as Fig.12The trimming process 175 may be performed in an isotropic manner such that the thickness of the base layer 107 on the top and sidewall surfaces of the sacrificial gate structure 130 and the semiconductor layer stack 104 is reduced. For example, the base layer 107 on the top surface of the sacrificial gate structure 130 is reduced from a thickness of H0 ( Fig.11 ) is reduced to H0′, and the base layer 107 on the sidewall surface of the sacrificial gate structure 130 and the semiconductor layer stack 104 is reduced from the thickness H1 ( Fig.11 ) is reduced to H1'. In some embodiments, the thickness of the base layer 107 on the top surface of the substrate 101 is reduced from H2 ( Fig.11 ) is reduced to H2′. After the trimming process 175 , the gap 113 at the corner between the base layer 107 on the sidewall surface of the semiconductor layer stack 104 and the base layer 107 on the substrate 101 is widened.

[0057] In some embodiments, the base layer 107 is trimmed so that the highest point (e.g., center point) of the base layer 107 on the top surface of the substrate 101 is at a height above the interface 109 defined by the bottommost first semiconductor layer 106 and the dielectric spacer 144. In some embodiments, the highest point of the base layer 107 on the top surface of the substrate 101 is at a height between the top surface and the bottom surface of the bottommost first semiconductor layer 106.

[0058] In some embodiments, base layer 107 is trimmed such that the highest point (eg, center point) of base layer 107 on the top surface of substrate 101 is at a height slightly below an interface 109 defined by bottommost first semiconductor layer 106 and dielectric spacer 144 .

[0059] In some embodiments, the trimming process 175 is performed using NH 4 The trim process 175 may be a wet etching process of DI water, HF or diluted HF, deionized (DI) water, tetramethylammonium hydroxide (TMAH), other suitable solutions, or a combination of the foregoing. In some embodiments, the trim process 175 may be a standard clean-2 (SC2) followed by a standard clean-1 (SC1), wherein SC2 is DI water, hydrochloric acid (HCl), and hydrogen peroxide (H 2 O 2 ), and SC1 is a mixture of D1 water, NH 4 OH and H 2 O 2 In some embodiments, isopropyl alcohol (IPA) may be used after SC1. Other suitable wet etching processes may also be used, such as those including at least water (H 2 O), ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2) APM process, including at least H 2 O, H 2 O 2 and hydrogen chloride (HCl), comprising at least H 2 O 2 and sulfuric acid (H 2 SO 4 )'s SPM process (also known as piranha clean), or any combination of the foregoing.

[0060] In some embodiments, the trimming process 175 is a dry etching process using plasma or material radicals. For example, the trimming process 175 can use a reactive material generated by an in-situ hydrogen-containing gas in the reaction chamber or upstream of the reaction chamber (e.g., from a remote plasma generator). In some embodiments, the trimming process 175 is a plasma treatment process. Exemplary reactive materials may include hydrogen plasma or neutral radical materials, such as hydrogen radicals or atomic hydrogen. Other chemicals, such as chlorine-containing gases, may also be used. Plasma treatment may be any suitable plasma process, such as a decoupled plasma process, a remote plasma process, or a combination thereof. Plasma may be formed by a capacitively coupled plasma (CCP) source or an inductively coupled plasma (ICP) source driven by an RF power generator.

[0061] In the case of using an ICP source, the plasma treatment can be performed in a remote plasma generator having a chamber wall, a top plate, and a plasma source power applicator, the plasma source power applicator including a coil antenna disposed above the top plate and / or around the chamber wall. The plasma source power applicator is coupled to an RF power source through an impedance matching network, and the RF power source can use a continuous wave RF power generator or a pulsed RF power generator operating at a predetermined duty cycle. The source power ionizes the hydrogen-containing gas supplied to the remote plasma generator. The generated hydrogen ions can be filtered by a grounded showerhead disposed in the remote plasma generator before being supplied to the process chamber in which the semiconductor device structure 100 is disposed, to produce neutral radical species (e.g., hydrogen radicals). In an exemplary embodiment, the decoupled plasma process is formed by an ICP source driven by an RF power generator using an adjustable frequency in the range of about 2 MHz to about 13.56 MHz and operating the process chamber for a process time of about 3 seconds to about 50 seconds at a pressure in the range of about 0.5 Torr to about 8 Torr and a temperature of about 300 degrees Celsius to about 600 degrees Celsius. A process gas (e.g., hydrogen-containing gas) flow of about 200 sccm to about 5000 sccm may be provided. The RF power generator is operated to provide a power between about 50 watts and about 1000 watts, and the output of the RF power generator is controlled by a pulse signal having a duty cycle in the range of about 20% to about 80%. In the case where the base layer 107 is formed of silicon, a portion of the base layer 107 may be converted into hydrogenated amorphous silicon and removed by plasma or neutral radical species.

[0062] At block 1026, the semiconductor device structure 100 is subjected to a treatment process 177 to convert a portion of the trimmed base layer 107 into a sacrificial layer 111, such as Fig.13 After the treatment process 177, the thickness of the sacrificial layer 111 may be increased. For example, the base layer 107 on the top surface of the sacrificial gate structure 130 may be increased from a thickness of H0′ ( Fig.12 ) increases to H0″, and the base layer 107 on the sidewall surface of the sacrificial gate structure 130 and the semiconductor layer stack 104 increases from the thickness H1′ ( Fig.12 ) increases to H1". In some embodiments, the thickness of the base layer 107 on the top surface of the substrate 101 increases from H2' ( Fig.12 ) is reduced to H2". After the treatment process 177, the gap 113 at the corner between the base layer 107 on the sidewall surface of the semiconductor layer stack 104 and the base layer 107 on the substrate 101 remains open.

[0063] In some embodiments, the base layer 107 is processed so that the highest point (e.g., the center point) of the resulting sacrificial layer 111 on the top surface of the substrate 101 is at a height above the interface 109 defined by the bottommost first semiconductor layer 106 and the dielectric spacer 144. In some embodiments, the highest point of the resulting sacrificial layer 111 on the top surface of the substrate 101 is at a height between the top surface and the bottom surface of the bottommost first semiconductor layer 106.

[0064] In some embodiments, base layer 107 is processed so that the highest point (eg, center point) of the resulting sacrificial layer 111 on the top surface of substrate 101 is at substantially the same height as interface 109 defined by bottommost first semiconductor layer 106 and dielectric spacer 144 .

[0065] In various embodiments, the treatment process 177 may be a nitridation process using plasma or material radicals. For example, the treatment process 177 may use a reactive material generated by an in-situ nitrogen-containing gas in the reaction chamber or upstream of the reaction chamber (e.g., from a remote plasma generator). In some embodiments, the treatment process 177 is a plasma treatment process. Exemplary reactive materials may include nitrogen plasma or neutral radical materials, such as hydrogen radicals or atomic hydrogen. Alternatively, the treatment process 177 may be an oxidation process. In this case, the treatment process 177 may use a reactive material generated by an oxygen-containing gas (e.g., oxygen plasma, oxygen radicals, or atomic oxygen). Additionally or alternatively, the treatment process 177 may be a combination of a nitridation process and an oxidation process. Plasma treatment may be any suitable plasma process, such as a decoupled plasma process, a remote plasma process, or a combination thereof. The plasma may be formed by a CCP source or an ICP source driven by an RF power generator.

[0066] In the case of using an ICP source, the plasma treatment can be performed in a remote plasma generator. Similarly, the plasma source power can use a continuous wave RF power generator or a pulsed RF power generator operating at a predetermined duty cycle. The source power ionizes the nitrogen-containing or oxygen-containing gas supplied to the remote plasma generator. The generated nitrogen or oxygen ions can be filtered to generate neutral radical species (e.g., nitrogen radicals) before being supplied to the process chamber in which the semiconductor device structure 100 is set. In an exemplary embodiment, the decoupled plasma process is formed by an ICP source driven by an RF power generator with an adjustable frequency in the range of about 2 MHz to about 13.56 MHz and operating the process chamber for a process time of about 3 seconds to about 50 seconds at a pressure in the range of about 0.5 Torr to about 8 Torr and a temperature of about 300 degrees Celsius to about 600 degrees Celsius. A processing gas (e.g., nitrogen-containing gas) flow of about 200 sccm to about 5000 sccm can be provided. Suitable nitrogen-containing gases may include, but are not limited to, nitrogen (N 2 ), ammonia (NH 3 ), nitrous oxide (N 2 O), etc. Suitable oxygen-containing gases may include, but are not limited to, oxygen (O 2 ), ozone (O 3 ) or water vapor. The RF power generator is operated to provide a power between about 50 watts and about 1000 watts, and the output of the RF power generator is controlled by a pulse signal having a duty cycle in the range of about 20% to about 80%. In the case where the base layer 107 is formed of silicon, the base layer 107 can be partially or completely converted into silicon nitride or silicon oxide, depending on the process gas used during the treatment process 177.

[0067] In some embodiments that may be combined with any one or more embodiments of the present disclosure, the surface portion of the substrate 101 exposed by the gap 113 is nitrided or oxidized after the treatment process 177, and a nitrided or oxidized region 141 is formed, such as Fig.14 In the case where the substrate 101 is formed of silicon, the nitrided or oxidized region 141 may include silicon nitride or silicon oxide. The thickness of the nitrided or oxidized region 141 may extend into the substrate 101. In some embodiments, the nitrided or oxidized region 141 may have a depth H3 in the range of about 0.5 nm to about 10 nm. Figure 14-1 1 is an enlarged view of a portion of the semiconductor device structure 100 showing the nitrided or oxidized region 141 after the treatment process 177. The nitrided or oxidized region 141 may extend radially in the substrate 101 and contact a portion of the bottom surface of the base layer 107 that contacts the dielectric spacer 144 and a portion of the bottom surface of the base layer 107 that contacts the substrate 101.

[0068] At block 1028, a protective layer 147 is formed on the sacrificial layer 111. Fig.15 As shown. The protective layer 147 may be a polymer, a spin-on carbon material, or other suitable photoresist layer. The protective layer 147 protects the lower portion of the sacrificial layer 111 (particularly the sacrificial layer 111 on the substrate 101) from being damaged during the subsequent back etching process. The protective layer 147 may be deposited until it overfills the recess 139 ( Fig.13 The protective layer 147 may be deposited using spin coating or any suitable deposition process.

[0069] At block 1030, an etch back process is performed to remove a portion of the protective layer 147, such as Fig.16 As shown. The protective layer 147 may be recessed until the upper portion of the sacrificial layer 111 is exposed. In some embodiments, the protective layer 147 is recessed so that the top of the protective layer 147 is substantially at or slightly below the interface defined by the mask layer 136 and the sacrificial gate electrode layer 134. The etch-back process may be a selective etching process that removes the protective layer 147 but does not remove the sacrificial layer 111. Since the thickness of the sacrificial layer 111 on the top surface of the sacrificial gate structure 130 is greater than the thickness of the sacrificial layer 111 on the sidewall surfaces of the sacrificial gate structure 130 and the semiconductor layer stack 104, a longer etching time may be required. The use of the protective layer 147 ensures that the sacrificial layer 111 on the upper portion of the sacrificial gate structure 130 is completely removed without substantially affecting the sacrificial gate structure 130 and the sacrificial layer 111 on the substrate 101. In some embodiments, the protective layer 147 may be recessed so that the top of the protective layer 147 is at a height slightly higher than the upper surface of the bottommost first semiconductor layer 106.

[0070] At block 1032, the sacrificial layer 111 exposed on the upper portion of the sacrificial gate structure 130 is removed. Fig.17 The sacrificial layer 111 may be removed using any suitable removal process, such as wet etching, dry etching, or a combination thereof. The removal process is performed to selectively remove the sacrificial layer 111 that is not covered by the protective layer 147. The removal process may be a selective etching process that removes the sacrificial layer 111 but does not remove the sacrificial gate structure 130 and the protective layer 147. Depending on the material of the sacrificial layer 111, for example, the removal process may include hot phosphoric acid (H 3 PO 4 ) solution to remove silicon nitride, or HF solution to remove silicon oxide.

[0071] At block 1034, the remaining protective layer 147 is removed, such as Fig.18After removing the protective layer 147, the recess 139 and the gap 113 are exposed, and the sacrificial layer 111 on the sidewall surface of the sacrificial gate structure 130, the sidewall surface of the semiconductor layer stack 104, and the sacrificial layer 111 on the substrate 101 are exposed. At this stage, the sacrificial layer 111 has a width H4. The protective layer 147 can be removed by ashing or any suitable process.

[0072] At block 1036, if Fig.19 As shown, the sacrificial layer 111 on the sidewall surface of the sacrificial gate structure 130 and the sidewall surface of the semiconductor layer stack 104 is removed. The removal of the sacrificial layer 111 can be completed by an etching process 179, and the etching process 179 can be a wet etching, a dry etching, or a combination thereof. The etching process 179 can be a selective etching process that removes the sacrificial layer 111, but does not remove the sacrificial gate structure 130, the first semiconductor layer 106, and the dielectric spacer 144. A portion of the sacrificial layer 111 on the top surface of the substrate 101 can also be removed. However, due to the high aspect ratio of the recess 139, the etching rate of the sacrificial layer 111 on the substrate 101 is slower than the etching rate of the sacrificial layer 111 on the sidewall surface of the sacrificial gate structure 130 and the sidewall surface of the semiconductor layer stack 104. The etching process 179 can be performed until the sacrificial layer 111 on the sidewall surface of the sacrificial gate structure 130 and the sidewall surface of the semiconductor layer stack 104 is removed, thereby exposing the bottommost dielectric spacer 144. The sacrificial layer 111 remaining on the top surface of the substrate 101 becomes a support layer 111' after the etching process 179. The support layer 111' has a rounded head or a curved (e.g., convex) profile that follows the shape of the sacrificial layer 111 on the substrate 101. The support layer 111' has a height or thickness H2'' that is less than the thickness H2''. In some embodiments, the thickness H2'' is less than about 8 nm, for example, about 4 nm to about 6 nm. The support layer 111' has a height from Fig.18 The width H4 is shown as a reduced width H4'.

[0073] In some embodiments, the support layer 111' is etched so that the highest point (e.g., the center point) of the support layer 111' on the top surface of the substrate 101 is at a height above the interface 109 defined by the bottommost first semiconductor layer 106 and the dielectric spacer 144. In some embodiments, the highest point of the support layer 111' on the top surface of the substrate 101 is at a height between the top surface and the bottom surface of the bottommost first semiconductor layer 106. In any case, the presence of the support layer 111' helps prevent subsequent source / drain features from filling in the space between the substrate 101 and the source / drain features, thereby maintaining the gap 113 at the corner of the bottommost dielectric spacer 144 and the substrate 101 during the formation of the epitaxial source / drain features 146. The use of the support layer 11' is helpful, especially when the recess 139 has a high aspect ratio.

[0074] Above Figures 15 to 19 The illustrated embodiment shows a removal scheme in which the sacrificial gate structure 130 and the sacrificial layer 111 on the sidewall surfaces of the semiconductor layer stack 104 are removed in a two-step process involving the use of a protective layer (e.g., protective layer 147). Figure 20-1A and Figure 20-1B In the illustrated alternative embodiment, after the base layer 107 is converted into the sacrificial layer 111, an etching process is performed on the sacrificial layer 111 without using a protective layer. In this case, an etching process 179, which may be a directional isotropic etching process, is used to remove the sacrificial layer 111 on the sidewall surfaces of the sacrificial gate structure 130 and the semiconductor layer stack 104, as well as the sacrificial layer 111 on the substrate 101. Due to the high aspect ratio of the recess 139, the etching rate for removing the sacrificial layer 111 on the top and sidewall surfaces of the sacrificial gate structure 130 and the sidewall surfaces of the semiconductor layer stack 104 is greater than the etching rate for removing the sacrificial layer 111 on the substrate 101. Likewise, the sacrificial layer 111 remaining on the top surface of the substrate 101 becomes a supporting layer 111' after the etching process 179', as shown in FIG. Figure 20-1B As shown. The support layer 111' has a rounded head or a curved (e.g., convex) profile that generally follows the shape of the sacrificial layer 111 on the substrate 101 before the etching process 179'. The support layer 111' has a thickness H2"' that is less than the thickness H2". In some embodiments, the thickness H2"' is less than about 8nm, for example, about 4nm to about 6nm.

[0075] Figure 21-1A to Figure 21-1D 1 shows cross-sectional side views of various stages of fabricating a semiconductor device structure according to some alternative embodiments. Figure 21-1AIn the present invention, before forming the base layer 107, a liner 159 is formed on the exposed surface of the sacrificial gate structure 130 and the semiconductor layer stack 104 and a portion of the exposed surface of the substrate 101. In some embodiments, the liner 159 is an oxygen-containing layer, such as silicon oxide (SiO x ) and the like. In some embodiments, the liner 159 is a semiconductor layer, such as doped silicon. The liner 159 may be a conformal layer formed by a conformal process, such as an ALD process, a PECVD process, a molecular beam deposition (MBD) process, or the like, or a combination of the foregoing. The liner 159 may have a thickness in the range of about 0.5 nm to about 3 nm. The liner 159 serves as a capping layer and may be used to protect the channel layer (e.g., the first semiconductor layer 106) during subsequent processes.

[0076] exist Figure 21-1B In the embodiment, a base layer 107-1 is formed on the liner 159 (as shown in the above reference Fig.11 The base layer 107-1 may be formed in a similar manner to the base layer 107 such that the base layer 107-1 adjacent to the bottommost dielectric spacer 144 and the base layer 107-1 above the substrate 101 are separated from each other by the gap 113-1.

[0077] exist Figure 21-1C In the embodiment of the present invention, the base layer 107-1 is subjected to a trimming process 175' (like the trimming process 175) to remove a portion of the base layer 107-1. Likewise, the trimming process 175' can be performed in a similar manner to the trimming process 175, so that the thickness of the base layer 107-1 above the top and sidewall surfaces of the sacrificial gate structure 130 and the semiconductor layer stack 104 is reduced. After the trimming process 175', the thickness of the base layer 107-1 on the top surface of the substrate 101 is also reduced, and the gap 113-1 is widened. The liner 159 protects the semiconductor device structure 100 during the trimming process 175'.

[0078] exist Figure 21-1DIn the process 177, the semiconductor device structure 100 is subjected to a treatment process 177' (like the treatment process 177) to convert a portion of the trimmed base layer 107-1 into a sacrificial layer 111-1. The liner 159 prevents the first semiconductor layer 106 from converting during the treatment process 177'. Likewise, after the treatment process 177', the thickness of the sacrificial layer 111-1 can be increased, and the gap 113-1 at the corner between the base layer 107-1 on the sidewall surface of the semiconductor layer stack 104 and the base layer 107-1 on the substrate 101 remains open after the treatment process 177. The base layer 107-1 can be treated so that the highest point (e.g., the center point) of the resulting sacrificial layer 111' on the top surface of the substrate 101 is at a height higher than the interface 109 defined by the bottommost first semiconductor layer 106 and the dielectric spacer 144. In some embodiments, the highest point of the resulting sacrificial layer 111 ′ on the top surface of the substrate 101 is at a height between the top and bottom surfaces of the bottommost first semiconductor layer 106 .

[0079] Although not shown, it can be Fig.19 and Figure 20-1B The sacrificial layer 111-1 shown is formed as follows: After removing portions of the sacrificial layer 111-1 from the sacrificial gate structure 130 and the semiconductor layer stack 104, leaving the sacrificial layer 111-1 on the top surface of the substrate 101 (later becoming a support layer), various processes are performed, such as those described above with reference to Figures 15 to 19 or Figure 20-1A One or more etching processes may be performed to further remove the exposed liner 159. In some embodiments, the one or more etching processes are performed such that the liner 159 not covered by the sacrificial layer 111-1 is removed. In some embodiments, the one or more etching processes are performed such that only the liner 159 in contact with the bottommost dielectric spacer 144 and the substrate 101 remains.

[0080] Figure 21-2 According to some alternative embodiments Figure 21-1D FIG. 1 is an enlarged view of a portion of the semiconductor device structure 100 in FIG. Figure 21-2 The embodiment shown is similar to Figure 21-1A to Figure 21-1DThe embodiment shown, in addition to selectively forming a liner 159' on the sidewall surface of the first semiconductor layer 106 and the well portion 116 of the substrate 101. The liner 159' can be made of any suitable material that can hinder chemical reactions during the subsequent conversion of the base layer 107-1 into the sacrificial layer 111-1. The liner 159' can have a thickness in the range of about 0.5nm to about 3nm. The liner 159' can be made of a chemical material different from the first semiconductor layer 106 and the subsequent base layer 107-1. In some embodiments, the liner 159' is a semiconductor material. In some embodiments, the liner 159' is a dielectric material. In the case where the liner 159' is formed of a semiconductor material (e.g., doped silicon), a dopant of a Group III element, such as boron, can be used. In an exemplary embodiment, the liner 159' is boron-doped silicon (Si:B). Using Si:B as the liner 159' may be advantageous because the boron dopant may change the crystal orientation of the underlying materials (e.g., the first semiconductor layer 106 and the well portion 116 of the substrate 101) to facilitate the subsequent growth of the base layer 107-1 on the liner 159'. The liner 159' may be selectively formed using any suitable selective deposition process (e.g., a cyclic deposition etch (CDE) epitaxial process or a selective etch growth (SEG)). The precursors and temperature used to form the liner 159' may be controlled to achieve selective or preferential growth of the liner layer 159' on the semiconductor surface of the first semiconductor layer 106 above the dielectric surface of the dielectric spacer 144.

[0081] In the case where the liner 159' is formed of a dielectric material, the selective deposition of the liner 159' may be achieved by first forming the liner 159' entirely on the exposed surface of the semiconductor device structure 100 by an ALD process, and then removing the liner 159' from the dielectric spacers 144 by one or more selective etching processes (e.g., plasma treatment or atomic layer etching (ALE)), leaving the liner 159' on the first semiconductor layer 106. Suitable dielectric materials for the liner 159' may include, but are not limited to, SiN, SiCN, SiON, SiOCN, or any suitable nitride-based dielectric.

[0082] Thereafter, a base layer 107-1 is formed on the exposed surface of the semiconductor device structure 100 and covers the liner 159', and then the base layer 107-1 is treated to form the base layer 107-1 in a manner similar to that described above. Figures 11 to 13 The discussed method is converted into the sacrificial layer 111-1. Various processes (such as those referenced above) Figures 15 to 19 or Figure 20-1AThe process discussed above is performed to remove portions of the sacrificial layer 111-1 from the sacrificial gate structure 130 and the semiconductor layer stack 104, leaving the sacrificial layer 111-1 on the top surface of the substrate 101, as shown in FIG. Fig.19 and Figure 20-1B shown.

[0083] At block 1038, epitaxial S / D features 146 are formed on the support layer 111' in the source / drain (S / D) region, such as FIG. 22A to FIG. 22D As shown. The second semiconductor layer 108 below the sacrificial gate structure 130 is separated from the epitaxial S / D feature 146 by a dielectric spacer 144. The epitaxial S / D feature 146 may include one or more layers of Si, SiP, SiC, and SiCP for n-type FETs or Si, SiGe, Ge for p-type FETs. The epitaxial S / D feature 146 may be formed by an epitaxial growth method using selective epitaxial growth (SEG), CVD, ALD, or MBE. The epitaxial S / D feature 146 may be an S / D region. For example, one epitaxial S / D feature located on one side of the sacrificial gate structure 130 in a pair of epitaxial S / D features 146 may be a source region, and the other epitaxial S / D feature located on the other side of the sacrificial gate structure 130 in the pair of epitaxial S / D features 146 may be a drain region. A pair of S / D epitaxial features 146 include a source epitaxial feature 146 and a drain epitaxial feature 146 connected by a channel (i.e., the first semiconductor layer 106). The source / drain region may be referred to as a source or a drain, individually or collectively depending on the context. In the present disclosure, source and drain are used interchangeably and their structures are substantially the same.

[0084] The epitaxial S / D features 146 may be grown laterally from the sidewalls of the first semiconductor layer 106. The epitaxial S / D features 146 of the fin structure may be merged with the epitaxial S / D features 146 of the adjacent fin structure and formed as a whole. The epitaxial S / D features 146 may be grown vertically and horizontally to form facets, which may correspond to the crystal planes of the material used for the first semiconductor layer 106. After epitaxial growth, the upper portion of the support layer 111' may be in contact with or covered by the epitaxial S / D features 146. The bottom surface 146b of each epitaxial S / D feature 146 may have a concave shape or a curved surface, depending on the profile of the support layer 111'.

[0085] Figure 22A-1 Shows Fig.22A1. An enlarged view of a portion of the semiconductor device structure 100 shown. In some embodiments, the bottom surface 146b of the epitaxial S / D feature 146 may have a first portion 146-1 and a second portion 146-2 around the first portion 146-1. The first portion 146-1 is a curved surface having a first curvature, and the second portion 146-2 is a curved surface having a second curvature. In some embodiments, the first curvature is different from the second curvature. In some embodiments, the first curvature is opposite to the second curvature. In some embodiments, the first portion 146-1 has a concave surface, and the second portion 146-2 has a convex surface. In any case, the presence of the support layer 111' prevents the epitaxial S / D feature 146 from growing into the region around the lower portion of the support layer 111'. After the epitaxial S / D feature 146 is formed, the gap 113 remains open and becomes an air gap (or air corner) 115 around the lower portion of the support layer 111'. The air gap 115 is defined by the bottom surface of the epitaxial S / D features 146, the sidewalls of the dielectric spacer 144, the sidewalls of the support layer 111', and the top surface of the substrate 101. In particular, the air gap 115 can effectively reduce the distance between the epitaxial source / drain features 146 and the gate electrode layer in the subsequent replacement gate structure (e.g., Fig.26A The capacitance between the gate electrode layer 182).

[0086] At block 1040 , a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100 , such as FIG. 23A to FIG. 23D As shown. CESL 162 covers the top surface of the sacrificial gate structure 130, the insulating material 118, the epitaxial S / D features 146, and the exposed surface of the semiconductor stack 104. CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination of the foregoing, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. Materials for the ILD layer 164 may include compounds containing Si, O, C, and / or H, such as silicon oxide, TEOS oxide, SiCOH, and SiOC. Organic materials (e.g., polymers) may also be used for the ILD layer 164. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques.

[0087] At block 1042 , after forming the ILD layer 164 , a planarization operation (eg, CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed.

[0088] At block 1044, the sacrificial gate structure 130 and the second semiconductor layer 108 are sequentially removed, such as FIG. 25A to FIG. 25D As shown. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening 166 between the gate spacers 138 and between the adjacent first semiconductor layers 106. The ILD layer 164 protects the epitaxial S / D features 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process (e.g., dry etching, wet etching, or a combination thereof), followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof.

[0089] The removal of the sacrificial gate structure 130 exposes the first semiconductor layer 106 and the second semiconductor layer 108. An etching process (which may be any suitable etching process, such as dry etching, wet etching, or a combination thereof) is then performed to remove the second semiconductor layer 108 and expose the dielectric spacer 144. The etching process may be a selective etching process that removes the second semiconductor layer 108 but does not remove the gate spacer 138, the dielectric spacer 144, the ILD layer 164, the CESL 162, and the first semiconductor layer 106. In one embodiment, the second semiconductor layer 108 may be removed using a wet etchant (such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO 3 ), hydrochloric acid (HCl), phosphoric acid (H 3 PO 4 )), dry etchants (e.g., based on fluorine (e.g., F 2 ) or chlorine-based gases (such as Cl 2 After the etching process, the portion of the first semiconductor layer 106 not covered by the dielectric spacer 144 is exposed through the opening 166 .

[0090] At block 1046, a replacement gate structure 190 is formed, such as FIG. 26A to FIG. 26DAs shown. Each replacement gate structure 190 may include an interface layer (IL) 178, a gate dielectric layer 180, and a gate electrode layer 182. The interface layer (IL) 178 is formed to surround the exposed surface of the first semiconductor layer 106 along the channel region. The IL 178 may include or be made of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride, silicon oxynitride, oxynitride, etc.), and / or a dielectric layer (e.g., hafnium silicate) formed by thermal oxidation or chemical oxidation of the first semiconductor layer 106. The IL 178 may be formed by CVD, ALD, a cleaning process, or any suitable process. Next, a gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100 (e.g., on the IL 178, the sidewalls of the gate spacer 138, the top surface of the first ILD layer 164, the CESL 162, and the dielectric spacer 144). The gate dielectric layer 180 may include or be made of a high-k dielectric material, such as hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), silicon oxynitride (SiON), or other suitable high-k materials. The gate dielectric layer 180 may be a conformal layer formed by a conformal process, such as an ALD process, a PECVD process, a molecular beam deposition (MBD) process, or a combination of the foregoing.

[0091] After forming the IL 178 and the gate dielectric layer 180, a gate electrode layer 182 is formed on the gate dielectric layer 180. The gate electrode layer 182 fills the opening 166 ( Fig.25A and Fig.25B) and surrounds a portion of each first semiconductor layer 106. The gate electrode layer 182 includes one or more layers of a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, a metal alloy, other suitable materials, and / or combinations of the foregoing. The gate electrode layer 182 may be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) may be conformally deposited between the gate dielectric layer 180 and the gate electrode layer 182 (and if more than one, sequentially). The one or more optional conformal layers may include one or more barrier and / or capping layers and one or more work function tuning layers. The one or more barrier and / or capping layers may include or be: nitrides, silicon nitrides, carbonitrides, and / or aluminum nitrides of tantalum and / or titanium; nitrides, carbonitrides, and / or carbides of tungsten; etc.; or combinations of the foregoing. The one or more work function tuning layers may include or be: nitrides, silicon nitrides, carbonitrides, aluminum nitrides, aluminum oxides, and / or aluminum carbides of titanium and / or tantalum; nitrides, carbonitrides, and / or carbides of tungsten; cobalt; platinum; etc.; or combinations of the foregoing.

[0092] At block 1048, one or more metal gate etch back (MGEB) processes may be performed on the gate electrode layer 182. The MGEB process is performed to recess the top surfaces of the gate electrode layer 182 and the gate dielectric layer 180 to a level below the top surface of the gate spacer 138. In some embodiments, the gate spacers 138 are also recessed to a level below the top surface of the ILD layer 164. A self-aligned contact layer 173 is formed over the gate electrode layer 182 and the gate dielectric layer 180 between the gate spacers 138, as shown in FIG. FIG. 27A to FIG. 27B As shown, the self-aligned contact layer 173 may be a dielectric material having an etching selectivity with respect to the ILD layer 164. In some embodiments, the self-aligned contact layer 173 includes silicon nitride.

[0093] Then, a contact opening is formed through the ILD layer 164 and the CESL 162 to expose the epitaxial S / D features 146. A silicide layer 184 is then formed on the S / D epitaxial features 146, and a source / drain (S / D) contact 186 is formed in the contact opening on the silicide layer 184. The S / D contact 186 may include a conductive material, such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The silicide layer 184 may include a metal or metal alloy silicide, and the metal may include a noble metal, a refractory metal, a rare earth metal, an alloy thereof, or a combination thereof. Next, a conductive material is formed in the contact opening and the S / D contact 186 is formed, such as Fig.27A and Fig.27B As shown. The conductive material may be made of a material including one or more of the following: Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. Although not shown, a barrier layer (e.g., TiN, TaN, etc.) may be formed on the sidewalls of the contact opening before forming the S / D contact 186. Then, a planarization process (e.g., CMP) is performed to remove excess deposited contact material and expose the top surface of the gate electrode layer 182.

[0094] Fig.28 An enlarged view of a portion of a semiconductor device structure 100 according to some embodiments is shown. In addition to providing a liner 159-1 (eg, as described above with reference to FIG. 1 ) between the support layer 111' and the substrate 101, Figure 21-1A to Figure 21-2 In addition to the lining discussed in 159), Fig.28 The embodiment shown is substantially similar to Figure 22A-1 Embodiment. In this embodiment, the liner 159-1 covers the entire top surface of the substrate 101 and extends upward to cover the sidewall surface of the bottommost dielectric spacer 144. It can be seen that the top surface of the support layer 111' has a rounded head or a curved (e.g., convex) profile, which contacts the first portion 146-1 of the bottom surface 146b of the epitaxial S / D feature 146. In particular, the top surface of the support layer 111' is disposed at a height higher than the bottom surface of the bottommost first semiconductor layer 106. The support layer 111' has a substantially flat bottom surface in contact with the liner 159-1. The air gap 115 is defined by the second portion 146-2 of the bottom surface 146b of the epitaxial S / D feature 146, the sidewall of the support layer 111', and the liner 159-1.

[0095] Fig.29 1 shows an enlarged view of a portion of a semiconductor device structure 100 according to some embodiments. In addition to the support layer 111 ′ having a curved bottom surface that follows the curved contour of the top surface of the substrate 101, Fig.29 The embodiment shown is substantially similar to Fig.28 In this embodiment, the substrate 101 between adjacent replacement gate structures 190 has a curved (eg, convex) top surface. Fig. 9A ), the top surface of substrate 101 can be etched to form a concave top surface. In some cases, a deposition process is performed to redeposit material (e.g., silicon) on the concave top surface so that the top surface of substrate 101 becomes the convex profile shown. Liner 159-1 and support layer 111' thus follow the convex profile of substrate 101. Similarly, air gap 115 is defined by second portion 146-2 of bottom surface 146b of epitaxial S / D feature 146, sidewalls of support layer 111', and liner 159-1.

[0096] In some embodiments, the top surface 101t of the substrate 101 has a first portion 101-1 and a second portion 101-2 around the first portion 101-1. The first portion 101-1 is a curved surface having a first curvature, and the second portion 101-2 is a curved surface having a second curvature. In some embodiments, the first curvature is different from the second curvature. In some embodiments, the first curvature is opposite to the second curvature. In some embodiments, the first portion 101-1 has a convex surface, and the second portion 101-2 has a concave surface.

[0097] Fig.30 1 shows an enlarged view of a portion of a semiconductor device structure 100 according to some embodiments. In addition to forming a support layer 111' directly on the curved top surface of the substrate 101 without providing a liner 159-1 between the support layer 111' and the substrate 101, Fig.30 The embodiment shown is similar to Fig.29 Embodiment of the invention.

[0098] Fig.31 An enlarged view of a portion of a semiconductor device structure 100 according to some embodiments is shown. In addition to the surface portion of the substrate 101 being further nitrided or oxidized to form a nitrided or oxidized region 141 (as described above with reference to Fig.14 and Figure 14-1 In addition to the process discussed, Fig.31 The embodiment shown is similar to Figure 22A-1 In some embodiments, the nitrided or oxidized region 141 extends radially in the substrate 101 and contacts the bottom surface of the bottommost dielectric spacer 144 and a portion of the bottom surface of the support layer 111 ′. The air gap 115 is defined by a second portion 146 - 2 of the bottom surface 146 b of the epitaxial S / D feature 146 , the sidewalls of the support layer 111 ′, the sidewalls of the dielectric spacer 144, and the nitrided or oxidized region 141 .

[0099] Various embodiments of the present disclosure relate to a nanosheet device structure having a support layer disposed between a substrate and epitaxial source / drain features. The support layer is formed by a bottom-up deposition technique and has a rounded head with a raised profile that helps to induce the formation of an air gap during the formation of the epitaxial source / drain features. The air gap surrounds the lower portion of the support layer at the corner between the substrate and the bottommost dielectric spacer of the nanosheet device structure. The air gap can effectively reduce the capacitance between the epitaxial source / drain features and the gate. Therefore, the device performance is improved.

[0100] One embodiment is a semiconductor device structure. The semiconductor device structure includes: a source / drain (S / D) feature disposed on a substrate and between two adjacent semiconductor layers; a support layer disposed between the S / D feature and the substrate; and a dielectric spacer disposed between and in contact with the semiconductor layer and the substrate, wherein the dielectric spacer, the substrate, the support layer, and the S / D feature define an air gap therebetween.

[0101] Another embodiment is a semiconductor device structure. The semiconductor device structure includes: a plurality of semiconductor layers vertically stacked on a substrate; a gate electrode layer surrounding a portion of each semiconductor layer; a first dielectric spacer disposed between and in contact with two adjacent semiconductor layers; a source / drain (S / D) feature in contact with each of the plurality of semiconductor layers; and a support layer disposed between the substrate and the S / D feature, wherein the S / D feature has a curved bottom surface that contacts a portion of a top surface of the support layer.

[0102] Yet another embodiment is a method for forming a semiconductor device structure. The method includes: depositing a sacrificial gate structure over a portion of a first fin structure and a portion of a second fin structure formed from a substrate, wherein the first fin structure and the second fin structure each include a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked. The method also includes: removing portions of the first fin structure and the second fin structure that are not covered by the sacrificial gate structure to form a recess on the opposite side of the sacrificial gate structure; forming a base layer on a portion of the top surface of the substrate exposed by the recess, wherein the base layer includes a first material. The method also includes: converting the base layer into a support layer by treating the base layer with plasma or free radicals of a substance generated from a second material; forming a source / drain (S / D) layer on the support layer, wherein the S / D layer covers the top of the support layer so that an air gap is formed between the bottom surface of the S / D layer and the top surface of the substrate. The method also includes: removing a plurality of second semiconductor layers to expose a portion of each first semiconductor layer of the first fin structure and the second fin structure; and forming a gate electrode layer to at least surround the exposed portion of the first semiconductor layer of the plurality of first semiconductor layers of the first fin structure and the second fin structure.

[0103] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, comprising: a source / drain (S / D) feature disposed above the substrate and between two adjacent semiconductor layers; a support layer disposed between the S / D features and the substrate; as well as a dielectric spacer disposed between the semiconductor layer and the substrate and in contact with the semiconductor layer and the substrate, Wherein the dielectric spacer, the substrate, the support layer, and the S / D features define an air gap therebetween.

2. The semiconductor device structure according to claim 1, wherein: The support layer has a curved top surface.

3. The semiconductor device structure according to claim 1, wherein: The support layer is disposed between and in contact with the S / D features and the substrate.

4. The semiconductor device structure according to claim 1, further comprising: A lining is disposed on the substrate.

5. The semiconductor device structure according to claim 4, wherein: The liner covers the entire top surface of the substrate.

6. The semiconductor device structure according to claim 5, wherein: The liner further extends to cover sidewalls of the dielectric spacer.

7. The semiconductor device structure according to claim 4, wherein: The support layer is disposed between and in contact with the S / D features and the liner.

8. The semiconductor device structure according to claim 4, wherein: The liner is an oxide or a nitride.

9. A semiconductor device structure, comprising: A plurality of semiconductor layers are vertically stacked on a substrate; a gate electrode layer surrounding a portion of each semiconductor layer; a first dielectric spacer disposed between two adjacent semiconductor layers and in contact with the two adjacent semiconductor layers; a source / drain (S / D) feature in contact with each of the plurality of semiconductor layers; as well as A support layer is disposed between the substrate and the S / D feature, wherein the S / D feature has a curved bottom surface that contacts a portion of a top surface of the support layer.

10. A method for forming a semiconductor device structure, comprising: depositing a sacrificial gate structure over a portion of a first fin structure and a portion of a second fin structure formed from a substrate, wherein the first fin structure and the second fin structure each include a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked; removing portions of the first fin structure and the second fin structure not covered by the sacrificial gate structure to form recesses on opposite sides of the sacrificial gate structure; forming a base layer on a portion of the top surface of the substrate exposed by the recess, wherein the base layer comprises a first material; converting the base layer into a support layer by treating the base layer with plasma or free radicals of a species generated from a second material; forming a source / drain (S / D) layer on the support layer, wherein the S / D layer covers a top portion of the support layer such that an air gap is formed between a bottom surface of the S / D layer and a top surface of the substrate; removing the plurality of second semiconductor layers to expose a portion of each of the first semiconductor layers of the first fin structure and the second fin structure; and A gate electrode layer is formed to surround at least an exposed portion of a first semiconductor layer among the plurality of first semiconductor layers of the first and second fin structures.

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