Solar cell and photovoltaic module

Abstract

The embodiment of the invention relates to the field of solar cells, and provides a solar cell and a photovoltaic module, and the solar cell comprises a substrate, and the surface of the substrate is provided with metal regions and non-metal regions which are alternately arranged; the semiconductor doping layer is located on the surface, corresponding to the metal region, of the substrate, and P-type doping elements are arranged in the semiconductor doping layer; the first tunneling dielectric layer is positioned on the surface of the substrate corresponding to the non-metal region; the first polycrystalline silicon layer is located on the surface of the first tunneling dielectric layer, and aluminum elements are doped in at least part of the first polycrystalline silicon layer; the first passivation layer is located on the surface of the semiconductor doping layer and the surface of the first polycrystalline silicon layer; and the first electrode is located on the surface of the first passivation layer corresponding to the metal region, and the first electrode is electrically connected with the semiconductor doping layer. The solar cell and the photovoltaic module provided by the embodiment of the invention at least can improve the photoelectric conversion efficiency of the cell.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of solar cells, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] At present, with the gradual depletion of fossil energy, solar cells are becoming more and more widely used as a new energy alternative. Solar cells are devices that convert sunlight into electrical energy. Solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0003] The current solar cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact), PERC cells (Passivated emitter and real cell) and heterojunction cells, etc. The photoelectric conversion efficiency of solar cells is improved by reducing optical losses and reducing the recombination of photogenerated carriers on the surface and in the body of the silicon substrate through different film layer settings and functional limitations.

[0004] However, the photoelectric conversion efficiency of current solar cells is still poor. Summary of the invention

[0005] The embodiments of the present application provide a solar cell and a photovoltaic module, which are at least beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0006] According to some embodiments of the present application, on the one hand, an embodiment of the present application provides a solar cell, comprising: a substrate, a surface of the substrate having metal areas and non-metal areas arranged alternately; a semiconductor doping layer, the semiconductor doping layer being located on the surface of the substrate corresponding to the metal area, the semiconductor doping layer having a P-type doping element; a first tunneling dielectric layer, the first tunneling dielectric layer being located on the surface of the substrate corresponding to the non-metal area; a first polycrystalline silicon layer, the first polycrystalline silicon layer being located on the surface of the first tunneling dielectric layer, at least a portion of the first polycrystalline silicon layer being doped with aluminum; a first passivation layer, the first passivation layer being located on the surface of the semiconductor doping layer and the surface of the first polycrystalline silicon layer; a first electrode, the first electrode being located on the surface of the first passivation layer corresponding to the metal area, and the first electrode being electrically connected to the semiconductor doping layer.

[0007] In some embodiments, the first polysilicon layer includes: a first polysilicon portion, the first polysilicon portion is located on a partial surface of the first tunneling dielectric layer, the first polysilicon portion is doped with the aluminum element; a second polysilicon portion, the second polysilicon portion is adjacent to the first polysilicon portion and is located on the remaining surface of the first tunneling dielectric layer, the second polysilicon portion is doped with the P-type doping element, and the concentration of the P-type doping element in the second polysilicon portion is less than or equal to the concentration of the P-type doping element in the semiconductor doping layer.

[0008] In some embodiments, the second polysilicon portion and the first polysilicon portion are alternately arranged along the first direction, and both ends of the first polysilicon portion along the second direction are respectively in contact with two adjacent semiconductor doping layers, and both ends of a portion of the second polysilicon portion are respectively in contact with two adjacent semiconductor doping layers.

[0009] In some embodiments, the second polysilicon portion is located between the semiconductor doping layer and the first polysilicon portion.

[0010] In some embodiments, the first polysilicon portion accounts for greater than or equal to 60% of the area of ​​the first polysilicon layer.

[0011] In some embodiments, the doping concentration of the aluminum element is 1×10 18 cm -3 ~1×10 21 cm -3 .

[0012] In some embodiments, the thickness of the first polysilicon layer is 20 nm to 500 nm.

[0013] In some embodiments, the method further includes: an aluminum oxide layer, wherein the aluminum oxide layer is located on the surface of the first polysilicon layer and between the first polysilicon layer and the first passivation layer.

[0014] In some embodiments, the doping concentration of the aluminum element in the first polysilicon layer decreases along a third direction, where the third direction is a thickness direction of the first polysilicon layer and points to a direction of the substrate.

[0015] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a photovoltaic assembly, including: a battery string, wherein the battery string is composed of a plurality of solar cells as described in any one of the above embodiments; a packaging film for covering the surface of the battery string; and a cover plate for covering the surface of the packaging film facing away from the battery string.

[0016] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0017] In the solar cell provided in the embodiment of the present application, the solar cell has a metal area and a non-metal area respectively, and the substrate surface corresponding to the metal area has a semiconductor doping layer, and the P-type doping element in the semiconductor doping layer can provide more P-type ions, so that it can exist as a PN junction, effectively generate and separate photogenerated carriers, and the electrode is electrically connected to the semiconductor doping layer, so as to have a lower contact resistance and reduce electrical losses; the substrate surface corresponding to the non-metal area has a first tunneling dielectric layer and a first polycrystalline silicon layer. The double passivation effect of the first tunneling dielectric layer and the first polycrystalline silicon layer can effectively reduce the carrier recombination rate of the substrate, thereby improving the photoelectric conversion efficiency. In addition, the first polycrystalline silicon layer is doped with aluminum, and the solid solubility of aluminum in polycrystalline silicon is low, so that it is relatively easy to obtain a first polycrystalline silicon layer with a low doping concentration of aluminum, and the non-metallic area can avoid the recombination loss caused by the high doping concentration. Moreover, the first polycrystalline silicon layer containing aluminum has a good degree of impurity absorption (high minority carrier lifetime), so that the substrate can be better passivated, thereby improving the photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by the figures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A cross-sectional view of a solar cell provided in one embodiment of the present application;

[0020] Figure 2 A top view of a first surface of a solar cell provided in an embodiment of the present application;

[0021] Figure 3 Another top view of the first surface of a solar cell provided in an embodiment of the present application;

[0022] Figure 4 Another top view of the first surface of a solar cell provided in an embodiment of the present application;

[0023] Figure 5 Another cross-sectional view of a solar cell provided in one embodiment of the present application;

[0024] Figures 6 to 12A cross-sectional view of a solar cell corresponding to each step in a method for preparing a solar cell provided in another embodiment of the present application;

[0025] Fig.13 A cross-sectional view of a laminated battery provided in yet another embodiment of the present application;

[0026] Fig.14 A schematic diagram of the structure of a photovoltaic module provided in yet another embodiment of the present application;

[0027] Fig.15 for Fig.14 A cross-section along the M1-M2 section. DETAILED DESCRIPTION

[0028] As can be seen from the background art, the photoelectric conversion efficiency of current solar cells is poor.

[0029] The embodiments of the present application provide a solar cell and a photovoltaic module, wherein a first polysilicon layer doped with aluminum is formed in a non-metallic region of the solar cell to reduce a recombination rate and improve photoelectric conversion efficiency.

[0030] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0031] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0032] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0033] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0034] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0035] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0036] In the drawings corresponding to the embodiments of the present application, the thickness and area of ​​the layers are exaggerated for better understanding and ease of description. When describing a component (such as a layer, film, region or substrate) on another component or on the surface of another component, the component may be "directly" located on the surface of the other component, or a third component may be present between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0037] In the description of the embodiments of the present application, when a component "includes" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may exist in between. In addition, when a component such as a layer, film, region, or plate is "directly located on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located in between.

[0038] The terms used in the description of the various embodiments described herein are only used to describe specific embodiments and are not intended to be limiting. As used in the description of the various embodiments described and in the appended claims, "the part" is also intended to include the plural form unless the context clearly indicates otherwise. Among them, a component includes a layer, a film, a region, or a plate.

[0039] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0040] Figure 1 A cross-sectional view of a solar cell provided in one embodiment of the present application.

[0041] According to some embodiments of the present application, the present application provides a solar cell. Figure 1 The solar cell includes a substrate 100, and the surface of the substrate 100 has metal areas 11 and non-metal areas 12 arranged alternately. The solar cell includes a semiconductor doping layer 112, which is located on the surface of the substrate 100 corresponding to the metal area 11, and the semiconductor doping layer 112 has a P-type doping element. The solar cell includes a first tunneling dielectric layer 121, and the first tunneling dielectric layer 121 is located on the surface of the substrate 100 corresponding to the non-metal area 12. The solar cell includes a first polycrystalline silicon layer 122, and the first polycrystalline silicon layer 122 is located on the surface of the first tunneling dielectric layer 121, and at least part of the first polycrystalline silicon layer 122 is doped with aluminum. The solar cell includes a first passivation layer 105, and the first passivation layer 105 is located on the surface of the semiconductor doping layer 112 and the surface of the first polycrystalline silicon layer 122. The solar cell includes a first electrode 106, and the first electrode 106 is located on the surface of the first passivation layer 105 corresponding to the metal area 11, and the first electrode 106 is electrically connected to the semiconductor doping layer 112.

[0042] In the solar cell provided in the embodiment of the present application, the solar cell has a metal region 11 and a non-metal region 12, respectively, and the surface of the substrate 100 corresponding to the metal region 11 has a semiconductor doping layer 112, and the P-type doping element in the semiconductor doping layer 112 can provide more P-type ions, so that it can exist as a PN junction, effectively generate and separate photogenerated carriers, and the electrode is electrically connected to the semiconductor doping layer 112, so that it has a lower contact resistance and reduces electrical losses; the surface of the substrate 100 corresponding to the non-metal region 12 has a first tunnel dielectric layer 121 and a first polysilicon layer 122. The double passivation effect of the first tunnel dielectric layer 121 and the first polysilicon layer 122 can effectively reduce the carrier recombination rate of the substrate 100, thereby improving the photoelectric conversion efficiency. In addition, the first polysilicon layer 122 is doped with aluminum, and the solid solubility of aluminum in polysilicon is low, so that the first polysilicon layer 122 with a low doping concentration can be obtained more easily, and the non-metallic region 12 can avoid the recombination loss caused by the high doping concentration. Moreover, the first polysilicon layer 122 containing aluminum elements has a good degree of doping (high minority carrier lifetime), so that the substrate 100 can be better passivated, thereby improving the photoelectric conversion efficiency of the battery.

[0043] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be in a single crystalline state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a single crystalline state and an amorphous state is referred to as a microcrystalline state), for example, silicon may be at least one of single crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0044] In some embodiments, the material of the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenide, and the like. The substrate 100 may also be a sapphire substrate 100, a silicon-on-insulator substrate 100, or a germanium-on-insulator substrate 100.

[0045] In some embodiments, the substrate 100 may be an N-type semiconductor substrate. The N-type semiconductor substrate 100 is doped with an N-type doping element, which may be any one of the Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0046] In some embodiments, the substrate 100 has a first surface and a second surface that are arranged opposite to each other. The solar cell is a single-sided cell, the first surface can be used as a light-receiving surface for receiving incident light, and the second surface is used as a backlight surface. Among them, the backlight surface can also receive incident light, but the efficiency of receiving the incident light is weaker than the efficiency of the light-receiving surface receiving the incident light.

[0047] In some embodiments, the metal region 11 refers to the region where the orthographic projection of the first electrode 106 on the substrate 100 is located, and the non-metal region 12 refers to the region other than the orthographic projection of the first electrode 106 on the substrate 100. In order to ensure that the film layer contacted by the first electrode 106 has a relatively high doping concentration or the region contacted by the first electrode 106 is a semiconductor doping layer 112 with a high concentration, the area of ​​the metal region 11 is generally set to be greater than or equal to the area of ​​the orthographic projection of the first electrode 106 on the substrate 100.

[0048] The conductivity type of the doping element doped in the semiconductor doping layer is different from the conductivity type of the doping element in the substrate 100. If the substrate 100 is an N-type substrate, the semiconductor doping layer is doped with a P-type doping element.

[0049] In some embodiments, the semiconductor doping layer 112 is doped with boron, and the solid solubility of boron in semiconductor materials is relatively high. Therefore, the doping concentration of the semiconductor doping layer 112 doped with boron is relatively high, that is, the semiconductor doping layer 112 serves as a local heavily doped region, which can reduce the contact resistance between the first electrode 106 and the semiconductor doping layer 112 and form a good ohmic contact.

[0050] The boron element has a relatively large segregation coefficient in silicon, so the resistivity of the semiconductor doping layer 112 is uniform everywhere, and the resistance value of each region is the same, so that the first electrode 106 can have a higher contact performance when in contact with the semiconductor doping layer 112, thereby reducing electrical losses. Secondly, the boron segregation coefficient in silicon is relatively large, and in the process of preparing the semiconductor doping layer 112, it can be avoided that the concentration of the semiconductor doping layer 112 is low, and then the electric field force of the formed PN junction is weak, the carrier migration rate is low, and the final photoelectric conversion efficiency is affected.

[0051] In some embodiments, the semiconductor doping layer 112 may be doped with other P-type doping elements, such as any one of the III-group elements such as aluminum (Al), gallium (Ga), or indium (In).

[0052] In some embodiments, the semiconductor doping layer 112 and the substrate 100 are the same initial substrate. After the diffusion process, part of the initial substrate serves as the semiconductor doping layer 112, and part of the initial substrate serves as the substrate 100. That is, there is no obvious boundary between the substrate 100 and the semiconductor doping layer 112, but the area formed by the PN junction serves as the distinction, that is, the substrate 100 is the N region, and the semiconductor doping layer 112 is the P region.

[0053] In some embodiments, the semiconductor doping layer 112 is a film layer formed on the substrate 100 through a deposition process or an in-situ formation process, and then formed into a diffusion layer through in-situ doping or diffusion doping.

[0054] The first tunnel dielectric layer 121 and the first polysilicon layer 122 form a passivation contact structure. Due to the special energy band structure of the passivation contact structure, the first polysilicon layer 122 is in electrical contact with the substrate, so that the energy band of the substrate is bent downward, reducing the electron transmission barrier. Therefore, the ultra-thin first tunnel dielectric layer can allow majority carriers (the substrate is an N-type substrate, the first polysilicon layer 122 is a P region, and the majority carriers here are holes) to tunnel while blocking minority carriers (the minority carriers here are electrons) from passing through, thereby separating electrons and holes, reducing recombination, and reducing the recombination rate.

[0055] Specifically, the ultra-thin first tunnel dielectric layer 121 causes an asymmetric shift in the energy band on the surface of the substrate 100, so that the potential barrier to the majority carriers (also known as majority carriers) among the carriers is lower than the potential barrier to the minority carriers (also known as minority carriers) among the carriers. Therefore, the majority carriers can easily perform quantum tunneling through the first tunnel dielectric layer 121, while the minority carriers are difficult to pass through the first tunnel dielectric layer 121 to achieve selective transmission of carriers. Secondly, the first tunnel dielectric layer 121 has a chemical passivation effect. Due to the presence of interface state defects at the interface between the substrate 100 and the first tunnel dielectric layer 121, the interface state density on the surface of the substrate is relatively large. The increase in the interface state density will promote the recombination of photogenerated carriers, increase the fill factor, short-circuit current and open-circuit voltage of the solar cell, and improve the photoelectric conversion efficiency of the solar cell. In other words, the first tunnel dielectric layer 121 reduces the carrier recombination rate by saturating the dangling bonds of the substrate 100, reducing the defect state density of the substrate 100, and reducing the recombination center of the substrate 100.

[0056] In some embodiments, the thickness of the first tunnel dielectric layer 121 is 0.5 nm to 10 nm. The thickness of the first tunnel dielectric layer 121 ranges from 0.5 nm to 1.3 nm, 1.3 nm to 4.6 nm, 4.6 nm to 6.1 nm, or 6.1 nm to 10 nm. When the first tunnel dielectric layer 121 is within any of the above ranges, the thickness of the first tunnel dielectric layer 111 is thinner, and majority carriers can easily perform quantum tunneling through the first tunnel dielectric layer 121, while minority carriers have difficulty passing through the first tunnel dielectric layer 121, so as to achieve selective transmission of carriers.

[0057] In some embodiments, the material of the first tunnel dielectric layer 121 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0058] The first polysilicon layer 122 has a field passivation effect. Specifically, an electrostatic field pointing to the inside of the substrate 100 is formed on the surface of the substrate 100, so that minority carriers escape from the interface, thereby reducing the minority carrier concentration, so that the carrier recombination rate at the interface of the substrate 100 is reduced, thereby increasing the open circuit voltage, short circuit current and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0059] The first polysilicon layer 122 not only acts as a passivation layer to passivate the substrate surface, but also acts as a part of the emitter. The semiconductor doping layer 112 acts as a heavily doped region in the emitter, i.e., a deep junction region, and the first polysilicon layer 122 acts as a lightly doped region in the emitter, i.e., a shallow junction region. The semiconductor doping layer 112 and the first polysilicon layer 122 together constitute a selective emitter (SE). This structure can reduce the contact resistance of the silver aluminum paste and the metal electrode contact area, and at the same time reduce the composite current density of the non-metal electrode contact area, thereby increasing the open circuit voltage and fill factor of the battery, and thus improving the photoelectric conversion efficiency.

[0060] The aluminum element doped in the first polysilicon layer 122 can avoid the problem of light attenuation caused by the boron-oxygen complex formed by the combination of boron and oxygen, thereby increasing the life of the solar cell. The aluminum element is doped in the polysilicon layer, and the solid solubility of the aluminum element in the polysilicon is low, so it is relatively easy to obtain a polysilicon layer with a low doping concentration, and the non-metallic area can avoid the composite loss caused by the high doping concentration. Moreover, the polysilicon layer containing aluminum elements has a good degree of doping (high minority carrier lifetime), so that the substrate can be better passivated, thereby improving the photoelectric conversion efficiency of the battery.

[0061] In some embodiments, the doping concentration of aluminum is 1×10 18 cm -3 ~1×10 21 cm -3 This doping concentration range can form a PN junction between the first polysilicon layer 122 corresponding to the non-metallic region and the substrate 100, thereby generating photogenerated carriers and improving the photoelectric conversion efficiency of the battery; it also makes the doping concentration of the first polysilicon layer 122 lower, thereby having lower parasitic absorption and carrier recombination losses, thereby reducing optical losses.

[0062] In some embodiments, the doping concentration of aluminum element may be 1×10 18 cm -3 , 3×10 18 cm -3 , 6×10 18 cm -3 , 8×10 18 cm -3, 2×10 19 cm -3 , 5×10 19 cm -3 ,9×10 19 cm -3 , 3×10 20 cm -3 , 6×10 20 cm -3 or 1×10 21 cm -3 .

[0063] In some embodiments, the thickness of the first polysilicon layer 122 is 20 nm to 500 nm. The thickness range of the first polysilicon layer 122 can reduce the parasitic absorption of the first polysilicon layer 122, thereby reducing optical loss and improving photoelectric conversion efficiency.

[0064] The thickness of the first polysilicon layer 122 may be 20 nm, 110 nm, 180 nm, 210 nm, 250 nm, 280 nm, 320 nm, 380 nm, 430 nm, or 500 nm.

[0065] Figure 2 A top view of a first surface of a solar cell provided in an embodiment of the present application; Figure 3 Another top view of the first surface of a solar cell provided in an embodiment of the present application; Figure 4 This is another top view of the first surface of a solar cell provided in an embodiment of the present application.

[0066] refer to Figure 2 The first polysilicon layer 122 is located in the non-metallic region 12, and the semiconductor doping layer 112 is located in the metal region 11, and the two are independent of each other to prevent the area contacted by the first electrode 106 from being a lightly doped area.

[0067] It should be noted that although Figure 2 The boundary between the first polysilicon layer 122 and the semiconductor doping layer 112 is obvious, and the first polysilicon layer 122 is only located in the non-metallic area, and the semiconductor doping layer 112 is only located in the metal area. However, in actual operation, the doping elements in the first polysilicon layer 122 may be partially diffused into the semiconductor doping layer 112, and the doping elements in the semiconductor doping layer 112 may be partially diffused into the first polysilicon layer 122, that is, the boundary between the two may not be so clear, which is also the scope protected by the embodiments of the present application; similarly, the first polysilicon layer 122 may extend to the metal area, and the semiconductor doping layer 112 may extend to the non-metallic area, which are also the scope protected by the embodiments of the present application.

[0068] refer to Figure 3 or Figure 4The first polysilicon layer 122 includes: a first polysilicon portion 151, the first polysilicon portion 151 is located on a portion of the surface of the first tunnel dielectric layer, and the first polysilicon portion 151 is doped with aluminum; a second polysilicon portion 152, the second polysilicon portion 152 is adjacent to the first polysilicon portion 151 and is located on the remaining portion of the surface of the first tunnel dielectric layer, and the second polysilicon portion 152 is doped with a P-type doping element, and the concentration of the P-type doping element in the second polysilicon portion 152 is less than or equal to the concentration of the P-type doping element in the semiconductor doping layer 112. The first polysilicon portion 151 is used to improve the passivation effect, and the second polysilicon portion 152 is used to improve the carrier transmission capacity. In this way, the first polysilicon layer 122 corresponding to the non-metallic area can generate photogenerated carriers, transport the carriers through the second polysilicon portion 152, and then be collected by the first electrode, which can improve the photoelectric conversion efficiency of the battery.

[0069] In some embodiments, reference Figure 3 The second polysilicon portion 152 is located between the semiconductor doping layer 112 and the first polysilicon portion 151. The first polysilicon portion 151 and the second polysilicon portion 152 are arranged so that the second polysilicon portion 152 serves as an intermediate layer of two different doping concentrations so that there is no large crossing platform for carrier migration.

[0070] In some embodiments, reference Figure 4 , the second polysilicon portion 152 and the first polysilicon portion 151 are alternately arranged along the first direction Y, and the two ends of the first polysilicon portion 151 along the second direction X are respectively in contact with two adjacent semiconductor doping layers 112, and the two ends of part of the second polysilicon portion 152 are respectively in contact with two adjacent semiconductor doping layers 112. The arrangement of the first polysilicon portion 151 and the second polysilicon portion 152, and the second polysilicon portion 152 in contact with the semiconductor doping layer 112, serve as a lateral transmission channel.

[0071] refer to Figure 3 or Figure 4 , the first polysilicon portion 151 accounts for more than or equal to 60% of the area of ​​the first polysilicon layer 122. In this way, the content of doping elements that require high temperature activity is reduced, so as to reduce the time required for high temperature activation of the solar cell, thereby reducing the thermal damage to the cell; the first polysilicon portion 151 accounts for a large area of ​​the first polysilicon layer 122, that is, the proportion of the low-doping area corresponding to the non-metallic area is large, which can reduce the recombination rate of the non-metallic area, thereby improving the passivation effect and the photoelectric conversion efficiency of the cell.

[0072] Continue to refer Figure 1 The first passivation layer 105 covers the surface of the first polysilicon layer 122 and the surface of the semiconductor doping layer 112 .

[0073] In some embodiments, the first passivation layer 105 may be a single-layer structure or a stacked-layer structure, and the material of the first passivation layer 105 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, titanium oxide, hafnium oxide or aluminum oxide.

[0074] Figure 5 Another cross-sectional view of a solar cell provided in one embodiment of the present application.

[0075] refer to Figure 5 In some other embodiments, the solar cell further includes: an aluminum oxide layer 123, the aluminum oxide layer 123 is located on the surface of the first polysilicon layer 122, and is located between the first polysilicon layer 122 and the first passivation layer 105. The aluminum oxide layer 123 can be used as a passivation layer, which can passivate the first polysilicon layer 122, thereby reducing the recombination rate of the first polysilicon layer 122; the aluminum oxide layer can also be used as a fixed negative charge layer to increase the electric field effect of the first polysilicon layer 122 and promote the migration of carriers to the P region.

[0076] In some embodiments, the doping concentration of the aluminum element of the first polysilicon layer 122 decreases along the third direction, and the third direction is the thickness direction of the first polysilicon layer 122 and points to the direction of the substrate. The polysilicon layer is formed by using the AIC (aluminum-induced crystallization) process. The closer to the substrate, the greater the concentration of the aluminum element, the better the passivation effect of the formed first polysilicon layer 122, and this process realizes the activation of the aluminum element at a lower temperature, which can shorten the heat treatment time of the solar cell.

[0077] Continue to refer Figure 1 , the first electrode 106 serves as an electrode for collecting carriers. The first electrode 106 can be formed by sintering a burn-through paste. The method for forming the first electrode 106 includes: printing a metal paste on a surface of a portion of the anti-reflection layer using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel. Then, the metal paste is subjected to a sintering process, and the metal paste contains a material with highly corrosive components such as glass powder. In this way, during the sintering process, the corrosive components will corrode the first passivation layer 105, so that the metal paste penetrates into the first passivation layer 105 and makes electrical contact with the semiconductor doping layer 112.

[0078] In some embodiments, the first electrode 106 may be sintered from LECO (Laser-enhanced contact optimization) slurry, and part of the LECO slurry corrodes and penetrates into the first passivation layer 105 and contacts the semiconductor doping layer 112 or forms an electrical connection with the semiconductor doping layer 112 through crystals.

[0079] It should be noted that the substrate includes a first surface and a second surface, and the above-mentioned film layers are located on the first surface or the second surface of the substrate. The embodiment of the present application takes the first surface as the front surface, the second surface as the back surface, the above-mentioned film layers are located on the first surface, and the first electrode is a front electrode as an example. The first surface is not described as the back surface, the second surface is the front surface, the above-mentioned film layers are located on the first surface, and the first electrode is the back electrode, which is also within the scope of the embodiment of the present application.

[0080] In the solar cell provided in the embodiment of the present application, the thickness relationship between the semiconductor doping layer 112 and the thickness relationship between the first polysilicon layer 122 located in the non-metallic region and which one has a higher top surface than the other can be set according to actual needs. Figure 1 and Figure 2 The relationships shown are merely examples and do not constitute limiting relationships.

[0081] In some embodiments, the first surface of the substrate has a velvet structure 111, and the velvet structure 111 includes a plurality of protrusion structures 101. The inclined surfaces of the protrusion structures 101 can increase the internal reflection of the incident light, thereby improving the utilization rate of the incident light and improving the photoelectric conversion efficiency.

[0082] Continue to refer Figure 1 The solar cell further includes: a second tunneling dielectric layer 131, the second tunneling dielectric layer 131 is located on the second surface of the substrate 100; a doped semiconductor layer 132, the doped semiconductor layer 132 is located on the surface of the second tunneling dielectric layer 131; a second passivation layer 115, the second passivation layer 115 is located on the surface of the doped semiconductor layer 132; a second electrode 116, the second electrode 116 is located on the surface of the second passivation layer 115, and the second electrode 116 is electrically connected to the doped semiconductor layer 132.

[0083] It should be noted that the content of the second tunnel dielectric layer 132 may refer to the content of the first tunnel dielectric layer 121 , which will not be described in detail here.

[0084] The doped semiconductor layer 132 has a field passivation effect. Specifically, an electrostatic field pointing to the inside of the substrate 100 is formed on the surface of the substrate 100, so that minority carriers escape from the interface, thereby reducing the minority carrier concentration, so that the carrier recombination rate at the interface of the substrate 100 is reduced, thereby increasing the open circuit voltage, short circuit current and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0085] In some embodiments, the substrate 100 is doped with N-type doping elements, and the doping elements in the doped semiconductor layer 132 have the same conductivity type as the doping elements in the substrate 100 , that is, the doped semiconductor layer 132 is doped with N-type doping elements.

[0086] The concentration of doping elements in the doped semiconductor layer 132 is greater than the concentration of doping elements in the substrate 100, and a high-low junction is formed between the doped semiconductor layer 132 and the substrate 100. Under the electric field formed by the high-low junction, a sufficiently high potential barrier can be formed on the surface of the substrate 100, so that majority carriers in the substrate 100 can pass through the second tunneling dielectric layer 131 to the doped semiconductor layer 132, which is beneficial to improving carrier mobility.

[0087] In some embodiments, the doped semiconductor layer 132 includes at least one of a doped amorphous silicon layer, a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, or a doped silicon carbide layer.

[0088] In some embodiments, the second passivation layer 115 may be a single-layer structure or a stacked-layer structure, and the material of the second passivation layer 115 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, titanium oxide, hafnium oxide or aluminum oxide.

[0089] In some embodiments, the second electrode 116 can be formed by sintering a burn-through paste. The method for forming the second electrode 116 includes: printing a metal paste on a portion of the back passivation layer surface using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel. Then, the metal paste is subjected to a sintering process, and the metal paste contains a material with a highly corrosive component such as glass powder. In this way, during the sintering process, the corrosive component will corrode the second passivation layer 115, so that the metal paste penetrates into the second passivation layer 115 and is in electrical contact with the doped semiconductor layer 132.

[0090] In some embodiments, the second electrode 116 may be formed by sintering LECO slurry, and a portion of the LECO slurry corrodes the second passivation layer 115 to contact the doped semiconductor layer 132 or to form an electrical connection with the doped semiconductor layer 132 through crystals.

[0091] In the solar cell provided in the embodiment of the present application, the solar cell has a metal region 11 and a non-metal region 12 respectively, and the surface of the substrate 100 corresponding to the metal region 11 has a semiconductor doping layer 112, and the P-type doping element in the semiconductor doping layer 112 can provide more P-type ions, so that it can exist as a PN junction, effectively generate and separate photogenerated carriers, and the electrode is electrically connected to the semiconductor doping layer 112, so that it has a lower contact resistance and reduces electrical losses; the surface of the substrate 100 corresponding to the non-metal region 12 has a first tunnel dielectric layer 121 and a first polysilicon layer 122. The double passivation effect of the first tunnel dielectric layer 121 and the first polysilicon layer 122 can effectively reduce the carrier recombination rate of the substrate 100, thereby improving the photoelectric conversion efficiency. In addition, the first polysilicon layer 122 is doped with aluminum, and the solid solubility of aluminum in polysilicon is low, so that the first polysilicon layer 122 with a low doping concentration of aluminum can be obtained more easily, and the non-metallic region 12 can avoid the recombination loss caused by the high doping concentration. Moreover, the first polysilicon layer 122 containing aluminum elements has a good degree of doping (high minority carrier lifetime), so that the substrate 100 can be better passivated, thereby improving the photoelectric conversion efficiency of the battery.

[0092] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a method for preparing a solar cell, which is used to prepare the solar cell provided by the above embodiments. The technical features that are the same or corresponding to the above embodiments will not be described in detail here.

[0093] Figures 6 to 12 A cross-sectional view of a solar cell corresponding to each step in a method for preparing a solar cell provided in another embodiment of the present application.

[0094] refer to Figure 6 , providing an initial substrate 107.

[0095] refer to Figure 7 , a velvet treatment is performed on one side of the initial substrate 107 so that one side of the initial substrate 107 has a velvet structure 111. The velvet structure 111 includes a plurality of first protruding structures 101. The surface of the initial substrate has metal areas and non-metal areas arranged alternately, and the surfaces of the metal areas and the non-metal areas both have the velvet structure 111.

[0096] In some embodiments, the texturing process includes: chemical etching, for example, a mixed solution of potassium hydroxide and hydrogen peroxide solution can be used to clean the initial substrate 107, and the suede structure with the expected morphology can be formed by controlling the concentration ratio of potassium hydroxide and hydrogen peroxide solution. In some embodiments, the suede structure can also be formed by laser etching, mechanical method or plasma etching. In laser etching, the suede structure with the expected morphology is obtained by controlling the laser process parameters.

[0097] refer to Figure 8 and Fig. 9 The preparation method includes forming a semiconductor doping layer 112, the semiconductor doping layer 112 is located on the substrate surface corresponding to the metal area, and the semiconductor doping layer 112 has a P-type doping element.

[0098] refer to Figure 8 The diffusion layer 102 is formed by high temperature diffusion or ion implantation. The initial substrate 100 of a partial thickness is diffused to form the diffusion layer 102.

[0099] refer to Fig. 9 A diffusion layer is formed on the surface of the diffusion layer corresponding to the metal area, and the diffusion layer corresponding to the non-metal area is removed, and the remaining diffusion layer serves as the semiconductor doping layer 112.

[0100] Before removing the diffusion layer corresponding to the non-metallic region, a mask layer 104 is formed on the diffusion layer corresponding to the metal region.

[0101] refer to Fig.10 The preparation method includes: forming a first tunneling dielectric layer 121 , wherein the first tunneling dielectric layer 121 is located on a surface of the substrate 100 corresponding to the non-metallic region 12 .

[0102] The first tunnel dielectric layer 121 is formed by an oxidation process, a heat treatment process or a deposition process.

[0103] It should be noted that if the first tunnel dielectric layer is formed by an oxidation process or a heat treatment process, there is no first tunnel dielectric layer on the mask layer. If the first tunnel dielectric layer is formed by a deposition process, there is a first tunnel dielectric layer on the mask layer, but it is not formed on the mask layer. Fig.10 Shown in.

[0104] refer to Figures 10 to 12 The preparation method includes: forming a first polysilicon layer 122, the first polysilicon layer 122 is located on the surface of the first tunnel dielectric layer, and at least a portion of the first polysilicon layer 122 is doped with aluminum.

[0105] There are two methods for forming the first polysilicon layer 122 , which will be described in detail below with reference to the relevant drawings.

[0106] The first one: using diffusion process.

[0107] refer to Fig.10 , forming a semiconductor film 113, which is an intrinsic polycrystalline silicon film. Fig.12 , an ion implantation process is performed on the semiconductor film 113 to transform the intrinsic polysilicon film into a first polysilicon layer 122 doped with aluminum.

[0108] Since the aluminum element does not require a high-temperature activation process, that is, no subsequent high-temperature activation step is required, the number of high-temperature treatments of the solar cell is reduced, reducing the thermal damage to the solar cell.

[0109] In other embodiments, reference Fig.10 , forming a semiconductor film 113, which is an intrinsic polycrystalline silicon film. Fig.11 , forming a doping source layer 114, wherein the doping source layer 114 contains aluminum elements; Fig.12 , a laser doping process is performed on the semiconductor film 113 to diffuse the aluminum element in the doping source layer 114 into the intrinsic polysilicon film, so that the intrinsic polysilicon film is converted into a first polysilicon layer 122 doped with aluminum element.

[0110] The second method uses the AIC process.

[0111] refer to Fig.10 , forming a semiconductor film 113, which is an intrinsic amorphous silicon (a-Si) film. Fig.11 , forming a doping source layer 114, wherein the doping source layer 114 is an aluminum layer; Fig.12 , the semiconductor film is subjected to a low temperature induction process, and Al atoms diffuse into a-Si through the Al / a-Si interface, so that the Si-Si covalent bond is transformed into a Si-Al metallic bond. The silicide formed near the interface further accelerates the mutual diffusion between Al atoms and Si atoms, resulting in the formation of a Si-Al mixed phase. Since the solid solubility of Si in Al is almost negligible at low temperatures, the supersaturated Si in Al will precipitate and nucleate from the interface of Al / a-Si, and the crystal nucleus will gradually grow and finally form polycrystalline silicon. While the supersaturated Si precipitates from the Si-Al mixed phase in the form of nuclei, the remaining Al atoms tend to move to the surface of the sample and eventually precipitate all on the top layer. That is, the intrinsic polycrystalline silicon film is converted into a first polycrystalline silicon layer 122 doped with aluminum elements.

[0112] The polysilicon layer prepared by the AIC process has a thinner thickness and a lower annealing temperature. The crystallized polysilicon layer has a high degree of crystallization and good crystal orientation. That is, the prepared first polysilicon layer 122 has fewer physical defects.

[0113] In some embodiments, after forming the first polysilicon layer 122 , the aluminum layer on the surface may be removed; or the aluminum layer on the surface may be oxidized to form an aluminum oxide layer.

[0114] refer to Figure 1The preparation method includes: forming a first passivation layer 105, the first passivation layer 105 is located on the surface of the semiconductor doping layer 112 and the surface of the first polysilicon layer 122. The preparation method includes: forming a first electrode 106, the first electrode 106 is located on the surface of the first passivation layer 105 corresponding to the metal area 11, and the first electrode 106 is electrically connected to the semiconductor doping layer 112.

[0115] Continue to refer Figure 1 The preparation method includes: forming a second tunneling dielectric layer 131, the second tunneling dielectric layer 131 is located on the second surface of the substrate 100; forming a doped semiconductor layer 132, the doped semiconductor layer 132 is located on the surface of the second tunneling dielectric layer 131; forming a second passivation layer 115, the second passivation layer 115 is located on the surface of the doped semiconductor layer 132; forming a second electrode 116, the second electrode 116 is located on the surface of the second passivation layer 115, and the second electrode 116 is electrically connected to the doped semiconductor layer 132.

[0116] The method for preparing a solar cell provided in the embodiment of the present application forms the first polysilicon layer 122 through a diffusion process and an AIC process, thereby avoiding a high-temperature activation step and reducing the preparation cost.

[0117] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a stacked battery.

[0118] Fig.13 A cross-sectional view of a stacked battery provided in yet another embodiment of the present application.

[0119] refer to Fig.13 The stacked battery includes: a bottom battery 150, which is a solar cell as in any one of the above embodiments or a solar cell prepared by the preparation method as in any one of the above embodiments; a top battery 180, which is located on a side of the substrate 100 in the bottom battery 150 away from the first electrode 106.

[0120] In some embodiments, the stacked battery has a first gridline 186 of a first polarity and a second gridline of a second polarity, wherein the first gridline 186 is in electrical contact with the top battery 180 and the second gridline is in electrical contact with the bottom battery 150. The second gridline is the first electrode 106 of the bottom battery.

[0121] In some embodiments, an interface layer 181 is provided between the top cell and the bottom cell, and the interface layer 181 also covers the passivation contact structure on the back side, that is, covers the doped conductive layer 132 .

[0122] It is worth noting that the stacked cell in the embodiment of the present application only illustrates two layers of solar cells, and those skilled in the art can set three layers of solar cells or more than three layers of stacked solar cells according to actual needs.

[0123] In some embodiments, the top cell 180 may be a perovskite solar cell, which includes: a stacked first transmission layer 182, a perovskite substrate 183, a second transmission layer 184, a transparent conductive layer 185, and an anti-reflection layer (not shown), wherein the first transmission layer is opposite to the bottom cell.

[0124] In some embodiments, the first transport layer may be one of an electron transport layer and a hole transport layer, and the second transport layer may be the other of the electron transport layer and the hole transport layer.

[0125] Accordingly, according to some embodiments of the present application, the embodiments of the present application further provide a photovoltaic module, including the solar cell provided in the above embodiments, and the technical features that are the same as or corresponding to the above embodiments are not described in detail here.

[0126] Fig.14 A schematic diagram of the structure of a photovoltaic module provided in yet another embodiment of the present application; Fig.15 for Fig.14 A cross-section along the M1-M2 section.

[0127] refer to Fig.14 and Fig.15 The photovoltaic module includes: a battery string, the battery string is composed of a plurality of solar cells 20 as in any one of the above embodiments; a packaging film 21, used to cover the surface of the battery string; a cover plate 22, used to cover the surface of the packaging film 21 away from the battery string.

[0128] Specifically, in some embodiments, multiple cells can be electrically connected through a connecting member 218, and the connecting member 218 is welded to a main grid on the cell. The main grid includes a main electrode electrically connected to the first electrode 106 and a main electrode electrically connected to the second electrode 116.

[0129] In some embodiments, no intervals are set between the battery cells, that is, the battery cells overlap each other.

[0130] In some embodiments, the connection component 218 is welded to the secondary grid 208 on the solar cell, and the secondary grid 208 includes the first electrode 106 and the second electrode 116 .

[0131] In some embodiments, the encapsulation film 21 includes a first encapsulation layer and a second encapsulation layer, the first encapsulation layer covers one of the front side or the back side of the solar cell, and the second encapsulation layer covers the other of the front side or the back side of the solar cell. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as a polyvinyl butyral (PVB) film, an ethylene-vinyl acetate copolymer (EVA) film, a polyethylene octene co-elastomer (POE) film or a polyethylene terephthalate (PET) film.

[0132] It is worth noting that there is a boundary line between the first encapsulation layer and the second encapsulation layer before lamination. After lamination, the photovoltaic module is no longer a first encapsulation layer and a second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 21.

[0133] In some embodiments, the cover plate 22 may be a glass cover plate, a plastic cover plate or the like with a light-transmitting function. Specifically, the surface of the cover plate 22 facing the encapsulation film 21 may be a concave-convex surface, thereby increasing the utilization rate of the incident light. The cover plate 22 includes a first cover plate and a second cover plate, the first cover plate is opposite to the first encapsulation layer, and the second cover plate is opposite to the second encapsulation layer; or the first cover plate is opposite to one side of the solar cell, and the second cover plate is opposite to the other side of the solar cell.

[0134] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application, and therefore the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A solar cell, It is characterized in that include: A substrate, wherein the surface of the substrate has metal areas and non-metal areas arranged alternately; A semiconductor doping layer, the semiconductor doping layer is located on the surface of the substrate corresponding to the metal region, and the semiconductor doping layer contains a P-type doping element; A first tunneling dielectric layer, wherein the first tunneling dielectric layer is located on a surface of the substrate corresponding to the non-metallic region; a first polysilicon layer, wherein the first polysilicon layer is located on a surface of the first tunnel dielectric layer, and at least a portion of the first polysilicon layer is doped with aluminum; a first passivation layer, the first passivation layer being located on a surface of the semiconductor doping layer and a surface of the first polysilicon layer; A first electrode is located on a surface of the first passivation layer corresponding to the metal region, and the first electrode is electrically connected to the semiconductor doping layer.

2. The solar cell according to claim 1, It is characterized in that The first polysilicon layer comprises: a first polysilicon portion, the first polysilicon portion being located on a partial surface of the first tunnel dielectric layer, the first polysilicon portion being doped with the aluminum element; A second polysilicon portion, wherein the second polysilicon portion is adjacent to the first polysilicon portion and is located on the surface of the remaining portion of the first tunneling dielectric layer, the second polysilicon portion is doped with the P-type doping element, and the concentration of the P-type doping element in the second polysilicon portion is less than or equal to the concentration of the P-type doping element in the semiconductor doping layer.

3. The solar cell according to claim 2, It is characterized in that The second polysilicon portion and the first polysilicon portion are alternately arranged along the first direction, and both ends of the first polysilicon portion along the second direction are respectively in contact with the two adjacent semiconductor doping layers, and both ends of a portion of the second polysilicon portion are respectively in contact with the two adjacent semiconductor doping layers.

4. The solar cell according to claim 2, It is characterized in that The second polysilicon portion is located between the semiconductor doping layer and the first polysilicon portion.

5. The solar cell according to claim 2, It is characterized in that The first polysilicon portion accounts for greater than or equal to 60% of the area of ​​the first polysilicon layer.

6. The solar cell according to claim 1, It is characterized in that The doping concentration of the aluminum element is 1×10 18 cm -3 ~1×10 21 cm -3 .

7. The solar cell according to claim 1, It is characterized in that The thickness of the first polysilicon layer is 20 nm to 500 nm.

8. The solar cell according to claim 1, It is characterized in that Also includes: An aluminum oxide layer is located on a surface of the first polysilicon layer and between the first polysilicon layer and the first passivation layer.

9. The solar cell according to claim 1, It is characterized in that The doping concentration of the aluminum element in the first polysilicon layer decreases along a third direction, and the third direction is a thickness direction of the first polysilicon layer and points to a direction of the substrate.

10. A photovoltaic module, It is characterized in that include: A battery string, the battery string being composed of a plurality of solar cells as claimed in any one of claims 1 to 9; A packaging film, used to cover the surface of the battery string; The cover plate is used to cover the surface of the packaging film facing away from the battery string.

Images