Solar cell, assembly and system

Abstract

The invention discloses a solar cell, an assembly and a system. The solar cell includes: a silicon substrate; the homojunction is located in the silicon substrate and extends inwards from the first surface and / or the second surface of the silicon substrate, the surface doping concentration of the homojunction is 1 * 10 < 15 > cm <-3 >-1 * 10 < 19 > cm <-3 >, and the junction depth of the homojunction is larger than or equal to 100 nm and smaller than or equal to the thickness of the silicon substrate; the heterojunction is located on the surface of the side, provided with the homojunction, of the silicon substrate; the heterojunction comprises a passivation selective contact structure, the passivation selective contact structure comprises a passivation layer and a selective transmission layer which are sequentially stacked on the surface of the homojunction, and the selective transmission layer comprises a hole selective transmission layer and / or an electron selective transmission layer; or the heterojunction comprises an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure comprises an intrinsic amorphous silicon layer and a doped semiconductor layer which are sequentially stacked on the surface of the homojunction. The solar cell provided by the invention has relatively high conversion efficiency.

Description

Technical Field

[0001] The present invention generally relates to the technical field of solar cells, and in particular to a solar cell, a component and a system. Background Art

[0002] For heterojunction technology, taking silicon-based heterojunction (SHJ) cells as an example, the use of heterojunctions can isolate the crystalline silicon substrate and metal, significantly reducing metal recombination losses. Heterogeneous emitters with high doping concentrations help to form strong built-in electric fields and low contact resistance. The strong built-in electric field determines that the heterojunction has a high passivation contact selectivity coefficient, which is conducive to achieving high open circuit voltage and fill factor. However, the free carrier absorption and narrow optical band gap caused by the high doping concentration make optical parasitic absorption losses unavoidable. Selective passivation contact technology uses an electron selection layer or a hole selection layer structure to replace the original doped amorphous silicon emitter to effectively reduce the optical parasitic absorption losses caused by doped amorphous silicon, but the current traditional selective passivation contact technology has the problem of poor passivation and transmission performance, that is, low selectivity, resulting in poor open circuit voltage and fill factor. The emergence of these problems is related to the fact that the new selective materials themselves do not have good chemical passivation and high resistivity. In addition, compared with the advantage of a homojunction that can form a deeper junction depth, the electric field formed entirely by a heterojunction also has the problem of a smaller field passivation influence depth on a silicon substrate with a higher doping concentration.

[0003] For homojunction technology, taking PERC and TOPCon front pn junction as examples, the most ideal homojunction emitter doping is heavy doping junction depth. Heavy doping can effectively reduce contact resistance, increase FF, enhance the built-in electric field and obtain a higher V OC However, the heavy doping increases the probability of Auger recombination, shortens the lifetime of photogenerated carriers, and reduces V OC In addition, the shallow junction depth is not conducive to the separation and collection of photogenerated carriers deep in the silicon substrate, and also affects V OC and FF.

[0004] Therefore, it is of great significance to combine the advantages of homojunction and heterojunction to improve the photoelectric conversion efficiency of solar cells. Summary of the invention

[0005] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a solar cell, component and system that can utilize the advantages of the high doping concentration of the heterojunction to form a strong built-in electric field, and while reducing the metal contact resistance, introduce a homojunction with a lower doping concentration and a deeper junction depth, thereby enhancing the ability of carrier separation and extraction inside the silicon substrate, thereby improving the photoelectric conversion efficiency of the solar cell.

[0006] In a first aspect, the present invention provides a solar cell, comprising: Silicon substrate; The homojunction is located in the silicon substrate and extends inward from the first surface and / or the second surface of the silicon substrate. The surface doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100nm and less than or equal to the thickness of the silicon substrate; and a heterojunction, the heterojunction being located on the surface of the silicon substrate on the side where the homojunction is provided; The heterojunction includes a passivation selective contact structure, the passivation selective contact structure includes a passivation layer and a selective transport layer sequentially stacked on the surface of the homojunction, and the selective transport layer includes a hole selective transport layer and / or an electron selective transport layer; And / or, the heterojunction includes an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer sequentially stacked on a homojunction surface.

[0007] As an optional solution, the passivation selective contact structure and the amorphous silicon heterojunction are located in different regions of the same surface of the silicon substrate, or the passivation selective contact structure and the amorphous silicon heterojunction are located on different side surfaces of the silicon substrate.

[0008] As an alternative, the doping concentration of the homojunction is 1×10 16 cm -3 ~5×10 18 cm -3 .

[0009] As an optional solution, the junction depth of the homojunction is 300nm~2000nm.

[0010] As an optional solution, the hole selective transport layer includes a hole selective layer, or a hole selective layer and a hole transport layer facing away from the surface of the silicon substrate, or a hole selective layer and an electron transport layer facing away from the surface of the silicon substrate; The electron selective transport layer includes an electron selective layer, or an electron selective layer and an electron transport layer facing away from the surface of the silicon substrate, or an electron selective layer and a hole transport layer facing away from the surface of the silicon substrate.

[0011] As an optional solution, based on the projection on the surface of the silicon substrate, the projection of the selective transmission layer is located within the projection range of the homojunction; or the projection of the intrinsic amorphous silicon layer is located within the projection range of the homojunction.

[0012] As an optional solution, the solar cell further includes a metal electrode, and based on the projection on the surface of the silicon substrate, the projection of the metal electrode is within the projection range of the selective transmission layer; or the projection of the metal electrode is within the projection range of the intrinsic amorphous silicon layer.

[0013] As an optional solution, the metal electrode includes a first metal electrode and a second metal electrode, and the solar cell further includes: A passivation anti-reflection layer is located on the silicon substrate and the selective transmission layer; one of the first metal electrode and the second metal electrode passes through the passivation anti-reflection layer and contacts the selective transmission layer; Or, a second transmission layer is located on the doped semiconductor layer; one of the first metal electrode and the second metal electrode is in contact with the second transmission layer.

[0014] As an optional solution, the homojunction is located in the first surface of the silicon substrate, and the passivation layer and the selective transmission layer are sequentially stacked on the first surface; The second surface of the silicon substrate comprises a second intrinsic amorphous silicon layer and a second doped semiconductor layer which are stacked in sequence and are away from the surface of the silicon substrate.

[0015] As an optional solution, the homojunction is located in the first surface of the silicon substrate, and the intrinsic amorphous silicon layer and the doped semiconductor layer are sequentially stacked on the first surface; The second surface of the silicon substrate includes a third intrinsic amorphous silicon layer and a third doped semiconductor layer which are stacked in sequence away from the silicon substrate.

[0016] As an optional solution, the homojunction is located in the first surface of the silicon substrate, and the passivation layer and the selective transmission layer are located on the first surface; The second surface of the silicon substrate includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence away from the silicon substrate.

[0017] As an optional solution, the homojunction is located in the first surface, and the intrinsic amorphous silicon layer and the doped semiconductor layer are located on the first surface; The second surface includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence and are away from the silicon substrate.

[0018] As an optional solution, the back side of the silicon substrate includes a plurality of first regions and a plurality of second regions which are spaced apart from each other; A homojunction is located within the surface of the first region, and a passivation layer and a selective transport layer are located on the surface of the first region; The surface of the second region includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence and are away from the surface of the second region.

[0019] As an optional solution, the homojunction is located in the surfaces of the first region and the second region, and the passivation layer and the selective transmission layer are located on the surface of the first region; and an intrinsic amorphous silicon layer and a doped semiconductor layer located on the surface of the second region.

[0020] As an optional solution, the back side of the silicon substrate includes a plurality of first regions and a plurality of second regions which are spaced apart from each other; A homojunction is located in the surface of the first region, and an intrinsic amorphous silicon layer and a doped semiconductor layer are located on the surface of the first region; The surface of the second region includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence and are away from the surface of the second region.

[0021] In a second aspect, the present invention provides a method for preparing a solar cell, comprising the following steps: Pre-depositing a doping source layer on the surface of the silicon substrate, the doping source layer comprising a first pre-doping layer and PSG formed on the surface of the silicon substrate, or a second pre-doping layer and BSG formed; Removing PSG or BSG from the surface of the silicon substrate; A homojunction is formed on the surface of the silicon substrate by means of a finite source; the doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100nm and less than or equal to the thickness of the silicon substrate; forming a heterojunction on a surface of the silicon substrate on which the homojunction is provided; The heterojunction includes a passivation selective contact structure, the passivation selective contact structure includes a passivation layer and a selective transport layer sequentially stacked on the surface of the homojunction, and the selective transport layer includes a hole selective transport layer and / or an electron selective transport layer; And / or, the heterojunction includes an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer sequentially stacked on a homojunction surface.

[0022] In a third aspect, a method for preparing a solar cell comprises the following steps: A tunnel dielectric layer and a doped polysilicon layer are sequentially prepared on the surface of a silicon substrate to form an inner expansion layer on the silicon substrate; removing the doped polysilicon layer; The inner diffusion layer is diffused into the silicon substrate surface to form a homojunction with a doping concentration of 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100nm and less than or equal to the thickness of the silicon substrate; forming a heterojunction on a surface of the silicon substrate on which the homojunction is provided; The heterojunction includes a passivation selective contact structure, the passivation selective contact structure includes a passivation layer and a selective transport layer sequentially stacked on the surface of the homojunction, and the selective transport layer includes a hole selective transport layer and / or an electron selective transport layer; And / or, the heterojunction includes an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer sequentially stacked on a homojunction surface.

[0023] In a fourth aspect, the present invention provides a solar cell assembly, comprising a solar cell according to the first aspect.

[0024] In a fifth aspect, the present invention provides a solar cell system, comprising a solar cell assembly according to the fourth aspect.

[0025] The solar cell of the present invention uses a specially designed homojunction superimposed heterojunction technology. By setting a homojunction, the doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100nm and less than or equal to the thickness of the silicon substrate; and the homojunction is combined with a selective passivation contact structure or an amorphous amorphous silicon heterojunction structure. On the one hand, the introduction of a heterojunction is conducive to the formation of a strong built-in electric field and reduces the metal contact resistance. The highly doped heterogeneous emitter or selective transmission layer isolates the silicon substrate from the metal, which is conducive to the formation of a strong built-in electric field while suppressing contact recombination and reducing contact resistance. On the other hand, the introduction of a homojunction with a lower doping concentration and a deeper junction depth helps to enhance the ability of carrier separation and extraction inside the silicon substrate. A lower doping concentration is conducive to reducing Auger recombination losses. Therefore, the special design of the present invention helps to make full use of the advantages of homojunctions and heterojunctions and improve the photoelectric conversion efficiency of solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 A schematic diagram of the structure on one side of a silicon substrate in a solar cell according to an embodiment of the present invention; Figure 2 A schematic diagram of the structure on one side of a silicon substrate in another solar cell according to an embodiment of the present invention; Figure 3 is a schematic structural diagram of a solar cell according to Example 1; Figure 4 is a schematic structural diagram of a solar cell according to Example 2; Figure 5 is a schematic structural diagram of a solar cell according to Example 3; Figure 6 is a schematic structural diagram of a solar cell according to Example 4; Figure 7 is a schematic structural diagram of a solar cell according to Example 5; Figure 8 is a schematic structural diagram of a solar cell according to Example 6; Fig. 9 is a schematic structural diagram of a solar cell according to Example 7; Fig.10 is a schematic structural diagram of a solar cell according to Example 8; Fig.11 is a schematic structural diagram of a solar cell according to Example 9; Fig.12 is a schematic structural diagram of a solar cell according to Example 10; Fig.13 is a schematic structural diagram of a solar cell according to Example 11; Fig.14 is a schematic structural diagram of a solar cell according to Example 12; Fig.15 is a schematic structural diagram of a solar cell according to Example 13; Fig.16 is a schematic structural diagram of a solar cell according to Example 14; Fig.17 is a schematic structural diagram of a solar cell according to Example 15; Fig.18 is a schematic structural diagram of a solar cell according to Example 16; Fig.19 This is a doping curve diagram of the homojunction in the solar cell of Example 17.

[0027] In the figure, 10. Silicon substrate, 20. Homojunction; 11. a passivation anti-reflection layer, 111. a first passivation anti-reflection layer, 112. a second passivation anti-reflection layer, 113. an aluminum oxide layer, 114. a silicon nitride layer, 115. a magnesium fluoride layer; 110, passivation layer, 12, first passivation layer, 13, second passivation layer, 120, selective transport layer, 14, hole selective transport layer, 141, hole selective layer, 142, first transport layer, 15, electron selective transport layer, 151, electron selective layer; 30. Intrinsic amorphous silicon layer, 31. Doped semiconductor layer, 311. N-type doped semiconductor layer, 312. P-type doped semiconductor layer, 32. Second transmission layer, 321. Third transmission layer, 322. Fourth transmission layer; 40. a first metal electrode, 50. a second metal electrode; 60. Selective emitter, 70. Light extension region, 80. Tunneling dielectric layer, 90. Doped polysilicon layer. DETAILED DESCRIPTION

[0028] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0029] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] In the related technologies, for homojunction technology, thermal diffusion junction and laser doping superimposed high temperature activation technology are relatively mature methods for forming homojunction. The most ideal homojunction emitter doping is to dope the junction depth. Heavy doping can effectively reduce contact resistance, increase FF, reduce contact recombination probability and increase space electric field to obtain higher V OC However, the recombination probability increases, shortening the lifetime of photogenerated carriers and reducing V OC The deeper the junction, the more light will be absorbed by the emitter, which will have a great impact on V OC The greater the impact, the greater the effect. Homojunction heavy doping and shallow junction depth are a compromise choice. Although the compounding effect brought by high doping is suppressed by reducing the thickness, this is a compromise choice. The impact cannot be eliminated, and the shallow junction depth is not conducive to the separation and collection of photogenerated carriers deep in the silicon substrate, and affects VOC and FF at the same time. Under the condition of ensuring ohmic contact with the metal electrode, lightly doped deep junction depth is also very ideal, but this premise cannot be achieved in homojunction batteries.

[0031] For heterojunction technology, double-sided intrinsic and doped amorphous silicon SHJ cells have high selectivity coefficients, but optical parasitic absorption losses cannot be avoided. The passivation selective contact structure technology uses an electron or hole selection layer structure to replace the original doped amorphous silicon emitter to effectively reduce the optical parasitic absorption losses caused by doped amorphous silicon, but there are currently problems with poor passivation and transmission performance. The emergence of these problems is related to the fact that the selective material itself does not have good chemical passivation and high resistivity. In addition, the passivation selective contact structure technology also has the problem of small depth of field passivation. For high and low work function hole electron selection materials, most of these materials have high resistivity and low doping concentration, or even intrinsic materials. The high resistivity determines that the thickness needs to be very thin. When combined with the low doping concentration, the width of the space charge region is affected, reducing the ability of the silicon substrate to separate and extract carriers, which is not conducive to the improvement of FF and Voc.

[0032] If a homojunction is superimposed on such a heterojunction, it will be a design that takes advantage of the strengths of both the homojunction and heterojunction solutions. For the heterojunction, the separation and extraction capabilities of the photogenerated carriers in the silicon substrate will be improved while achieving the built-in electric field gain brought by the high and low work functions and reducing the parasitic absorption loss. For the homojunction, the surface doping concentration can be reduced and the junction depth can be deepened to reduce the recombination loss while improving the extraction capability of the photogenerated carriers deep in the silicon substrate.

[0033] Based on the above problems, an embodiment of the present application provides a solar cell, such as Figure 1 and 2 As shown, including: Silicon substrate 10; The homojunction 20 is located in the silicon substrate and extends inward from the first surface and / or the second surface of the silicon substrate. The surface doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100nm and less than or equal to the thickness of the silicon substrate; and a heterojunction, the heterojunction being located on the surface of the silicon substrate 10 on the side where the homojunction 20 is provided; The heterojunction includes a passivation selective contact structure, the passivation selective contact structure includes a passivation layer and a selective transport layer sequentially stacked on the surface of the homojunction, and the selective transport layer includes a hole selective transport layer and / or an electron selective transport layer; And / or, the heterojunction includes an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer stacked in sequence on the surface of the heterojunction; The passivation selective contact structure and the amorphous silicon heterojunction structure are located in different regions of the same surface of the silicon substrate; or the passivation selective contact structure and the amorphous silicon heterojunction are located on different side surfaces of the silicon substrate.

[0034] Among them, the homojunction can be a pn junction formed by the silicon substrate 10, or it can be an electric field formed by the conductivity type of the external doping element and the conductivity type of the doping element in the silicon substrate being the same but the doping concentration of the external doping element and the doping concentration of the doping element in the silicon substrate being different (also called a high-low junction); the heterojunction refers to a pn junction formed between heterogeneous materials, or it can be an electric field formed by the same conductivity type but different doping concentrations (also called a high-low junction); the amorphous silicon in the amorphous silicon heterojunction structure can be nanocrystalline silicon, microcrystalline silicon, nanocrystalline silicon oxide, microcrystalline silicon oxide, etc.

[0035] It is understandable that the silicon substrate 10 contains doping elements, and the doping element type is N-type or P-type. The N-type element can be a V group element such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As), and the P-type element can be a III group element such as boron (B), aluminum (Al), gallium (Ga) or indium (In). For example, when the silicon substrate 10 is a P-type substrate, the type of doping element inside it is P-type. For another example, when the silicon substrate 10 is an N-type substrate, the type of doping element inside it is N-type. A lower doping concentration of the silicon substrate 10 is conducive to forming a wide space charge region, but it will also significantly increase the series resistance and affect FF; therefore, in the embodiment of the present application, the doping concentration of the silicon substrate 10 is characterized by the resistivity of the silicon substrate 10, and the resistivity of the silicon substrate 10 can be 0.3 – 2×10 5 Ωcm, preferably the resistivity of the silicon substrate 10 is 0.7-6 Ωcm.

[0036] The light-receiving surface of the silicon substrate is recorded as the front side of the silicon substrate, and the backlight side of the silicon substrate is recorded as the back side of the silicon substrate. The silicon substrate 10 is a region that absorbs incident photons and generates photogenerated carriers. In some embodiments, the silicon substrate 10 may include one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. Exemplarily, the silicon substrate 10 in the present application is a single crystal silicon substrate 10.

[0037] It can also be understood that the doping concentration of the homojunction 20 refers to the doping concentration of the homojunction 20 on the surface of the silicon substrate 10, and the junction depth of the homojunction 20 refers to the doping depth of the homojunction 20 inside the silicon substrate 10; the doping concentration of the homojunction 20 in the embodiment of the present application can be but is not limited to 1×10 15 cm -3 , 2×10 15 cm -3 , 2×10 18 cm -3 , 3×10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 or 1×10 19 cm -3etc.; the junction depth of the homojunction 20 may be, but is not limited to, 100nm, 200nm, 300nm, 500nm, 100nm, 1500nm, 2000nm, 5000nm, 10μm, 50μm, 100μm, 150μm or 200μm, etc. In the embodiments of the present application, the doping concentration and junction depth of the homojunction 20 of the present application are beneficial to reduce the influence of Auger recombination while ensuring the strengthening of the built-in electric field of the homojunction 20, thereby improving the carrier separation and extraction capabilities; on the other hand, the doping concentration and junction depth of the homojunction 20 of the present application can enhance the concentration difference between the doped amorphous silicon layer and the silicon substrate 10, thereby enhancing the built-in electric field on the surface of the heterojunction silicon substrate 10, which is of great help to the separation of carriers near the interface, and effectively improves the V of the solar cell. OC and FF, thereby improving the conversion efficiency of solar cells.

[0038] It should be noted that the homojunction 20 can be set on the front side of the silicon substrate 10, or on the back side of the silicon substrate 10, and of course can also be set on the front side of the silicon substrate and the back side of the silicon substrate 10 at the same time; correspondingly, the heterostructure and the homojunction 20 are set on the same side of the silicon substrate 10.

[0039] Due to the existence of heterogeneous emitters or selective layers, there is no direct contact between the silicon substrate and the metal, which reduces the contact recombination and contact resistance. The design of the silicon substrate homogeneous emitter can avoid the use of traditional homojunction high-doping shallow diffusion process, further eliminate the recombination loss under high-concentration doping, and further broaden the range of carrier extraction and separation. The curve of homojunction diffusion concentration versus depth can be referred to Fig.19 A higher surface doping concentration is conducive to forming a larger doping concentration gradient in the homojunction, which is helpful for enhancing the built-in electric field of the homojunction. A low surface doping concentration can further reduce the impact of higher doping on the one hand, and enhance the built-in electric field strength and depth of the heterojunction on the other hand.

[0040] For heterojunction cells (HJT), the passivation selective contact structure and the homojunction 20 can be superimposed simultaneously. In some embodiments, the front side of the silicon substrate 10 is an HJT structure, and the back side of the silicon substrate 10 is a homojunction 20 and a passivation selective contact structure; in other embodiments, the front side of the silicon substrate 10 is a homojunction 20 and an HJT structure, and the back side of the silicon substrate 10 is an HJT structure; in other embodiments, the front side of the silicon substrate 10 is a homojunction 20 and an HJT structure, and the back side of the silicon substrate 10 is a passivation selective contact structure; in other embodiments, the front side of the silicon substrate 10 is a passivation selective contact structure, and the back side of the silicon substrate 10 is a homojunction 20 and an HJT structure; of course, other combinations are also included, and the embodiments of the present application are not listed here one by one.

[0041] For TOPCon cells, the other side of the tunneling oxygen / poly-Si passivated TOPCon structure is matched with a passivation selective contact structure or an amorphous silicon heterojunction structure, which can also optimize the carrier selection and extraction capabilities. In some embodiments, the back side of the silicon substrate 10 is a tunneling oxygen and doped polysilicon structure, and the front side of the silicon substrate 10 is a homojunction 20 and a passivation selective contact structure; in other embodiments, the back side of the silicon substrate 10 is a homojunction 20 and a passivation selective contact structure, and the front side of the silicon substrate 10 is a tunneling oxygen and doped polysilicon structure; in other embodiments, the back side of the silicon substrate 10 is a tunneling oxygen, doped polysilicon and a passivation selective contact structure, and the front side of the silicon substrate 10 is a homojunction 20 and a passivation selective contact structure; in other embodiments, the back side of the silicon substrate 10 is a homojunction 20 and a passivation selective contact structure, and the front side of the silicon substrate 10 is a tunneling oxygen, doped polysilicon and a passivation selective contact structure; of course, other combinations are also included, and the embodiments of the present application are not listed here one by one.

[0042] For a back contact (BC) cell, the back side may be combined with at least one of a homojunction 20, a passivation selective contact structure, a HJT structure, and a tunneling oxygen / doped polysilicon structure. In some embodiments, the first area on the back side of the silicon substrate 10 is a homojunction 20 and a passivation selective contact structure, and the second area is a tunneling oxygen / doped polysilicon structure; in other embodiments, the first area on the back side of the silicon substrate 10 is a homojunction 20 and a HJT structure, and the second area is a passivation selective contact structure; in other embodiments, the first area on the back side of the silicon substrate 10 is a homojunction 20, a tunneling oxygen / doped polysilicon layer, and the second area is a passivation selective contact structure; in other embodiments, the first area on the back side of the silicon substrate 10 is a homojunction 20 and a passivation selective contact structure, and the second area is a HJT structure; in other embodiments, the first area on the back side of the silicon substrate 10 is a homojunction 20 and a passivation selective contact structure, and the second area is a HJT structure; in other implementations, the first area on the back side of the silicon substrate 10 is a homojunction 20 and a passivation selective contact structure, and the second area is a homojunction 20 and a HJT structure. Of course, other combinations are also included, and the embodiments of the present application are not listed here one by one.

[0043] It can also be understood that the passivation layer can be any material, and generally a material with a wide bandgap, stable properties, and / or positive and negative fixed charges, and / or containing chemical passivation elements such as oxygen and hydrogen is selected. Depending on the different batteries, the passivation layer can be a tunneling material (for example but not limited to silicon oxide), a transmission material (for example but not limited to titanium oxide) or a passivation anti-reflection material (for example but not limited to aluminum oxide, silicon nitride), etc., and the specific selection is based on the actual processing technology and battery type.

[0044] It can also be understood that the passivation selective contact structure includes a passivation layer and a selective transmission layer, and introduces high-quality non-silicon materials to form a strong back field or junction, enhances asymmetric carrier transport and separation, effectively enhances carrier extraction and passivation capabilities, and improves the selectivity coefficient. The introduction of the passivation layer provides chemical and field effect passivation for the passivation selective contact area, suppresses interface defect states to eliminate the Fermi level pinning phenomenon, and provides a prerequisite for the high-quality field passivation provided by the selective layer. The selective transmission layer can compensate for the carrier transmission difficulties caused by the large resistance of the selective layer, improve FF, and especially adapt to local metallization. Additional hydrogen passivation gain can be introduced through other processes, such as the forming gas annealing (FGA) process, which can further enhance the passivation effect. The superimposed passivation anti-reflection layer can provide additional chemical passivation gain; in this way, under the synergistic effect of the passivation layer, the selective transmission layer and the passivation anti-reflection layer, an excellent passivation contact effect is achieved; and there is no need to use narrow bandgap highly doped silicon materials, which reduces optical parasitic absorption losses and improves photoelectric conversion efficiency.

[0045] The solar cell of the embodiment of the present application solves the problems of poor passivation and transmission performance of the existing passivation selective contact structure and large optical parasitic absorption of the amorphous silicon heterojunction structure. In the embodiment of the present application, a homojunction 20 is provided, and the doping concentration of the homojunction 20 is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction 20 is greater than or equal to 100nm and less than or equal to the thickness of the silicon substrate 10; and the homojunction 20 is combined with a selective passivation contact structure or a heterojunction structure, and the homojunction is combined with a selective passivation contact structure or an amorphous amorphous silicon heterojunction structure. On the one hand, the introduction of a heterojunction is conducive to the formation of a strong built-in electric field and reduces the metal contact resistance. The highly doped heterogeneous emitter or selective transmission layer isolates the silicon substrate from the metal, which is conducive to the formation of a strong built-in electric field while suppressing contact recombination and reducing contact resistance. On the other hand, the introduction of a homojunction with a lower doping concentration and a deeper junction depth helps to enhance the ability of carrier separation and extraction inside the silicon substrate. A lower doping concentration is conducive to reducing Auger recombination losses. Therefore, the special design of the present invention helps to make full use of the advantages of homojunctions and heterojunctions to improve the photoelectric conversion efficiency of solar cells.

[0046] In a preferred embodiment, the surface doping concentration of the homojunction 20 is 1×10 16 cm -3 ~5×10 18 cm -3 .

[0047] The doping concentration of the homojunction 20 of this embodiment is beneficial to reducing Auger recombination, and is particularly beneficial to the transfer of the heterojunction electric field to the silicon substrate, thereby increasing the induced electric field strength and depth of the heterojunction in the silicon substrate.

[0048] In a preferred embodiment, the junction depth of the homojunction 20 is 300 nm to 2000 nm. The junction depth of the homojunction 20 of this embodiment helps to enhance the capability of carrier separation and extraction inside the silicon substrate.

[0049] As an achievable manner, based on the projection on the surface of the silicon substrate 10, the projection of the selective transmission layer 120 is located within the projection range of the homojunction 20; or the projection of the intrinsic amorphous silicon layer 30 is located within the projection range of the homojunction 20. This embodiment is conducive to enhancing the ability of carrier separation and extraction inside the silicon substrate.

[0050] As a feasible method, based on the projection on the surface of the silicon substrate 10, the projection of the metal electrode is located within the projection range of the selective transmission layer 120; the projection area of ​​the intrinsic amorphous silicon layer 30 is larger than or equal to the projection area of ​​the metal electrode. Since the selective output layer 120 has a very high transmittance and lateral conductivity, the projection area of ​​the metal electrode is as small as possible without affecting the selective output layer, which is conducive to ensuring a higher double-sidedness.

[0051] The metal electrode includes a first metal electrode 40 and a second metal electrode 50. The first metal electrode and the second metal electrode can each be a single-layer structure or a stacked structure. The metal in contact with the selective transport layer should be a material of the same type as the selective transport layer (for example, the metal in contact with the hole selective transport layer is a high work function metal, and the metal in contact with the electron selective transport layer is a low work function metal). The stacked structure includes a seed layer, an intermediate layer and a protective layer. For example, the seed layer is selected from a high work function metal (>4.2eV), and the thickness of the seed layer can be 0μm-50μm, preferably 5nm-1μm; the intermediate layer is selected from a high conductivity (>1×10 at 20°C) 17 S / m) metal, the thickness of the intermediate layer can be 0μm-100μm, preferably 50 nm-20μm; the protective layer is selected from a metal with stable chemical properties, the thickness of the protective layer can be 0μm-50μm, preferably 20nm-1μm. For another example, the seed layer is selected from a metal with low work function (<3.5eV), the thickness of the seed layer can be 0-50μm, preferably 5nm-1μm; the intermediate layer is selected from a metal with high electrical conductivity (>1×10 at 20°C) 17 The thickness of the intermediate layer can be 0-100 μm, preferably 50 nm - 20 μm; the protective layer is selected from a metal with stable chemical properties, and the thickness of the protective layer can be 0-50 μm, preferably 20 nm - 1 μm.

[0052] As an achievable manner, the projection of the selective transmission layer 120 on the surface of the silicon substrate 10 may cover a partial area of ​​the surface of the silicon substrate 10 , or may cover the entire area of ​​the surface of the silicon substrate 10 .

[0053] As a feasible manner, the hole selective transport layer 14 includes a hole selective layer 141, or a hole selective layer 141 and a hole transport layer stacked toward the surface away from the silicon substrate, or a hole selective layer 141 and an electron transport layer stacked toward the surface away from the silicon substrate; the electron selective transport layer 15 includes an electron selective layer 151, or an electron selective layer 151 and an electron transport layer stacked toward the surface away from the silicon substrate, or an electron selective layer 151 and a hole transport layer stacked toward the surface away from the silicon substrate.

[0054] The electron transport layer and the hole transport layer may be collectively referred to as the first transport layer 142 .

[0055] Among them, the hole selection layer 141 and the first transport layer 142 are also made of high work function materials, and there is a work function difference between the two materials. The hole selection layer 141 is mainly used to form an electric field to repel electrons, and the first transport layer 142 is used to improve the contact performance of the metal electrode. For the local structure, when the projection area of ​​the hole selection layer 141 is not much larger than the projection area of ​​the metal electrode, the first transport layer 142 can be omitted; the same is true for the electron selection layer and the transport layer.

[0056] In some embodiments, the hole selection layer 141 is selected from materials with a work function greater than 4.8 eV and a valence band gap ΔE V A material with a V of less than 0.5 eV, or a monomolecular layer material; the hole transport layer is selected from at least one of oxides, nitrides, oxynitrides, chalcogenides, halides, thiocyanates and organic conductive polymers; The electron selective layer 151 is selected from materials with a work function less than 4.2 eV and a conduction band gap ΔE C A material with a FET of less than 0.5 eV, or an organic conductive polymer; the electron transport layer is selected from at least one of doped or intrinsic oxides, nitrides, carbides, oxynitrides, carbon oxides, carbonitride oxides, chalcogenides, halides, or organic conductive polymers.

[0057] Specifically, the hole selection layer 141 is selected from at least one of doped or intrinsic molybdenum oxide, vanadium oxide, tungsten oxide, chromium oxide, titanium oxide, copper oxide, nickel oxide, cobalt oxide, rhenium oxide, copper iodide, PEDOT:PSS, silicon carbide and a phosphate group monolayer; The hole transport layers are each independently selected from at least one of doped or intrinsic nickel oxide, copper oxide, copper iodide, copper thiocyanate, thienyl, PEDOT:PSS, PTAA, Spiro-OMeTAD and fluorinated indoprofen derivatives; The electron selective layer 151 is selected from at least one of doped or intrinsic lithium fluoride, magnesium fluoride, potassium fluoride, rubidium fluoride, cesium fluoride, calcium fluoride, strontium fluoride, barium fluoride, cerium fluoride, europium fluoride, tantalum oxide, zinc oxide, indium oxide, titanium oxide, magnesium oxide, zinc oxide, tin oxide, cesium oxide, niobium oxide, barium oxide, tantalum nitride, titanium nitride, titanium oxynitride, silicon carbide, cesium chloride, cesium bromide, cesium iodide, cesium carbonate, potassium carbonate, rubidium carbonate, calcium carbonate, strontium carbonate, barium carbonate, zinc sulfide, cadmium sulfide, indium sulfide, fullerene derivatives and bathocuproine; The electron transport layer is selected from at least one of doped or intrinsic zinc oxide, indium oxide, tin oxide, titanium oxide, cadmium sulfide, cadmium selenide, fullerene derivatives and bathocuproine.

[0058] Furthermore, the thickness of the hole selective transport layer 14 is 0.1 nm-700 nm, and the thickness of the passivation anti-reflection layer is 0 nm-525 nm.

[0059] In some embodiments, the thickness of the electron selective transport layer 15 is 0.1 nm-700 nm.

[0060] In a preferred embodiment, the thickness of the hole selective transport layer 15 is 0.5 nm-340 nm.

[0061] In a preferred embodiment, the thickness of the electron selective transport layer 14 is 0.5 nm-340 nm.

[0062] In a preferred embodiment, the thickness of the passivation anti-reflection layer 11 is 30 nm-300 nm.

[0063] In some embodiments, the thickness of the electron selective layer 151 is 0.1 nm-100 nm, preferably 0.5 nm-40 nm; the thickness of the electron transport layer is 0 nm-600 nm, preferably 0 nm-300 nm.

[0064] It can also be understood that, due to the provision of the hole selective transport layer 14 and the electron selective transport layer 15 , the metal electrode can be made of low-cost metal, which is beneficial to greatly reduce the cost of metallization materials.

[0065] As an achievable method, one or more anti-reflection layers, such as magnesium fluoride, may be further provided on the outer surfaces of the hole selective transport layer 14, the electron selective transport layer 15, and the passivation anti-reflection layer 11. Specifically, if the hole selective transport layer 14 is located at the outermost side, an anti-reflection layer is provided on the outer surface of the hole selective transport layer 14; if the electron selective transport layer 15 is located at the outermost side, an anti-reflection layer is provided on the outer surface of the electron selective transport layer 15; if the passivation anti-reflection layer 11 is located at the outermost side, an anti-reflection layer is provided on the outer surface of the passivation anti-reflection layer 11.

[0066] As an achievable manner, the passivation layer 110 includes a first passivation layer 12 and a second passivation layer 13 . The first passivation layer 12 is arranged corresponding to the hole selective transport layer 14 , and the second passivation layer 13 is arranged corresponding to the electron selective transport layer 15 .

[0067] In some implementations, the first passivation layer 12 and the second passivation layer 13 are each selected from at least one of silicon oxide, silicon oxynitride, aluminum oxide, phosphorus oxide, boron oxide, hafnium oxide, silicon carbide, titanium oxide, tin oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, and silicon oxynitride.

[0068] The first passivation layer 12 and the second passivation layer 13 can each be prepared by thermal oxidation, nitric acid oxidation, ozone oxidation, plasma-assisted oxidation, CVD, ALD, VPE, PVD, solution method (including nitric acid oxidation (NAOS), spin coating, spray coating, drop coating, meniscus coating, dipping method, CBD, SILAR, electroplating, chemical plating, anodic reaction deposition) or a two-step oxidation method.

[0069] As an achievable manner, the thickness of each of the first passivation layer 12 and the second passivation layer 13 is 0.1-300 nm.

[0070] In some embodiments, the first passivation layer 12 and the second passivation layer 13 each have a thickness of 0.1-10 nm.

[0071] In a preferred embodiment, the thickness of the first passivation layer 12 is 1.6 nm.

[0072] As an achievable method, the solar cell further comprises: A passivation anti-reflection layer is located on the silicon substrate 10 and the selective transmission layer; one of the first metal electrode 40 and the second metal electrode 50 passes through the passivation anti-reflection layer 11 and contacts the selective transmission layer; Or the second transmission layer 32 is located on the doped semiconductor layer 31 ; one of the first metal electrode 40 and the second metal electrode 50 is in contact with the second transmission layer 32 .

[0073] As an achievable manner, the doped semiconductor layer 31 includes a P-type doped semiconductor layer 312 and an N-type doped semiconductor layer 311 , the passivation anti-reflection layer 11 includes a first passivation anti-reflection layer 111 and a second passivation anti-reflection layer 112 , and the second transmission layer 32 includes a third transmission layer 321 and a fourth transmission layer 322 .

[0074] In some embodiments, the first passivation anti-reflection layer 111 and the second passivation anti-reflection layer 112 may each include an aluminum oxide layer 113 and a silicon nitride layer 114 that are stacked.

[0075] Among them, aluminum oxide and silicon nitride can both play a passivation role, and the anti-reflection effect mainly depends on silicon nitride; in a preferred embodiment, a multi-layer anti-reflection structure is set up, and silicon nitride can be set as a multi-layer silicon nitride layer with different refractive indexes; other anti-reflection layers, such as magnesium fluoride, can also be set on the silicon nitride surface.

[0076] In addition, silicon nitride may also be oxygen-doped or carbon-doped or both-doped silicon nitride, that is, silicon oxynitride, silicon carbide nitride, silicon carbon nitride oxynitride, and the like.

[0077] In some embodiments, aluminum oxide may be replaced by intrinsic or doped amorphous silicon, nanocrystalline silicon, microcrystalline silicon, microcrystalline silicon oxide, nanocrystalline silicon oxide, amorphous silicon oxide, phosphorus oxide, boron oxide, hafnium oxide, silicon carbide, titanium oxide, gallium oxide, zinc oxide, or tantalum oxide.

[0078] In some embodiments, one side of the silicon substrate 10 includes a homojunction 20 , a first passivation layer 12 , a hole selective transport layer 13 , and a first metal electrode 40 ; The other side of the silicon substrate 10 includes an intrinsic amorphous silicon layer 30 , a doped semiconductor layer 31 , a second transmission layer 32 and a second metal electrode 50 which are sequentially stacked from the inside to the outside.

[0079] In some embodiments, the homojunction 20 is located in the first surface of the silicon substrate 10, and the passivation layer and the selective transmission layer are sequentially stacked on the first surface; The second surface of the silicon substrate 10 includes a second intrinsic amorphous silicon layer and a second doped semiconductor layer which are stacked in sequence and are away from the surface of the silicon substrate 10 .

[0080] In some embodiments, the homojunction 20 is located in the first surface of the silicon substrate 10, and the intrinsic amorphous silicon layer and the doped semiconductor layer are sequentially stacked on the first surface; The second surface of the silicon substrate 10 includes a third intrinsic amorphous silicon layer and a third doped semiconductor layer which are stacked in sequence away from the silicon substrate 10 .

[0081] In some embodiments, the homojunction 20 is located within the first surface of the silicon substrate 10, and the passivation layer and the selective transmission layer are located on the first surface; The second surface of the silicon substrate 10 includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence away from the silicon substrate 10 .

[0082] In some embodiments, the homojunction 20 is located within the first surface, and the intrinsic amorphous silicon layer and the doped semiconductor layer are located on the first surface; The second surface includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence and are away from the silicon substrate 10 .

[0083] In some embodiments, the back side of the silicon substrate 10 includes a plurality of first regions and a plurality of second regions that are spaced apart from each other; A homojunction 20 is located in the surface of the first region, and a passivation layer and a selective transmission layer are located on the surface of the first region; The surface of the second region includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence and are away from the surface of the second region.

[0084] In some embodiments, the back side of the silicon substrate 10 includes a plurality of first regions and a plurality of second regions that are spaced apart from each other; The homojunction 20 is located in the surface of the first region and the second region, and the passivation layer and the selective transmission layer are located on the surface of the first region; And a fourth intrinsic amorphous silicon layer and a fourth doped semiconductor layer are located on the surface of the second region.

[0085] In some embodiments, the back side of the silicon substrate 10 includes a plurality of first regions and a plurality of second regions that are spaced apart from each other; The homojunction 20 is located in the surface of the first region, and the intrinsic amorphous silicon layer and the doped semiconductor layer are located on the surface of the first region; The surface of the second region includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence and are away from the surface of the second region.

[0086] In summary, the solar cell of the embodiment of the present application uses a specially designed homojunction superimposed heterojunction technology. By setting a homojunction, the doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100nm and less than or equal to the thickness of the silicon substrate; and the homojunction is combined with a selective passivation contact structure or an amorphous amorphous silicon heterojunction structure. On the one hand, the introduction of a heterojunction is conducive to the formation of a strong built-in electric field and reduces the metal contact resistance. The highly doped heterogeneous emitter or selective transmission layer isolates the silicon substrate from the metal, which is conducive to the formation of a strong built-in electric field while suppressing contact recombination and reducing contact resistance. On the other hand, the introduction of a homojunction with a lower doping concentration and a deeper junction depth helps to enhance the ability of carrier separation and extraction inside the silicon substrate. A lower doping concentration is conducive to reducing Auger recombination losses. Therefore, the special design of the present invention helps to make full use of the advantages of homojunctions and heterojunctions and improve the photoelectric conversion efficiency of solar cells.

[0087] In a second aspect, an embodiment of the present application provides a method for preparing a solar cell, which specifically comprises the following steps: S1, pre-depositing a doping source layer on the surface of a silicon substrate, the doping source layer comprising a first pre-doping layer and PSG formed on the surface of the silicon substrate, or a second pre-doping layer and BSG formed; S2, removing PSG or BSG on the surface of the silicon substrate; S3, forming a homojunction on the surface of the silicon substrate by means of a finite source; the doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100 nm and less than or equal to the thickness of the silicon substrate; S4, forming a heterojunction on the surface of the silicon substrate on which the homojunction is provided; The heterojunction includes a passivation selective contact structure, the passivation selective contact structure includes a passivation layer and a selective transport layer sequentially stacked on the surface of the homojunction, and the selective transport layer includes a hole selective transport layer and / or an electron selective transport layer; And / or, the heterojunction includes an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer sequentially stacked on a homojunction surface.

[0088] In step S1, a doping source layer is pre-deposited on the surface of the silicon substrate to form a pre-doping layer and PSG, or a pre-doping layer and BSG on the surface of the silicon substrate. The doping source layer can be understood as a region on the surface of the silicon substrate where the concentration reaches a shallow doping depth; the silicon substrate can be a polished surface or a textured surface; the process for preparing the doping source layer can be, but is not limited to, thermal diffusion (e.g., tube furnace thermal diffusion, silicon ink diffusion), laser doping (e.g., laser doping, spin-coating phosphorus source doping, laser chemical doping), or ion implantation, etc.

[0089] For example, taking an N-type silicon substrate as an example, LPCVD or PECVD can be used for thermal diffusion with a limited phosphorus source.

[0090] In step S2, the surface PSG and BSG can be removed by conventional processes.

[0091] In step S3, the limited source deep diffusion reduces the doping concentration on the surface of the doping source layer and pushes the doping source layer into the silicon substrate, thereby forming the homojunction, wherein the composite doping curve of the homojunction is as follows: Fig.19 As shown; wherein, the limited source deep diffusion can adopt the same process as step S1, but different process parameters can be adjusted according to the doping curve, such as temperature, gas flow, pressure and time, etc., which are specifically determined according to actual processing needs; The step S4 of preparing the selective passivation contact structure or the step S5 of preparing the heterojunction structure comprises: First, an intrinsic amorphous silicon layer or a passivation layer is prepared on the homojunction surface; wherein the passivation layer has a good passivation effect to avoid the problem of Fermi level pinning caused by high interface defect state density. It is required to have a wide bandgap, high resistance, and the properties of chemical passivation and field effect passivation. The materials of the passivation layer include but are not limited to some oxides, nitrides, oxynitrides, carbides, oxycarbons, etc.

[0092] The method for preparing the intrinsic amorphous silicon layer or the passivation layer includes but is not limited to: Thermal oxidation growth method: CVD: Ozone gas oxidation (OGO), plasma-assisted nitrous oxide oxidation (PANO), APCVD, LPCVD, UHVCVD, LCVD, photo-CVD, PECVD, HDPCVD, MPCVD, HTCVD, MTCVD, ICPCVD, MOCVD, HWCVD, VPE, ThermalALD, PEALD PVD: thermal evaporation, electron beam evaporation, magnetron sputtering, reactive sputtering, DC sputtering, RF sputtering, ion beam sputtering, ion plating, ion beam deposition, ion assisted deposition (IAD), MBE, LPE, HWE, close space sublimation (CSS); Solution method: nitric acid oxidation (NAOS), spin coating, spray coating, drop coating, meniscus coating, dipping, CBD, SILAR, electroplating, chemical plating, anodic reaction deposition Two-step oxidation (TSO).

[0093] It should be noted that the preparation of the passivation layer can also adopt a high temperature process, but the impact on the homojunction needs to be considered, so it is necessary to combine the doping curve to select step S1 and the process conditions for preparing the passivation layer; Secondly, prepare a doped semiconductor layer or a selective transport layer (hole selective transport layer and electron selective transport layer). For example, a low temperature process is used to form a highly doped (even degenerate) non- / micro / nanocrystalline silicon emitter or a selective transport layer. The low temperature process will not affect the doping concentration and junction depth of the homojunction; wherein the preparation method of doped non- / micro / nanocrystalline silicon includes but is not limited to PECVD or LPCVD. The preparation method of the selective transport layer includes but is not limited to the above-mentioned PVD, CVD or solution method.

[0094] As an achievable approach, for cells with different structures, an emitter, a second transport layer and / or other passivation anti-reflection layers are prepared on the surface of the selective transport layer or the doped semiconductor layer.

[0095] In a preferred embodiment, the homojunction is deeply diffused by a finite source so that the doping concentration of the homojunction is 1×10 15 cm -3 ~1×1019cm-3 , the junction depth of the homojunction is greater than or equal to 100nm and less than or equal to the thickness of the silicon substrate.

[0096] In a preferred embodiment, step S4, preparing a selective passivation contact structure on the homojunction surface, comprises: preparing a passivation layer on the homojunction surface; A selective transmission layer is prepared on the surface of the passivation layer by a low temperature process.

[0097] In a preferred embodiment, step S5, preparing a heterojunction structure on the homojunction surface, comprises: preparing an intrinsic amorphous silicon layer on the homojunction surface; A doped semiconductor layer is prepared on the surface of the amorphous silicon layer by a low temperature process.

[0098] The specific operations are the same as those in the above steps S4 and S5 and will not be described in detail here.

[0099] In summary, the method for preparing a solar cell of the embodiment of the present application is conducive to controlling the doping concentration and junction depth of the homojunction, and the subsequent selective passivation contact structure or heterojunction structure adopts a low-temperature process, which will not affect the homojunction. The preparation process is simple and safe, which is conducive to ensuring the efficiency of the solar cell.

[0100] For example, taking the N-type battery double-sided non-silicon selection layer structure as an example, the battery structure includes: a homogeneous junction on the back side of the silicon substrate, a first passivation layer, a hole selection layer, a transport layer and a first metal electrode; the front side of the silicon substrate is stacked from the inside to the outside with a second passivation layer, an electron selection layer, an electron transport layer and a second metal electrode. The specific preparation process includes the following steps: (1) Cleaning of silicon substrate and texturing of the back side of silicon substrate; (2) Boron diffusion into silicon substrate; (3) Etching the front side of the silicon substrate to remove BSG and the boron expansion area, and texturing the front side of the silicon substrate; (4) depositing a first passivation layer and a second passivation layer on the front and back sides of the silicon substrate; (5) depositing an electron selective layer on the front side of the silicon substrate; (6) depositing a hole selection layer on the back side of the silicon substrate; (7) depositing an electron transport layer on the front side of the silicon substrate and a transport layer on the back side of the silicon substrate; (8) Low-temperature metallization treatment of the front and back sides of the silicon substrate; (9) Light injection.

[0101] In a third aspect, an embodiment of the present application provides another method for preparing a solar cell, comprising the following steps: S1, sequentially preparing a tunnel dielectric layer and a doped polysilicon layer on the surface of a silicon substrate to form an inner expansion layer on the silicon substrate; S2, removing the doped polysilicon layer; S3, the inner expansion layer is diffused by limited source to form a homojunction, and the doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100nm and less than or equal to the thickness of the silicon substrate; S4, forming a homogeneous junction on the surface of the silicon substrate by means of limited source diffusion of the inner diffusion layer; The heterojunction includes a passivation selective contact structure, the passivation selective contact structure includes a passivation layer and a selective transport layer sequentially stacked on the surface of the homojunction, and the selective transport layer includes a hole selective transport layer and / or an electron selective transport layer; And / or, the heterojunction includes an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer sequentially stacked on a homojunction surface.

[0102] It can be understood that the preparation of the doped polysilicon layer in step S1 includes: Deposition of doped intrinsic amorphous silicon; The intrinsic amorphous silicon is crystallized to form the polysilicon layer and the inner diffusion layer.

[0103] In-situ doping can also be achieved by first preparing intrinsic amorphous silicon and then crystallizing it through a high-temperature process to form doped amorphous silicon and an inner diffusion layer.

[0104] In step S2, the doped polysilicon layer may be removed and the tunnel dielectric layer may be removed; In step S3, the high-concentration inner diffusion layer on the surface of the silicon substrate is pushed into the interior of the silicon substrate by limited source diffusion to form the required homojunction doping concentration and junction depth.

[0105] The structure of the solar cell according to the embodiment of the present application is described in detail below with reference to a specific embodiment.

[0106] Example 1 like Figure 3 As shown, the back side of the silicon substrate 10 includes a homojunction 20, an intrinsic amorphous silicon layer 30, a P-type doped semiconductor layer 312, a fourth transmission layer 322 and a first metal electrode 40; The front side of the silicon substrate 10 includes an intrinsic amorphous silicon layer 30 , an N-type doped semiconductor layer 311 , a third transmission layer 321 and a second metal electrode 50 stacked in sequence from the inside to the outside.

[0107] Example 2 like Figure 4 As shown, the back side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14 and a first metal electrode 40, and the first metal electrode 40 is in contact with the hole selective transport layer 14; The front side of the silicon substrate 10 includes an intrinsic amorphous silicon layer 30 , an N-type doped semiconductor layer 311 , a third transmission layer 321 and a second metal electrode 50 stacked in sequence from the inside to the outside.

[0108] Example 3 like Figure 5 As shown, the back side of the silicon substrate 10 includes an intrinsic amorphous silicon layer 30, a P-type doped semiconductor layer 312, a fourth transmission layer and a first metal electrode 40 stacked in sequence from the inside to the outside; The front side of the silicon substrate 10 includes a homojunction 20 , an intrinsic amorphous silicon layer 30 , an N-type doped semiconductor layer 311 , a third transmission layer 321 and a second metal electrode 50 .

[0109] Example 4 like Figure 6 As shown, the back side of the silicon substrate 10 includes an intrinsic amorphous silicon layer 30, a P-type doped semiconductor layer 312, a fourth transmission layer 322 and a first metal electrode 40' stacked in sequence from the inside to the outside. The front side of the silicon substrate 10 includes a homojunction 20 , a second passivation layer 13 , an electron selective transport layer 15 and a second metal electrode 50 .

[0110] Example 5 like Figure 7 As shown, the back side of the silicon substrate 10 includes a first passivation layer 12, a hole selective transport layer 14 and a first metal electrode 40 stacked in sequence from the inside to the outside; The front side of the silicon substrate 10 includes a homojunction 20 , a second passivation layer 13 , an electron selective transport layer 15 and a second metal electrode 50 .

[0111] Example 6 like Figure 8 As shown, the back side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14 and a first metal electrode 40; The front side of the silicon substrate 10 includes a second passivation layer 13 , an electron selective transport layer 15 and a second metal electrode 50 stacked in sequence from the inside to the outside.

[0112] TOPCon cells integrated with passivation selective contact structures or HJT composite structure technology - homojunction 20 is designed on one side of the passivation selective contact structure, such as a TOPCon structure with tunneling oxygen / doped polysilicon passivation and a passivation selective contact structure or HJT on the other side, and a homojunction 20 can also be introduced to optimize carrier selection and extraction capabilities. The following Examples 7-10 show only TOPCon with a passivation selective contact structure as an example, and the design concept of the HJ structure is similar. Since the selective emitter 60 is additionally introduced, there is no need to worry about the hole selection layer being only for hole extraction. The silicon substrate can be selected as either n-type or p-type, which is highly flexible. In addition, since the resistance of the passivation selective contact is large and the local contact area is small, the introduction of a diffused selective emitter 60 with a doping higher than the substrate helps to improve the lateral transfer resistance.

[0113] Example 7 like Fig. 9 As shown, the back side of the silicon substrate 10 includes a tunnel dielectric layer 80, a doped polysilicon layer 90, a first passivation anti-reflection layer 111 and a first metal electrode 40 stacked in sequence from the inside to the outside; The front side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a second passivation anti-reflection layer 112, and a second metal electrode 50; wherein the projections of the first passivation layer 12 and the hole selective transport layer 14 on the surface of the silicon substrate 10 cover a partial area of ​​the surface of the silicon substrate 10; Example 8 like Fig.10 As shown, the back side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a first passivation anti-reflection layer 111 and a first metal electrode 40; wherein the projections of the first passivation layer 12 and the hole selective transport layer 14 on the surface of the silicon substrate 10 cover the entire area of ​​the surface of the silicon substrate 10; The front side of the silicon substrate 10 includes a tunnel dielectric layer 80 , a doped polysilicon layer, a first passivation anti-reflection layer 112 and a second metal electrode 50 stacked in sequence from the inside to the outside.

[0114] Example 9 like Fig.11 As shown, the back side of the silicon substrate 10 includes a tunnel dielectric layer 80, a doped polysilicon layer, an electron selection layer 151, a first passivation anti-reflection layer 111 and a first metal electrode 40 stacked in sequence from the inside to the outside; wherein the projection of the electron selection layer 151 on the surface of the silicon substrate 10 covers a part of the surface of the silicon substrate 10 The front side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a first passivation anti-reflection layer 112 and a second metal electrode 50; wherein the projections of the first passivation layer 12 and the hole selective transport layer 14 on the surface of the silicon substrate 10 cover a partial area of ​​the surface of the silicon substrate 10.

[0115] Example 10 like Fig.12 As shown, the back side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a first passivation anti-reflection layer 111 and a first metal electrode 40; wherein the projections of the first passivation layer 12 and the hole selective transport layer 14 on the surface of the silicon substrate 10 cover the entire area of ​​the surface of the silicon substrate 10.

[0116] The front side of the silicon substrate 10 includes a tunneling dielectric layer 80, a doped polysilicon layer, an electron selection layer 151, a first passivation anti-reflection layer 112 and a second metal electrode 50 stacked in sequence from the inside to the outside; wherein the projection of the electron selection layer 151 on the surface of the silicon substrate 10 covers a partial area of ​​the surface of the silicon substrate 10.

[0117] The PERC cell technology integrated in the passivation selective contact structure technology, the homojunction 20 is designed on one side of the passivation selective contact structure. By using the passivation selective contact structure technology to replace the aluminum back field, Examples 11-14 can suppress the serious recombination loss caused by the aluminum back field. Superimposing the homojunction 20 can further optimize the back electric field and enhance the extraction and separation capabilities of back carriers. The double-sided diffusion process is conducive to the formation of a gradient band structure on both sides and enhances the electric field on both sides. Although the double-sided diffusion process is difficult to implement, it is also achievable. For example, by introducing a masking layer and optimizing the preparation order of the diffusion selective emitter 60 (that is, the side with a higher temperature is done first).

[0118] Embodiment 11 like Fig.13 As shown, the back side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a first passivation anti-reflection layer 111 and a first metal electrode 40; wherein the projections of the first passivation layer 12 and the hole selective transport layer 14 on the surface of the silicon substrate 10 cover a partial area of ​​the surface of the silicon substrate 10; The front side of the silicon substrate 10 includes a selective emitter 60 , a light extension region 70 , a first passivation anti-reflection layer 112 and a second metal electrode 50 stacked in sequence from the inside to the outside.

[0119] Example 12 like Fig.14As shown, the back side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a first passivation anti-reflection layer 111 and a first metal electrode 40; wherein the projections of the first passivation layer 12 and the hole selective transport layer 14 on the surface of the silicon substrate 10 cover a partial area of ​​the surface of the silicon substrate 10; The front side of the silicon substrate 10 includes a selective emitter 60, a lower doped emitter 70, an electron selective layer 151, a first passivation anti-reflection layer 112 and a second metal electrode 50 stacked in sequence from the inside to the outside; wherein the projection of the electron selective layer 151 on the surface of the silicon substrate 10 covers a partial area of ​​the surface of the silicon substrate 10.

[0120] Embodiment 13 like Fig.15 As shown, the back side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a first passivation anti-reflection layer 111 and a first metal electrode 40; wherein the projections of the first passivation layer 12 and the hole selective transport layer 14 on the surface of the silicon substrate 10 cover the entire surface area of ​​the silicon substrate 10; The front side of the silicon substrate 10 includes a selective emitter 60 , a lightly extended region 70 , a first passivation anti-reflection layer 112 and a second metal electrode 50 . The doping concentration of the lightly extended region 70 is higher than that of the homojunction 20 .

[0121] Embodiment 14 like Fig.16 As shown, the back side of the silicon substrate 10 includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a first passivation anti-reflection layer 111 and a first metal electrode 40; wherein the projections of the first passivation layer 12 and the hole selective transport layer 14 on the surface of the silicon substrate 10 cover the entire surface area of ​​the silicon substrate 10; The front side of the silicon substrate 10 includes a selective emitter 60, a lightly expanded region 70, an electron selective layer 151, a first passivation anti-reflection layer 112 and a second metal electrode 50; wherein the projection of the electron selective layer 151 on the surface of the silicon substrate 10 covers a partial area of ​​the surface of the silicon substrate 10, and the doping concentration of the lightly expanded region 70 is higher than the doping concentration of the homojunction 20.

[0122] The homojunction 20 and the passivation selective contact structure and / or HJT are integrated into the back contact cell, as shown in Example 15-Example 16: Embodiment 15 like Fig.17 As shown, the back side of the silicon substrate 10 includes a plurality of first regions and a plurality of second regions that are spaced apart from each other; The first region includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a first passivation anti-reflection layer 111 and a first metal electrode 40; The second region includes a tunnel dielectric layer 80, a doped polysilicon layer 90, a first passivation anti-reflection layer 111 and a second metal electrode 50 stacked from inside to outside on the surface of the silicon substrate 10; A second passivation anti-reflection layer 112 is disposed on the front surface of the silicon substrate 10 .

[0123] Example 16 like Fig.18 As shown, the solar cell includes: the back side of the silicon substrate 10 includes a plurality of first regions and a plurality of second regions arranged at intervals; The first region includes a homojunction 20, a first passivation layer 12, a hole selective transport layer 14, a first passivation anti-reflection layer 111, a magnesium fluoride layer 115 and a first metal electrode 40; The second region includes a homojunction 20, an intrinsic amorphous silicon layer 30, an N-type doped semiconductor layer 311, a third transmission layer 321, a magnesium fluoride layer 115, and a second metal electrode 50; A second passivation anti-reflection layer 112 is disposed on the front side of the silicon substrate 10; Among them, the doping types of the homojunction 20 located in the first region and the homojunction 20 located in the second region are opposite, the homojunction 20 in the first region can be boron or gallium doped, and the homojunction 20 in the second region can be phosphorus doped; in order to avoid short circuit, the homojunction 20 located in the first region and the homojunction 20 located in the second region need to be insulated and isolated, for example: groove isolation can be performed, and a magnesium fluoride layer is set in the groove area to achieve passivation; of course, according to different preparation processes, the magnesium fluoride here can also be aluminum oxide and / or silicon nitride passivation.

[0124] In Examples 1 to 16, the front emitter can be either a selective emitter or a non-selective emitter; the front and back sides of the silicon substrate are both textured surfaces; it can also be a back-junction battery: the front side is a p-region and the back side is an n-region, and this structure includes local and global passivation selective contact structures; the material of the hole selective transport layer can be either an n-type material or a p-type material, combined with the actual structural design; the surface of the second transport layer and the passivation anti-reflection layer can be covered with an anti-reflection layer with a lower refractive index, such as MgF2; the global electron selective layer design can eliminate the preparation of aluminum oxide silicon nitride, and can directly cover the electron transport layer and / or the non-contact area anti-reflection layer, etc.

[0125] In a third aspect, an embodiment of the present application provides a solar cell assembly, comprising a front material layer, a front encapsulation layer, a battery, a back encapsulation layer and a back material layer arranged in sequence from top to bottom, wherein the battery is a solar cell of the second aspect. It is understandable that the solar cell assembly has all the features and advantages of the above-mentioned solar cell, which will not be described in detail here. In general, the solar cell assembly has a high battery efficiency.

[0126] In a fourth aspect, an embodiment of the present application provides a solar cell system, comprising at least one solar cell module, which is a solar cell module of the third aspect. It is understandable that the solar cell system has all the features and advantages of the above-mentioned solar cells, which will not be repeated here. In general, the solar cell system has a high cell efficiency.

[0127] It should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like used above to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0128] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A solar cell, characterized in that: include: Silicon substrate; A homojunction is located in the silicon substrate and extends inward from the first surface and / or the second surface of the silicon substrate, and the surface doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100 nm and less than or equal to the thickness of the silicon substrate; and a heterojunction, the heterojunction being located on a surface of the silicon substrate on a side where the homojunction is provided; The heterojunction includes a passivation selective contact structure, the passivation selective contact structure includes a passivation layer and a selective transport layer sequentially stacked on the surface of the homojunction, the selective transport layer includes a hole selective transport layer and / or an electron selective transport layer; And / or, the heterojunction includes an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer sequentially stacked on the surface of the heterojunction.

2. The solar cell according to claim 1, characterized in that: The passivation selective contact structure and the amorphous silicon heterojunction structure are located in different regions of the same surface of the silicon substrate; or the passivation selective contact structure and the amorphous silicon heterojunction are located on different side surfaces of the silicon substrate.

3. The solar cell according to claim 1, characterized in that The surface doping concentration of the homojunction is 1×10 16 cm -3 ~5×10 18 cm -3 .

4. The solar cell according to claim 1, characterized in that The junction depth of the homojunction is 300nm~2000nm.

5. The solar cell according to claim 1, characterized in that: The hole selective transport layer includes a hole selective layer, or a hole selective layer and a hole transport layer stacked and arranged away from the surface of the silicon substrate, or a hole selective layer and an electron transport layer stacked and arranged away from the surface of the silicon substrate; The electron selective transport layer includes an electron selective layer, or an electron selective layer and an electron transport layer stacked and arranged away from the surface of the silicon substrate, or an electron selective layer and a hole transport layer stacked and arranged away from the surface of the silicon substrate.

6. The solar cell according to claim 1, characterized in that Based on the projection on the surface of the silicon substrate, the projection of the selective transmission layer is located within the projection range of the homojunction; or the projection of the intrinsic amorphous silicon layer is located within the projection range of the homojunction.

7. The solar cell according to any one of claims 1 to 6, characterized in that: The solar cell further comprises a metal electrode, and based on the projection on the surface of the silicon substrate, the projection of the metal electrode is located within the projection range of the selective transmission layer; or the projection of the metal electrode is located within the projection range of the intrinsic amorphous silicon layer.

8. The solar cell according to claim 7, characterized in that: The metal electrode includes a first metal electrode and a second metal electrode, and the solar cell further includes: a passivation anti-reflection layer located on the silicon substrate and the selective transmission layer; one of the first metal electrode and the second metal electrode passes through the passivation anti-reflection layer and contacts the selective transmission layer; Or, a second transmission layer is located on the doped semiconductor layer; one of the first metal electrode and the second metal electrode is in contact with the second transmission layer.

9. The solar cell according to any one of claims 1, 3 to 6, characterized in that: The homojunction is located in the first surface of the silicon substrate, and the passivation layer and the selective transmission layer are sequentially stacked on the first surface; The second surface of the silicon substrate comprises a second intrinsic amorphous silicon layer and a second doped semiconductor layer which are stacked in sequence and are away from the surface of the silicon substrate.

10. The solar cell according to any one of claims 1, 3 to 6, characterized in that: The homojunction is located in the first surface of the silicon substrate, and the intrinsic amorphous silicon layer and the doped semiconductor layer are sequentially stacked on the first surface; The second surface of the silicon substrate includes a third intrinsic amorphous silicon layer and a third doped semiconductor layer which are stacked in sequence and are away from the silicon substrate.

11. The solar cell according to any one of claims 1, 3 to 6, characterized in that: The homojunction is located in the first surface of the silicon substrate, and the passivation layer and the selective transmission layer are located on the first surface; The second surface of the silicon substrate includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence away from the silicon substrate.

12. The solar cell according to any one of claims 1, 3 to 6, characterized in that: The homojunction is located in the first surface, and the intrinsic amorphous silicon layer and the doped semiconductor layer are located on the first surface; The second surface includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence and are away from the silicon substrate.

13. The solar cell according to any one of claims 1, 3 to 6, characterized in that: The back side of the silicon substrate includes a plurality of first regions and a plurality of second regions which are spaced apart from each other; The homojunction is located in the surface of the first region, and the passivation layer and the selective transmission layer are located on the surface of the first region; The surface of the second region includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence and are away from the surface of the second region.

14. The solar cell according to any one of claims 1 to 6, characterized in that: The back side of the silicon substrate includes a plurality of first regions and a plurality of second regions which are spaced apart from each other; The homojunction is located in the surfaces of the first region and the second region, and the passivation layer and the selective transmission layer are located on the surface of the first region; and an intrinsic amorphous silicon layer and a doped semiconductor layer located on the surface of the second region.

15. The solar cell according to any one of claims 1, 3 to 6, characterized in that: The back side of the silicon substrate includes a plurality of first regions and a plurality of second regions which are spaced apart from each other; The homojunction is located in the surface of the first region, and the intrinsic amorphous silicon layer and the doped semiconductor layer are located on the surface of the first region; The surface of the second region includes a tunnel dielectric layer and a doped polysilicon layer which are stacked in sequence away from the surface of the second region.

16. A method for preparing a solar cell, characterized in that: The steps include: Pre-depositing a doping source layer on the surface of the silicon substrate, wherein the doping source layer includes a first pre-doping layer and PSG formed on the surface of the silicon substrate, or a second pre-doping layer and BSG formed on the surface of the silicon substrate; removing PSG or BSG on the surface of the silicon substrate; A homojunction is formed on the surface of the silicon substrate by means of a finite source; the doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100 nm and less than or equal to the thickness of the silicon substrate; forming a heterojunction on the surface of the silicon substrate on the side where the homojunction is provided; The heterojunction includes a passivation selective contact structure, the passivation selective contact structure includes a passivation layer and a selective transport layer sequentially stacked on the surface of the homojunction, the selective transport layer includes a hole selective transport layer and / or an electron selective transport layer; And / or, the heterojunction includes an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer sequentially stacked on the surface of the heterojunction.

17. A method for preparing a solar cell, characterized in that: The steps include: Sequentially preparing a tunnel dielectric layer and a doped polysilicon layer on the surface of a silicon substrate to form an inner expansion layer on the silicon substrate; removing the doped polysilicon layer; The inner diffusion layer forms a homojunction on the surface of the silicon substrate by limited source diffusion, and the doping concentration of the homojunction is 1×10 15 cm -3 ~1×10 19 cm -3 , the junction depth of the homojunction is greater than or equal to 100 nm and less than or equal to the thickness of the silicon substrate; forming a heterojunction on the surface of the silicon substrate on the side where the homojunction is provided; The heterojunction includes a passivation selective contact structure, the passivation selective contact structure includes a passivation layer and a selective transport layer sequentially stacked on the surface of the homojunction, the selective transport layer includes a hole selective transport layer and / or an electron selective transport layer; And / or, the heterojunction includes an amorphous silicon heterojunction structure, and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer sequentially stacked on the surface of the heterojunction.

18. A solar cell module, characterized in that: A solar cell comprising any one of claims 1 to 15.

19. A solar cell system, characterized in that: A solar cell module comprising claim 18.

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