Dynamic protection circuit, power supply circuit and control method thereof

Abstract

The invention discloses a dynamic protection circuit, a power supply circuit and a control method of the power supply circuit. The dynamic protection circuit comprises an adjusting circuit, a detection circuit, a control circuit and a counter circuit. The adjusting circuit adjusts an output voltage according to a preset value. The detection circuit detects whether the output voltage is greater than an upper limit value or less than a lower limit value. The control circuit changes the preset value and disables the detection circuit when the preset value is changed. When the detection circuit is disabled, the counter circuit starts to adjust a count value. When the counter circuit adjusts the counting value, the control circuit adjusts the upper limit value and the lower limit value in equal proportion according to the output voltage. When the count value is equal to a target value, the counter circuit enables the detection circuit.

Description

Technical Field

[0001] The present invention relates to a power supply circuit, and in particular to a dynamic protection circuit, a power supply circuit and a control method thereof for adjusting a voltage upper limit value and a voltage lower limit value in proportion when adjusting an output voltage. Background Art

[0002] A general power supply circuit provides appropriate power to an external device according to the needs of the external device. The power supply circuit usually has an overvoltage protection function and an undervoltage protection function. When the power exceeds an overvoltage protection value or is lower than an undervoltage protection value, it indicates that the power supply is abnormal. Therefore, the power supply circuit may suspend the power supply. However, while the power supply circuit adjusts the power supply, it may not be able to adjust the overvoltage protection value and the undervoltage protection value immediately due to insufficient internal bus, thus causing malfunction, mistakenly thinking that an overvoltage event or an undervoltage event has occurred. Summary of the invention

[0003] One embodiment of the present invention provides a dynamic protection circuit, including an adjustment circuit, a detection circuit, a control circuit and a counter circuit. The adjustment circuit adjusts an output voltage according to a preset value. The detection circuit detects whether the output voltage is greater than an upper limit value or less than a lower limit value. The control circuit changes the preset value and disables the detection circuit when changing the preset value. When the detection circuit is disabled, the counter circuit starts to adjust a count value. When the counter circuit adjusts the count value, the control circuit proportionally adjusts the upper limit value and the lower limit value according to the output voltage. When the count value is equal to a target value, the counter circuit enables the detection circuit.

[0004] The present invention further provides a power supply circuit, including a conversion circuit, a processing circuit, a switch and a dynamic protection circuit. The conversion circuit converts an external power supply into a DC power supply. The processing circuit processes the DC power supply to generate an output voltage. The switch is used to transmit the output voltage. The dynamic protection circuit includes an adjustment circuit, a detection circuit, a control circuit and a counter circuit. The adjustment circuit adjusts the output voltage according to a preset value. The detection circuit detects whether the output voltage is greater than an upper limit value or less than a lower limit value. The control circuit changes the preset value and disables the detection circuit when changing the preset value. When the detection circuit is disabled, the counter circuit starts to adjust a count value. When the counter circuit adjusts the count value, the control circuit proportionally adjusts the upper limit value and the lower limit value according to the output voltage. When the count value is equal to a target value, the counter circuit enables the detection circuit.

[0005] The present invention further provides a control method, including generating an output voltage according to a preset value; changing the preset value; disabling an overvoltage protection circuit and an undervoltage protection circuit, wherein the overvoltage protection circuit determines whether the output voltage exceeds an upper limit value, and the undervoltage protection circuit determines whether the output voltage is less than a lower limit value; performing a timing operation; adjusting the upper limit value and the lower limit value; when the timing operation time reaches a target value, stopping adjusting the upper limit value and the lower limit value and stopping disabling the overvoltage protection circuit and the undervoltage protection circuit.

[0006] The control method of the present invention can be implemented through the power supply circuit of the present invention, which is hardware or firmware that can execute specific functions, or can be recorded in a recording medium in the form of a program and implemented in combination with specific hardware. When the program is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a power supply circuit for implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic diagram of the operating system of the present invention.

[0008] Figure 2 Schematic diagram of the dynamic protection circuit of the present invention.

[0009] Figure 3 Schematic diagram of the detection circuit of the present invention.

[0010] Figure 4 It is a flow chart of the control method of the present invention.

[0011] Explanation of symbols

[0012] 100: Operating System

[0013] 110: Power supply circuit

[0014] 120: External device

[0015] 130: Conversion circuit

[0016] 140: Processing circuit

[0017] 150: Switch

[0018] 160: Dynamic protection circuit

[0019] VBUS: output voltage

[0020] VEX: External Power Supply

[0021] VDC: DC power supply

[0022] 141: Rectifier

[0023] 142: Transformer

[0024] 143: Optocoupler

[0025] Vin, VCOMP, CC1, CC2, Din+, Din-, VIN_G: Pin

[0026] VP: Process voltage

[0027] CP: Primary coil

[0028] CN: Secondary coil

[0029] 170: Connection port

[0030] 180: Microcontroller circuit

[0031] 190: Bus

[0032] VCC: voltage

[0033] 111: Current detection device

[0034] 112: Temperature detection device

[0035] 210: Adjustment circuit

[0036] 220: Detection circuit

[0037] 230: Control circuit

[0038] 240: Counter circuit

[0039] P_VA: Preset value

[0040] S_CP: Compensation signal

[0041] U_VA: Upper limit value

[0042] L_VA: Lower limit value

[0043] S_OFF: Turn off signal

[0044] C_VA: count value

[0045] T_VA: Target value DETAILED DESCRIPTION

[0046] In order to make the purpose, features and advantages of the present invention more clearly understood, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the embodiments are for the purpose of simplifying the description and do not mean the relevance between different embodiments.

[0047] Figure 1 Schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 100 includes a power supply circuit 110 and an external device 120. The power supply circuit 110 generates an output voltage VBUS and provides the output voltage VBUS to the external device 120. The external device 120 uses the output voltage VBUS as its own system power supply. After the external device 120 receives the output voltage VBUS, the external device 120 operates normally. In some embodiments, the power supply circuit 110 may adjust the output voltage VBUS according to a request issued by another external device (not shown).

[0048] In this embodiment, the external device 120 has a connection port (not shown) for receiving the output voltage VBUS. In other embodiments, the external device 120 communicates with the power supply circuit 110 through the connection port. In this example, the external device 120 issues a voltage request. The power supply circuit 110 adjusts the level of the output voltage VBUS according to the voltage request issued by the external device 120.

[0049] The power supply circuit 110 includes a conversion circuit 130, a processing circuit 140, a switch 150 and a dynamic protection circuit 160. The conversion circuit 130 converts an external power source VEX into a DC power source VDC. The present invention does not limit the type of the external power source VEX. In one possible embodiment, the external power source VEX may be an AC power source. In this example, the conversion circuit 130 is an AC / DC converter. In another possible embodiment, the external power source VEX is a DC power source. In this example, the conversion circuit 130 is a DC / DC converter. The conversion circuit 130 converts the voltage value of the external power source VEX and uses the converted power source as the DC power source VDC. The present invention does not limit the architecture of the conversion circuit 130. Any circuit that can convert power can be used as the conversion circuit 130.

[0050] The processing circuit 140 processes the DC power source VDC to generate an output voltage VBUS. In one possible embodiment, the processing circuit 140 includes a rectifier 141, a transformer 142, and an optical coupler 143. The rectifier 141 has a pin Vin for receiving the DC power source VDC. The rectifier 141 rectifies the DC power source VDC to generate a processing voltage VP. In another possible embodiment, the rectifier 141 further has a pin VCOMP. The rectifier 141 adjusts the processing voltage VP according to the voltage level of the pin VCOMP. In this example, when the voltage level of the pin VCOMP increases, the rectifier 141 increases the processing voltage VP. When the voltage level of the pin VCOMP decreases, the rectifier 141 reduces the processing voltage VP. The present invention does not limit the circuit architecture of the rectifier 141. Any circuit with a rectification function can be used as the rectifier 141.

[0051] The transformer 142 generates an output voltage VBUS according to the processing voltage VP. In the present embodiment, the transformer 142 has a primary coil CP and a secondary coil CN. When the processing voltage VP enters the primary coil CP, the secondary coil CN generates an induced voltage. In this example, the induced voltage is used as the output voltage VBUS. When the processing voltage VP increases, the output voltage VBUS also increases. When the processing voltage VP decreases, the output voltage VBUS also decreases. In one possible embodiment, the transformer 142 further includes at least one capacitor (not shown) for storing the induced voltage. In this example, the voltage of the capacitor is used as the output voltage VBUS.

[0052] The optocoupler 143 is used to adjust the process voltage VP. In some embodiments, when the optocoupler 143 is enabled, the optocoupler 143 adjusts the process voltage VP, such as increasing the process voltage VP. When the optocoupler 143 is not enabled, the optocoupler 143 stops adjusting the process voltage VP. In some embodiments, the optocoupler 143 controls the voltage level of the pin VCOMP of the rectifier 141. In this example, the rectifier 141 adjusts the process voltage VP according to the voltage level of the pin VCOMP.

[0053] The switch 150 is used to transmit the output voltage VBUS. In the present embodiment, when the switch 150 is turned on, the switch 150 transmits the output voltage VBUS to the connection port 170. When the switch 150 is not turned on, the switch 150 stops transmitting the output voltage VBUS to the connection port 170. The present invention does not limit the type of the switch 150. In one possible embodiment, the switch 150 is an N-type transistor. In other embodiments, the connection port 170 is a universal serial bus (USB) Type C connection port.

[0054] The dynamic protection circuit 160 controls the processing circuit 140 and the switch 150 to generate an appropriate output voltage VBUS. In one embodiment, the dynamic protection circuit 160 detects the output voltage VBUS. When the output voltage VBUS does not reach a target voltage, the dynamic protection circuit 160 enables the optical coupler 143 to increase the output voltage VBUS. When the output voltage VBUS reaches the target voltage, the dynamic protection circuit 160 stops enabling the optical coupler 143. In some embodiments, when the output voltage VBUS reaches the target voltage, the dynamic protection circuit 160 turns on the switch 150.

[0055] In the present embodiment, the dynamic protection circuit 160 has an overvoltage protection function and an undervoltage protection function. For example, when the output voltage VBUS exceeds an upper limit, it indicates that an overvoltage event occurs. Therefore, the dynamic protection circuit 160 does not turn on the switch 150 to prevent the output voltage VBUS from damaging the external device 120. When the output voltage VBUS is lower than a lower limit, it indicates that an undervoltage event occurs. Therefore, the dynamic protection circuit 160 does not turn on the switch 150 to prevent the external device 120 from malfunctioning. When the output voltage VBUS does not exceed the upper limit and is not lower than the lower limit, it indicates that the output voltage VBUS is normal. Therefore, the dynamic protection circuit 160 turns on the switch 150. The switch 150 provides the output voltage VBUS to the external device 120. In the present embodiment, the dynamic protection circuit 160 is coupled to the switch 150 through the pin VIN_G.

[0056] In other embodiments, the power supply circuit 110 further includes a microcontroller circuit (MCU) 180. The MCU 180 communicates with the dynamic protection circuit 160 via an inter-integrated circuit (I2C) bus 190. The MCU 180 may request the dynamic protection circuit 160 to adjust the output voltage VBUS. In addition, the dynamic protection circuit 160 may provide the voltage VCC to the MCU 180. The MCU 180 uses the voltage VCC as its own system voltage.

[0057] In some embodiments, the dynamic protection circuit 160 receives a request signal (not shown) from the external device 120 through the connection port 170. For example, the dynamic protection circuit 160 has at least pins CC1, CC2, Din+, and Din-. The dynamic protection circuit 160 receives a request signal from the external device 120 through at least one of the pins CC1, CC2, Din+, and Din-. In this example, the dynamic protection circuit 160 decodes the request signal and outputs the decoding result to the micro-control circuit 180. The micro-control circuit 180 generates a response signal (not shown) according to the request of the external device 120. The dynamic protection circuit 160 encodes the response signal and outputs the encoding result to the external device 120 through at least one of the pins CC1, CC2, Din+, and Din-. In one possible embodiment, the dynamic protection circuit 160 dynamically adjusts the output voltage VBUS according to the response signal generated by the micro-control circuit 180.

[0058] In other embodiments, the power supply circuit 110 further includes a current detection device 111. The current detection device 111 detects whether an overcurrent phenomenon occurs. When an overcurrent phenomenon occurs, the dynamic protection circuit 160 suspends operation, for example, stops supplying power to the external device 120 and the micro-control circuit 180. In another possible embodiment, the power supply circuit 110 further includes a temperature detection device 112. The dynamic protection circuit 160 knows whether the internal temperature of the power supply circuit 110 exceeds a preset value based on the detection result of the temperature detection device 112. When the internal temperature of the power supply circuit 110 exceeds a preset value, the dynamic protection circuit 160 suspends operation.

[0059] Figure 2 Schematic diagram of the dynamic protection circuit 160 of the present invention. The dynamic protection circuit 160 includes an adjustment circuit 210, a detection circuit 220, a control circuit 230 and a counter circuit 240. The adjustment circuit 210 adjusts the output voltage VBUS according to a preset value P_VA. Different preset values ​​P_VA correspond to different target voltages. In one possible embodiment, the preset value P_VA is stored in the adjustment circuit 210 in advance and adjusted by an external circuit (independent of the adjustment circuit 210). In some embodiments, the preset value P_VA is provided by a micro-control circuit outside the dynamic protection circuit 160. The micro-control circuit may use the I2C bus to write the preset value P_VA into a digital-to-analog converter (not shown) of the adjustment circuit 210. In one possible embodiment, the adjustment circuit 210 has a register (not shown) for storing the preset value P_VA.

[0060] The adjustment circuit 210 receives the output voltage VBUS through the pin VIN, and sets a compensation signal S_CP according to the output voltage VBUS. For example, when the output voltage VBUS does not reach a target voltage, the adjustment circuit 210 enables the compensation signal S_CP and outputs the compensation signal S_CP through the pin CATH. In one possible embodiment, Figure 1 The optocoupler 143 is coupled to the pin CATH for receiving the compensation signal S_CP. In this example, the optocoupler 143 controls the voltage level of the pin VCOMP of the rectifier 141 according to the enabled compensation signal S_CP. The rectifier 141 increases the processing voltage VP according to the voltage level of the pin VCOMP. The transformer 142 increases the output voltage VBUS according to the increased processing voltage VP. When the output voltage VBUS reaches the target voltage, the adjustment circuit 210 stops enabling the compensation signal S_CP. The optocoupler 143 stops adjusting the voltage level of the pin VCOMP. At this time, the output voltage VBUS is equal to the target voltage. The present invention does not limit the architecture of the adjustment circuit 210. Any circuit that can adjust the output voltage VBUS can be used as the adjustment circuit 210.

[0061] The detection circuit 220 detects whether the output voltage VBUS is greater than an upper limit value U_VA or less than a lower limit value L_VA. In one possible embodiment, the upper limit value U_VA and the lower limit value L_VA are pre-written into the detection circuit 220 and adjusted by an external circuit (independent of the detection circuit 220). In some embodiments, the detection circuit 220 has two registers (not shown) to store the upper limit value U_VA and the lower limit value L_VA respectively. In other embodiments, the upper limit value U_VA and the lower limit value L_VA are provided by a micro-control circuit outside the dynamic protection circuit 160 or provided by the control circuit 230.

[0062] In some embodiments, when the output voltage VBUS is greater than the upper limit value U_VA or less than the lower limit value L_VA, it indicates that the output voltage VBUS is abnormal. Therefore, the detection circuit 220 enables a shutdown signal S_OFF. When the output voltage VBUS is not greater than the upper limit value U_VA and not less than the lower limit value L_VA, it indicates that the output voltage VBUS is not abnormal. Therefore, the detection circuit 220 does not enable the shutdown signal S_OFF. In a possible embodiment, the detection circuit 220 outputs the shutdown signal S_OFF through the pin VIN_G to control an external switch.

[0063] by Figure 1 For example, the switch 150 is coupled to the pin VIN_G. When the shutdown signal S_OFF is enabled, the switch 150 is not turned on to stop transmitting the output voltage VBUS to the connection port 170. When the shutdown signal S_OFF is not enabled, the switch 150 is turned on to transmit the output voltage VBUS to the connection port 170.

[0064] The control circuit 230 is coupled to the adjustment circuit 210 and the detection circuit 220. In one possible embodiment, the control circuit 230 writes a preset value P_VA into the adjustment circuit 210, and writes an upper limit value U_VA and a lower limit value L_VA into the detection circuit 220. In this embodiment, while the control circuit 230 changes the preset value P_VA, the control circuit 230 disables the detection circuit 220. When the detection circuit 220 is disabled, the control circuit 230 proportionally adjusts the upper limit value U_VA and the lower limit value L_VA.

[0065] In some embodiments, the control circuit 230 appropriately adjusts the upper limit value U_VA and the lower limit value L_VA according to the output voltage VBUS. For example, when the output voltage VBUS increases, the control circuit 230 increases the upper limit value U_VA and the lower limit value L_VA. In one possible embodiment, the upper limit value U_VA and the lower limit value L_VA increase by the same amount as the output voltage VBUS increases. Similarly, when the output voltage VBUS decreases, the control circuit 230 decreases the upper limit value U_VA and the lower limit value L_VA. In one possible embodiment, the upper limit value U_VA and the lower limit value L_VA decrease by the same amount as the output voltage VBUS decreases. In some embodiments, the control circuit 230 waits until the output voltage VBUS is stable (i.e., the output voltage VBUS has reached the target voltage), and then adjusts the upper limit value U_VA and the lower limit value L_VA according to the amplitude of the change in the output voltage VBUS.

[0066] In other embodiments, when the detection circuit 220 is disabled, the control circuit 230 adjusts the upper limit value U_VA and the lower limit value L_VA according to the preset value P_VA. For example, when the new preset value is greater than the original preset value, the control circuit 230 increases the upper limit value U_VA and the lower limit value L_VA. When the new preset value is less than the original preset value, the control circuit 230 decreases the upper limit value U_VA and the lower limit value L_VA.

[0067] The present invention does not limit how the control circuit 230 adjusts the upper limit value U_VA and the lower limit value L_VA according to the preset value P_VA. In one possible embodiment, the control circuit 230 uses a preset formula to calculate the preset value P_VA to generate an overvoltage protection value and an undervoltage protection value. In this example, the control circuit 230 uses the overvoltage protection value as the upper limit value U_VA and the undervoltage protection value as the lower limit value L_VA. In another possible embodiment, the control circuit 230 uses a lookup table to find an overvoltage protection value and an undervoltage protection value corresponding to the preset value P_VA. Different preset values ​​correspond to different overvoltage protection values ​​and different undervoltage protection values. In this example, the control circuit 230 uses the overvoltage protection value as the upper limit value U_VA and the undervoltage protection value as the lower limit value L_VA.

[0068] In some embodiments, the control circuit 230 changes the preset value P_VA according to a control instruction (not shown). Figure 1 For example, the microcontroller circuit 180 generates a control instruction and provides the control instruction to the control circuit 230 via the I2C bus 190. In this example, the control circuit 230 changes the preset value P_VA according to the control instruction. In other embodiments, the control circuit 230 adjusts the upper limit value U_VA and the lower limit value L_VA according to the control instruction.

[0069] When the detection circuit 220 is disabled, the counter circuit 240 starts to adjust a count value C_VA. In one possible embodiment, when the control circuit 230 disables the detection circuit 220, the control circuit 230 enables the counter circuit 240, so that the counter circuit 240 starts to adjust the count value C_VA. In some embodiments, before enabling the counter circuit 240, the control circuit 230 resets the counter circuit 240 to set the count value C_VA equal to an initial value. Then, the counter circuit 240 starts to adjust the count value C_VA again.

[0070] When the counter circuit 240 adjusts the count value C_VA, the control circuit 230 proportionally adjusts the upper limit value U_VA and the lower limit value L_VA. When the count value C_VA is equal to a target value T_VA, the counter circuit 240 enables the detection circuit 220. In another possible embodiment, when the count value C_VA is equal to the target value T_VA, the control circuit 230 enables the detection circuit 220. After the detection circuit 220 is enabled, the detection circuit 220 determines whether the output voltage VBUS is between the upper limit value U_VA and the lower limit value L_VA. When the output voltage VBUS is greater than the upper limit value U_VA or less than the lower limit value L_VA, the detection circuit 220 enables the shutdown signal S_OFF.

[0071] In one possible embodiment, the target value T_VA is provided by the control circuit 230. In this example, when the control circuit 230 adjusts the preset value P_VA, the control circuit 230 also adjusts the target value T_VA. Different preset values ​​P_VA correspond to different target values ​​T_VA. After setting the target value T_VA, the control circuit 230 restarts the counter circuit 240. When the count value C_VA is equal to the target value T_VA, the counter circuit 240 stops adjusting the count value C_VA, and the control circuit 230 stops adjusting the upper limit value U_VA and the lower limit value L_VA. The detection circuit 220 determines whether the output voltage VBUS exceeds the upper limit value U_VA or is less than the lower limit value L_VA based on the adjusted upper limit value U_VA and the lower limit value L_VA.

[0072] Figure 3Schematic diagram of the detection circuit 220 of the present invention. The detection circuit 200 includes a voltage divider circuit 310, processing circuits 320A, 320B, comparators 330A, 330B, digital de-bounce circuits 340A, 340B, and a logic circuit 350. The voltage divider circuit 310 divides the output voltage VBUS to generate voltages V1 and V2. In one possible embodiment, the voltage divider circuit 310 has a plurality of series resistors to generate a plurality of divided voltages. In this example, the voltage divider circuit 310 uses one of the divided voltages as the voltage V1 and uses the other of the divided voltages as the voltage V2 according to a control signal S_CT. In some embodiments, the control signal S_CT is provided by the control circuit 230.

[0073] The processing circuit 320A generates an upper limit value U_VA according to the voltage V1. The processing circuit 320B generates a lower limit value L_VA according to the voltage V2. The present invention does not limit the architecture of the processing circuits 320A and 320B. In one possible embodiment, the processing circuits 320A and 320B are storage circuits. The processing circuit 320A stores the voltage V1 and uses the voltage V1 as the upper limit value U_VA. The processing circuit 320B stores the voltage V2 and uses the voltage V2 as the lower limit value L_VA. In another possible embodiment, the processing circuits 320A and 320B are digital-to-analog converters (DACs). In this example, the processing circuit 320A converts the voltage V1 and uses the conversion result as the upper limit value U_VA, and the processing circuit 320B converts the voltage V2 and uses the conversion result as the lower limit value L_VA.

[0074] The comparator 330A generates a comparison signal S_CP1 according to the output voltage VBUS and the upper limit value U_VA. The comparator 330B generates a comparison signal S_CP2 according to the output voltage VBUS and the lower limit value L_VA. In one possible embodiment, the comparators 330A and 330B are coupled to the pin VIN to receive the output voltage VBUS. In another possible embodiment, the voltage divider circuit 310 divides the output voltage VBUS to generate a voltage V3. In this example, the comparator 330A compares the voltage V3 with the upper limit value U_VA to generate the comparison signal S_CP1. In addition, the comparator 330B compares the voltage V3 with the lower limit value L_VA to generate the comparison signal S_CP2. In some embodiments, even if the output voltage VBUS is higher, since the voltage divider circuit 310 reduces the output voltage VBUS and uses the reduction result as the voltage V3, the comparators 330A and 330B do not need to withstand high voltage.

[0075] The digital anti-bounce circuit 340A processes the comparison signal S_CP1 to generate a processing signal S_P1. The digital anti-bounce circuit 340B processes the comparison signal S_CP2 to generate a processing signal S_P2. In some embodiments, the digital anti-bounce circuits 340A and 340B may be omitted. In this example, the logic circuit 350 directly receives the comparison signals S_CP1 and S_CP2.

[0076] The logic circuit 350 sets the shutdown signal S_OFF according to the processing signals S_P1 and S_P2. In the present embodiment, the logic circuit 350 further receives an overvoltage function signal OVP_Gate_EN and an undervoltage function signal UVP_Gate_EN. The overvoltage function signal OVP_Gate_EN and the undervoltage function signal UVP_Gate_EN are controlled by an external circuit (independent of the detection circuit 220). In a possible embodiment, the control circuit 230 provides the overvoltage function signal OVP_Gate_EN and the undervoltage function signal UVP_Gate_EN.

[0077] Taking the overvoltage function signal OVP_Gate_EN as an example, the control circuit 230 may set the overvoltage function signal OVP_Gate_EN to a specific level (such as a low level) to disable the overvoltage function signal OVP_Gate_EN. Therefore, the logic circuit 350 suspends an overvoltage detection operation. However, when the overvoltage function signal OVP_Gate_EN is not a specific level (for example, the overvoltage function signal OVP_Gate_EN is a high level), it indicates that the overvoltage function signal OVP_Gate_EN is enabled. Therefore, the logic circuit 350 performs an overvoltage detection operation. At this time, when the voltage V3 is greater than the upper limit value U_VA, it indicates that an overvoltage event has occurred. Therefore, the logic circuit 350 enables the shutdown signal S_OFF. However, when the voltage V3 is not greater than the upper limit value U_VA, it indicates that no overvoltage event has occurred. Therefore, the logic circuit 350 does not enable the shutdown signal S_OFF.

[0078] In another possible embodiment, when the undervoltage function signal UVP_Gate_EN is enabled, the logic circuit 350 performs an undervoltage detection operation. When the voltage V3 is less than the lower limit value L_VA, it indicates that an undervoltage event has occurred. Therefore, the logic circuit 350 enables the shutdown signal S_OFF. However, when the voltage V3 is not less than the lower limit value L_VA, it indicates that an undervoltage event has not occurred. Therefore, the logic circuit 350 does not enable the shutdown signal S_OFF. In some embodiments, when the undervoltage function signal UVP_Gate_EN is not enabled, the logic circuit 350 suspends the undervoltage detection operation.

[0079] In other embodiments, when the overvoltage function signal OVP_Gate_EN and the undervoltage function signal UVP_Gate_EN are both enabled, the logic circuit 350 performs an overvoltage detection operation and an undervoltage detection operation. When an overvoltage event or an undervoltage event occurs, the logic circuit 350 enables the shutdown signal S_OFF. When neither the overvoltage event nor the undervoltage event occurs, the logic circuit 350 does not enable the shutdown signal S_OFF.

[0080] In some embodiments, when the control circuit 230 changes the preset value P_VA, the control circuit 230 does not enable the overvoltage function signal OVP_Gate_EN and the undervoltage function signal UVP_Gate_EN. Therefore, the logic circuit 350 suspends the overvoltage detection operation and the undervoltage detection operation. In this example, the control circuit 230 adjusts the upper limit value U_VA and the lower limit value L_VA through the control signal S_CT, and starts the counter circuit 240. When the counter circuit 240 completes a counting operation (that is, the count value of the counter circuit 240 reaches a target value T_VA), the counter circuit 240 enables the overvoltage function signal OVP_Gate_EN and the undervoltage function signal UVP_Gate_EN. In another possible embodiment, when the counter circuit 240 completes a counting operation, the counter circuit 240 notifies the control circuit 230, so that the control circuit 230 enables the overvoltage function signal OVP_Gate_EN and the undervoltage function signal UVP_Gate_EN.

[0081] In this embodiment, the logic circuit 350 includes logic gates 351-354. The logic gate 351 generates a processing signal S_P3 according to the processing signal S_P1 and the overvoltage function signal OVP_Gate_EN. In other embodiments, when the digital anti-bounce circuit 340A is omitted, the logic gate 351 generates the processing signal S_P3 according to the comparison signal S_CP1 and the overvoltage function signal OVP_Gate_EN. In this embodiment, the logic gate 351 is an AND gate. In one possible embodiment, the comparator 330A and the logic gate 351 constitute an overvoltage protection circuit.

[0082] The logic gate 352 generates a processing signal S_P4 according to the processing signal S_P2 and the undervoltage function signal UVP_Gate_EN. In other embodiments, when the digital anti-bounce circuit 340B is omitted, the logic gate 352 generates the processing signal S_P4 according to the comparison signal S_CP2 and the undervoltage function signal UVP_Gate_EN. In this embodiment, the logic gate 352 is an AND gate. In a possible embodiment, the comparator 330B and the logic gate 352 constitute an undervoltage protection circuit.

[0083] The logic gate 353 receives the processing signals S_P3 and S_P4. The logic gate 354 controls the shutdown signal S_OFF according to the output of the logic gate 353. In some embodiments, the logic gate 354 further receives a setting signal PVIN_EN. When the setting signal PVIN_EN is not enabled, the logic gate 354 does not enable the shutdown signal S_OFF. In this embodiment, the logic gate 353 is an OR gate, and the logic gate 354 is an AND gate.

[0084] Figure 4 4 is a flow chart of the control method of the present invention. The control method of the present invention may exist in the form of a program. When the program is loaded and executed by a machine, the machine becomes a power supply circuit for implementing the present invention. First, an output voltage is generated according to a preset value (step S411). Different preset values ​​correspond to different output voltages. In a possible embodiment, the power supply circuit provides the output voltage to an external device. In this example, the external device is a power receiving device.

[0085] Next, the preset value is changed (step S412), and an overvoltage protection circuit and an undervoltage protection circuit are disabled (step S413). The present invention does not limit the order of steps S412 and S413. In one possible embodiment, steps S412 and S413 are performed simultaneously. In another possible embodiment, step S412 may be performed earlier than step S413, or later than step S413.

[0086] In one possible embodiment, an external device may issue a voltage request, requiring the power supply circuit to change the output voltage, such as increasing the output voltage. In this case, the power supply circuit decodes the voltage request and adjusts the preset value according to the decoding result. Since the output voltage is related to the preset value, when the preset value is adjusted, the output voltage also changes accordingly.

[0087] In another possible embodiment, the overvoltage protection circuit operates according to an overvoltage function signal, and the undervoltage protection circuit operates according to an undervoltage function signal. In this example, when the overvoltage function signal is enabled, the overvoltage protection circuit starts to determine whether an output voltage exceeds an upper limit value. When the overvoltage function signal is not enabled, the overvoltage protection circuit stops determining whether an output voltage exceeds an upper limit value. Similarly, when the undervoltage function signal is enabled, the undervoltage protection circuit starts to determine whether an output voltage is less than a lower limit value. When the undervoltage function signal is not enabled, the undervoltage protection circuit stops determining whether an output voltage is less than a lower limit value.

[0088] Then, a timing operation is performed (step S414). In one possible embodiment, step S414 enables a counter circuit. After being enabled, the counter circuit performs a counting operation, such as adjusting a count value according to the number of pulses of a clock signal. When the count value of the counter circuit reaches a target value, the counter circuit stops operating. In some embodiments, step S412 further provides a target value to the counter circuit. In this example, different preset values ​​may correspond to different target values.

[0089] Adjust an upper limit value and a lower limit value (step S415). In one possible embodiment, step S415 adjusts the upper limit value and the lower limit value in proportion to the new preset value. In this example, whenever the preset value is changed, the upper limit value of the overvoltage protection circuit and the lower limit value of the undervoltage protection circuit are adjusted in proportion. Step S415 may substitute the new preset value into a specific formula to calculate and generate a corresponding overvoltage protection value and an undervoltage protection value. In this example, step S415 writes the overvoltage protection value into the overvoltage protection circuit, and writes the undervoltage protection value into the undervoltage protection circuit. In another possible embodiment, step S415 uses a lookup table to obtain a corresponding overvoltage protection value and an undervoltage protection value. In this example, the lookup table records multiple preset values, each of which corresponds to an overvoltage protection value and an undervoltage protection value.

[0090] Next, it is determined whether the time of the timing operation reaches a target value (step S416). In one possible embodiment, step S416 determines whether the count value of a counter reaches a target value. When the time of the timing operation reaches a target value, steps S417 and S418 are executed. Step S417 stops adjusting the upper limit value and the lower limit value. Step S418 starts the overvoltage protection circuit and the undervoltage protection circuit. In one possible embodiment, step S418 enables the overvoltage function signal and the undervoltage function signal. Therefore, the overvoltage protection circuit operates according to the adjusted upper limit value, and the undervoltage protection circuit operates according to the adjusted lower limit value.

[0091] Since the upper limit and lower limit of the power supply circuit change with the preset value, when the power supply circuit adjusts the output voltage according to a request signal, the power supply circuit first suspends the overvoltage protection function and the undervoltage protection function. After adjusting the upper limit of the overvoltage protection circuit and the lower limit of the undervoltage protection circuit, the power supply circuit restarts the overvoltage protection function and the undervoltage protection function. Since the time point of adjusting the upper limit and the lower limit of the power supply circuit is similar to the time point of adjusting the output voltage, the power supply circuit can immediately and appropriately perform the overvoltage protection function and the undervoltage protection function.

[0092] The control method of the present invention, or a specific form or part thereof, may exist in the form of a program. The program may be stored in a physical medium, such as a floppy disk, a CD, a hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product not limited to an external form, wherein when the program is loaded and executed by a machine, such as a computer, the machine becomes used to participate in the power supply circuit of the present invention. The program may also be transmitted through some transmission medium, such as wires or cables, optical fibers, or any transmission mode, wherein when the program is received, loaded and executed by a machine, such as a computer, the machine becomes used to participate in the power supply circuit of the present invention. When implemented in a general-purpose processing unit, the program combines with the processing unit to provide a unique device that operates similarly to an application-specific logic circuit.

[0093] Unless otherwise defined, all words (including technical and scientific words) herein are generally understood by those with ordinary knowledge in the technical field to which the present invention belongs. In addition, unless expressly indicated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in the relevant technical field, and should not be interpreted as an ideal state or overly formal tone. Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0094] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the definition of the claims.

Claims

1. A dynamic protection circuit, characterized in that: include: an adjusting circuit, adjusting an output voltage according to a preset value; a detection circuit, detecting whether the output voltage is greater than an upper limit value or less than a lower limit value; a control circuit, which changes the preset value and disables the detection circuit when changing the preset value; and a counter circuit, which starts adjusting a count value when the detection circuit is disabled; in: When the counter circuit adjusts the count value, the control circuit adjusts the upper limit value and the lower limit value in proportion to the output voltage; When the count value is equal to a target value, the counter circuit enables the detection circuit.

2. The dynamic protection circuit according to claim 1, characterized in that: The detection circuit includes: a voltage divider circuit for dividing the output voltage to generate a first voltage and a second voltage; a first digital-to-analog converter, generating the upper limit value according to the first voltage; and A second digital-to-analog converter generates the lower limit value according to the second voltage.

3. The dynamic protection circuit according to claim 2, characterized in that: The detection circuit further comprises: a first comparator, generating a first comparison signal according to the output voltage and the upper limit value; a second comparator, generating a second comparison signal according to the output voltage and the lower limit value; and A logic circuit enables a shutdown signal according to the first comparison signal and the second comparison signal.

4. The dynamic protection circuit according to claim 3, characterized in that: The voltage divider circuit divides the output voltage to generate a third voltage, the first comparator compares the third voltage with the upper limit value to generate the first comparison signal, and the second comparator compares the third voltage with the lower limit value to generate the second comparison signal.

5. The dynamic protection circuit according to claim 3, characterized in that: The detection circuit further comprises: a first digital anti-bounce circuit, processing the first comparison signal to generate a first processed signal; and a second digital anti-bounce circuit, processing the second comparison signal to generate a second processed signal; The logic circuit enables the shutdown signal according to the first processing signal and the second processing signal.

6. A power supply circuit, characterized in that: include: a conversion circuit, converting an external power source into a DC power source; a processing circuit for processing the DC power supply to generate an output voltage; a switch for transmitting the output voltage; as well as A dynamic protection circuit comprising: an adjustment circuit, adjusting the output voltage according to a preset value; a detection circuit, detecting whether the output voltage is greater than an upper limit value or less than a lower limit value; a control circuit, which changes the preset value and disables the detection circuit when changing the preset value; and a counter circuit, which starts adjusting a count value when the detection circuit is disabled; in: When the counter circuit adjusts the count value, the control circuit adjusts the upper limit value and the lower limit value in proportion to the output voltage; When the count value is equal to a target value, the counter circuit enables the detection circuit.

7. The power supply circuit according to claim 6, characterized in that: The processing circuit comprises: a rectifier for rectifying the DC power supply to generate a processing voltage; a transformer having a primary coil and a secondary coil, wherein when the processing voltage enters the primary coil, the secondary coil generates the output voltage; and An optical coupler is used to adjust the process voltage.

8. The power supply circuit according to claim 7, characterized in that: The adjustment circuit controls the optical coupler according to the output voltage.

9. The power supply circuit according to claim 8, characterized in that: When the output voltage does not reach a target voltage, the adjustment circuit enables the optical coupler to adjust the process voltage. When the output voltage reaches the target voltage, the adjustment circuit stops enabling the optical coupler to stop adjusting the process voltage.

10. A control method, characterized in that: include: Generate an output voltage according to a preset value; changing the preset value; disabling an overvoltage protection circuit and an undervoltage protection circuit, wherein the overvoltage protection circuit determines whether the output voltage exceeds an upper limit value, and the undervoltage protection circuit determines whether the output voltage is less than a lower limit value; performing a timing operation; adjusting the upper limit value and the lower limit value; When the duration of the timing operation reaches a target value: Stop adjusting the upper limit value and the lower limit value; as well as Stop disabling the overvoltage protection circuit and the undervoltage protection circuit.

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