A fast discharge circuit applicable to high-voltage LDO and its discharge method

Abstract

The present invention discloses a fast discharge circuit applicable to a high-voltage LDO and its discharge method, which includes PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, current source I0, and Zener diode Z2. The sources of PMOS transistors M1, M2, and M3 are connected to the input power supply Vin, and PMOS transistors M1, M2, and M3 form a current mirror. The drain of NMOS transistor M4 and NMOS transistor M6 form a current mirror. The input signal EN controls NMOS transistor M7, and the Zener diode Z2 limits the gate voltage of NMOS transistor M5. The present invention can achieve the fast discharge function of the output signal Vout in the off state of the high-voltage LDO with a small off-state current and a simple circuit structure.

Description

Technical Field

[0001] The present invention relates to a discharge circuit and a discharge method thereof, in particular to a fast discharge circuit and a discharge method thereof suitable for a high-voltage LDO, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] To meet the requirements of high-voltage application scenarios, it is usually necessary to use a high-voltage LDO to provide a stable power supply voltage for various electronic devices. Generally, a large capacitor of the uF level is connected to the output stage, which causes slow discharge at the output when the high-voltage LDO is powered off and can still continue to provide power for subsequent devices for a period of time, resulting in disordered power-on and power-off timings of subsequent devices and abnormal functions. To solve this problem, a conventional method is to connect a fast discharge branch to the output stage of the high-voltage LDO to ensure that the power output can be quickly pulled down when powered off.

[0003] As Figure 2 shown, in the traditional high-voltage LDO structure, the pre-voltage-dividing circuit converts the power supply Vin into an internal power supply voltage VDD to provide a suitable power supply voltage for the low-voltage part in the high-voltage LDO. Among them, the input signal EN controls the working state of the pull-down mos tube M5 of the output Vout through an inverter. When the input signal EN is low, that is, in the circuit off state, the input signal EN outputs a high level through the inverter to turn on the mos tube M5 to quickly discharge the output Vout. However, this requires the internal power supply voltage VDD to remain high in the LDO off state, increasing the leakage path of the power supply to the ground in the LDO off state, which will greatly increase the off-current of the entire high-voltage LDO. Therefore, the traditional high-voltage LDO cannot simultaneously achieve both low off-current and fast discharge of the output Vout in the off state. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a fast discharge circuit and a discharge method thereof suitable for a high-voltage LDO to achieve the fast discharge function of the output signal Vout in the off state of the high-voltage LDO with a relatively small off-current.

[0005] To solve the above technical problem, the technical solution adopted by the present invention is:

[0006] A fast discharge circuit applicable to a high-voltage LDO, including PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, current source I0 and Zener diode Z2. The source electrodes of PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 are connected to the input power supply Vin. The gate electrode of PMOS transistor M1 is connected to the drain electrode of PMOS transistor M1, one end of current source I0, the gate electrode of PMOS transistor M2 and the gate electrode of PMOS transistor M3. The drain electrode of PMOS transistor M2 is connected to the drain electrode of NMOS transistor M4, the gate electrode of NMOS transistor M4 and the gate electrode of NMOS transistor M6. The drain electrode of PMOS transistor M3 is connected to the drain electrode of NMOS transistor M6, the cathode of Zener diode Z2 and the gate electrode of NMOS transistor M5. The source electrode of NMOS transistor M6 is connected to the drain electrode of NMOS transistor M7. The gate electrode of NMOS transistor M7 is connected to the input signal EN. The drain electrode of NMOS transistor M5 is connected to the output signal Vout. The other end of current source I0, the source electrode of NMOS transistor M4, the source electrode of NMOS transistor M7, the anode of Zener diode Z2 and the source electrode of NMOS transistor M5 are grounded. Among them, the pulling-down ability of NMOS transistor M6 is stronger than the pulling-up ability of PMOS transistor M3.

[0007] Further, a gate protection circuit is provided at the gate electrode of NMOS transistor M7.

[0008] Further, the gate protection circuit includes resistor R1 and Zener diode Z1. One end of resistor R1 is connected to the input signal EN. The other end of resistor R1 is connected to the cathode of Zener diode Z1 and the gate electrode of NMOS transistor M7. The anode of Zener diode Z1 is grounded.

[0009] Further, the gate voltage of NMOS transistor M7 does not exceed voltage V Z1 and voltage V Z1 is equal to the reverse breakdown voltage of Zener diode Z1.

[0010] Further, the width-to-length ratios of PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 are the same. The number ratio of PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 is 1:1:m. Let the currents flowing through PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 be I1, I2 and I3 respectively, and the current of current source I0 be I0. Then I3 = m * I2 = m * I1 = m * I0.

[0011] Further, the width-to-length ratios of NMOS transistor M4 and NMOS transistor M6 are the same. The number ratio of NMOS transistor M4 and NMOS transistor M6 is 1:n. Let the currents flowing through NMOS transistor M4 and NMOS transistor M6 be I4 and I6 respectively. Then I6 = n * I4 = n * I0, and n > m.

[0012] A discharging method based on a fast discharging circuit applicable to a high-voltage LDO, comprising the following steps:

[0013] When the input signal EN is at a high level, the high-voltage LDO is in a normal operating state, and the NMOS transistor M7 operates in the linear region, that is, the NMOS transistor M7 is turned on. At this time, the branch where the PMOS transistor M3 is located and the branch where the NMOS transistor M6 is located are turned on simultaneously. Since the pulling-down ability of the NMOS transistor M6 is stronger than the pulling-up ability of the PMOS transistor M3, the gate voltage of the NMOS transistor M5 is pulled down to ground by the NMOS transistor M6 at this time, and the NMOS transistor M5 is in an off state, having no influence on the output signal Vout, and the output signal Vout is normally output;

[0014] When the input signal EN is at a low level, the high-voltage LDO is in an off state, and the NMOS transistor M7 operates in the cut-off region, that is, the NMOS transistor M7 is turned off. At this time, the branch where the PMOS transistor M3 is located is turned on while the branch where the NMOS transistor M6 is located is turned off. The gate of the NMOS transistor M5 is pulled up to the voltage V Z2 by the PMOS transistor M3, and the voltage V Z2 is equal to the reverse breakdown voltage of the Zener diode Z2. The NMOS transistor M5 is in an on state, providing a fast discharging path for the output signal Vout of the high-voltage LDO in the circuit off state.

[0015] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a fast discharging circuit applicable to a high-voltage LDO and its discharging method. The control signal for pulling down the NMOS transistor M5 is generated in the voltage domain of the input signal Vin. In the circuit off state, even if the internal power supply voltage VDD after pre-voltage division is at a low level, the NMOS transistor M5 can still be normally turned on to quickly discharge the output signal Vout. The present invention can achieve the fast discharging function of the output signal Vout in the off state of the high-voltage LDO with a small off-state current and a simple circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a fast discharging circuit applicable to a high-voltage LDO according to the present invention.

[0017] Figure 2 is a schematic diagram of a prior art high-voltage LDO with a fast discharging path. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] To elaborate in detail on the technical solutions adopted by the present invention to achieve the predetermined technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments. Moreover, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0019] As Figure 1 shown, a fast discharge circuit applicable to a high-voltage LDO of the present invention includes PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, current source I0, and Zener diode Z2. The source electrodes of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are connected to the input power supply Vin. The gate electrode of PMOS transistor M1 is connected to the drain electrode of PMOS transistor M1, one end of current source I0, the gate electrode of PMOS transistor M2, and the gate electrode of PMOS transistor M3. The drain electrode of PMOS transistor M2 is connected to the drain electrode of NMOS transistor M4, the gate electrode of NMOS transistor M4, and the gate electrode of NMOS transistor M6. The drain electrode of PMOS transistor M3 is connected to the drain electrode of NMOS transistor M6, the cathode of Zener diode Z2, and the gate electrode of NMOS transistor M5. The source electrode of NMOS transistor M6 is connected to the drain electrode of NMOS transistor M7. The gate electrode of NMOS transistor M7 is connected to the input signal EN. The drain electrode of NMOS transistor M5 is connected to the output signal Vout. The other end of current source I0, the source electrode of NMOS transistor M4, the source electrode of NMOS transistor M7, the anode of Zener diode Z2, and the source electrode of NMOS transistor M5 are grounded, where the pulling-down ability of NMOS transistor M6 is stronger than the pulling-up ability of PMOS transistor M3.

[0020] The Zener diode Z2 makes the gate voltage of NMOS transistor M5 not higher than the voltage V Z2 , and the voltage V Z2 is equal to the reverse breakdown voltage of the Zener diode Z2. Therefore, during actual operation, since the input signal Vin is relatively large, when the gate of NMOS transistor M5 is at a high level, it is equal to the voltage V Z2 , so that even if the input signal Vin is larger than the internal voltage VDD, the stable and safe operation of the circuit can be ensured.

[0021] A gate protection circuit is provided at the gate of NMOS transistor M7. The gate protection circuit includes resistor R1 and Zener diode Z1. One end of resistor R1 is connected to the input signal EN, and the other end of resistor R1 is connected to the cathode of Zener diode Z1 and the gate electrode of NMOS transistor M7. The anode of Zener diode Z1 is grounded.

[0022] The gate voltage of NMOS transistor M7 does not exceed voltage V Z1 and voltage V Z1 is equal to the reverse breakdown voltage of Zener diode Z1, thereby protecting NMOS transistor M7.

[0023] PMOS transistors M1, M2, and M3 have the same width-to-length ratio, and the number ratio of PMOS transistors M1, M2, and M3 is 1:1:m. Let the currents flowing through PMOS transistors M1, M2, and M3 be I1, I2, and I3 respectively, and the current of current source I0 be I0. Then I3 = m * I2 = m * I1 = m * I0.

[0024] NMOS transistors M4 and M6 have the same width-to-length ratio, and the number ratio of NMOS transistors M4 and M6 is 1:n. Let the currents flowing through NMOS transistors M4 and M6 be I4 and I6 respectively. Then I6 = n * I4 = n * I0, and n > m, that is, the pulling-down ability of NMOS transistor M6 is stronger than the pulling-up ability of PMOS transistor M3.

[0025] A discharging method based on a fast discharging circuit applicable to a high-voltage LDO includes the following steps:

[0026] When the input signal EN is at a high level, the high-voltage LDO is in a normal working state, and NMOS transistor M7 operates in the linear region and can be regarded as a switch transistor in the conducting state, that is, NMOS transistor M7 is conducting. At this time, the branch where PMOS transistor M3 is located and the branch where NMOS transistor M6 is located are both conducting. Since the pulling-down ability of NMOS transistor M6 is stronger than the pulling-up ability of PMOS transistor M3, the gate voltage of NMOS transistor M5 is pulled down to ground by NMOS transistor M6 at this time, and NMOS transistor M5 is in the off state, having no influence on the output signal Vout, and the output signal Vout is normally output.

[0027] When the input signal EN is at a low level, the high-voltage LDO is in the off state, and NMOS transistor M7 operates in the cut-off region and can be regarded as a switch transistor in the off state, that is, NMOS transistor M7 is off. At this time, the branch where PMOS transistor M3 is located is conducting while the branch where NMOS transistor M6 is located is off, and the gate of NMOS transistor M5 is pulled up to voltage V Z2 and voltage V Z2 is equal to the reverse breakdown voltage of Zener diode Z2, and NMOS transistor M5 is in the on state, providing a fast discharging path for the output signal Vout of the high-voltage LDO in the circuit off state.

[0028] A fast discharge circuit applicable to a high-voltage LDO according to the present invention uses the input signal Vin as the input voltage instead of the VDD generated inside the high-voltage LOD. In this way, even if the VDD becomes low level when the high-voltage LDO is turned off, it will not affect the operation of the fast discharge circuit applicable to the high-voltage LDO of the present invention.

[0029] The present invention provides a fast discharge circuit applicable to a high-voltage LDO and its discharge method. The control signal of the pull-down NMOS transistor M5 is generated in the voltage domain of the input signal Vin. In the circuit off state, even if the internal power supply voltage VDD after pre-voltage division is at a low level, the NMOS transistor M5 can still be normally turned on to quickly discharge the output signal Vout. The present invention can achieve the fast discharge function of the output signal Vout in the off state of the high-voltage LDO with a small off-state current and a simple circuit structure.

[0030] The above are only the preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention and is based on the technical essence of the present invention, any simple modification, equivalent replacement, and improvement made to the above embodiments still fall within the protection scope of the technical solution of the present invention.

Claims

1. A fast discharge circuit applicable to a high-voltage LDO, characterized in that: It includes PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, current source I0 and Zener diode Z2. The sources of PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 are connected to input power supply Vin. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M1, one end of current source I0, the gate of PMOS transistor M2 and the gate of PMOS transistor M3. The drain of PMOS transistor M2 is connected to the drain of NMOS transistor M4, the gate of NMOS transistor M4 and the gate of NMOS transistor M6. The drain of PMOS transistor M3 is connected to the drain of NMOS transistor M6, the cathode of Zener diode Z2 and the gate of NMOS transistor M5. The source of NMOS transistor M6 is connected to the drain of NMOS transistor M7. The gate of NMOS transistor M7 is connected to input signal EN. The drain of NMOS transistor M5 is connected to output signal Vout. The other end of current source I0, the source of NMOS transistor M4, the source of NMOS transistor M7, the anode of Zener diode Z2 and the source of NMOS transistor M5 are grounded. Among them, the pulling-down ability of NMOS transistor M6 is stronger than the pulling-up ability of PMOS transistor M3. When input signal EN is at a high level, the high-voltage LDO is in a normal working state, and NMOS transistor M5 is in an off state, which has no influence on output signal Vout, and output signal Vout is normally output. When input signal EN is at a low level, the high-voltage LDO is in an off state, and NMOS transistor M5 is in an on state, providing a fast discharge path for output signal Vout of the high-voltage LDO in the circuit off state.

2. The fast discharge circuit applicable to a high-voltage LDO according to claim 1, wherein: A gate protection circuit is provided at the gate of the NMOS transistor M7.

3. The fast discharge circuit for high-voltage LDO according to claim 2, characterized in that: The gate protection circuit includes resistor R1 and Zener diode Z1. One end of resistor R1 is connected to input signal EN, and the other end of resistor R1 is connected to the cathode of Zener diode Z1 and the gate of NMOS transistor M7. The anode of Zener diode Z1 is grounded.

4. The fast discharge circuit applicable to a high-voltage LDO according to claim 3, wherein: The gate voltage of the NMOS transistor M7 does not exceed the voltage V Z1 , and the voltage V Z1 is equal to the reverse breakdown voltage of the Zener diode Z1.

5. A fast discharge circuit applicable to a high-voltage LDO according to claim 1, characterized in that: The width-to-length ratios of PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 are the same, and the number ratio of PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 is 1:1:m. Let the currents flowing through PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 be I1, I2 and I3 respectively, and the current of current source I0 be I0. Then I3 = m * I2 = m * I1 = m * I0.

6. The fast discharge circuit applicable to a high-voltage LDO according to claim 5, characterized in that: The width-to-length ratios of NMOS transistor M4 and NMOS transistor M6 are the same, and the number ratio of NMOS transistor M4 and NMOS transistor M6 is 1:n. Let the currents flowing through NMOS transistor M4 and NMOS transistor M6 be I4 and I6 respectively. Then I6 = n * I4 = n * I0, and n > m.

7. A discharging method for a fast discharging circuit applicable to a high-voltage LDO according to any one of claims 1-6, characterized in that It includes the following steps: When the input signal EN is at a high level, the high-voltage LDO is in a normal operating state, and the NMOS transistor M7 operates in the linear region, that is, the NMOS transistor M7 is turned on. At this time, the branch where the PMOS transistor M3 is located and the branch where the NMOS transistor M6 are located are turned on simultaneously. Since the pulling-down ability of the NMOS transistor M6 is stronger than the pulling-up ability of the PMOS transistor M3, the gate voltage of the NMOS transistor M5 is pulled down to ground by the NMOS transistor M6 at this time, and the NMOS transistor M5 is in an off state, which has no effect on the output signal Vout, and the output signal Vout is normally output; When the input signal EN is at a low level, the high-voltage LDO is in the off state, and the NMOS transistor M7 operates in the cut-off region, that is, the NMOS transistor M7 is turned off. At this time, the branch where the PMOS transistor M3 is located is turned on while the branch where the NMOS transistor M6 is located is turned off. The gate of the NMOS transistor M5 is pulled up to the voltage V Z2 by the PMOS transistor M3. The voltage V Z2 is equal to the reverse breakdown voltage of the Zener diode Z2, and the NMOS transistor M5 is in the on state, providing a fast discharge path for the output signal Vout of the high-voltage LDO in the circuit off state.

Images