Driving circuit

Abstract

The embodiment of the invention provides a driving circuit and a method thereof. The drive circuit comprises: an input stage configured to provide a control signal for the drive circuit; a delay stage coupled to the input stage and configured to apply a delay to the control signal provided by the input stage to generate a delayed control signal; a first output stage coupled to the input stage and the delay stage, configured to immediately output a first level in response to the control signal becoming a high level, and configured to delay output of the first level based on a delay control signal in response to the control signal becoming a low level; and a second output stage coupled to the input stage and the delay stage, configured to delay to output a second level based on the delayed control signal in response to the control signal becoming a high level, and configured to immediately output the second level in response to the control signal becoming a low level.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and more particularly, to a driving circuit with adjustable dead time. Background Art

[0002] Metal-oxide semiconductor field effect transistors (MOSFETs) are often used in buck circuits to replace diodes due to their low on-resistance and high switching speed to improve the efficiency and switching speed of buck circuits. Usually, for the drive circuit, a high-side MOSFET and a low-side MOSFET form a half-bridge circuit, and using MOSFETs instead of diodes, the drive of the buck circuit is converted into the drive of the half-bridge circuit. One half-bridge circuit can drive the buck circuit, two half-bridge circuits can form an H-bridge circuit to control a DC brush motor, and three half-bridge circuits can form a control circuit for a three-phase DC brushless motor to control a three-phase motor. Therefore, driving a half-bridge circuit is a prerequisite for driving a buck circuit or driving a motor.

[0003] Existing solutions usually design the half-bridge drive circuit into an integrated chip, but the integrated half-bridge drive solution is often highly specialized, and the drive dead time of the high-voltage side and the low-voltage side cannot be adjusted by hardware. In addition, each half-bridge drive usually requires two PWM controls, which will occupy more hardware resources in actual use. Summary of the invention

[0004] An embodiment of the present application provides a driving circuit, comprising: an input stage, configured to provide a control signal for the driving circuit; a delay stage, coupled to the input stage and configured to apply a delay to the control signal provided by the input stage to generate a delayed control signal; a first output stage, coupled to the input stage and the delay stage, configured to immediately output a first level in response to the control signal becoming a high level, and configured to delay the output of the first level based on the delayed control signal in response to the control signal becoming a low level; and a second output stage, coupled to the input stage and the delay stage, configured to delay the output of a second level based on the delayed control signal in response to the control signal becoming a high level, and configured to immediately output the second level in response to the control signal becoming a low level.

[0005] An embodiment of the present application provides a method for controlling a circuit, comprising: receiving a control signal; applying a delay to the control signal to generate a delayed control signal; immediately outputting a first level in response to the control signal becoming a high level, and delaying the output of the first level based on the delayed control signal in response to the control signal becoming a low level; and delaying the output of a second level based on the delayed control signal in response to the control signal becoming a high level, and immediately outputting the second level in response to the control signal becoming a low level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solution of the embodiment of the present application, the following briefly describes the drawings involved in the embodiment of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In the drawings:

[0007] Figure 1 shows a schematic structural diagram of a driving circuit according to an embodiment of the present application;

[0008] Figure 2 Another schematic structural diagram of a driving circuit according to an embodiment of the present application is shown;

[0009] Figure 3 A schematic circuit diagram of a driving circuit according to an embodiment of the present application is shown;

[0010] Figure 4 A timing diagram of a driving circuit according to an embodiment of the present application is shown; and

[0011] Figure 5 A flow chart of a method for controlling a circuit according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0012] The features and exemplary embodiments of various aspects of the application will be described in detail below. In order to make the purpose, scheme, and advantages of the application clearer, the details of the application are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and are not intended to limit the application. For those skilled in the art, the application can be implemented without some of the details in these specific details. The following description of the embodiments is only to provide a better understanding of the application by illustrating the example of the application.

[0013] It should be noted that, in this article, relational terms such as first, second, third, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. In addition, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, including a process, method, article or device of a series of elements not only including these elements, but also including other elements not explicitly listed, or also including elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the statement "include..." do not exclude the presence of other elements in the process, method, article or device including the elements.

[0014] Embodiments of the present application will now be described with reference to the accompanying drawings. Figure 1, shows a schematic structural diagram of a driving circuit 100 according to an embodiment of the present application. Figure 1 As shown, in some embodiments, the driving circuit 100 may include an input stage 110 , a delay stage 120 , a first output stage 130 , and a second output stage 140 .

[0015] like Figure 1 As shown, in some embodiments, the input stage 110 may be configured to provide a control signal to the driving circuit 100. In some embodiments, the delay stage 120 may be coupled to the input stage 110 and configured to apply a delay to the control signal provided by the input stage 110 to generate a delayed control signal.

[0016] like Figure 1 As shown, in some embodiments, the first output stage 130 may be coupled to the input stage 110 and the delay stage 120, and configured to output the first level immediately in response to the control signal becoming a high level, and configured to output the first level with a delay based on the delay control signal in response to the control signal becoming a low level. In some embodiments, the second output stage 140 may be coupled to the input stage 110 and the delay stage 120, and configured to output the second level with a delay based on the delay control signal in response to the control signal becoming a high level, and configured to output the second level immediately in response to the control signal becoming a low level.

[0017] In some embodiments, the first level may be one of a high level and a low level, the second level may also be one of a high level and a low level, and the high level of the first level may be different from the high level of the second level. For example, the high level of the first level may be 24V, and the high level of the second level may be 12V. It will be appreciated by those skilled in the art that the high level of the first level and the high level of the second level may be any other suitable voltage value. In some embodiments, for example, the low level of the first level and the second level may be 0V.

[0018] According to an embodiment of the present application, the delay stage 120 may be configured to add a delay to the input control signal of the driving circuit 100 , and by adjusting the parameters of the delay stage 120 , the dead time of the output driving signal of the driving circuit 100 may be adjusted.

[0019] refer to Figure 2 , shows a more detailed schematic structural diagram of the driving circuit 100 according to an embodiment of the present application. Figure 2 As shown, the input stage 110 of the driving circuit 100 may include an input module 1101 , an output terminal of the input module 1101 may be configured to be used as an output terminal of the input stage 110 , and the input module 1101 may be configured to provide a control signal for the driving circuit 100 .

[0020] In some embodiments, Figure 2 As shown, the delay stage 120 of the driving circuit 100 may include a delay module 1201 and a switch circuit 1202, wherein the input end of the delay module 1201 may be configured to be used as the input end of the delay stage 120, and the output end of the delay module 1201 may be coupled to the input end of the switch circuit 1202. The first input end of the first output stage 130 of the driving circuit 100 may be coupled to the output end of the input stage 110 (i.e., the input module 1101), and the second input end of the first output stage 130 may be coupled to the output end of the delay module 1201. In addition, the first input end of the second output stage 140 of the driving circuit 100 may be coupled to the output end of the input stage 110 (i.e., the input module 1101), and the second input end of the second output stage 140 may be coupled to the output end of the switch circuit 1202.

[0021] In some embodiments, Figure 2 As shown, the first output stage 130 may include a first logic circuit 1301, a first input terminal of the first logic circuit 1301 may be configured to be used as the first input terminal of the first output stage 130, and a second input terminal of the first logic circuit 1301 may be configured to be used as the second input terminal of the first output stage 130. In addition, in some embodiments, the first output stage 130 may further include a first amplification circuit 1302 and a first output module 1303, an input terminal of the first amplification circuit 1302 may be coupled to an output terminal of the first logic circuit 1301, and an input terminal of the first output module 1303 may be coupled to an output terminal of the first amplification circuit 1302. In some embodiments, the first output module 1302 may be configured to output a first level.

[0022] In some embodiments, Figure 2 As shown, the second output stage 140 may include a second logic circuit 1401, a first input terminal of the second logic circuit 1401 may be configured to be used as the first input terminal of the second output stage 140, and a second input terminal of the second logic circuit 1401 may be configured to be used as the second input terminal of the second output stage 140. In addition, in some embodiments, the second output stage 140 may further include a second amplification circuit 1402 and a second output module 1403, an input terminal of the second amplification circuit 1402 may be coupled to the output terminal of the second logic circuit 1401, and an input terminal of the second output module 1403 may be coupled to the output terminal of the second amplification circuit 1402. In some embodiments, the second output module 1403 may be configured to output a second level.

[0023] refer to Figure 3 , shows a schematic circuit diagram of a driving circuit 100 according to an embodiment of the present application. In some embodiments, Figure 3As shown, the input module 1101 can be configured as a control signal input source of the driving circuit 100 (in Figure 3 For example, the input module 1101 may be configured to provide a pulse width modulation (PWM) signal as a control signal for the drive circuit 100, and the specific amplitude and frequency of the PWM signal may be set based on the actual design requirements of the drive circuit 100. Those skilled in the art will appreciate that the input module 110 may also be configured to provide any other suitable control signal for the drive circuit 100.

[0024] In some embodiments, Figure 3 As shown, the delay module 1201 may include a first resistor R3 and a first capacitor C1, wherein a first end of the first resistor R3 is coupled to an output end of the input stage 110 (i.e., the input module 1101), a second end of the first resistor R3 is coupled to a first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded. For the delay module 1201, the resistance value of the first resistor R3 and the capacitance value of the first capacitor C1 may be set based on the actual design requirements of the driving circuit 100, for example, the first resistor R3 may be 350Ω, and the first capacitor C1 may be 10n. In some embodiments, as Figure 3 As shown, the first end of the first resistor R3 can be configured as the input end of the delay module 1201 , and the second end of the first resistor R3 (or the first end of the first capacitor C1 ) can be configured as the output end of the delay module 1201 .

[0025] Those skilled in the art will understand that Figure 3 The delay module 1201 shown including the first resistor R3 and the first capacitor C1 is only an example of a delay module that can be applied to the present application. The delay module of the present application is not limited to this configuration, and any form of delay module can be applied to the present application and is within the scope of the present application.

[0026] In some embodiments, Figure 3 As shown, the switching circuit 1202 may include a second resistor R19, a third resistor R15 and a first transistor M1, wherein a first end of the second resistor R19 is coupled to a second end of the first resistor R3 and a first end of the first capacitor C1 and is coupled to a source of the first transistor M1, a second end of the second resistor R19 is coupled to a first end of the third resistor R15 and a gate of the first transistor M1, and a second end of the third resistor R15 is grounded.

[0027] As described above, in the delay module 1201, the second end of the first resistor R3 is coupled to the first end of the first capacitor C1, so the first end of the second resistor R19 can be coupled to both the second end of the first resistor R3 and the first end of the first capacitor C1, and coupled to the source of the first transistor M1. Figure 3 As shown, the first end of the second resistor R19 can be configured as an input end of the switch circuit 1202 , and the drain of the first transistor M1 can be configured as an output end of the switch circuit 1202 .

[0028] For the switch circuit 1202, the resistance values ​​of the second resistor R19 and the third resistor R15 can be set based on the actual design requirements of the driving circuit 100. For example, the second resistor R19 can be 1 kΩ, and the third resistor R15 can be 3 kΩ. In addition, in an embodiment, the type of the first transistor M1 can be selected based on the actual design requirements of the driving circuit 100. For example, the first transistor M1 can be a PMOS transistor, such as Figure 3 shown.

[0029] In some embodiments, Figure 3 As shown, the first logic circuit 1301 of the first output stage 130 may include a first diode D1, a second diode D2, a fourth resistor R5, a fifth resistor R1, a second transistor Q1 and a sixth resistor R2, wherein the anode of the first diode D1 is coupled to the output end of the input stage 110 (i.e., the input module 1101), the anode of the second diode D2 is coupled to the second end of the first resistor R3 (and the first end of the first capacitor C1), the first end of the fourth resistor R5 is coupled to both the cathode of the first diode D1 and the cathode of the second diode D2, the second end of the fourth resistor R5 is coupled to the first end of the fifth resistor R1 and the base of the second transistor Q1, the second end of the fifth resistor R1 is coupled to the emitter of the second transistor Q1 and is grounded, the collector of the second transistor Q1 is coupled to the first end of the sixth resistor R2, and the second end of the sixth resistor R2 is coupled to the power supply voltage V2.

[0030] As described above, in the delay module 1201, the second end of the first resistor R3 is coupled to the first end of the first capacitor C1, so the anode of the second diode D2 can be coupled to both the second end of the first resistor R3 and the first end of the first capacitor C1. Figure 3 As shown, the anode of the second diode D2 is also coupled to the first end of the second resistor R19 in the switch circuit 1202 and the source of the first transistor M1. Figure 3 As shown, the anode of the first diode D1 and the anode of the second diode D2 can be configured as the first input terminal and the second input terminal of the first logic circuit 1301 respectively, and the output terminal of the first logic circuit 1301 can be derived from the collector of the second transistor Q1 and the first end of the sixth resistor R2.

[0031] For the first logic circuit 1301, the resistance values ​​of the fourth resistor R5, the fifth resistor R1 and the sixth resistor R2 can be set according to the actual design requirements of the driving circuit 100. For example, the fourth resistor R5 can be 2kΩ, the fifth resistor R1 can be 2kΩ, and the sixth resistor R2 can be 2kΩ. In addition, in an embodiment, the type of the second transistor Q1 can be selected based on the actual design requirements of the driving circuit 100. For example, the second transistor Q1 can be an NPN transistor, such as Figure 3 In addition, for example, the power supply voltage V2 may be a 5V power supply voltage.

[0032] In some embodiments, Figure 3 As shown, the first amplifier circuit 1302 of the first output stage 130 may include an eighth resistor R11, a fifth transistor Q10, a ninth resistor R12, a tenth resistor R13, and a sixth transistor Q11, wherein a first end of the eighth resistor R11 is coupled to the collector of the second transistor Q1 in the first logic circuit 1301 and the first end of the sixth resistor R2 and is coupled to the base of the fifth transistor Q10, a second end of the eighth resistor R11 is coupled to the emitter of the fifth transistor Q10 and is grounded, a collector of the fifth transistor Q10 is coupled to the first end of the ninth resistor R12, a second end of the ninth resistor R12 is coupled to the first end of the tenth resistor R13 and the base of the sixth transistor Q11, and a second end of the tenth resistor R13 is coupled to the power supply voltage V4 and the emitter of the sixth transistor Q11. Figure 3 As shown, the emitter of the sixth transistor Q11 may also be coupled to the power supply voltage V4.

[0033] like Figure 3 As shown, the first end of the eighth resistor R11 (and the base of the fifth transistor Q10) can be configured as the input end of the first amplifier circuit 1302, and the output end of the first amplifier circuit 1302 can be derived from the collector of the sixth transistor Q11. For the first amplifier circuit 1302, the resistance values ​​of the eighth resistor R11, the ninth resistor R12 and the tenth resistor R13 can be set based on the actual design requirements of the driving circuit 100. For example, the eighth resistor R11 can be 2kΩ, the ninth resistor R12 can be 10kΩ, and the tenth resistor R13 can be 2kΩ. In addition, in an embodiment, the types of the fifth transistor Q10 and the sixth transistor Q11 can be selected based on the actual design requirements of the driving circuit 100. For example, the fifth transistor Q10 can be an NPN transistor, and the sixth transistor Q11 can be a PNP transistor, such as Figure 3 In addition, for example, the power supply voltage V4 may be a 24V power supply voltage.

[0034] In some embodiments, Figure 3As shown, the first output module 1303 of the first output stage 130 may include an eleventh resistor R14, a fourth diode D4 and a seventh transistor Q12, wherein a first end of the eleventh resistor R14 is coupled to the collector of the sixth transistor Q11 in the first amplifying circuit 1302 and is coupled to the anode of the fourth diode D4 and the base of the seventh transistor Q12, a second end of the eleventh resistor R14 is grounded, a cathode of the fourth diode D4 is coupled to the emitter of the seventh transistor Q12, and the collector of the seventh transistor Q12 is grounded.

[0035] like Figure 3 As shown, the first end of the eleventh resistor R14 (as well as the anode of the fourth diode D4 and the base of the seventh transistor Q12) can be configured as the input end of the first output module 1303, and the output end ( Figure 3 The output voltage (shown as out1) can be drawn from the cathode of the fourth diode D4 and the emitter of the seventh transistor Q12. For the first output module 1303, the resistance value of the eleventh resistor R14 can be set based on the actual design requirements of the drive circuit 100. For example, the eleventh resistor R14 can be 10 kΩ. In addition, in an embodiment, the type of the seventh transistor Q12 can be selected based on the actual design requirements of the drive circuit 100. For example, the seventh transistor Q12 can be a PNP transistor, such as Figure 3 shown.

[0036] In some embodiments, Figure 3 As shown, the second logic circuit 1401 of the second output stage 140 may include a third diode D7, a third transistor Q6, a fourth transistor Q5 and a seventh resistor R18, wherein the anode of the third diode D7 is coupled to the output end of the input stage 110 (i.e., the input module 1101), the cathode of the third diode D7 is coupled to the base of the third transistor Q6, the emitter of the third transistor Q6 is coupled to the collector of the fourth transistor Q5, the base of the fourth transistor Q5 is coupled to the drain of the first transistor M1, the emitter of the fourth transistor Q5 is coupled to the first end of the seventh resistor R18, and the second end of the seventh resistor R18 is grounded. In addition, as Figure 3 As shown, the collector of the third transistor Q6 can be coupled to the enable signal EN of the driving circuit 100 .

[0037] In some embodiments, Figure 3As shown, the anode of the third diode D7 and the base of the fourth transistor Q5 can be configured as the first input terminal and the second input terminal of the second logic circuit 1401, respectively, and the output terminal of the second logic circuit 1401 can be derived from the emitter of the fourth transistor Q5 and the first end of the seventh resistor R18. For the second logic circuit 1401, the resistance value of the seventh resistor R18 can be set based on the actual design requirements of the driving circuit 100. For example, the seventh resistor R18 can be 4.7 kΩ. In addition, in an embodiment, the types of the third transistor Q6 and the fourth transistor Q5 can be selected based on the actual design requirements of the driving circuit 100. For example, the third transistor Q6 and the fourth transistor Q5 can both be NPN transistors, such as Figure 3 shown.

[0038] In some embodiments, Figure 3 As shown, the second amplifier circuit 1402 of the second output stage 140 may include a twelfth resistor R4, a thirteenth resistor R6, an eighth transistor Q2, a fourteenth resistor R7, a fifteenth resistor R8, and a ninth transistor Q3, wherein a first end of the twelfth resistor R4 is coupled to the emitter of the fourth transistor Q5 in the second logic circuit 1401 and a first end of the seventh resistor R18, a second end of the twelfth resistor R4 is coupled to a first end of the thirteenth resistor R6 and a base of the eighth transistor Q2, a second end of the thirteenth resistor R6 is coupled to the emitter of the eighth transistor Q2 and is grounded, a collector of the eighth transistor Q2 is coupled to a first end of the fourteenth resistor R7, a second end of the fourteenth resistor R7 is coupled to a first end of the fifteenth resistor R8 and a base of the ninth transistor Q3, and a second end of the fifteenth resistor R8 is coupled to a power supply voltage V1 and an emitter of the ninth transistor Q3. Figure 3 As shown, the emitter of the ninth transistor Q3 may also be coupled to the supply voltage V1.

[0039] like Figure 3 As shown, the first end of the twelfth resistor R4 can be configured to be used as the input end of the second amplifier circuit 1402, and the output end of the second amplifier circuit 1402 can be derived from the collector of the ninth transistor Q3. For the second amplifier circuit 1402, the resistance values ​​of the twelfth resistor R4, the thirteenth resistor R6, the fourteenth resistor R7 and the fifteenth resistor R8 can be set based on the actual design requirements of the drive circuit 100. For example, the twelfth resistor R4 can be 2kΩ, the thirteenth resistor R6 can be 2kΩ, the fourteenth resistor R7 can be 10kΩ, and the fifteenth resistor R8 can be 2kΩ. In addition, in an embodiment, the types of the eighth transistor Q2 and the ninth transistor Q3 can be selected based on the actual design requirements of the drive circuit 100. For example, the eighth transistor Q2 can be an NPN transistor, and the ninth transistor Q3 can be a PNP transistor, such as Figure 3In addition, for example, the power supply voltage V1 may be a 12V power supply voltage.

[0040] In some embodiments, Figure 3 As shown, the second output module 1403 of the second output stage 140 may include a sixteenth resistor R9, a fifth diode D5 and a tenth transistor Q4, wherein a first end of the sixteenth resistor R9 is coupled to the collector of the ninth transistor Q3 in the second amplifying circuit 1402 and coupled to the anode of the fifth diode D5 and the base of the tenth transistor Q4, a second end of the sixteenth resistor R9 is grounded, a cathode of the fifth diode D5 is coupled to the emitter of the tenth transistor Q4, and the collector of the tenth transistor Q4 is grounded.

[0041] like Figure 3 As shown, the first end of the sixteenth resistor R9 (as well as the anode of the fifth diode D5 and the base of the tenth transistor Q4) can be configured as the input end of the second output module 1403, and the output end ( Figure 3 The first output module 1403 is shown as out2 in the figure. ... Figure 3 shown.

[0042] Please refer to Figure 3 and Figure 4 , Figure 4 FIG. 1 shows a timing diagram of a driving circuit 100 in an example according to an embodiment of the present application. Specifically, Figure 4 An example is shown when the control signal provided by the input stage 110 of the driving circuit 100 is a PWM control signal with an amplitude of 5V and a frequency of 10K, and waveforms of the control signal of the driving circuit 100 (i.e., the PWM control signal, shown as V(input)), the first level output by the first output stage 130 (shown as V(output1)), and the second level output by the second output stage 140 (shown as V(output2)) are respectively shown.

[0043] like Figure 3 and Figure 4As shown, when the rising edge of the PWM control signal arrives, the high-level signal of the PWM control signal immediately reaches the base of the second transistor Q1 through the first diode D1, so that the second transistor Q1 is turned on, and the high-level signal of the PWM control signal also immediately reaches the base of the third transistor Q6 through the third diode D7. When the second transistor Q1 is turned on, the collector of the second transistor Q1 can be regarded as grounded, and the second transistor Q1 immediately outputs a low level through its collector. In addition, when the second transistor Q1 is turned on, the base of the fifth transistor Q10 can also be regarded as grounded, so that the fifth transistor Q10 is turned off. When the fifth transistor Q10 is turned off, the base voltage of the sixth transistor Q11 is approximately equal to the power supply voltage V4 (i.e., 24V), and at this time the sixth transistor Q11 is also turned off, and the voltage of the collector of the sixth transistor Q11 is pulled to the ground through the eleventh resistor R14, that is, a low level. At this time, the seventh transistor Q12 is turned on.

[0044] Therefore, when the rising edge of the PWM control signal arrives, the first logic circuit 1301 immediately outputs a low level, and the first amplifier circuit 1302 also outputs a low level. At this time, the level of the output end (i.e., out1) of the first output module 1303 is also a low level, that is, the first output stage 130 immediately outputs a low level, and the first level (V(output1)) is 0V.

[0045] As reference Figure 1-3 As shown, the delay stage 120 of the driving circuit 100 includes a delay module 1201 and a switch circuit 1202. Due to the delay effect of the delay module 1201, when the rising edge of the PWM control signal arrives, the first transistor M1 in the switch circuit 1202 is turned on after a delay period, and after the first transistor M1 is turned on, the high level signal of the PWM control signal reaches the base of the fourth transistor Q5.

[0046] As described above, when the rising edge of the PWM control signal arrives, the high-level signal of the PWM control signal immediately reaches the base of the third transistor Q6 through the third diode D7, and the high-level signal of the PWM control signal reaches the base of the fourth transistor Q5 after a delay period. Then, when the bases of the third transistor Q6 and the fourth transistor Q5 are both at a high level, the third transistor Q6 and the fourth transistor Q5 are turned on. Therefore, when the rising edge of the PWM control signal arrives, the emitter of the fourth transistor Q5 outputs a high level after a delay period, and at this time, the eighth transistor Q2 is turned on, so that the base of the ninth transistor Q3 is turned on at a low level, and the collector of the ninth transistor Q3 outputs a high level. At this time, the eighth transistor Q4 is turned off.

[0047] Therefore, when the rising edge of the PWM control signal arrives, the second logic circuit 1401 outputs a high level after a delay period, and then the second amplifier circuit 1402 outputs a high level. At this time, the level of the output end of the second output module 1403 (i.e., out2) is also a high level, that is, the second output stage 140 outputs a high level after a delay period, and the second level (V(output2)) is 12V.

[0048] In addition, if Figure 3 and Figure 4 As shown, when the falling edge of the PWM control signal arrives, due to the low level signal of the PWM control signal, the third diode D7 is turned off and the third transistor Q6 is turned off, and at this time the fourth transistor Q5 is also turned off, so that the emitter of the fourth transistor Q5 immediately outputs a low level. In this case, the eighth transistor Q2 and the ninth transistor Q3 are both turned off, so when the falling edge of the PWM control signal arrives, the collector of the ninth transistor Q3 also immediately outputs a low level. At this time, the eighth transistor Q4 is turned on.

[0049] Therefore, when the falling edge of the PWM control signal arrives, the second logic circuit 1401 immediately outputs a low level, and the second amplifier circuit 1402 also outputs a low level. At this time, the level of the output end of the second output module 1403 is also a low level, that is, the second output stage 140 immediately outputs a low level, and the second level is 0V.

[0050] However, due to the delay effect of the delay module 1201, when the falling edge of the PWM control signal arrives, the voltage of the first capacitor C1 does not immediately become zero but slowly decreases. When the voltage of the first capacitor C1 drops to the base voltage of the second transistor Q1 and the emitter junction of the second transistor Q1 cannot be turned on, the second transistor Q1 is turned off. Therefore, when the falling edge of the PWM control signal arrives, the second transistor Q1 is still turned on and turned off after the delay period, and the collector of the second transistor Q1 outputs a high level after the delay period. When the second transistor Q1 is turned off, the base voltage of the fifth transistor Q10 becomes a high level and the fifth transistor Q10 is turned on. At this time, the sixth transistor Q11 is also turned on, and the collector of the sixth transistor Q11 outputs a high level. At this time, the seventh transistor Q12 is turned off.

[0051] Therefore, when the falling edge of the PWM control signal arrives, the first logic circuit 1301 outputs a high level after a delay period, and then the first amplifier circuit 1302 outputs a high level. At this time, the level of the output end of the first output module 1303 is also a high level, that is, the first output stage 130 outputs a high level after a delay period, and the first level is 24V.

[0052] like Figure 4As shown, when the rising edge of the PWM control signal arrives, the first output stage 130 immediately outputs a low level (0V), and the second output stage 140 outputs a high level (12V) after a delay period; when the falling edge of the PWM control signal arrives, the second output stage 140 immediately outputs a low level (0V), and the first output stage 130 outputs a high level (24V) after a delay period. In the present application, the time period when the first level and the second level are both low levels is the dead time of the driving circuit 100, and its size can be adjusted by changing the parameters of the delay stage 120, for example, the resistance value and capacitance value of the resistor and capacitor included in the delay stage 120.

[0053] refer to Figure 5 , shows a flow chart of a method for controlling circuit 100 according to an embodiment of the present application. Figure 5 As shown, the method comprises the following steps:

[0054] Step S110: receiving a control signal;

[0055] Step S120: applying a delay to the control signal to generate a delayed control signal;

[0056] Step S130: immediately outputting the first level in response to the control signal becoming a high level, and delaying the outputting of the first level based on the delay control signal in response to the control signal becoming a low level;

[0057] Step S140 : outputting the second level with delay based on the delay control signal in response to the control signal becoming a high level, and outputting the second level immediately in response to the control signal becoming a low level.

[0058] In some embodiments, the first level may be one of a high level and a low level, the second level may also be one of a high level and a low level, and the high level of the first level may be different from the high level of the second level. For example, the high level of the first level may be 24V, and the high level of the second level may be 12V. It will be appreciated by those skilled in the art that the high level of the first level and the high level of the second level may be any other suitable voltage value. In some embodiments, for example, the low level of the first level and the second level may be 0V.

[0059] Although the present application shows and describes the steps of the method for controlling a circuit in a specific order, it should be understood that these steps can be performed in different order. Figure 5 Execute in the order shown.

[0060] According to the drive circuit and method provided by the embodiment of the present application, the drive circuit can be controlled by only one PWM control signal, which can simplify the circuit structure and reduce the use of hardware resources. The dead time of the high-voltage side drive and the low-voltage side drive of the drive circuit can be adjusted according to the actual application, and the adjustment is implemented by hardware, so the use of software resources can also be reduced. In addition, the drive circuit according to the embodiment of the present application has a wide range of applications, for example, it can be used for each drive circuit such as half-bridge drive, H-bridge drive, three-phase bridge drive, and the like, and compared with the form of an integrated chip, the cost of the drive circuit according to the embodiment of the present application is lower.

[0061] Those skilled in the art will appreciate that the present application is not limited to the specific structures and steps described above and shown in the accompanying drawings. For the sake of simplicity, the description of known structures and methods is omitted herein. In the above-described embodiments, several specific steps are described and shown as examples. However, the method of the present application is not limited to the specific steps described and shown, and without departing from the scope of the present application, those skilled in the art can make various changes, modifications and additions to the embodiments of the present application, or change the order between the steps.

[0062] The functional blocks shown in the above structured block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), suitable firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. These programs or code segments can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. A machine-readable medium can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0063] The above disclosures are only some specific implementation methods of the present application. Those skilled in the art will appreciate that, for the convenience and brevity of description, the specific working processes of the above systems, modules, and units can refer to the corresponding processes in the method embodiments, which will not be described in detail herein. In addition, it should be understood that the protection scope of the present application is not limited thereto, and those skilled in the art can think of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and these equivalent modifications or substitutions are all covered within the protection scope of the present application.

Claims

1. A driving circuit, comprising: An input stage configured to provide a control signal to the driving circuit; a delay stage coupled to the input stage and configured to apply a delay to a control signal provided by the input stage to generate a delayed control signal; a first output stage coupled to the input stage and the delay stage, configured to output a first level immediately in response to the control signal becoming a high level, and configured to output the first level with a delay based on the delay control signal in response to the control signal becoming a low level; as well as A second output stage, coupled to the input stage and the delay stage, is configured to output a second level with delay based on the delay control signal in response to the control signal becoming a high level, and is configured to output the second level immediately in response to the control signal becoming a low level.

2. The driving circuit according to claim 1, wherein: The first level is one of a high level and a low level, and wherein the second level is one of a high level and a low level.

3. The driving circuit according to claim 1, wherein: The input stage includes: an input module configured to provide the control signal.

4. The driving circuit according to claim 1, wherein: The delay stage includes a delay module and a switch circuit, wherein an input terminal of the delay module is configured to be used as an input terminal of the delay stage, and an output terminal of the delay module is coupled to an input terminal of the switch circuit.

5. The driving circuit according to claim 4, wherein: The delay module includes a first resistor and a first capacitor, wherein a first end of the first resistor is coupled to an output end of the input stage, a second end of the first resistor is coupled to a first end of the first capacitor, and a second end of the first capacitor is grounded.

6. The driving circuit according to claim 5, wherein: The switching circuit includes a second resistor, a third resistor and a first transistor, the first end of the second resistor is coupled to the second end of the first resistor and the first end of the first capacitor and coupled to the source of the first transistor, the second end of the second resistor is coupled to the first end of the third resistor and the gate of the first transistor, and the second end of the third resistor is grounded.

7. The driving circuit according to claim 4, wherein: A first input of the first output stage is coupled to an output of the input stage, and a second input of the first output stage is coupled to an output of the delay module.

8. The driving circuit according to claim 5, wherein: The first output stage includes a first logic circuit, a first input terminal of the first logic circuit is configured to serve as a first input terminal of the first output stage, and a second input terminal of the first logic circuit is configured to serve as a second input terminal of the first output stage.

9. The driving circuit according to claim 8, wherein: The first logic circuit includes a first diode, a second diode, a fourth resistor, a fifth resistor, a second transistor and a sixth resistor, wherein an anode of the first diode is coupled to the output terminal of the input stage, an anode of the second diode is coupled to the second terminal of the first resistor, a first terminal of the fourth resistor is coupled to a cathode of the first diode and a cathode of the second diode, a second terminal of the fourth resistor is coupled to a first terminal of the fifth resistor and a base of the second transistor, a second terminal of the fifth resistor is coupled to an emitter of the second transistor and is grounded, a collector of the second transistor is coupled to a first terminal of the sixth resistor, and a second terminal of the sixth resistor is coupled to a power supply voltage.

10. The driving circuit according to claim 8, wherein: The first output stage further includes a first amplifying circuit and a first output module, the input end of the first amplifying circuit is coupled to the output end of the first logic circuit, and the input end of the first output module is coupled to the output end of the first amplifying circuit.

11. The driving circuit according to claim 10, wherein: The first output module is configured to output the first level.

12. The driving circuit according to claim 4, wherein: A first input terminal of the second output stage is coupled to an output terminal of the input stage, and a second input terminal of the second output stage is coupled to an output terminal of the switching circuit.

13. The driving circuit according to claim 6, wherein: The second output stage includes a second logic circuit, a first input terminal of the second logic circuit is configured to be used as a first input terminal of the second output stage, and a second input terminal of the second logic circuit is used as a second input terminal of the second output stage.

14. The driving circuit according to claim 13, wherein: The second logic circuit includes a third diode, a third transistor, a fourth transistor and a seventh resistor, the anode of the third diode is coupled to the output end of the input stage, the cathode of the third diode is coupled to the base of the third transistor, the emitter of the third transistor is coupled to the collector of the fourth transistor, the base of the fourth transistor is coupled to the drain of the first transistor, the emitter of the fourth transistor is coupled to the first end of the seventh resistor, and the second end of the seventh resistor is grounded.

15. The driving circuit according to claim 13, wherein: The second output stage further includes a second amplifying circuit and a second output module, an input terminal of the second amplifying circuit is coupled to an output terminal of the second logic circuit, and an input terminal of the second output module is coupled to an output terminal of the second amplifying circuit.

16. The driving circuit according to claim 15, wherein: The second output module is configured to output the second level.

17. A method for controlling a circuit, comprising: receiving a control signal; applying a delay to the control signal to generate a delayed control signal; immediately outputting a first level in response to the control signal becoming a high level, and delaying outputting the first level based on the delay control signal in response to the control signal becoming a low level; as well as The second level is output with delay based on the delay control signal in response to the control signal becoming a high level, and the second level is output immediately in response to the control signal becoming a low level.

18. The method according to claim 17, wherein: The first level is one of a high level and a low level, and wherein the second level is one of a high level and a low level.

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