A circuit and its control method for enhancing the input impedance of a chopper amplifier

Abstract

This application discloses a circuit and its control method for enhancing the input impedance of a chopper amplifier. The circuit includes an OTA operational amplifier module, a chopper module, an input capacitor, a feedback capacitor, a peak detector, a valley detector, a subtractor, a comparator integrator, and a variable capacitor. The method includes: acquiring a differential input signal and performing chopping and amplification processing to obtain an output signal; performing peak detection processing to obtain positive and negative peak voltages; performing subtraction calculations to obtain the peak-to-peak value of the OTA signal; performing integration and ripple filtering processing to obtain a DC voltage signal with amplitude information; converting it into a DC current signal with amplitude information, and performing current compensation on the differential input signal through a positive feedback loop. The embodiments of this application can accurately compensate for on-chip parasitic capacitances, thereby avoiding current draw from the signal source and enhancing the input impedance of the chopper capacitor-coupled instrumentation amplifier. This application can be widely applied in the field of analog integrated circuit design technology.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit design technology, and in particular to a circuit and control method for enhancing the input impedance of a chopper amplifier. Background Technology

[0002] Capacitively coupled instrumentation amplifiers (CAAs) are widely used in wearable medical devices due to their low noise and high power efficiency. Chopper stabilization techniques are typically used to assist CAAs in reducing flicker noise, thereby improving the system's noise efficiency ratio (NOR). However, in the input stage of this combined structure, the periodic charging and discharging of the amplifier's input capacitor by the chopper significantly reduces the amplifier's input impedance, leading to a degraded common-mode rejection ratio (CMRR) and severe signal amplitude attenuation. Simultaneously, the input impedance of the instrumentation amplifier is also limited by internal pin parasitics and the influence of the input stage. Internal pin parasitics typically originate from parasitic capacitances on the printed circuit board (PCB), pads, and on-chip ESD devices. These parasitics primarily exist between the amplifier's input parasitic capacitance and other nodes within the chip. These parasitics can all cause a decrease in input impedance, resulting in signal loss, phase shift, and circuit instability, which also contributes to a narrowing of the amplifier's operating frequency band.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to propose a circuit and control method for enhancing the input impedance of a chopper amplifier, which can accurately compensate for on-chip parasitic capacitance, thereby preventing the draw of current from the signal source and enhancing the input impedance of the chopper capacitor-coupled instrumentation amplifier.

[0005] To achieve the above objectives, one aspect of this application provides a circuit for enhancing the input impedance of a chopper amplifier. The circuit includes an OTA operational amplifier module, a chopper module, an input capacitor, a feedback capacitor, a peak detector, a valley detector, a subtractor, a comparator integrator, and a variable capacitor. The chopper module includes a first-stage chopper, a second-stage chopper, a third-stage chopper, and a fourth-stage chopper. The second terminal of the first-stage chopper is connected to the first terminal of the input capacitor and the first terminal of the variable capacitor, respectively. The second terminal of the input capacitor is connected to the first terminal of the feedback capacitor and the first terminal of the OTA operational amplifier module, respectively. The second terminal of the feedback capacitor is connected to... The first terminal of the third-stage chopper is connected to the first terminal of the second-stage chopper, the second terminal of the OTA operational amplifier module is connected to the first terminal of the second-stage chopper, the second terminal of the variable capacitor is connected to the first terminal of the fourth-stage chopper, the second terminal of the fourth-stage chopper, the second terminal of the third-stage chopper, the second terminal of the second-stage chopper, the input terminal of the peak detector, and the input terminal of the valley detector are all connected to the input terminal of the subtractor, the output terminal of the subtractor is connected to the input terminal of the comparator integrator, and the output terminal of the comparator integrator is connected to the input terminal of the variable capacitor, wherein:

[0006] The chopper module is used to chop the input differential signal to obtain the chopped input differential signal.

[0007] The OTA operational amplifier module is used to amplify the chopped input differential signal to obtain an amplified input differential signal.

[0008] The peak detector and the valley detector are used to perform peak detection processing on the amplified input differential signal to obtain positive peak voltage and negative peak voltage;

[0009] The subtractor is used to subtract the positive peak voltage from the negative peak voltage to obtain the peak-to-peak value of the OTA signal;

[0010] The comparison integrator is used to perform integration calculation on the peak-to-peak value of the OTA signal and filter out ripple to obtain a DC voltage signal with amplitude information.

[0011] The input capacitor, the feedback capacitor, and the variable capacitor are used to convert the DC voltage signal with amplitude information and to compensate the input differential signal.

[0012] In some embodiments, the peak detector includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first capacitor, and a first galvanometer. The sources of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are connected. The gates of the first transistor, the second transistor, and the second transistor are connected to the drain of the tenth transistor. The drains of the first transistor, the ninth transistor, the third transistor, and the third transistor are connected to the fourth transistor. The gates of the transistors are connected; the source of the ninth transistor, the source of the tenth transistor, and the drain of the thirteenth transistor are connected; the source of the thirteenth transistor, the second terminal of the first galvanometer, the second terminal of the first capacitor, and the source of the fourteenth transistor are connected; the drain of the fourth transistor, the gate of the tenth transistor, the first terminal of the first galvanometer, the drain of the fifth transistor, the first terminal of the first capacitor, and the gate of the eleventh transistor are connected; the gate of the fifth transistor, the gate of the sixth transistor, the drain of the sixth transistor, the drain of the eighth transistor, and the drain of the twelfth transistor are connected; the gate of the seventh transistor, the drain of the seventh transistor, the gate of the eighth transistor, and the drain of the eleventh transistor are connected; the source of the eleventh transistor, the source of the twelfth transistor, and the drain of the fourteenth transistor are connected.

[0013] In some embodiments, the valley detector includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a second capacitor, and a second galvanometer. The source of the fifteenth transistor, the source of the sixteenth transistor, a first terminal of the second capacitor, and a first terminal of the second galvanometer are connected. The drain of the fifteenth transistor, the source of the seventeenth transistor, and the source of the eighteenth transistor are connected. The drain of the seventeenth transistor, the drain of the twenty-first transistor, the drain of the twenty-third transistor, and the gate of the twenty-third transistor are connected to the gate of the twenty-fourth transistor. The drain of the eighteenth transistor, the drain of the twenty-second transistor, and the gate of the twenty-first transistor are connected to the gate of the twenty-second transistor. The gate of the eighteenth transistor, the second terminal of the second capacitor, the second terminal of the second galvanometer, the drain of the twenty-fourth transistor, the drain of the twenty-fifth transistor, and the gate of the nineteenth transistor are connected. The drain of the nineteenth transistor, the drain of the twenty-seventh transistor, and the gate of the twenty-seventh transistor are connected to the gate of the twenty-eighth transistor. The drain of the twenty-sixth transistor, the source of the nineteenth transistor, and the source of the twentieth transistor are connected. The drain of the twentieth transistor, the drain of the twenty-eighth transistor, the drain of the twenty-sixth transistor, and the gate of the twenty-fifth transistor are connected to the gate of the twenty-sixth transistor. The sources of the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, the twenty-fifth transistor, the twenty-sixth transistor, the twenty-seventh transistor, and the twenty-eighth transistor are connected.

[0014] In some embodiments, the subtractor includes a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein the second end of the third resistor and the first end of the fourth resistor are connected to the negative input terminal of the first operational amplifier, the second end of the first resistor and the first end of the second resistor are connected to the positive input terminal of the first operational amplifier, the second end of the fourth resistor is connected to the output terminal of the first operational amplifier, and the second resistor is grounded.

[0015] In some embodiments, the comparator integrator includes a second operational amplifier, a fifth resistor, a sixth resistor, and a third capacitor, wherein the second terminal of the fifth resistor, the first terminal of the sixth resistor, and the first terminal of the third capacitor are connected to the negative input terminal of the second operational amplifier, and the second terminal of the sixth resistor and the second terminal of the third capacitor are connected to the output terminal of the second operational amplifier.

[0016] In some embodiments, the variable capacitor includes a seventh resistor, an eighth resistor, a fourth capacitor, a fifth capacitor, and a MOS varactor diode, wherein the second terminal of the fourth capacitor, the second terminal of the seventh resistor, and the first terminal of the MOS varactor diode are connected, and the second terminal of the MOS varactor diode, the second terminal of the eighth resistor, and the first terminal of the fifth capacitor are connected.

[0017] To achieve the above objectives, another aspect of this application proposes a control method for a circuit used to enhance the input impedance of a chopper amplifier, the method comprising the following steps:

[0018] The differential input signal is acquired and chopped and amplified to obtain the first output signal and the second output signal.

[0019] Peak detection processing is performed on the first output signal and the second output signal to obtain positive peak voltage and negative peak voltage;

[0020] The peak-to-peak value of the OTA signal is obtained by subtracting the positive peak voltage from the negative peak voltage.

[0021] The peak-to-peak value of the OTA signal is integrated and ripple is filtered out to obtain a DC voltage signal with amplitude information.

[0022] The DC voltage signal with amplitude information is converted into a DC current signal with amplitude information, and the differential input signal is compensated for current through a positive feedback loop.

[0023] In some embodiments, the step of integrating the peak-to-peak value of the OTA signal and filtering out ripple to obtain a DC voltage signal with amplitude information includes:

[0024] Set the reference voltage of the comparator integrator according to the ideal amplitude of the amplifier;

[0025] The control voltage is obtained by integrating the peak-to-peak value of the OTA signal with the reference voltage.

[0026] The control voltage is processed to remove ripple, resulting in the DC voltage signal with amplitude information.

[0027] In some embodiments, the expression for the DC voltage signal with amplitude information is:

[0028]

[0029] In the above formula, V ouf V represents a DC voltage signal with amplitude information. inf- V represents the peak-to-peak value of the OTA signal. REF The reference voltage is represented by C3, the value of the third capacitor is represented by C3, and the value of the fifth resistor is represented by R5.

[0030] In some embodiments, the positive feedback loop includes a positive feedback loop and a negative feedback loop, wherein the positive feedback loop is composed of an input capacitor and a variable capacitor, and the negative feedback loop is composed of an input capacitor and a feedback capacitor.

[0031] The embodiments of this application include at least the following beneficial effects: This application provides a circuit and control method for enhancing the input impedance of a chopper amplifier. This scheme is based on oscillation detection, and automatic calibration is achieved by introducing a comparator integrator. Furthermore, an input capacitor, a feedback capacitor, and a variable capacitor are introduced to form a positive feedback loop to compensate for the input differential signal. The on-chip parasitic capacitance can be compensated by adjusting the positive feedback strength by detecting the magnitude of the oscillation amplitude. The introduction of a variable capacitor further decouples the control signal from the input signal, and has high linearity and wide tuning range characteristics. It can accurately compensate for the on-chip parasitic capacitance, thereby not drawing current from the signal source and enhancing the input impedance of the chopper capacitor-coupled instrumentation amplifier. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a circuit for enhancing the input impedance of a chopper amplifier, provided in an embodiment of this application.

[0033] Figure 2 This is a schematic diagram of the steps of a control method for a circuit used to enhance the input impedance of a chopper amplifier, as provided in an embodiment of this application.

[0034] Figure 3 This is a schematic diagram of the circuit principle of the peak detector provided in the embodiment of this application;

[0035] Figure 4 This is a schematic diagram of the circuit principle of the valley detector provided in the embodiments of this application;

[0036] Figure 5 This is a schematic diagram of the circuit principle of the subtractor provided in the embodiments of this application;

[0037] Figure 6 This is a schematic diagram of the circuit principle of the comparator integrator provided in the embodiments of this application;

[0038] Figure 7 This is a schematic diagram of the circuit principle of the variable capacitor provided in the embodiment of this application;

[0039] Figure 8 This is a schematic diagram of the structure of the MOS varactor diode provided in the embodiments of this application;

[0040] Figure 9 The control voltage V provided in the embodiments of this application C A schematic diagram showing the relationship between capacitance value and capacitance.

[0041] Figure reference numerals: 1. OTA op-amp module; 201. First-stage chopper; 202. Second-stage chopper; 203. Third-stage chopper; 204. Fourth-stage chopper; 3. Input capacitor; 4. Feedback capacitor; 5. Peak detector; 6. Valley detector; 7. Subtractor; 8. Comparison integrator; 9. Variable capacitor. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of systems and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0043] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0044] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0046] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0047] Chopper and input capacitor C IN The combination of these can be considered as an equivalent resistance, and this resistance value is the input impedance Z of the instrumentation amplifier. IN It can be represented as:

[0048]

[0049] Where f chop This refers to the chopping frequency. Input impedance is inversely proportional to the input capacitance and the chopping frequency. In instrumentation amplifiers, the input capacitance should be large enough to minimize total system noise and closed-loop gain error caused by parasitic capacitance, but a large input capacitance will reduce the input impedance. Furthermore, the chopping frequency should be much higher than the intersection of flicker noise and thermal noise to mitigate residual flicker noise, which further reduces the input impedance. This makes it difficult to achieve a high-impedance, low-noise instrumentation amplifier without enhancement techniques.

[0050] Some shortcomings exist in related technologies, such as the common use of positive feedback loops to increase the input impedance of amplifiers. This is because most of the charging current is provided by the feedback loop and does not draw current from the signal source, thus allowing for a larger signal voltage at the instrumentation amplifier input. However, this technique is not ideal for high-gain amplifiers because it is difficult to manufacture low-value capacitors with high precision. Furthermore, for amplifiers with different gains, the value of the positive feedback capacitor needs to be reconfigured to suit the different gains of the instrumentation amplifiers. Another impedance enhancement technique is the use of auxiliary pre-charge buffers, which increase the input impedance by providing the required charging current in each switching interval. However, these buffers operate on a duty cycle basis, which introduces additional noise and gain mismatch, leading to performance degradation of the instrumentation amplifier.

[0051] In view of this, this application provides a circuit for enhancing the input impedance of a chopper amplifier. Oscillation-based calibration eliminates the need for manual fine-tuning, enabling automatic calibration. On-chip parasitic capacitance is compensated by adjusting the positive feedback strength based on the oscillation amplitude. Decoupling of the control signal from the input signal is achieved through a variable capacitor, resulting in high linearity and a wide tuning range. Furthermore, it achieves capacitance resolution exceeding that of Flyphalman, thus avoiding the limitations of traditional LSB capacitor arrays. Because on-chip parasitic capacitance is precisely compensated, it does not draw current from the signal source, enabling ultra-high input impedance for chopper capacitor-coupled instrumentation amplifiers without introducing additional noise or gain mismatch. It is also suitable for instrumentation amplifiers with different gains.

[0052] Reference Figure 1 , Figure 1 This is a schematic diagram of a circuit for enhancing the input impedance of a chopper amplifier, provided in an embodiment of the present invention. (Refer to...) Figure 1 The circuit includes an OTA operational amplifier module 1, a chopper module, an input capacitor 3, a feedback capacitor 4, a peak detector 5, a valley detector 6, a subtractor 7, a comparator integrator 8, and a variable capacitor 9. The chopper module includes a first-stage chopper 201, a second-stage chopper 202, a third-stage chopper 203, and a fourth-stage chopper 204. The second terminal of the first-stage chopper is connected to the first terminal of the input capacitor and the first terminal of the variable capacitor, respectively. The second terminal of the input capacitor is connected to the first terminal of the feedback capacitor and the first terminal of the OTA operational amplifier module, respectively. The second terminal of the feedback capacitor is connected to the first terminal of the OTA operational amplifier module 9. The first terminal of the three-stage chopper is connected to the first terminal of the second-stage chopper. The second terminal of the OTA operational amplifier module is connected to the first terminal of the second-stage chopper. The second terminal of the variable capacitor is connected to the first terminal of the fourth-stage chopper. The second terminals of the fourth-stage chopper, the third-stage chopper, and the second-stage chopper, the input terminal of the peak detector, and the input terminal of the valley detector are connected to each other. The output terminals of the peak detector and the valley detector are both connected to the input terminal of the subtractor. The output terminal of the subtractor is connected to the input terminal of the comparator integrator. The output terminal of the comparator integrator is connected to the input terminal of the variable capacitor. Where:

[0053] The chopper module is used to chop the input differential signal to obtain the chopped input differential signal.

[0054] The OTA operational amplifier module is used to amplify the chopped input differential signal to obtain the amplified input differential signal.

[0055] Peak detectors and valley detectors are used to perform peak detection processing on the amplified input differential signal to obtain positive peak voltage and negative peak voltage;

[0056] In this embodiment, as Figure 3As shown, the peak detector includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M1. 10 11th transistor M 11 Twelfth transistor M 12 Thirteenth transistor M 13 Fourteenth transistor M 14 The first capacitor C1 and the first ammeter I b1 In this configuration, the sources of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors are connected; the gates of the first, second, and third transistors are connected to the drain of the tenth transistor; the drains of the first, ninth, and third transistors are connected to the gate of the fourth transistor; and the sources of the ninth, tenth, and thirteenth transistors are connected. The source of the thirteenth transistor and the source of the first... The second terminal of the galvanometer, the second terminal of the first capacitor, and the source of the fourteenth transistor are connected. The drain of the fourth transistor, the gate of the tenth transistor, the first terminal of the first galvanometer, the drain of the fifth transistor, and the first terminal of the first capacitor are connected to the gate of the eleventh transistor. The gate of the fifth transistor, the gate of the sixth transistor, the drain of the sixth transistor, and the drain of the eighth transistor are connected to the drain of the twelfth transistor. The gate of the seventh transistor, the drain of the seventh transistor, and the gate of the eighth transistor are connected to the drain of the eleventh transistor. The source of the eleventh transistor and the source of the twelfth transistor are connected to the drain of the fourteenth transistor.

[0057] Furthermore, such as Figure 4 As shown, the valley detector includes the fifteenth transistor M. 15 The sixteenth transistor M 16 The seventeenth transistor M 17 The eighteenth transistor M 18 The nineteenth transistor M 19 20th transistor M 20 Twenty-first transistor M 21 Twenty-second transistor M 22 Twenty-third transistor M 23 24th transistor M 24 Twenty-fifth transistor M 25 26th transistor M 26 Twenty-seventh transistor M 27 28th transistor M 28 The second capacitor C2 and the second ammeter Ib2 In this configuration, the source of the fifteenth transistor, the source of the sixteenth transistor, the first terminal of the second capacitor, and the first terminal of the second galvanometer are connected; the drain of the fifteenth transistor, the source of the seventeenth transistor, and the source of the eighteenth transistor are connected; the drain of the seventeenth transistor, the drain of the twenty-first transistor, the drain of the twenty-third transistor, and the gate of the twenty-third transistor are connected to the gate of the twenty-fourth transistor; the drain of the eighteenth transistor, the drain of the twenty-second transistor, and the gate of the twenty-first transistor are connected to the gate of the twenty-second transistor; and the gate of the eighteenth transistor, the second terminal of the second capacitor, the second terminal of the second galvanometer, the drain of the twenty-fourth transistor, the drain of the twenty-fifth transistor, and the nineteenth transistor are connected. The gates of the transistors are connected as follows: the drain of the nineteenth transistor, the drain of the twenty-seventh transistor, the gate of the twenty-seventh transistor and the gate of the twenty-eighth transistor are connected; the drain of the twenty-sixth transistor, the source of the nineteenth transistor and the source of the twentieth transistor are connected; the drain of the twentieth transistor, the drain of the twenty-eighth transistor, the drain of the twenty-sixth transistor, the gate of the twenty-fifth transistor and the gate of the twenty-sixth transistor are connected; the sources of the twenty-first transistor, the source of the twenty-second transistor, the source of the twenty-third transistor, the source of the twenty-fourth transistor, the source of the twenty-fifth transistor, the source of the twenty-sixth transistor, the source of the twenty-seventh transistor and the source of the twenty-eighth transistor are connected.

[0058] The subtractor is used to subtract the positive peak voltage from the negative peak voltage to obtain the peak-to-peak value of the OTA signal;

[0059] In this embodiment, as Figure 5 As shown, the subtractor includes a first operational amplifier A1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The second end of the third resistor and the first end of the fourth resistor are connected to the negative input terminal of the first operational amplifier. The second end of the first resistor and the first end of the second resistor are connected to the positive input terminal of the first operational amplifier. The second end of the fourth resistor is connected to the output terminal of the first operational amplifier. The second resistor is grounded.

[0060] The comparator integrator is used to integrate the peak-to-peak value of the OTA signal and filter out ripple to obtain a DC voltage signal with amplitude information.

[0061] In this embodiment, as Figure 6 As shown, the comparator integrator includes a second operational amplifier A2, a fifth resistor R5, a sixth resistor R6, and a third capacitor C3. The second terminal of the fifth resistor, the first terminal of the sixth resistor, and the first terminal of the third capacitor are connected to the negative input terminal of the second operational amplifier, and the second terminal of the sixth resistor and the second terminal of the third capacitor are connected to the output terminal of the second operational amplifier.

[0062] Input capacitors, feedback capacitors, and variable capacitors are used to convert DC voltage signals with amplitude information and to compensate for input differential signals.

[0063] In this embodiment, as Figure 7 As shown, the variable capacitor includes a seventh resistor R7, an eighth resistor R8, a fourth capacitor C4, a fifth capacitor C5, and a MOS varactor diode C. V The second terminal of the fourth capacitor, the second terminal of the seventh resistor, and the first terminal of the MOS varactor diode are connected, and the second terminal of the MOS varactor diode, the second terminal of the eighth resistor, and the first terminal of the fifth capacitor are connected.

[0064] Please see Figure 2 This application also provides a control method for a circuit used to enhance the input impedance of a chopper amplifier, which can implement the above-mentioned circuit for enhancing the input impedance of a chopper amplifier. The method includes:

[0065] S100: Acquire the differential input signal and perform chopping and amplification processing to obtain the first output signal and the second output signal;

[0066] In some specific embodiments, the differential input signal is transmitted through V IN+ and V IN- After entering the instrumentation amplifier and passing through the first-stage chopper, the signal is converted in the time domain to a frequency of f. chop The square wave is modulated to f in the frequency domain. chop And its odd harmonics. After being amplified by the OTA amplifier, the signal comes to the second-stage chopper, where the modulated signal is demodulated back to a low frequency and passed through the first output signal V. OUT+ With the second output signal V OUT- Output. In this invention, the input capacitor C IN With feedback capacitor C FU Forming a negative feedback loop, the input capacitor C IN With variable capacitor C IBL This forms a positive feedback loop.

[0067] S200: Perform peak detection processing on the first output signal and the second output signal to obtain positive peak voltage and negative peak voltage;

[0068] In some specific embodiments, the peak detector and the valley detector are used as amplitude detectors to detect the first output signal V. OUT+ With the second output signal V OUT- The peak value. The peak detector has a differential input and single-ended output structure.

[0069] Among them, the first transistor M1, the second transistor M2, the ninth transistor M9, and the tenth transistor M 10 Thirteenth transistor M13 And the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M 11 Twelfth transistor M 12 Fourteenth transistor M 14 As a feedback operational amplifier, transistors M3, M4, M5, and M6 form current mirrors, capacitor C1 is a holding capacitor, and the first ammeter I... b1 This is the discharge current source. The differential output of the OTA is the differential input of the peak detector, with mirrored left and right sides. The left side is used to detect the in-phase output signal V of the instrumentation amplifier. OUT+ The peak value, the right side is used to detect the inverted output signal V. OUT- The peak value. Output V o1 The output peak voltage charges the capacitors on both sides, charging once every half cycle.

[0070] The basic principle is as follows: Taking the left side as an example, the first transistor M1, the second transistor M2, the ninth transistor M9, and the tenth transistor M 10 Thirteenth transistor M 13 This is a classic 5-transistor op-amp used to compare the input signal V. in1+ With the current peak voltage V at the output terminal o1 The difference. When the diode is on, the feedback op-amp acts as a buffer stage, isolating the input and accelerating the output's following speed. The output of the feedback op-amp is at the drain of the first transistor M1 and the ninth transistor M9. Current flows from the feedback op-amp into the current mirror, the third transistor M3 and the fourth transistor M4. When the current mirror is on, the diode conducts in the forward direction, and the current is copied to the branch of the fourth transistor M4 to charge the capacitor. When the current mirror is off, the diode is inverted and cut off, there is no current in the branch of the fourth transistor M4, and the capacitor maintains its peak voltage.

[0071] Specifically, when the input signal V in1+ As the voltage rises, the gate voltage of the ninth transistor M9 is higher than the output voltage V. o1 The peak output voltage will increase the small-signal current of input transistor M9. However, due to the clamping effect of the first transistor M1 and the second transistor M2 on the branch current, the current of the first transistor M1 remains unchanged. According to the KCL equation of the drain junction of the first transistor M1 and the ninth transistor M9, the increased small-signal current can only be drawn from the third transistor M3. The increased current of the third transistor M3 is copied to the output branch by the third transistor M3 and the fourth transistor M4 of the current mirror. This current will charge the first capacitor C1, and the output voltage will rise.

[0072] Conversely, when the input signal V in1+ The voltage drops, and the gate voltage of input transistor M9 is lower than that of output transistor V. o1The peak output voltage will decrease, the small-signal current of input transistor M9 will decrease, and the tenth transistor M... 10 The gate voltage rises, and the tenth transistor M 10 As the current increases, the current copied to the input branch through the current mirrors first transistor M1 and second transistor M2 increases, so that the drain junctions of first transistor M1 and ninth transistor M9 no longer need to draw current from third transistor M3. Third transistor M3 only provides current and does not consume current. The drain junction potentials of first transistor M1 and ninth transistor M9 will be pulled up to VDD. Third transistor M3 is turned off, fourth transistor M4 is turned off, and the circuit enters a brief equilibrium state. The output is the peak value of the current signal, and the peak detector is always detecting the maximum value of the signal.

[0073] Similarly, the valley detector continuously detects the minimum value of the signal. The valley detector functions in the opposite way to the peak detector, with the circuit structure reversed. The principle by which the valley detector detects negative peaks is the same as the principle by which the peak detector detects positive peaks, and will not be elaborated further here.

[0074] Typically, the charging and discharging speed of capacitor C depends on 1 / RC, where R is the discharge current source I. b The larger the impedance R, the larger the capacitance C, and the faster the charging and discharging speed. This can be expressed by the slew rate SR.

[0075]

[0076] The slew rate (SR) is adjusted by changing the discharge current and the holding capacitor. A higher SR results in a steeper slope, allowing for better tracking of signals with rapidly changing amplitudes. The current source I can be adjusted... b The size allows for both fast tracking speed and minimal ripple.

[0077] The in-phase input of the peak detector V in1+ Connect to the non-inverting output terminal V of OTA OUT+ Inverting input V in1- Connected to the reverse output terminal V of OTA OUT- The peak detector output V o1 The peak voltage of the signal is obtained, and the output V of the valley detector is obtained. o2 The negative peak voltage of the signal is obtained. Therefore, the positive peak values ​​of the in-phase and out-of-phase output signals of the instrumentation amplifier are detected by the peak detector, and the negative peak values ​​of the in-phase and out-of-phase output signals are detected by the valley detector.

[0078] S300: Subtract the positive peak voltage from the negative peak voltage to obtain the peak-to-peak value of the OTA signal;

[0079] In some specific embodiments, the subtractor is used to subtract the positive peak value detected by the peak detector from the negative peak value detected by the valley detector to obtain the peak-to-peak value of the OTA signal. For example, if the peak detector detects a positive peak value of 1V and the valley detector detects a negative peak value of 0.2V, then the peak-to-peak value output by the subtractor will be 0.8V. pp .

[0080] A1 represents the operational amplifier. The non-inverting input V of the subtractor... i+ The output V of the preceding peak detector o1 Inverting input V i- Connect to the output V of the preceding valley detector o2 Output terminal V o Connect the inverting input of the subsequent integrator. Connect four resistors R1 to R4 between the input and output of the operational amplifier to form a closed-loop feedback, thereby realizing the function of subtracting the two differential inputs.

[0081] S400: Integrate the peak-to-peak value of the OTA signal and filter out ripple to obtain a DC voltage signal with amplitude information;

[0082] It should be noted that in some embodiments, step S400 may include: S410, setting the reference voltage of the integrator according to the ideal amplitude of the amplifier; S420, integrating the peak-to-peak value of the OTA signal with the reference voltage to obtain the control voltage; S430, filtering out ripples from the control voltage to obtain a DC voltage signal with amplitude information.

[0083] In some specific embodiments, the integrator is used to perform integration and filter ripple. The inverting input V... inf- The amplitude of the output from the preceding subtractor is connected to the non-inverting input, and a reference voltage V of 0.1V is connected to it. REF Output terminal V ouf Connect the voltage control terminal of the subsequent variable capacitor. Add a resistor and a capacitor between the input and output terminals of the operational amplifier to form a closed-loop feedback, thereby realizing the function of the integrator.

[0084] Its principle is as follows: The integrator first takes the input V inf- With the preset reference voltage V REF Comparison is made. The integrator's input V... inf- V is the peak-to-peak value of the OTA op-amp output of the subtractor. REF The amplitude is set to the ideal value of the instrumentation amplifier. Then, the integrator integrates the difference between the two inputs, and the integrated voltage V... ouf It is the control voltage V of the positive feedback loop. C This is supplied to the variable capacitor to adjust the gain. Based on the virtual short and virtual open conditions, the current flowing through the integrating capacitor C3 is...

[0085]

[0086] The output voltage of the integrator can be obtained as follows:

[0087]

[0088] And because the integrator's input V inf- and reference voltage V REF Since they are all DC voltages that do not change with time t, they can be simplified to:

[0089]

[0090] In this design, a feedback resistor R6 is connected in parallel with capacitor C3 of the integrator to implement a low-pass filter to remove high-frequency components. Therefore, the output voltage V of the integrator... ouf It is a DC voltage with amplitude information, which can be used as the capacitance value of the voltage-tunable variable capacitor.

[0091] The stability boundary of the instrumentation amplifier is detected by an amplitude detector. During this process, if the instrumentation amplifier oscillates and the signal amplitude exceeds the reference voltage V, the stability boundary is determined. REF Then the integrator is triggered to perform integral tuning control voltage V. C Therefore, a set of feedback currents is provided in the feedback loop with a variable capacitor until the output amplitude of the instrumentation amplifier remains below the reference voltage V. REF The voltage.

[0092] S500: Convert the DC voltage signal with amplitude information into a DC current signal with amplitude information, and perform current compensation on the differential input signal through a positive feedback loop;

[0093] In some specific embodiments, C4 and C5 in the variable capacitor circuit are ordinary capacitors. The variable capacitor of this invention can decouple the signal node from the control node, wherein V C It is the control voltage, V A V B It is a signal node. MOS varactor diode C V It is made of a varactor diode, which achieves higher capacitance density by replacing p+ doping with n+ ions, as is common in MOS transistors. Figure 8 As shown, the capacitance seen from the gate is an oxide capacitor. Since an increase in amplitude typically indicates overcompensation in the feedback loop, the value of the variable capacitor needs to be reduced to decrease the compensation degree. Therefore, the control voltage V generated by the integrator... C The relationship is inversely proportional to the capacitance value of the variable capacitor. Control voltage V C Different bias V bias The capacitance value is as follows Figure 9 As shown.

[0094] This voltage-controlled variable capacitor positive feedback topology has two advantages: first, it can realize capacitors with resolutions exceeding those of traditional capacitor arrays (LSBs) without being limited by them; second, adjusting the capacitor value via voltage does not change the size of the parasitic capacitance at the input compared to a switching matrix.

[0095] A variable capacitor and a chopper are connected in the positive feedback path between the input and output of the instrumentation amplifier. This chopper converts the output voltage into current, which is then injected back into the input node. This current compensates for the voltage drop caused by the chopper frequency f. chop and input capacitor C IN The current drawn from the signal source by the switched capacitor resistor compensates for the signal source current drawn by the on-chip parasitic capacitance, thereby greatly increasing the input impedance of the instrumentation amplifier.

[0096] In summary, the signal gain of an instrumentation amplifier is determined by the ratio of the input capacitance to the feedback capacitance, i.e., Gain = C. IN / C FB To ensure the gain accuracy of the instrumentation amplifier is higher than 0.1%, the gain of the OTA should be greater than 100dB. Therefore, this invention employs a two-stage OTA op-amp with Miller compensation. The offset and 1 / f noise of the OTA op-amp are shifted to higher frequencies by the chopper module without affecting the signal baseband.

[0097] The enhancement technique in this invention utilizes the stability criterion of a positive feedback loop, namely, overcompensation of positive feedback can cause OTA output oscillation. To find the stability boundary in calibration mode, a small signal pulse can be applied to the input of the instrumentation amplifier to observe the output waveform. When the variable capacitor C... IBL When the capacitance is small, there is weak positive feedback in the loop, the instrumentation amplifier operates normally, and the loop is stable. On the other hand, when the variable capacitor C... IBL When the input pulse is too large, the instrumentation amplifier will exhibit oscillations with a gradually increasing amplitude due to the strong regenerative characteristics of positive feedback. Therefore, the stability of the amplifier loop can be determined by observing the output at the end of the input pulse.

[0098] This invention utilizes an amplitude detector to monitor whether the amplifier is in an output oscillation state. Then, based on the output amplitude information, the feedback strength of the positive feedback loop is adjusted until the OTA output changes from an oscillation to a stable state. The variable capacitor acts as a compensation element and provides positive feedback gain, which is controlled by the voltage V. C Adjustment, V C This is generated by the monitoring loop. In this loop, a peak detector and a valley detector are used to detect the positive and negative peak values ​​of the OTA output, respectively; a subtractor subtracts the positive peak value from the negative peak value to obtain the peak-to-peak value of the instrumentation amplifier output signal; and an integrator multiplies the peak-to-peak value by the reference voltage V.REF After comparison, integrate the difference and output the control voltage V. C In this invention, the reference voltage is selected as 100mV. That is, when the loop detects that the amplitude gradually changes from oscillation to less than 100mV, V... C No longer changed to provide a definite capacitance value C IBL .

[0099] This invention checks the oscillation amplitude of the OTA output and adjusts the variable capacitor C accordingly. IBL The size is adjusted to achieve marginal stability of the instrumentation amplifier, and can almost completely compensate for the parasitic capacitance at the input of the instrumentation amplifier to achieve maximum input impedance.

[0100] It is understood that the content of the above method embodiments is applicable to this circuit embodiment. The specific functions implemented in this circuit embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0101] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A circuit for enhancing the input impedance of a chopper amplifier, characterized in that, The circuit includes an OTA operational amplifier module, a chopper module, an input capacitor, a feedback capacitor, a peak detector, a valley detector, a subtractor, a comparator integrator, and a variable capacitor. The chopper module includes a first-stage chopper, a second-stage chopper, a third-stage chopper, and a fourth-stage chopper. The first terminal of the first-stage chopper is connected to the input of the differential signal; the second terminal of the first-stage chopper is connected to the first terminal of the input capacitor and the first terminal of the variable capacitor, respectively. The second terminal of the input capacitor is connected to the first terminal of the feedback capacitor and the first terminal of the OTA operational amplifier module, respectively. The second terminal of the feedback capacitor is connected to the third-stage chopper. The first terminal is connected, the second terminal of the OTA operational amplifier module is connected to the first terminal of the second-stage chopper, the second terminal of the variable capacitor is connected to the first terminal of the fourth-stage chopper, the second terminal of the fourth-stage chopper, the second terminal of the third-stage chopper, the second terminal of the second-stage chopper, the input terminal of the peak detector, and the input terminal of the valley detector are connected, the output terminals of the peak detector and the valley detector are both connected to the input terminal of the subtractor, the output terminal of the subtractor is connected to the input terminal of the comparator integrator, and the output terminal of the comparator integrator is connected to the input terminal of the variable capacitor, wherein: The first-stage chopper is used to chop the input differential signal to obtain the chopped input differential signal. The OTA operational amplifier module is used to amplify the chopped input differential signal to obtain an amplified input differential signal. The peak detector and the valley detector are used to perform peak detection processing on the amplified input differential signal to obtain positive peak voltage and negative peak voltage; The subtractor is used to subtract the positive peak voltage from the negative peak voltage to obtain the peak-to-peak value of the OTA signal; The comparison integrator is used to perform integration calculation on the peak-to-peak value of the OTA signal and filter out ripple to obtain a DC voltage signal with amplitude information. The variable capacitor is used to convert the DC voltage signal with amplitude information and to compensate the input differential signal.

2. The circuit according to claim 1, characterized in that, The peak detector includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first capacitor, and a first galvanometer. The sources of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are connected and commonly connected to VDD. The gates of the first transistor, the second transistor, and the drain of the second transistor are connected to... The drain of the tenth transistor is connected; the drains of the first transistor, the ninth transistor, the third transistor, and the gate of the third transistor are connected to the gate of the fourth transistor; the sources of the ninth transistor, the tenth transistor, and the thirteenth transistor are connected; the source of the thirteenth transistor, the second terminal of the first galvanometer, the second terminal of the first capacitor, and the source of the fourteenth transistor are connected and grounded together; the drain of the fourth transistor, the gate of the tenth transistor, the first terminal of the first galvanometer, the drain of the fifth transistor, the first terminal of the first capacitor, and the gate of the eleventh transistor are connected and together connected to the first output terminal. The gate of the fifth transistor, the gate of the sixth transistor, the drain of the sixth transistor, the drain of the eighth transistor, and the drain of the twelfth transistor are connected; the gate of the seventh transistor, the drain of the seventh transistor, and the gate of the eighth transistor are connected to the drain of the eleventh transistor; the source of the eleventh transistor, the source of the twelfth transistor, and the drain of the fourteenth transistor are connected; the gate of the ninth transistor is connected to the first input signal (…). The gate of the twelfth transistor is connected to the second input terminal ( The gate of the thirteenth transistor is connected to a bias voltage ( The gate of the fourteenth transistor is connected to a bias voltage ( ).

3. The circuit according to claim 1, characterized in that, The valley detector includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a second capacitor, and a second galvanometer. The source of the fifteenth transistor, the source of the sixteenth transistor, the first terminal of the second capacitor, and the first terminal of the second galvanometer are connected and commonly connected to VDD. The drain of the fifteenth transistor, the source of the seventeenth transistor, and the source of the eighteenth transistor are connected. The drain of the seventeenth transistor, the drain of the twenty-first transistor, the drain of the twenty-third transistor, and the gate of the twenty-third transistor are connected to the gate of the twenty-fourth transistor. The drain of the eighteenth transistor, the drain of the twenty-second transistor, the gate of the twenty-first transistor, and the gate of the nineteenth transistor are connected and commonly connected to a second output terminal. The drain of the nineteenth transistor, the drain of the twenty-seventh transistor, the gate of the twenty-seventh transistor, and the gate of the twenty-eighth transistor are connected; the drain of the sixteenth transistor, the source of the nineteenth transistor, and the source of the twentieth transistor are connected; the drain of the twentieth transistor, the drain of the twenty-eighth transistor, the drain of the twenty-sixth transistor, and the gate of the twenty-fifth transistor are connected to the gate of the twenty-sixth transistor; the sources of the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, the twenty-fifth transistor, the twenty-sixth transistor, the twenty-seventh transistor, and the twenty-eighth transistor are connected and grounded; the gates of the fifteenth transistor and the sixteenth transistor are both connected to a bias voltage (…). ).

4. The circuit according to claim 1, characterized in that, The subtractor includes a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor. The second terminal of the third resistor and the first terminal of the fourth resistor are connected to the negative input terminal of the first operational amplifier. The second terminals of the first and second resistors are connected to the positive input terminal of the first operational amplifier. The second terminal of the fourth resistor is connected to the output terminal of the first operational amplifier. The second resistor is grounded. The first terminal of the first resistor is connected to the inverting input terminal. The first end of the third resistor is connected to the non-inverting input terminal ( ). ).

5. The circuit according to claim 1, characterized in that, The comparator integrator includes a second operational amplifier, a fifth resistor, a sixth resistor, and a third capacitor. The second terminal of the fifth resistor, the first terminal of the sixth resistor, and the first terminal of the third capacitor are connected to the negative input terminal of the second operational amplifier. The second terminals of the sixth resistor and the third capacitor are connected to the output terminal of the second operational amplifier. The first terminal of the fifth resistor is connected to the peak-to-peak value of the OTA signal. ).

6. The circuit according to claim 1, characterized in that, The variable capacitor includes a seventh resistor, an eighth resistor, a fourth capacitor, a fifth capacitor, and a MOS varactor diode. The second terminal of the fourth capacitor, the second terminal of the seventh resistor, and the first terminal of the MOS varactor diode are connected. The second terminal of the MOS varactor diode, the second terminal of the eighth resistor, and the first terminal of the fifth capacitor are also connected. The first terminal of the fourth capacitor is connected to a first signal node. The first terminal of the seventh resistor is connected to the control voltage ( The first terminal of the eighth resistor is connected to a bias voltage ( The second terminal of the fifth capacitor is connected to the second signal node ( ).

7. A control method for a circuit used to enhance the input impedance of a chopper amplifier as described in any one of claims 1-6, characterized in that, The method includes the following steps: The differential input signal is acquired and chopped and amplified to obtain the first output signal and the second output signal. Peak detection processing is performed on the first output signal and the second output signal to obtain positive peak voltage and negative peak voltage; The peak-to-peak value of the OTA signal is obtained by subtracting the positive peak voltage from the negative peak voltage. The peak-to-peak value of the OTA signal is integrated and ripple is filtered out to obtain a DC voltage signal with amplitude information. The DC voltage signal with amplitude information is converted into a DC current signal with amplitude information, and the differential input signal is compensated for current through a positive feedback loop.

8. The method according to claim 7, characterized in that, The step of integrating the peak-to-peak value of the OTA signal and filtering out ripple to obtain a DC voltage signal with amplitude information includes: Set the reference voltage of the comparator integrator according to the ideal amplitude of the amplifier; The control voltage is obtained by integrating the peak-to-peak value of the OTA signal with the reference voltage. The control voltage is processed to remove ripple, resulting in the DC voltage signal with amplitude information.

9. The method according to claim 7, using the circuit for enhancing the input impedance of a chopper amplifier as described in claim 5, characterized in that, The expression for the DC voltage signal with amplitude information is: In the above formula, This represents a DC voltage signal with amplitude information. Indicates the peak-to-peak value of the OTA signal. Indicates the reference voltage. Indicates the value of the third capacitor. This indicates the fifth resistance value.

10. The method according to claim 7, characterized in that, The positive feedback loop includes a positive feedback loop and a negative feedback loop. The positive feedback loop is composed of an input capacitor and a variable capacitor, and the negative feedback loop is composed of an input capacitor and a feedback capacitor.

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