Driving circuit and electronic equipment

Abstract

The invention discloses a driving circuit and electronic equipment. The driving circuit comprises a pre-starting unit and an operational amplification unit, wherein the pre-starting unit is coupled with a bias voltage input end of the operational amplification unit and is suitable for switching a bias voltage input by the bias voltage input end of the operational amplification unit from a third level to a second level when a PWM signal is switched from a first level to the second level; and switching the bias voltage from the second level to a third level after the load unit forms an access, the output end of the operational amplification unit is coupled with the control end of the load unit, and the operational amplification unit is suitable for outputting a driving signal to drive the load unit after starting work; the third level is larger than the second level and smaller than the first level; the starting time of the operational amplification unit when the bias voltage is the second level is smaller than the starting time of the operational amplification unit when the bias voltage is the third level. The driving circuit provided by the invention is short in time delay and low in power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a driving circuit and an electronic device. Background Art

[0002] A pulse width modulation (PWM) signal is usually driven and amplified by a driving circuit to obtain a driving signal, and the driving signal is input to a load unit to drive the load unit to work.

[0003] However, due to the system response time of the drive circuit, there is a certain delay between the PWM signal input to the drive circuit and the drive signal. How to shorten the delay of the drive circuit to adapt to the high-speed response scenario has become a technical problem that needs to be solved urgently.

[0004] In the prior art, one solution to shorten the delay of the driving circuit is to set the driving circuit to a normally open state, but this consumes a lot of power. Summary of the invention

[0005] The present invention aims at providing a driving circuit with shorter delay and lower power consumption.

[0006] In a first aspect, the present invention provides a driving circuit suitable for driving a load unit, comprising: a pre-start unit and an operational amplifier unit; wherein: the pre-start unit is coupled to the bias voltage input terminal of the operational amplifier unit, and is suitable for switching the bias voltage input to the bias voltage input terminal of the operational amplifier unit from a third level to the second level when a pulse width modulation (PWM) signal switches from a first level to a second level; and, after the load unit forms a path, switching the bias voltage from the second level to the third level; the operational amplifier unit, whose output terminal is coupled to the control terminal of the load unit, is suitable for outputting a driving signal to drive the load unit after starting work; the third level is greater than the second level and less than the first level; the third level is the static operating voltage of the operational amplifier unit; the operational amplifier unit works when the bias voltage is the second level or the third level; the startup time of the operational amplifier unit when the bias voltage is the second level is less than the startup time of the operational amplifier unit when the bias voltage is the third level.

[0007] The driving circuit includes a pre-start unit, which is coupled to the bias voltage input terminal of the operational amplifier unit. When the PWM signal is switched from the first level to the second level, the bias voltage input to the bias voltage input terminal of the operational amplifier unit is switched to the second level. After the load unit forms a path, the bias voltage is switched from the second level to the third level. The operational amplifier unit can start working when the bias voltage is the second level or the third level. When the bias voltage is the second level, the startup time of the operational amplifier unit is less than the startup time of the operational amplifier unit when the bias voltage is the third level. Therefore, by setting the pre-start unit, when the level of the PWM signal changes, the operational amplifier unit can be quickly started, so the operational amplifier loop can be quickly established, shortening the system response time.

[0008] Optionally, the pre-start unit is further adapted to switch the bias voltage from the third level to the first level when the PWM signal switches from the second level to the first level; when the bias voltage is at the first level, the operational amplifier unit stops working.

[0009] When the PWM signal switches from the second level to the first level, the pre-start unit switches the bias voltage from the third level to the first level. When the bias voltage is at the first level, the operational amplifier unit stops working. Thus, the pre-start unit can control the drive circuit to enter a stop working state, thereby reducing the power consumption required by the drive circuit.

[0010] Optionally, the pre-start unit includes: a bias voltage adjustment module, a first current mirror module and a pull-down module, wherein: the bias voltage adjustment module includes a first adjustment branch and a second adjustment branch; wherein the first adjustment branch is suitable for switching the bias voltage from the third level to the first level when the PWM signal switches from the second level to the first level; the second adjustment branch is suitable for switching the bias voltage from the third level to the second level when the PWM signal switches from the first level to the second level; the first current mirror module includes a current generating branch and a current mirror branch; wherein the current generating branch is coupled to the bias voltage input terminal; the current mirror branch is coupled to the output terminal of the operational amplifier unit; the pull-down module, whose control terminal is coupled to the current mirror branch, whose first terminal is coupled to the second adjustment branch, and whose second terminal is grounded; is suitable for pulling down the voltage on the second adjustment branch to the first level when the current mirror branch outputs the mirror current, so as to open the second adjustment branch.

[0011] Optionally, the bias voltage adjustment module includes: a first inverter, a second inverter, a first PMOS tube and a first NMOS tube, wherein: the first inverter, whose input end is input with the PWM signal, and whose output end is coupled with the gate of the first PMOS tube; the first PMOS tube, whose source is input with the power supply voltage, and whose drain is coupled with the drain of the first NMOS tube; the second inverter, whose input end is input with the PWM signal, and whose output end is coupled with the gate of the first NMOS tube; the first NMOS tube, whose source is grounded; the drain of the first PMOS tube and the drain of the first NMOS tube are coupled with the output end of the bias voltage adjustment module; the first inverter and the first PMOS tube constitute the first adjustment branch, and the second inverter and the first PMOS tube constitute the second adjustment branch.

[0012] Optionally, the first current mirror module includes: a second PMOS tube and a third PMOS tube, wherein: the second PMOS tube has a source input of the power supply voltage, a gate coupled to the gate of the third PMOS tube, and a drain coupled to the bias voltage input terminal; the third PMOS tube has a source input of the power supply voltage, a gate input of the bias voltage, and a drain coupled to the output terminal of the operational amplifier unit; the second PMOS tube is located in the current generating branch, and the third PMOS tube is located in the current mirror branch.

[0013] Optionally, the driving circuit also includes: a second NMOS tube, whose drain is coupled to the drain of the third PMOS tube, whose gate is coupled to the output end of the operational amplifier unit, and whose source is grounded; the second NMOS tube and the third PMOS tube constitute a second-stage amplifier circuit of the operational amplifier unit.

[0014] The third PMOS tube and the second NMOS tube form a second stage amplifying circuit of the operational amplifier unit, which can realize the second stage amplification of the output signal of the operational amplifier unit and improve the gain.

[0015] Optionally, the pull-down module includes a third NMOS tube; the third NMOS tube has a drain coupled to the second adjustment branch, a gate coupled to the current mirror branch, and a source grounded.

[0016] Optionally, the driving circuit also includes: a current generating unit, suitable for generating a target current, forming a second current mirror module with the load unit; the load current on the load unit is obtained by mirroring the target current; the operational amplifier unit, whose first input terminal is coupled to the load unit and whose second input terminal is coupled to the current generating unit.

[0017] Optionally, the current generating unit includes a current source and a fourth NMOS tube, and the load unit includes a fifth NMOS tube and a sixth NMOS tube; wherein: the current source has a first end that inputs a power supply voltage, and a second end that is coupled to the drain of the fourth NMOS tube; the fourth NMOS tube has a drain that is also coupled to the second input end of the operational amplifier unit, a gate that is coupled to its drain and the gate of the sixth NMOS tube, and a source that is grounded; the fifth NMOS tube has a drain that inputs a power supply voltage, a gate that is coupled to the output end of the operational amplifier unit, and a source that is coupled to the drain of the sixth NMOS tube; the sixth NMOS tube has a drain that is also coupled to the first input end of the operational amplifier unit.

[0018] Optionally, the driving circuit may further include: a seventh NMOS tube, whose drain is coupled to the gate of the fourth NMOS tube, whose gate inputs a control signal in phase with the PWM signal, and whose source is grounded.

[0019] In a second aspect, the present invention further provides an electronic device, comprising any one of the driving circuits provided above. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of a driving circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In the prior art, one method of shortening the time delay of a driving circuit is to set the driving circuit to a normally-on state, that is, the driving circuit continuously outputs a driving signal to the load unit, resulting in a large power consumption of the driving circuit.

[0022] Another method to shorten the time delay of the driving circuit is to set up a fast response circuit to increase the response speed of the driving circuit. However, the additional fast response circuit increases the circuit complexity, reduces the circuit reliability, and occupies a large circuit area.

[0023] In the embodiment of the present invention, a pre-start unit is provided in the driving circuit, and when the level of the PWM signal changes, the operational amplifier unit can be quickly started, so that the operational amplifier loop can be quickly established, and the system response time can be shortened. In addition, there is no need to provide a fast response circuit externally. Therefore, while achieving a fast response of the driving circuit, the circuit complexity is not increased additionally.

[0024] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] An embodiment of the present invention provides a driving circuit suitable for driving a load unit.

[0026] In an embodiment of the present invention, the driving circuit may include a pre-start unit and an operational amplifier unit, wherein: The pre-start unit may be coupled to the bias voltage input terminal of the operational amplifier unit, and is adapted to switch the bias voltage input to the bias voltage input terminal of the operational amplifier unit from the third level to the second level when the input PWM signal switches from the first level to the second level; and, after the load unit forms a path, switch the bias voltage from the second level to the third level; The output end of the operational amplifier unit is coupled to the control end of the load unit; after starting to work, the operational amplifier unit outputs a driving signal to drive the load unit to form a path.

[0027] In a specific implementation, when the bias voltage is at the second level or the third level, the operational amplifier unit starts to work. It should be noted that when the bias voltage is at the second level, the startup time of the operational amplifier unit is shorter than when the bias voltage is at the third level.

[0028] For example, when the bias voltage is at the second level, the startup time of the operational amplifier unit is T1; when the bias voltage is at the third level, the startup time of the operational amplifier unit is T2, and T1<T2.

[0029] In a specific implementation, the third level is greater than the second level, and the third level is less than the second level.

[0030] Specifically, the first level may be a logic high level "1" in a digital circuit, and the second level may be a logic low level "0" in a digital circuit. The third level may be between the first level and the second level, and may be a static operating voltage of the operational amplifier unit.

[0031] For example, the first level is 5V, the second level is 0V, and the third level is 2.2V.

[0032] In the following embodiments, unless otherwise specified, the first level is a logic high level, and the second level is a logic low level.

[0033] In a specific implementation, the above bias voltage can be generated by a preset voltage generating circuit and output by the voltage generating circuit. The output voltage of the above voltage generating circuit is a third level.

[0034] In a specific implementation, the load unit may be a light emitting diode (LED) lamp bead, and the brightness, color temperature, etc. of the LED lamp bead may be adjusted by a driving signal output by a driving circuit.

[0035] Reference Figure 1 , a driving circuit in an embodiment of the present invention is given, and the following is combined with Figure 1 Provide detailed explanation.

[0036] In an embodiment of the present invention, the pre-start unit may include a bias voltage adjustment module, a first current mirror module and a pull-down module.

[0037] In a specific implementation, the bias voltage adjustment module may include a first adjustment branch and a second adjustment branch; wherein the first adjustment branch may adjust the bias voltage V when the PWM signal switches from the second level to the first level. BP The second adjustment branch can adjust the bias voltage V when the PWM signal switches from the first level to the second level. BP Switch from the third level to the second level.

[0038] When the PWM signal is at the first level, the first adjustment branch forms a path, and the output end of the bias voltage adjustment module outputs the first level; the second adjustment branch is disconnected; When the PWM signal is at the second level, the first adjustment branch is disconnected; the second adjustment branch forms a connection, and the bias voltage adjustment module outputs the second level.

[0039] The first current mirror module may include a current generating branch and a current mirror branch, wherein the current generating branch is coupled to the bias voltage input terminal of the operational amplifier unit OPA, and the current mirror branch is coupled to the output terminal of the operational amplifier unit OPA.

[0040] The control end of the pull-down module is coupled to the current mirror branch, the first end of the pull-down module is coupled to the second adjustment branch, and the second end of the pull-down module is grounded. When the current mirror branch outputs the mirror current, the pull-down module can pull the voltage on the second adjustment branch down to the second level, thereby disconnecting the second adjustment branch. Since the second adjustment branch is disconnected, the bias voltage V BP Switch from the second level to the third level.

[0041] In a specific implementation, the bias voltage adjustment module may include a first inverter INV1, a second inverter INV2, a first PMOS transistor MP1, and a first NMOS transistor MN1, wherein: The input end of the first inverter INV1 inputs the PWM signal, and the output end of the first inverter INV1 is coupled to the gate of the first PMOS tube MP1; The source of the first PMOS tube MP1 inputs the power supply voltage VDD, and the drain of the first PMOS tube MP1 is coupled to the drain of the first NMOS tube MN1; the first inverter INV1 and the first PMOS tube MP1 form a first adjustment branch; The input end of the second inverter INV2 inputs the PWM signal, and the output end of the second inverter INV2 is coupled to the gate of the first NMOS transistor MN1; The source of the first NMOS transistor MN1 is grounded, and the drain of the first NMOS transistor MN1 is coupled to the drain of the first PMOS transistor MP1 ; the second inverter INV2 and the first NMOS transistor MN1 form a second adjustment branch.

[0042] In a specific implementation, the drain of the first PMOS transistor MP1 and the drain of the first NMOS transistor MN1 are both coupled to the output end of the bias voltage adjustment module. When the PWM signal switches from the second level to the first level, the output end of the bias voltage adjustment module outputs the first level, thereby increasing the bias voltage V BP When the PWM signal switches from the first level to the second level, the output terminal of the bias voltage adjustment module outputs the second level, thereby increasing the bias voltage V BP Pull down from the third level to the first level.

[0043] In a specific implementation, the first current mirror module includes: a second PMOS tube MP2 and a third PMOS tube MP3, wherein: The source of the second PMOS tube MP2 is input with the power supply voltage VDD, the gate of the second PMOS tube MP2 is coupled with the gate of the third PMOS tube MP3, and the drain of the second PMOS tube MP2 is coupled with the bias voltage input terminal of the operational amplifier unit OPA; The source of the third PMOS tube MP3 inputs the power supply voltage VDD, and the gate of the third PMOS tube MP3 inputs the bias voltage V BP , a drain of the third PMOS tube MP3 is coupled to the output end of the operational amplifier unit OPA.

[0044] When the bias voltage V BP When the bias voltage V BP When it is at the second level or the third level, the second PMOS tube MP2 and the third PMOS tube MP3 are in a conducting state, and the operational amplifier unit OPA starts to work.

[0045] When the bias voltage V BP When the bias voltage V BP When the voltage is at the second level or the third level, the second PMOS tube MP2 outputs a current, and the third PMOS tube MP3 outputs a mirror current corresponding to the output current of the second PMOS tube MP2.

[0046] In a specific implementation, the driving circuit may further include a second NMOS transistor MN2. Specifically, the drain of the second NMOS transistor MN2 is coupled to the drain of the third PMOS transistor MP3, the gate of the second NMOS transistor MN2 is coupled to the output end of the operational amplifier unit OPA, and the source of the second NMOS transistor MN2 is grounded.

[0047] The second NMOS transistor MN2 and the third PMOS transistor MP3 may constitute a second-stage amplifying circuit of the operational amplifier unit OPA to further amplify the output signal of the operational amplifier unit OPA.

[0048] In a specific implementation, the pull-down module may include a third NMOS transistor MN3. Specifically, the drain of the third NMOS transistor MN3 is coupled to the second adjustment branch, the gate of the third NMOS transistor MN3 is coupled to the current mirror branch, and the source of the third NMOS transistor MN3 is grounded.

[0049] In the embodiment of the present invention, the pull-down capability of the third NMOS transistor MN3 is higher than the pull-up driving capability of the second inverter INV2. That is, the output current of the third NMOS transistor MN3 is higher than the output current of the second inverter INV2.

[0050] Since the drain of the third NMOS tube MN3 is coupled to the second adjustment branch, and the pull-down capability of the third NMOS tube MN3 is stronger than the pull-up driving capability of the second inverter INV2, when the third PMOS tube MP3 outputs the mirror current, the gate of the third NMOS tube MN3 is at a high level, and the third NMOS tube MN3 is turned on. When the third NMOS tube MN3 is turned on, the first level on the second adjustment branch will be quickly pulled down to the second level, thereby disconnecting the second adjustment branch, and further causing the bias voltage adjustment module to have no voltage output, so the bias voltage V BP Switch from the second level to the third level.

[0051] In a specific implementation, the current generating unit and the load unit can form a second current mirror module. The current generating unit can generate a target current, and the load current flowing through the load unit is obtained by mirroring the target current. The load current and the target current are in a certain proportional relationship.

[0052] The current generating unit may include a current source I and a fourth NMOS transistor MN4 , and the load unit may include a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6 .

[0053] Specifically, the first end of the current source I can input the power supply voltage VDD, and the second end of the current source I can be coupled to the drain of the fourth NMOS transistor MN4; the output current of the current source I is the target current; The drain of the fourth NMOS transistor MN4 is also coupled to the second input terminal of the operational amplifier unit OPA, the gate of the fourth NMOS transistor MN4 is coupled to the drain of the fourth NMOS transistor MN4 and the gate of the sixth NMOS transistor MN6, and the source of the fourth NMOS transistor MN4 is grounded; The drain of the fifth NMOS tube MN5 is input with the power supply voltage VDD, the gate of the fifth NMOS tube MN5 is coupled with the output end of the operational amplifier unit OPA, the source of the fifth NMOS tube MN5 is coupled with the drain of the sixth NMOS tube MN6; the gate of the fifth NMOS tube MN5 can be the control end of the load unit; The drain of the sixth NMOS transistor MN6 is also coupled to the first input terminal of the operational amplifier unit OPA.

[0054] The load current is the current flowing through the sixth NMOS transistor MN6 when the fifth NMOS transistor MN5 is turned on. The ratio of the load current to the target current can be determined by the quotient of the width-to-length ratio of the sixth NMOS transistor MN6 and the width-to-length ratio of the fourth NMOS transistor MN4. The load current can be adjusted by selecting the sixth NMOS transistor MN6 with different width-to-length ratios.

[0055] In a specific implementation, when the output terminal of the operational amplifier unit OPA is at a high level, the fifth NMOS transistor MN5 is turned on, and accordingly, the load unit forms a path, and current exists on the sixth NMOS transistor MN6. When the output terminal of the operational amplifier unit OPA is at a low level, the fifth NMOS transistor MN5 is turned off, and accordingly, the load unit is disconnected.

[0056] A load may be provided between the fifth NMOS transistor MN5 and the power supply voltage VDD, and the load may be an LED lamp. The LED lamp may realize a dimming function under the control of a PWM signal.

[0057] Below Figure 1 The specific working principle and process of the driving circuit provided in are described in detail.

[0058] The first level is set to be a high level, the second level is set to be a low level, and the third level is a static operating voltage, which is less than the first level and greater than the second level.

[0059] When the PWM signal is at a high level, the input end of the first inverter INV1 is at a high level, and the output end of the first inverter INV1 is at a low level, that is, the gate of the first PMOS tube MP1 is at a low level, and the source of the first PMOS tube MP1 inputs the power supply voltage VDD, then the first PMOS tube MP1 is turned on; correspondingly, the input end of the second inverter INV2 is at a high level, and the output end of the second inverter INV2 is at a low level, that is, the gate of the first NMOS tube MN1 is at a low level, and the first NMOS tube MN1 is turned off. In this scenario, the output end of the bias voltage adjustment module outputs a high level.

[0060] The gate of the seventh NMOS tube MN7 inputs a control signal in phase with the PWM signal, the drain of the seventh NMOS tube MN7 is coupled to the gate of the fifth NMOS tube MN5, and the source of the seventh NMOS tube MN7 is grounded. When the PWM signal is at a high level, the gate of the seventh NMOS tube MN7 is also at a high level. Then, the seventh NMOS tube MN7 is turned on, and the level of the gate of the fifth NMOS tube MN5 is pulled down to a low level, so the fifth NMOS tube MN5 is turned off.

[0061] Therefore, when the PWM signal is at a high level, the drive circuit is in a stopped working state.

[0062] When the PWM signal is at a low level, the input end of the first inverter INV1 is at a low level, and the output end of the first inverter INV1 is at a high level, that is, the gate of the first PMOS tube MP1 is at a high level, and the source of the first PMOS tube MP1 inputs the power supply voltage VDD, then the first PMOS tube MP1 is disconnected; correspondingly, the input end of the second inverter INV2 is at a low level, and the output end of the second inverter INV2 is at a high level, that is, the gate of the first NMOS tube MN1 is at a high level, and the first NMOS tube MN1 is turned on. Since the source of the first NMOS tube MN1 is grounded, when the first NMOS tube MN1 is turned on, the high level of its gate will be quickly pulled down to a low level. In this scenario, the output end of the bias voltage adjustment module outputs a low level.

[0063] Therefore, when the PWM signal switches from a high level to a low level, the output end of the first inverter INV1 and the output end of the second inverter INV2 both switch from a low level to a high level. The first PMOS transistor MP1 is disconnected, and the first NMOS transistor MN1 is turned on. Since the source of the first NMOS transistor MN1 is grounded, the high level on the first adjustment branch is quickly pulled down to a low level. Accordingly, the bias voltage V BP is quickly pulled down to a low level.

[0064] The gate of the second PMOS tube MP2 and the gate of the third PMOS tube MP3 input bias voltage V BP When the bias voltage V BPWhen the bias voltage V BP When the output current of the second PMOS tube MP2 is low, it is greater than the bias voltage V BP is the output current of the second PMOS transistor MP2 when the static working voltage is 0. Correspondingly, the output current of the third PMOS transistor MP3 can be a mirror image of the output current of the second PMOS transistor MP2.

[0065] After receiving a large current, the operational amplifier unit OPA starts up quickly, so an operational amplifier loop can be established quickly, shortening the system response time.

[0066] When the operational amplifier unit OPA is started, the output end of the operational amplifier unit OPA outputs a high level, and the gate levels of the third NMOS tube MN3 and the fifth NMOS tube MN5 are switched to a high level, so the third NMOS tube MN3 and the fifth NMOS tube MN5 are both turned on. When the third NMOS tube MN3 is turned on, since its drain is coupled to the second adjustment branch and its source is grounded, its pull-down capability is higher than the pull-up driving capability of the second inverter INV2, so it pulls the level of the second adjustment branch down to a low level. Therefore, the gate level of the first NMOS tube MN1 is switched from a high level to a low level, and the first NMOS tube MN1 is disconnected. In this scenario, the first PMOS tube MP1 and the first NMOS tube MN1 in the bias voltage adjustment module are both disconnected.

[0067] Bias voltage V BP After switching from a low level to a static operating voltage, the operational amplifier unit OPA operates normally.

[0068] When the operational amplifier unit OPA works normally, the second PMOS tube MP2 and the third PMOS tube MP3 are both turned on. The drain voltage of the sixth NMOS tube MN6 is clamped by the operational amplifier unit OPA to be equal to the drain voltage of the fourth NMOS tube MN4, so the target current flowing through the fourth NMOS tube MN4 can be accurately copied to the sixth NMOS tube MN6, thereby realizing accurate dimming of the LED lamp beads.

[0069] If the driving circuit provided by the present invention is not used, the establishment speed of the operational amplifier loop depends on the output current of the second PMOS tube MP2 and the third PMOS tube MP3. However, the voltage of the gate of the second PMOS tube MP2 is a static working voltage, the output current of the second PMOS tube MP2 is small, and the opening speed of the operational amplifier unit OPA is slow, which leads to a slow establishment speed of the operational amplifier loop.

[0070] When the driving circuit provided by the present invention is used, when the PWM signal jumps from a high level to a low level, the voltage of the gate of the second PMOS tube MP2 is a low level, so the output current of the second PMOS tube MP2 is relatively large, and the opening speed of the operational amplifier unit OPA is relatively fast, thereby accelerating the establishment speed of the operational amplifier loop. In addition, when the PWM signal jumps from a low level to a high level, the driving circuit is turned off, so that power consumption can be reduced.

[0071] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A driving circuit, characterized in that: Suitable for driving a load unit, comprising: a pre-start unit and an operational amplifier unit; wherein: The pre-start unit is coupled to the bias voltage input terminal of the operational amplifier unit, and is adapted to switch the bias voltage input to the bias voltage input terminal of the operational amplifier unit from a third level to the second level when the pulse width modulation (PWM) signal switches from a first level to a second level; and, after the load unit forms a path, switch the bias voltage from the second level to the third level; The operational amplifier unit, whose output terminal is coupled to the control terminal of the load unit, is suitable for outputting a driving signal to drive the load unit after starting operation; the third level is greater than the second level and less than the first level; the third level is a static operating voltage of the operational amplifier unit; The operational amplifier unit operates when the bias voltage is the second level or the third level; the startup time of the operational amplifier unit when the bias voltage is the second level is shorter than the startup time of the operational amplifier unit when the bias voltage is the third level.

2. The driving circuit according to claim 1, characterized in that: The pre-start unit is further adapted to switch the bias voltage from the third level to the first level when the PWM signal switches from the second level to the first level; when the bias voltage is at the first level, the operational amplifier unit stops working.

3. The driving circuit according to claim 2, characterized in that: The pre-start unit includes: a bias voltage adjustment module, a first current mirror module and a pull-down module, wherein: The bias voltage adjustment module comprises a first adjustment branch and a second adjustment branch; wherein the first adjustment branch is adapted to switch the bias voltage from the third level to the first level when the PWM signal switches from the second level to the first level; and the second adjustment branch is adapted to switch the bias voltage from the third level to the second level when the PWM signal switches from the first level to the second level; The first current mirror module comprises a current generating branch and a current mirroring branch; wherein the current generating branch is coupled to the bias voltage input terminal; and the current mirroring branch is coupled to the output terminal of the operational amplifier unit; The pull-down module has a control end coupled to the current mirror branch, a first end coupled to the second adjustment branch, and a second end grounded; and is suitable for pulling down the voltage on the second adjustment branch to the first level when the current mirror branch outputs the mirror current, so as to open the second adjustment branch.

4. The driving circuit according to claim 3, characterized in that: The bias voltage adjustment module includes: a first inverter, a second inverter, a first PMOS transistor and a first NMOS transistor, wherein: The first inverter has an input terminal inputting the PWM signal and an output terminal coupled to the gate of the first PMOS tube; The first PMOS tube has a source electrode inputting a power supply voltage and a drain electrode coupled to a drain electrode of the first NMOS tube; The second inverter has an input terminal inputting the PWM signal and an output terminal coupled to the gate of the first NMOS tube; The source of the first NMOS tube is grounded; the drain of the first PMOS tube and the drain of the first NMOS tube are coupled to the output end of the bias voltage adjustment module; The first inverter and the first PMOS transistor form the first adjustment branch, and the second inverter and the first PMOS transistor form the second adjustment branch.

5. The driving circuit according to claim 3, characterized in that: The first current mirror module includes: a second PMOS tube and a third PMOS tube, wherein: The second PMOS tube has a source electrode inputting a power supply voltage, a gate electrode coupled to the gate electrode of the third PMOS tube, and a drain electrode coupled to the bias voltage input terminal; The third PMOS tube has a source terminal inputting the power supply voltage, a gate terminal inputting the bias voltage, and a drain terminal coupled to the output terminal of the operational amplifier unit; The second PMOS transistor is located in the current generating branch, and the third PMOS transistor is located in the current mirroring branch.

6. The driving circuit according to claim 5, characterized in that: Also includes: The second NMOS tube has a drain coupled to the drain of the third PMOS tube, a gate coupled to the output end of the operational amplifier unit, and a source grounded; the second NMOS tube and the third PMOS tube constitute a second-stage amplifier circuit of the operational amplifier unit.

7. The driving circuit according to claim 3, characterized in that: The pull-down module includes a third NMOS transistor; the third NMOS transistor has a drain coupled to the second adjustment branch, a gate coupled to the current mirror branch, and a source connected to the ground.

8. The driving circuit according to any one of claims 1 to 7, characterized in that: Also includes: A current generating unit, adapted to generate a target current, and forming a second current mirror module with the load unit; The load current on the load unit is obtained by mirroring the target current; The operational amplifier unit has a first input terminal coupled to the load unit, and a second input terminal coupled to the current generating unit.

9. The driving circuit according to claim 8, characterized in that: The current generating unit includes a current source and a fourth NMOS transistor, and the load unit includes a fifth NMOS transistor and a sixth NMOS transistor; wherein: The current source has a first end inputting a power supply voltage and a second end coupled to the drain of the fourth NMOS tube; The fourth NMOS tube has a drain coupled to the second input terminal of the operational amplifier unit, a gate coupled to the drain and the gate of the sixth NMOS tube, and a source connected to the ground; The fifth NMOS tube has a drain electrode inputting a power supply voltage, a gate electrode coupled to the output terminal of the operational amplifier unit, and a source electrode coupled to the drain electrode of the sixth NMOS tube; The drain of the sixth NMOS tube is also coupled to the first input terminal of the operational amplifier unit.

10. The driving circuit according to claim 9, characterized in that: Also includes: The seventh NMOS tube has a drain coupled to the gate of the fourth NMOS tube, a gate inputting a control signal in phase with the PWM signal, and a source connected to the ground.

11. An electronic device, characterized in that: Comprising a driving circuit as described in any one of claims 1 to 10.

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