Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer defining a plurality of active regions and a plurality of gate structures crossing the active regions. Each of the gate structures includes a gate insulating layer on the active region and a gate electrode layer on the gate insulating layer, the gate insulating layer including a first region including a first material and a second region including a second material different from the first material. A concentration of the second material in the first region is less than a concentration of the second material in the second region, and a thickness of the first region is less than a thickness of the second region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As semiconductor elements become more and more integrated, there is an increasing demand for ensuring the operating characteristics of transistors despite the reduction in the size of transistors and the size of active regions in which the transistors are integrated.

[0003] The gate insulating layer of the transistor may be formed of an oxide layer obtained by performing an oxidation process on an active region of a semiconductor substrate such as a silicon substrate. During the oxidation process, silicon in the active region may be oxidized, wherein silicon (Si) in the active region is chemically changed.

[0004] This Si loss or silicon oxidation phenomenon reduces the current that can flow through the transistor, and thus may become a factor that deteriorates the operating characteristics of the transistor. Summary of the invention

[0005] Aspects of the present disclosure provide a semiconductor device capable of suppressing depletion or oxidation of an active region of a transistor.

[0006] Aspects of the present disclosure also provide a method for manufacturing a semiconductor device capable of suppressing depletion or oxidation of an active region of a transistor.

[0007] However, aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0008] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate, comprising an element isolation layer defining a plurality of active regions; and a plurality of gate structures intersecting the plurality of active regions, wherein each of the plurality of gate structures comprises: a gate insulating layer on the active region, the gate insulating layer comprising a first region comprising a first material and a second region comprising a second material different from the first material; and a gate electrode layer on the gate insulating layer, wherein a concentration of the second material in the first region is less than a concentration of the second material in the second region, and a thickness of the gate insulating layer in the first region is less than a thickness of the gate insulating layer in the second region.

[0009] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate, comprising an element isolation layer, the element isolation layer defining a cell area and a peripheral area around the cell area and defining a first active area in the cell area; and a cell gate structure in the cell area, the cell gate structure being formed in a first trench on the substrate and intersecting the first active area, wherein each of the cell gate structures comprises: a first barrier layer, comprising a first region comprising a first material and a second region comprising a second material, wherein the first barrier layer is in the first trench and extends along the sidewalls and bottom surface of the first trench; a first insulating layer, comprising the second material on the sidewalls of the first barrier layer and extending along the sidewalls and bottom surface of the first trench; a cell gate electrode layer on the sidewalls of the first insulating layer, the cell gate electrode layer filling the first trench; and a covering layer, on the top surface of the cell gate electrode layer and the sidewalls of the first insulating layer, wherein the concentration of the second material in the first barrier layer is less than the concentration of the second material in the first insulating layer.

[0010] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming an element isolation layer defining a plurality of active regions on a substrate; forming a first trench in the substrate intersecting at least a portion of the plurality of active regions; forming a barrier layer comprising a first material along the sidewalls and bottom surface of the first trench; forming an insulating layer on the sidewalls of the barrier layer, the insulating layer comprising a second material different from the first material; and forming a gate electrode layer on the sidewalls of the insulating layer and filling the interior of the first trench, wherein the thickness of the barrier layer relative to the sidewalls of the first trench is less than or equal to half the thickness of the insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a schematic layout diagram showing a semiconductor device according to some embodiments;

[0013] Figure 2 Shows Figure 1 Schematic layout of region R1;

[0014] Figure 3 Only shows Figure 1 The layout of word lines and active areas;

[0015] Figure 4 Shows Figure 1 Schematic layout of region R2;

[0016] Figure 5 is along Figure 2 An exemplary cross-sectional view taken along line AA of FIG.

[0017] Figure 6 is along Figure 2 An exemplary cross-sectional view taken along line BB of ;

[0018] Figure 7 is along Figure 2 An exemplary cross-sectional view taken along line CC of ;

[0019] Figure 8 is along Figure 2 An exemplary cross-sectional view taken along line DD;

[0020] Fig. 9 yes Figure 8 an enlarged view of a portion P;

[0021] Fig.10 is along Figure 4 An exemplary cross-sectional view taken along line EE of ;

[0022] Fig.11 is a schematic layout diagram showing a semiconductor device according to some embodiments;

[0023] Fig.12 and Fig.13 is along Fig.11 An exemplary cross-sectional view taken along lines FF and GG;

[0024] Fig.14 is a schematic layout diagram showing a semiconductor device according to some embodiments;

[0025] Fig.15 and Fig.16 is along Fig.14 An exemplary cross-sectional view taken along lines HH and II; and

[0026] Figures 17 to 23 are diagrams illustrating intermediate steps of a method for fabricating a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0027] The principles and embodiments of the present invention are generally directed to solving the phenomenon of silicon (Si) loss, in which the width of the active region is reduced due to chemical changes in the silicon (Si). In addition, the defect that the gate trench may not be filled with the gate electrode due to oxide formation in the silicon of the active region can be reduced or avoided.

[0028] Figure 1 2 is a schematic layout diagram showing a semiconductor device according to various embodiments. Figure 2 Shows Figure 1 Schematic layout of region R1. Figure 3 It is shown Figure 1 The layout of word lines and active areas. Figure 4 Shows Figure 1 Schematic layout of region R2. Figure 5 is along Figure 2 An exemplary cross-sectional view taken along line AA. Figure 6 is along Figure 2 An exemplary cross-sectional view taken along line BB. Figure 7 is along Figure 2 Cross-sectional view taken along line CC. Figure 8 is along Figure 2 A cross-sectional view taken along line DD. Fig. 9 yes Figure 8 Magnified view of portion P. Fig.10 is along Figure 4 A cross-sectional view taken along line EE.

[0029] In the drawings of semiconductor devices according to some embodiments, a dynamic random access memory (DRAM) is shown as an example, but the present disclosure is not limited thereto.

[0030] Reference Figures 1 to 4 , a semiconductor device according to some embodiments may include a cell region 20 , a cell region isolation layer 22 , and a peripheral region 24 .

[0031] In various embodiments, the cell isolation layer 22 may be formed along the perimeter of the cell region 20, wherein the cell isolation layer 22 may surround the cell region 20. The cell isolation layer 22 may separate the cell region 20 from the peripheral region 24, wherein the peripheral region 24 may surround the cell isolation layer 22 and the cell region 20.

[0032] In various embodiments, the cell region 20 may include a plurality of cell active regions ACT, wherein the cell active regions ACT may be defined by a cell element isolation layer 105 formed in the substrate 100 (see, for example, Figure 5 ). As the design rule of the semiconductor device is reduced, as shown in the figure, the unit active area ACT may be arranged in a diagonal strip shape or an inclined strip shape. The unit active area ACT may extend in the third direction DR3.

[0033] In various embodiments, a plurality of gate electrodes extending in the first direction DR1 may be disposed across the cell active area ACT. The plurality of gate electrodes may extend parallel to each other. The plurality of gate electrodes may be, for example, a plurality of word lines WL. The word lines WL may be arranged at equal intervals, wherein the width of the word lines WL and / or the intervals between the word lines WL may be determined according to design rules.

[0034] In various embodiments, the word line WL may extend to the cell region isolation layer 22 , wherein a portion of the word line WL may overlap the cell region isolation layer 22 in the fourth direction DR4 .

[0035] Each cell active region ACT may be divided into three parts by two word lines WL extending in the first direction DR1. The cell active region ACT may include a storage connection region 103b and a bit line connection region 103a. The bit line connection region 103a may be located at a central portion of the cell active region ACT, and the storage connection region 103b may be located at an end of the cell active region ACT.

[0036] In various embodiments, the bit line connection region 103a may be a region connected to the bit line BL, and the storage connection region 103b may be a region connected to the information storage unit 190 (see, for example, Figure 5 ) region. The bit line connection region 103a may correspond to the common drain region, and the storage connection region 103b may correspond to the source region. Each word line WL and the bit line connection region 103a and storage connection region 103b adjacent thereto may constitute a transistor.

[0037] exist Figure 3 In the embodiment, when the transistor including each word line WL and the bit line connection portion 103a and the storage connection portion 103b adjacent thereto is an NMOS, the storage connection portion 103b and the bit line connection portion 103a may include at least one of doped n-type impurities, such as phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi). When the transistor including each word line WL and the bit line connection portion 103a and the storage connection portion 103b adjacent thereto is a PMOS, the storage connection portion 103b and the bit line connection portion 103a may include doped p-type impurities, such as boron (B).

[0038] In various embodiments, a plurality of bit lines BL extending in a second direction DR2 perpendicular to the word line WL may be disposed on the word line WL. The plurality of bit lines BL may extend parallel to each other. The bit lines BL may be arranged at equal intervals. The width of the bit lines BL and / or the intervals between the bit lines BL may be determined according to design rules.

[0039] In various embodiments, the bit line BL may extend to the cell region isolation layer 22. A portion of the bit line BL may overlap the cell region isolation layer 22 in a fourth direction DR4. The fourth direction DR4 may be orthogonal to the first direction DR1, the second direction DR2, and the third direction DR3. The fourth direction DR4 may be a thickness direction of the substrate 100.

[0040] The semiconductor device according to various embodiments may include various contact arrangements formed on the cell active area ACT. The various contact arrangements may include, for example, a direct contact (DC), a buried contact (BC), a landing pad (LP), and the like.

[0041] In various embodiments, the direct contact DC may refer to a contact that electrically connects the cell active region ACT to the bit line BL. The buried contact BC may be a contact that connects the cell active region ACT to the lower electrode 191 of the capacitor (see, for example, Figure 5 ) contact. Due to the configuration structure, the contact area between the buried contact BC and the cell active region ACT can be small. Therefore, in order to increase the contact area with the cell active region ACT and increase the contact with the lower electrode 191 (see, for example Figure 5 ) contact area, a conductive landing pad LP can be introduced.

[0042] In various embodiments, the landing pad LP may be disposed between the buried contact BC and the lower electrode 191 of the capacitor (see, e.g., Figure 5 By introducing the landing pad LP to expand the contact area, the contact resistance between the cell active area ACT and the capacitor lower electrode 191 can be reduced.

[0043] In various embodiments, the direct contact DC may be electrically connected to the bit line connection region 103a. The buried contact BC may be electrically connected to the storage connection region 103b. Since the buried contact BC is located at both ends of the cell active region ACT, the landing pad LP may be adjacent to both ends of the cell active region ACT to at least partially overlap with the buried contact BC. The buried contact BC may be formed to contact the cell element isolation layer 105 (see, e.g., FIG. 1 ) between adjacent word lines WL and between adjacent bit lines BL. Figure 5 ) overlaps with the cell active area.

[0044] In various embodiments, the word line WL may be buried in the substrate 100. The word line WL may be disposed across the cell active area ACT between the direct contact DC or the buried contact BC. As shown, two word lines WL may cross one cell active area ACT. When the cell active area ACT extends along the third direction DR3, the word line WL may have an angle of less than 90 degrees relative to the cell active area ACT.

[0045] In various embodiments, the direct contact DC and the buried contact BC may be arranged symmetrically. Therefore, the direct contact DC and the buried contact BC may be arranged in a straight line along the first direction DR1 and the second direction DR2. In contrast to the direct contact DC and the buried contact BC, the landing pads LP may be arranged in a zigzag shape in the second direction DR2 in which the bit lines BL extend, wherein the positions of the landing pads LP may be staggered in the first direction DR1. The landing pads LP may be arranged to overlap the same side surfaces of their respective bit lines BL in the first direction DR1 in which the word lines WL extend.

[0046] In various embodiments, each landing pad LP in the first line may overlap a left side surface of a corresponding bit line BL, and each landing pad LP in the second line may overlap a right side surface of a corresponding bit line BL.

[0047] Reference Figures 1 to 10 , a semiconductor device according to various embodiments may include a plurality of unit gate structures 110 , a plurality of bit line structures 140ST, a plurality of bit line contacts 146 , an information storage unit 190 , and a peripheral gate structure 240ST.

[0048] In various embodiments, the substrate 100 may include a cell region 20, a cell region isolation layer 22, and a peripheral region 24. The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0049] In various embodiments, a plurality of cell gate structures 110, a plurality of bit line structures 140ST, a plurality of bit line contacts 146, and an information storage unit 190 may be disposed in the cell region 20. A peripheral gate structure 240ST may be disposed in the peripheral region 24.

[0050] The peripheral region 24 may include a peripheral active region P_ACT extending in the first direction DR1. The peripheral active region P_ACT may be defined by a peripheral element isolation layer 205 formed in the substrate 100 (see, for example, Fig.10 ).

[0051] In various embodiments, the peripheral gate structure 240ST may be disposed on the peripheral active region P_ACT defined by the peripheral element isolation layer 205. The peripheral gate structure 240ST may extend in the second direction DR2, wherein the peripheral gate structure 240ST may cross the peripheral active region P_ACT.

[0052] In various embodiments, a cell element isolation layer 105 may be formed in the substrate 100 of the cell region 20. The cell element isolation layer 105 may have a shallow trench isolation (STI) structure configured to provide element isolation characteristics. The cell element isolation layer 105 may define a cell active region ACT in the cell region 20.

[0053] In various embodiments, the cell active region ACT defined by the cell element isolation layer 105 may have a stadium shape (also referred to as an oblong or disc-rectangular shape) having a short axis and a long axis, such as Figure 2 and Figure 3As shown in . The cell active area ACT may have an inclined orientation or shape, wherein the cell active area ACT may have an angle of less than 90 degrees relative to the word line WL formed in the cell element isolation layer 105. In addition, the cell active area ACT may have an inclined orientation or shape, wherein the cell active area ACT may have an angle of less than 90 degrees relative to the bit line BL formed on the cell element isolation layer 105.

[0054] In various embodiments, the cell isolation layer 22 may have an STI structure. The cell region 20 may be defined by the cell isolation layer 22 .

[0055] In various embodiments, the cell element isolation layer 105 and the cell region isolation layer 22 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, but is not limited thereto.

[0056] In various embodiments, the cell element isolation layer 105 and the cell region isolation layer 22 may be formed of a single insulating layer, but are not limited thereto. Depending on the width of the cell element isolation layer 105 and the cell region isolation layer 22, the cell element isolation layer 105 and the cell region isolation layer 22 may be formed of a single insulating layer or multiple insulating layers.

[0057] exist Figure 5 , it is shown that the top surface of the cell element isolation layer 105 and at least a portion of the top surface of the substrate 100 are located on the same plane. However, this is to simplify the description, and the present disclosure is not limited thereto.

[0058] The cell gate structure 110 may be formed in the substrate 100 and the cell element isolation layer 105, for example, as shown in FIG. Figure 6 As shown in . The cell gate structure 110 may be formed on the cell element isolation layer 105 and the cell active area ACT defined by the cell element isolation layer 105. The cell gate structure 110 may be a multi-layer structure separated from the substrate by the cell element isolation layer 105. The storage contact 120 may be located between adjacent pairs of the cell gate structures 110. The fence pattern 170 may be on the cell gate structure 110.

[0059] Each of the plurality of cell gate structures 110 may include a cell gate trench 115, a cell gate insulating layer 111, a cell gate electrode layer 112, a cell gate capping conductive layer 113, and a cell gate capping layer 114. The cell gate insulating layer 111 may include a first barrier layer 111A in the cell gate trench 115 and a first insulating layer 111B on the first barrier layer 111A. The cell gate capping layer 114 may fill the cell gate trench 115 remaining after the cell gate electrode layer 112 and the cell gate capping conductive layer 113 are formed.

[0060] In various embodiments, the cell gate electrode layer 112 may correspond to a word line WL, where, for example, the cell gate electrode layer 112 may be a word line WL, such as Figure 2 In various embodiments, the cell gate structure 110 may not include the cell gate capping conductive layer 113 .

[0061] like Figure 7 As shown, along Figure 2 The cell gate trench 115 may be relatively deep in the cell element isolation layer 105 and relatively shallow in the cell active area ACT. The cell element isolation layer 105 may be discontinuous along the first direction DR1. The bottom surface of the cell gate electrode layer 112 forming the word line WL may be curved and correspond to the shape of the cell gate trench 115, for example, as shown in FIG. Figure 6 As shown in . The depth of the cell gate trench 115 in the cell element isolation layer 105 may be greater than the depth of the cell gate trench 115 in the cell active region ACT.

[0062] In various embodiments, the cell gate insulating layer 111 may extend along a sidewall and a bottom surface of the cell gate trench 115. The cell gate insulating layer 111 may extend along a contour of at least a portion of the cell gate trench 115.

[0063] In various embodiments, the cell gate insulating layer 111 may include a first barrier layer 111A on the cell active region ACT and a first insulating layer 111B on the first barrier layer 111A. The first barrier layer 111A may extend in the direction of the cell gate trench 115, wherein the first barrier layer 111A may cover the sidewalls and bottom surface of the cell gate trench 115. The first insulating layer 111B may be on the sidewalls of the first barrier layer 111A and extend along the sidewalls and bottom surface of the cell gate trench 115. The first barrier layer 111A may be referred to as a first region of the cell gate insulating layer 111, and the first insulating layer 111B may be referred to as a second region of the cell gate insulating layer 111.

[0064] In various embodiments, the first barrier layer 111A may include a first material layer M1 including a first material and a second material layer M2 including a second material, wherein the first insulating layer 111B may include the second material. For example, the first material may include at least one of silicon, carbon, and nitrogen, and the second material may include oxygen.

[0065] In various embodiments, the first material layer M1 may include both the first material and the second material, but may include a greater thickness of the first material than the second material. The second material layer M2 may include a greater thickness of the second material than the first material.

[0066] In various embodiments, the concentration of the second material in the first barrier layer 111A may be less than the concentration of the second material in the first insulating layer 111 B. The concentration of the first material in the first barrier layer 111A may be greater than the concentration of the first material in the first insulating layer 111 B. For example, the first insulating layer 111B may substantially exclude the first material.

[0067] In some embodiments, the concentration of the first material or the second material may refer to the concentration of the material per unit volume.

[0068] In various embodiments, the concentration of the first material in the cell gate insulating layer 111 may increase as it is closer to the cell active region ACT, and decrease as it is closer to the cell gate electrode layer 112. The concentration of the first material in the cell gate insulating layer 111 may be smaller in a region adjacent to the cell gate electrode layer 112 than in a region adjacent to the cell active region ACT.

[0069] In addition, the concentration of the second material in the cell gate insulating layer 111 may decrease as it is closer to the cell active region ACT, and increase as it is closer to the cell gate electrode layer 112. In this case, the concentration of the second material in the first barrier layer 111A may decrease as it is closer to the cell active region ACT, and increase as it is closer to the cell gate electrode layer 112. The concentration of the second material in the cell gate insulating layer 111 may be greater in a region adjacent to the cell gate electrode layer 112 than in a region adjacent to the cell active region ACT.

[0070] Reference Fig. 9 , the thickness T11 of the first barrier layer 111A may be less than the thickness T21 of the first insulating layer 111B relative to the sidewall or bottom surface of the cell gate trench 115. For example, the thickness T11 of the first barrier layer 111A may be less than or equal to half of the thickness T21 of the first insulating layer 111B.

[0071] In various embodiments, the first insulating layer 111B may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, at least one dielectric material selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0072] In various embodiments, a cell gate electrode layer 112 may be formed on the cell gate insulating layer 111, wherein the cell gate electrode layer 112 may cover at least a portion of the first insulating layer 111B on the sidewall of the cell gate trench 115. The cell gate electrode layer 112 may fill a portion of the cell gate trench 115. A cell gate capping conductive layer 113 may be formed on the cell gate electrode layer 112 and extend along a top surface of the cell gate electrode layer 112.

[0073] In various embodiments, the cell gate electrode layer 112 may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, or a conductive metal oxide. The cell gate electrode layer 112 may include, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto. The cell gate capping conductive layer 113 may include, for example, polysilicon or polysilicon germanium, but is not limited thereto. In various embodiments, the cell gate structure 110 may not include the cell gate capping conductive layer 113 .

[0074] In various embodiments, the cell gate capping layer 114 may be disposed on the cell gate electrode layer 112 and the cell gate capping conductive layer 113. The cell gate capping layer 114 may fill an upper portion of the cell gate trench 115 remaining after forming the cell gate electrode layer 112 and the cell gate capping conductive layer 113. The cell gate insulating layer 111 is illustrated as extending along a sidewall of the cell gate capping layer 114, but is not limited thereto.

[0075] In various embodiments, the cell gate capping layer 114 may be disposed on the top surface of the cell gate electrode layer 112 and the sidewall of the first insulating layer 111B. The bottom surface of the cell gate capping layer 114 may contact the top surface of the cell gate electrode layer 112, but may not contact each of the top surface of the first barrier layer 111A and the top surface of the first insulating layer 111B.

[0076] In various embodiments, the cell gate capping layer 114 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), SiO 2, silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN) or at least one of a combination thereof.

[0077] exist Figure 6 In the embodiment, the top surface of the cell element isolation layer 105 may extend toward the top surface of the cell gate capping layer 114, but is not limited thereto.

[0078] like Figure 8 As shown, an impurity-doped region may be formed on at least one side of the cell gate structure 110. The impurity-doped region may be a source / drain region of the transistor. Figure 3 An impurity doped region is formed in each of the storage connection portion 103b and the bit line connection portion 103a.

[0079] In various embodiments, the bit line structure 140ST may include a cell conductive line 140, a cell line capping layer 144, and a bit line spacer 150, for example, Figure 5 as shown in .

[0080] In various embodiments, the cell conductive line 140 may be disposed on the substrate 100 and the cell element isolation layer 105 on which the cell gate structure 110 is formed. The cell conductive line 140 may cross the cell element isolation layer 105 and the cell active area ACT defined by the cell element isolation layer 105. The cell conductive line 140 may be formed to cross the cell gate structure 110. Here, the cell conductive line 140 may correspond to the bit line BL. For example, the cell conductive line 140 may be Figure 2 The bit line BL.

[0081] In various embodiments, the unit conductive line 140 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a two-dimensional (2D) material, a metal, or a metal alloy. In the semiconductor device according to various embodiments, the 2D material may be a metal material and / or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound. For example, the two-dimensional (2D) material may include graphene, molybdenum disulfide (MoS 2 ), Molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) or tungsten disulfide (WS 2 ), but not limited to.

[0082] In various embodiments, the unit conductive line 140 may be a multi-layer. The unit conductive line 140 may include, for example, a first unit conductive layer 141, a second unit conductive layer 142, and a third unit conductive layer 143. The first to third unit conductive layers 141, 142, and 143 may be sequentially stacked on the substrate 100 and the unit element isolation layer 105. Although the unit conductive line 140 is shown as three layers, the present disclosure is not limited thereto and may have a greater or lesser number of layers.

[0083] Each of the first to third unit conductive layers 141, 142, and 143 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a metal, or a metal alloy. For example, the first unit conductive layer 141 may include a doped semiconductor material, the second unit conductive layer 142 may include at least one of a conductive silicide compound or a conductive metal nitride, and the third unit conductive layer 143 may include at least one of a metal or a metal alloy, but the present disclosure is not limited thereto.

[0084] In various embodiments, a bit line contact 146 may be formed between the cell conductive line 140 and the substrate 100, wherein the cell conductive line 140 may be formed on the bit line contact 146. For example, the bit line contact 146 may be formed at a point where the cell conductive line 140 crosses the central portion of the cell active area ACT having a stadium shape. The bit line contact 146 may be formed between the bit line connection region 103a and the cell conductive line 140.

[0085] In various embodiments, the bit line contact 146 may electrically connect the cell conductive line 140 to the substrate 100. Here, the bit line contact 146 may correspond to a direct contact (DC). The bit line contact 146 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.

[0086] exist Figure 5 , the cell conductive line 140 may include a second cell conductive layer 142 and a third cell conductive layer 143 in a region overlapping with a top surface of a bit line contact 146, wherein the second cell conductive layer 142 is in electrical contact with the bit line contact 146. The cell conductive line 140 may include first to third cell conductive layers 141, 142, and 143 in a region not overlapping with a top surface of the bit line contact 146.

[0087] In various embodiments, the cell line cover layer 144 may be disposed on the cell conductive line 140. The cell line cover layer 144 may extend in the second direction DR2 along the top surface of the cell conductive line 140. The cell line cover layer 144 may include, for example, at least one of a silicon nitride layer, silicon oxynitride, silicon carbon nitride, or silicon oxycarbon nitride.

[0088] In the semiconductor device according to various embodiments, the cell line cover layer 144 may include a silicon nitride layer. Although the cell line cover layer 144 is shown as a single layer, the present disclosure is not limited thereto. Unlike the illustration, the cell line cover layer 144 may be formed of multiple layers.

[0089] In various embodiments, the bit line spacer 150 may be disposed on sidewalls of the cell conductive line 140 and sidewalls of the cell line capping layer 144. The bit line spacer 150 may be elongated in the second direction DR2.

[0090] Although the bit line spacer 150 is shown as a single layer, this is only for simplifying the description, and the present disclosure is not limited thereto. The bit line spacer 150 may have a multi-layer structure. The bit line spacer 150 may include, for example, one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (SiON), a silicon oxycarbon nitride layer (SiOCN), air, or a combination thereof, but is not limited thereto.

[0091] In various embodiments, the cell insulating layer 130 may be formed on the substrate 100 and the cell element isolation layer 105. More specifically, the cell insulating layer 130 may be formed on the top surface of the cell element isolation layer 105 and the top surface of the substrate 100 on which the bit line contact 146 is not formed. The cell insulating film 130 may be formed between the substrate 100 and the cell conductive line 140 and between the cell element isolation layer 105 and the cell conductive line 140.

[0092] In various embodiments, the unit insulating layer 130 may be a single layer, but as shown in the figure, the unit insulating layer 130 may be a multilayer including a first unit insulating layer 131 and a second unit insulating layer 132. For example, the first unit insulating layer 131 may include a silicon oxide layer, and the second unit insulating layer 132 may include a silicon nitride layer, but they are not limited thereto. The unit insulating layer 130 may be a triple layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but is not limited thereto.

[0093] In a portion of the cell conductive line 140 where the bit line contact 146 is formed, a bit line spacer 150 may be formed on the substrate 100 and on at least a portion of the cell element isolation layer 105. The bit line spacer 150 may be disposed on sidewalls of the cell conductive line 140, the cell line capping layer 144, and the bit line contact 146.

[0094] In various embodiments, the bit line spacer 150 may be disposed on the cell insulating layer 130 in the remaining portion of the cell conductive line 140 where the bit line contact 146 is not formed. The bit line spacer 150 may be disposed on the sidewalls of the cell conductive line 140 and the cell line capping layer 144.

[0095] The fence pattern 170 may be disposed on the substrate 100 and the cell element isolation layer 105, such as Figure 6 The fence pattern 170 may be formed to overlap the cell gate structure 110 formed in the substrate 100 and the cell element isolation layer 105 .

[0096] In various embodiments, the fence pattern 170 may be disposed between the bit line structures 140ST extending along the second direction DR2, for example, Figure 7 The fence pattern 170 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0097] In various embodiments, the storage contact 120 may be disposed between the cell conductive lines 140 adjacent to each other in the first direction DR1, for example, Figure 5 The storage contact 120 may be disposed between the adjacent cell conductive lines 140 in the first direction DR1. More specifically, the storage contact 120 may be disposed between the bit line structures 140ST. The storage contact 120 may be disposed between the adjacent fence patterns 170 in the second direction DR2, for example, Figure 6 shown.

[0098] In various embodiments, the storage contact 120 may overlap the substrate 100 and the cell element isolation layer 105 between adjacent cell conductive lines 140. The storage contact 120 may be electrically connected to the cell active region ACT. More specifically, the storage contact 120 may be electrically connected to the storage connection portion 103b. Here, the storage contact 120 may correspond to Figure 2 The buried contact BC.

[0099] In various implementations, the storage contact 120 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.

[0100] In various embodiments, the storage pad 160 may be formed on the storage contact 120. The storage pad 160 may be electrically connected to the storage contact 120. The storage pad 160 may be electrically connected to the storage connection portion 103b of the cell active area ACT. Here, the storage pad 160 may correspond to a landing pad LP.

[0101] In various embodiments, the storage pad 160 may overlap a portion of a top surface of the bit line structure 140ST. The storage pad 160 may include, for example, at least one of a conductive metal nitride, a conductive metal carbide, a metal, or a metal alloy.

[0102] In various embodiments, a pad separation insulating layer 180 may be formed adjacent to the storage pad 160 and the bit line structure 140ST, wherein the fence pattern 170 may electrically separate the storage pad 160 and the storage contact 120 from the cell conductive line 140, the cell line capping layer 144, and the bit line spacer 150 of the bit line structure 140ST, for example, Figure 8 . The pad separation insulating layer 180 may be disposed on the fence pattern 170, the cell line capping layer 144, and the bit line spacer 150. The pad separation insulating layer 180 may define the storage pad 160, and the pad separation insulating layer 180 forms a plurality of isolation regions. The pad separation insulating layer 180 may not cover the top surface of the storage pad 160. The height of the top surface of the storage pad 160 may be the same as the height of the top surface of the pad separation insulating layer 180 relative to the top surface of the substrate 100.

[0103] In various embodiments, pad separation insulating layer 180 may include an electrically insulating material to electrically separate the plurality of storage pads 160 from each other. Pad separation insulating layer 180 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbon nitride layer, or a silicon carbon nitride layer.

[0104] The etch stop layer 295 may be disposed on the top surface of the storage pad 160 and the top surface of the pad separation insulating layer 180. The etch stop layer 295 may include, for example, at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), silicon oxycarbide (SiOC), or silicon boron nitride (SiBN).

[0105] In various embodiments, the information storage unit 190 may be formed on the storage pad 160. The information storage unit 190 may be electrically connected to the storage pad 160. A portion of the information storage unit 190 may be disposed within the etch stop layer 295.

[0106] In various embodiments, the information storage unit 190 may include, for example, a capacitor, but is not limited thereto. In various embodiments, the information storage unit 190 includes a lower electrode 191, a capacitor dielectric layer 192, and an upper electrode 193. For example, the upper electrode 193 may be a plate-shaped upper electrode having a plate shape.

[0107] In various embodiments, the lower electrode 191 may be disposed on the storage pad 160, wherein the lower electrode 191 may be in electrical contact with the storage pad 160. The lower electrode 191 may have, for example, a pillar shape.

[0108] In various embodiments, a capacitor dielectric layer 192 is formed on the lower electrode 191. The capacitor dielectric layer 192 may be formed along the contour of the lower electrode 191, wherein the capacitor dielectric layer 192 may be on the top surface and at least a portion of the sidewall of the lower electrode 191. An upper electrode 193 may be formed on the capacitor dielectric layer 192, wherein the upper electrode 193 may surround the outer wall of the lower electrode 191. Although the upper electrode 193 is shown as a single layer, this is only for the purpose of simplifying the description, and the present disclosure is not limited thereto.

[0109] Each of the lower electrode 191 and the upper electrode 193 may include, for example, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc.), metals (e.g., ruthenium, iridium, titanium, tantalum, etc.), conductive metal oxides (e.g., iridium oxide, niobium oxide, etc.), etc., but the present disclosure is not limited thereto.

[0110] In various embodiments, the capacitor dielectric layer 192 may include, for example, one of silicon oxide, silicon nitride, silicon oxynitride, high-k material, or a combination thereof, but is not limited thereto. In a semiconductor device according to some embodiments, the capacitor dielectric layer 192 may include a stacked structure in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence. In a semiconductor device according to some embodiments, the capacitor dielectric layer 192 may include a dielectric layer containing hafnium (Hf). In a semiconductor device according to some embodiments, the capacitor dielectric layer 192 may have a stacked structure including a ferroelectric material layer and a paraelectric material layer.

[0111] In various embodiments, the peripheral element isolation layer 205 may be formed in the substrate 100 in the peripheral region 24, for example, Fig.10 . The peripheral element isolation layer 205 may define a peripheral active region P_ACT in the peripheral region 24. The top surface of the peripheral element isolation layer 205 is shown to be on the same plane as the top surface of the substrate 100, but is not limited thereto. The peripheral element isolation layer 205 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, but the present disclosure is not limited thereto.

[0112] In various embodiments, the peripheral gate structure 240ST may be disposed on the substrate 100 in the peripheral region 24 .

[0113] In various embodiments, the peripheral gate structure 240ST may include a peripheral gate insulating layer 230, a peripheral gate conductive layer 240, and a peripheral capping layer 244 sequentially stacked on the substrate 100, for example, Fig.10 The peripheral gate structure 240ST may include a peripheral spacer 245 disposed on the sidewalls of the peripheral gate insulating layer 230 , the sidewalls of the peripheral gate conductive layer 240 , and the sidewalls of the peripheral capping layer 244 .

[0114] In various embodiments, the peripheral gate insulating layer 230 may include a second barrier layer 230A on the peripheral active region P_ACT and a second insulating layer 230B on the second barrier layer 230A.

[0115] In various embodiments, the second barrier layer 230A may include a first material and a second material. The second insulating layer 230B may include a second material. In some embodiments, the first material may include at least one of silicon, carbon, and nitrogen, and the second material may include oxygen.

[0116] In various embodiments, the concentration of the second material in the second barrier layer 230A may be less than the concentration of the second material in the second insulating layer 230B. The concentration of the first material in the second barrier layer 230A may be greater than the concentration of the first material in the second insulating layer 230B. For example, the second insulating layer 230B may not include the first material.

[0117] In various embodiments, the concentration of the first material in the peripheral gate insulating layer 230 may increase as it is closer to the peripheral active region P_ACT, and decrease as it is closer to the peripheral gate conductive layer 240. In addition, the concentration of the second material in the peripheral gate insulating layer 230 may decrease as it is closer to the peripheral active region P_ACT, and increase as it is closer to the peripheral gate conductive layer 240. The concentration of the second material in the second barrier layer 230A may decrease as it is closer to the peripheral active region P_ACT, and increase as it is closer to the peripheral gate conductive layer 240.

[0118] Reference Fig.10 , with respect to the fourth direction DR4, the thickness T12 of the second barrier layer 230A may be less than the thickness T22 of the second insulating layer 230B. For example, the thickness T12 of the second barrier layer 230A may be less than or equal to half of the thickness T22 of the second insulating layer 230B.

[0119] In various embodiments, the second insulating layer 230B may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, at least one dielectric material selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0120] In various embodiments, the peripheral gate conductive layer 240 may include first to third peripheral conductive layers 241, 242, and 243 sequentially stacked on the peripheral gate insulating layer 230. For example, no additional conductive layer may be provided between the peripheral gate conductive layer 240 and the peripheral gate insulating layer 230. An additional conductive layer such as a work function conductive layer may be provided between the peripheral gate conductive layer 240 and the peripheral gate insulating layer 230.

[0121] Although it is shown that one peripheral gate structure 240ST is disposed between adjacent peripheral element isolation layers 205 , this is only for simplifying the description and is not limited thereto.

[0122] In various embodiments, a peripheral etch stop layer 250 may be disposed on the substrate 100 and on the sidewalls of the peripheral spacer 245. The peripheral etch stop layer 250 may be formed along the contour of the peripheral gate structure 240ST and the top surface of the substrate 100. The peripheral etch stop layer 250 may be between the peripheral capping layer 244 and the interlayer insulating layer 291 thereover.

[0123] In various embodiments, the peripheral etch stop layer 250 may include, for example, at least one of silicon nitride, silicon oxynitride, silicon carbon nitride, or silicon oxycarbon nitride.

[0124] In various embodiments, a first peripheral interlayer insulating layer 290 may be disposed on the peripheral etch stop layer 250. The first peripheral interlayer insulating layer 290 may be disposed around the peripheral gate structure 240ST, wherein the peripheral etch stop layer 250 may separate the first peripheral interlayer insulating layer 290 from the peripheral gate structure 240ST.

[0125] In various embodiments, an insertion interlayer insulating layer 291 may be disposed on the peripheral gate structure 240ST and the first peripheral interlayer insulating layer 290. The insertion interlayer insulating layer 291 may cover the peripheral gate structure 240ST and the first peripheral interlayer insulating layer 290. The peripheral etch stop layer 250 may separate the peripheral capping layer 244 from the insertion interlayer insulating layer 291.

[0126] In various embodiments, the insertion interlayer insulating layer 291 may include a material different from that of the first peripheral interlayer insulating layer 290. The insertion interlayer insulating layer 291 may include, for example, a nitride-based insulating material, wherein, for example, the insertion interlayer insulating layer 291 may include silicon nitride.

[0127] Therefore, in the etching process included in the process of manufacturing the information storage unit 190, the insertion interlayer insulating layer 291 can protect the first peripheral interlayer insulating layer 290. In the etching process included in the process of manufacturing the information storage unit 190, the insertion interlayer insulating layer 291 can prevent defects caused by etching the first peripheral interlayer insulating layer 290.

[0128] In various embodiments, the peripheral wiring line 260 may be disposed on the interlayer insulating layer 291. Peripheral contact plugs connected to the peripheral wiring line 260 may be disposed on both sides of the peripheral gate structure 240ST. The peripheral contact plugs may penetrate the interlayer insulating layer 291 and the first peripheral interlayer insulating layer 290 and extend to the substrate 100 of the peripheral region 24.

[0129] In various embodiments, the peripheral wiring line 260 and the peripheral contact plug may include the same conductive material as the storage pad 160 .

[0130] In various embodiments, an etch stop layer 295 may be disposed on the peripheral wiring line 260. A second peripheral interlayer insulating layer 293 may be disposed on the etch stop layer 295. The second peripheral interlayer insulating layer 293 may cover the sidewalls of the first upper electrode 193. The second peripheral interlayer insulating layer 293 may include an insulating material.

[0131] Fig.11 is a schematic layout diagram illustrating a semiconductor device according to some embodiments. Fig.12 and Fig.13 is along Fig.11 For simplicity of description, the following description will focus on the reference Figures 1 to 10 The difference in description.

[0132] For reference, Fig.11 A first fin pattern 301 , a second fin pattern 302 , and a gate structure 330 are schematically illustrated, wherein a first gate contact CB1 is disposed between the first fin pattern 301 and the second fin pattern 302 .

[0133] Reference Figures 11 to 13 , a semiconductor device according to various embodiments may include a substrate 300, a first fin pattern 301, a second fin pattern 302, a field insulating layer 305, a gate structure 330, an interlayer insulating layer 320, a capping pattern 340, a source / drain region 350, and a first gate contact CB1. In some embodiments, the first fin pattern 301 and the second fin pattern 302 may mean an active region.

[0134] In various embodiments, the substrate 300 may be a bulk silicon or silicon-on-insulator (SOI) substrate. Alternatively, the substrate 300 may be a silicon substrate, or may include other materials, such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, the technical spirit of the present disclosure is not limited thereto. In the following, for simplicity of description, it is assumed that the substrate 300 is a substrate containing silicon.

[0135] In various embodiments, the first fin pattern 301 and the second fin pattern 302 may be defined by a field insulating layer 305. The first fin pattern 301 and the second fin pattern 302 may be spaced apart, but may be adjacent to each other. The first fin pattern 301 may extend in a fifth direction DR5 of the substrate 100. The second fin pattern 302 may be spaced apart from the first fin pattern 301 in a sixth direction DR6 of the substrate 100 and extend in the fifth direction DR5.

[0136] In various embodiments, the field insulation layer 305 may be formed to surround the first fin pattern 301 and the second fin pattern 302. The field insulation layer 305 may be disposed between the first fin pattern 301 and the second fin pattern 302, and may be in direct contact with the first fin pattern 301 and the second fin pattern 302. The field insulation layer 305 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

[0137] In various embodiments, for example, Fig.12 As shown, the gate structure 330 may extend in a sixth direction DR6 intersecting the fifth direction DR5 on the first fin pattern 301. The gate structure 330 may include a gate trench, a gate spacer 333, a barrier layer 331A, an insulating layer 331B, and a gate electrode layer 332. The gate electrode layer may be formed on the sidewall of the gate insulating layer and fill the inside of the gate trench. The barrier layer 331A and the insulating layer 331B may be referred to as a gate insulating layer.

[0138] Although the gate spacer 333 is shown as being formed of a single layer, the technical spirit of the present disclosure is not limited thereto. In some embodiments, the gate spacer 333 may be formed of a plurality of layers. The gate spacer 333 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), SiO 2 , silicon oxycarbon nitride (SiOCN), or at least one of a combination thereof. In some embodiments, the gate spacer 333 may be used as a guide for forming a self-aligned contact. Therefore, the gate spacer 333 may include a material having an etching selectivity with respect to the interlayer insulating layer 320 to be described later.

[0139] In various embodiments, the barrier layer 331A may include a first material and a second material. The insulating layer 331B may include the second material. In some embodiments, the first material may include at least one of silicon, carbon, and nitrogen, and the second material may include oxygen.

[0140] In various embodiments, the concentration of the second material in the barrier layer 331A may be less than the concentration of the second material in the insulating layer 331 B. The concentration of the first material in the barrier layer 331A may be greater than the concentration of the first material in the insulating layer 331 B. For example, the insulating layer 331B may not include the first material.

[0141] In various embodiments, the concentration of the first material in the gate insulating layer may increase as it is closer to the first fin pattern 301, and decrease as it is closer to the gate electrode layer 332. In addition, the concentration of the second material in the gate insulating layer may decrease as it is closer to the first fin pattern 301, and increase as it is closer to the gate electrode layer 332. The concentration of the second material in the barrier layer 331A may decrease as it is closer to the first fin pattern 301, and increase as it is closer to the gate electrode layer 332.

[0142] Reference Fig.12 , with respect to the fifth direction DR5 or the seventh direction DR7, a thickness T13 of the barrier layer 331A may be less than a thickness T23 of the insulating layer 331B.

[0143] In various embodiments, the insulating layer 331B may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, at least one dielectric material selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0144] In various embodiments, the gate electrode layer 332 may include a metal nitride including at least one of titanium (Ti) or tantalum (Ta) and / or at least one of W, Al, Co, Cu, Ru, Ni, Pt, or Ni-Pt. The gate electrode layer 332 is shown in the drawings as being formed as a single layer, but the technical spirit of the present disclosure is not limited thereto. In various embodiments, the gate electrode layer 332 may include a plurality of layers.

[0145] In various embodiments, an interlayer insulating layer 320 may be formed on the substrate 300, wherein the interlayer insulating layer 320 may surround the outer wall of the gate spacer 333 and the capping pattern 340. The interlayer insulating layer 320 may include, for example, SiO 2 , silicon nitride (SiN), silicon oxynitride (SiON), flowable oxide (FOX), eastern silazane (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material or a combination thereof. However, the technical spirit of the present disclosure is not limited thereto.

[0146] In various embodiments, a capping pattern 340 may be formed on and cover the gate structure 330. Unlike the illustration, a top surface of the capping pattern 340 may be coplanar with a top surface of the interlayer insulating layer 320. The capping pattern 340 may contact a sidewall of the interlayer insulating layer 320.

[0147] Since the capping pattern 340 may be used as a guide for forming a self-aligned contact, the capping pattern 340 may include a material that may be selectively etched relative to the interlayer insulating layer 320. The capping pattern 340 may include an insulating material, and may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), SiO 2 , silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN) or at least one of a combination thereof.

[0148] In various embodiments, for example, Fig.13 As shown, the first gate contact CB1 may be disposed on the gate structure 330 , and may be disposed between the first fin pattern 301 and the second fin pattern 302 .

[0149] In various embodiments, the first gate contact CB1 may penetrate the capping pattern 340 and may electrically contact the gate structure 330, wherein the first gate contact CB1 may electrically contact the gate electrode layer 332. The material of the first gate contact CB1 may be tungsten (W), but is not limited thereto.

[0150] Fig.14 2 is a schematic layout diagram showing a semiconductor device according to various embodiments. Fig.15 and Fig.16 is along Fig.14For simplicity of description, the following description will focus on the reference Figures 1 to 13 The difference in description.

[0151] Reference Figures 14 to 16 , a semiconductor device according to various embodiments may include a substrate 400 , a first fin pattern 401 , a second fin pattern 402 , a field insulation layer 405 , a gate structure 430 , an interlayer insulation layer 420 , a capping pattern 440 , a source / drain region 450 , a second gate contact CB2 , and a plurality of nanosheets 434 .

[0152] In various embodiments, in addition to the plurality of nanosheets 434, the configuration of the embodiments may correspond to Figures 11 to 13 Each of the substrate 300, the first fin pattern 301, the second fin pattern 302, the field insulation layer 305, the gate structure 330, the interlayer insulation layer 320, the capping pattern 340, the source / drain region 350 and the first gate contact CB1.

[0153] In various embodiments, three nanosheets 434 may be sequentially formed on the substrate 400, but the technical spirit of the present disclosure is not limited thereto. In various embodiments, the number of nanosheets formed on the substrate 400 may be different. The three nanosheets 434 may be sequentially stacked on the substrate 400 in the seventh direction DR7 and spaced apart from each other.

[0154] Each of the plurality of nanosheets 434 may extend in the fifth direction DR5. In addition, a top surface of the uppermost nanosheet on the first fin pattern 401 may be formed on substantially the same plane as a top surface of the source / drain region 450. However, the technical spirit of the present disclosure is not limited thereto.

[0155] In various embodiments, the plurality of nanosheets 434 may be surrounded by a gate structure 430. The plurality of nanosheets 434 may be surrounded by a gate insulating layer, wherein the barrier layer 431A and the insulating layer 431B may be referred to as a gate insulating layer. The plurality of nanosheets 434 may each be surrounded by a gate electrode layer 432, wherein the gate electrode layer 432 surrounds the gate insulating layer.

[0156] According to some embodiments, each of the plurality of nanosheets 434 may serve as a channel region, and the material may vary according to the shape of the semiconductor device.

[0157] When the semiconductor device according to some embodiments is an NMOS transistor, each of the plurality of nanosheets 434 may include, for example, a material having high electron mobility, and when the semiconductor device according to some embodiments is a PMOS transistor, each of the plurality of nanosheets 434 may include, for example, a material having high hole mobility.

[0158] In various embodiments, the barrier layer 431A may include a first material and a second material. The insulating layer 431B may include the second material. In some embodiments, the first material may include at least one of silicon, carbon, and nitrogen, and the second material may include oxygen.

[0159] In various embodiments, the concentration of the second material in the blocking layer 431A may be less than the concentration of the second material in the insulating layer 431 B. The concentration of the first material in the blocking layer 431A may be greater than the concentration of the first material in the insulating layer 431 B. In various embodiments, the insulating layer 431B may not include the first material.

[0160] In various embodiments, the concentration of the first material in the gate insulating layer may increase as it is closer to the first fin pattern 401, and decrease as it is closer to the gate electrode layer 432. In addition, the concentration of the second material in the gate insulating layer may decrease as it is closer to the first fin pattern 401, and increase as it is closer to the gate electrode layer 432. The concentration of the second material in the barrier layer 431A may decrease as it is closer to the first fin pattern 401, and increase as it is closer to the gate electrode layer 432.

[0161] Reference Fig.15 , with respect to the fifth direction DR5 or the seventh direction DR7, the thickness of the barrier layer 431A may be smaller than the thickness of the insulating layer 431B.

[0162] In various embodiments, the insulating layer 431B may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, at least one dielectric material selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0163] Figures 17 to 23 is a diagram showing intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Figures 1 to 10 To simplify the description, Fig.18 , Fig. 20 and Fig. 22 The first direction DR1 and the third direction DR3 in FIG. 5 may be illustrated and described as crossing directions that are perpendicular to each other.

[0164] For reference, Fig.17is a layout diagram for describing a method for manufacturing a semiconductor device according to some embodiments. Fig.18 , Fig. 20 and Fig. 22 yes Fig.17 A magnified view of section Q. Fig.19 , Fig.21 and Fig.23 is along Fig.17 A cross-sectional view taken along line JJ.

[0165] Reference Fig.17 A cell element isolation layer 105 may be formed in the substrate 100, wherein the cell element isolation layer 105 may have a shallow trench isolation (STI) structure configured to provide an element isolation characteristic. The cell element isolation layer 105 may define a cell active region ACT in a memory cell region.

[0166] In various embodiments, the cell element isolation layer 105 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, but the present invention is not limited thereto.

[0167] Although the cell element isolation layer 105 is shown as a single layer, this is only for simplifying the description, and the present disclosure is not limited thereto. The cell element isolation layer 105 may be formed of one insulating layer, or may be formed of a plurality of insulating layers.

[0168] Reference Fig.18 and Fig.19 , a first trench 115 may be formed in the substrate 100 and the cell element isolation layer 105. For example, after a mask pattern is formed on the substrate 100, the substrate 100 may be etched using the mask pattern as an etching mask to form the first trench 115. The first trench 115 may extend in the first direction DR1. The first trench 115 may be formed across the cell element isolation layer 105 and the cell active region ACT, wherein the cell active region ACT may be separated by the cell element isolation layer 105. The first trench 115 may have a circular bottom surface.

[0169] Reference Fig. 20 and Fig.21 , a pre-blocking layer 111PA including a first material may be formed along sidewalls and a bottom surface of the first trench 115 .

[0170] In various embodiments, the pre-blocking layer 111PA may include at least one of silicon (Si), silicon carbide (SiC), silicon nitride (SiN), silicon carbon nitride (SiCN), or silicon oxynitride (SiON).

[0171] In various embodiments, the pre-blocking layer 111PA can be formed by using diisopropylaminosilane (DIPAS), C 2 H4 , C 3 H 6 etc. as a gas phase doping (GPD) method for a source material containing carbon.

[0172] In various embodiments, the pre-blocking layer 111PA may be formed using a SiN layer as a source material for containing nitrogen. Alternatively, the pre-blocking layer 111PA may be formed by a method of nitriding the surface of the cell active area ACT using plasma.

[0173] In various embodiments, the pre-blocking layer 111PA may be formed by a method of additionally depositing a Si layer or additionally depositing a Si-rich oxide layer on the surface of the cell active area ACT.

[0174] In various embodiments, the pre-blocking layer 111PA may include, for example, silicon, carbon, nitrogen, or oxygen.

[0175] Reference Fig. 22 and Fig.23 , a pre-insulating layer 111PB including a second material different from the first material may be formed on a sidewall of the pre-blocking layer 111PA.

[0176] With respect to the sidewall of the first trench 115, the thickness T1 of the pre-blocking layer 111PA may be less than or equal to half of the thickness T2 of the pre-insulating layer 111PB. For example, the thickness T1 of the pre-blocking layer 111PA may be or smaller, but not limited thereto.

[0177] In various embodiments, the pre-insulating layer 111PB may be formed using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The pre-insulating layer 111PB may be formed along the sidewalls and bottom surface of the first trench 115. The pre-insulating layer 111PB may include silicon oxide. The pre-insulating layer 111PB may include an interface oxide layer formed by oxidizing the pre-blocking layer 111PA on the cell active area ACT. The interface oxide layer and the pre-insulating layer 111PB may include the same material, and in this case, the interface between the interface oxide layer and the pre-insulating layer 111PB may not be distinguished.

[0178] Therefore, the pre-insulating layer 111PB may include, for example, a second material such as oxygen.

[0179] The first barrier layer 111A may be formed from the pre-barrier layer 111PA by a radical oxidation process (see, e.g., Figure 8 ).

[0180] In various embodiments, the free radical oxidation process refers to the process of activating oxygen (O 2) to induce oxygen radicals (O*) and an oxidation reaction using the oxygen radicals with silicon (Si) or a silicon source, wherein the oxygen radicals (O*) are free radicals.

[0181] In various embodiments, when the first material is nitrogen, a radical oxidation process may be performed to substantially oxidize the silicon nitride included in the pre-blocking layer 111PA into silicon oxide. The radical oxidation process may be performed by providing radicals of an oxidation source and a reduction source. Oxygen may be provided as an oxidation source, and hydrogen may be provided as a reducing gas. Oxygen radicals (O*) may be provided as an oxidation source on the pre-blocking layer 111PA, and hydrogen radicals (H*) may be provided as a reduction source for reducing nitrogen included in the nitride. Oxygen radicals (O*) and hydrogen radicals (H*) may destroy the silicon-nitrogen bonding of the pre-blocking layer 111PA, induce silicon-oxygen bonding, and induce nitrogen to be removed as a byproduct such as nitrogen hydrate. That is, silicon nitride may be oxidized or converted into silicon oxide by a radical oxidation process.

[0182] The first barrier layer 111A (see, e.g., Figure 8 ) may include a first material and a second material. In this case, the first insulating layer 111B (see, for example, Figure 8 The concentration of the first material in the first insulating layer 111B (see, for example, Figure 8 ) may be greater in a region adjacent to the cell active region ACT and smaller in a region adjacent to the cell gate electrode layer 112.

[0183] In various embodiments, a concentration of the first material in the first barrier layer 111A may be greater than a concentration of the first material in the first insulating layer 111 B. For example, the first insulating layer 111B may substantially exclude the first material.

[0184] In various embodiments, when the first material is nitrogen, the pre-blocking layer 111PA including the silicon nitride layer is subjected to radical oxidation, and as a result of transmission electron microscopy (TEM) analysis of the resulting layer, it can be confirmed that silicon and oxygen are detected, while a very small amount of nitrogen is detected. That is, it can be understood that the first blocking layer 111A oxidized by the radical oxidation process substantially includes a silicon oxide layer. A small amount of nitrogen components can be detected at the interface portion between the cell active area ACT and the first blocking layer 111A.

[0185] In various embodiments, the first barrier layer 111A is formed by a radical oxidation process (see, e.g., Figure 8 ) may have a concentration of the second material less than that of the first insulating layer 111B (see, for example Figure 8). The concentration of the second material in the cell gate insulating layer 111 may decrease as it is closer to the cell active region ACT, and increase as it is closer to the cell gate electrode layer 112. The concentration of the second material in the cell gate insulating layer 111 may be greater in a region adjacent to the cell gate electrode layer 112 than in a region adjacent to the cell active region ACT.

[0186] This oxygen concentration can be measured, for example, by secondary ion mass spectrometry (SIMS), which analyzes the mass of ions (secondary ions) separated from the sample surface when ions (primary ions) with a certain energy collide with the sample surface. In this case, the oxygen concentration can be identified by measuring the distribution obtained by the number of oxygen atoms bouncing off the sample surface using a sputtering process.

[0187] In the free radical oxidation process, because the reactivity of oxygen radicals (O*) is high, the dependence on the Si surface can be small, an oxide layer with conformal thickness can be obtained, and the Si-Si bonding within the oxide layer can be destroyed, thereby reducing trapped charges in the oxide layer.

[0188] In the radical oxidation process according to some embodiments, the pre-blocking layer 111PA is oxidized, so that the oxidation of the lower cell active area ACT can be effectively suppressed. As a result, the cell gate electrode layer 112 in the first trench 115 can be formed to have a more uniform thickness in the third direction DR3. The defect of excessive formation of the gate dielectric layer without filling the gate electrode due to the interface oxide formed in the silicon of the active area can be prevented.

[0189] In various embodiments, silicon oxidation or silicon loss in the lower cell active region ACT shielded by the first barrier layer 111A can be effectively suppressed. Since silicon loss or oxidation in the cell active region ACT can be effectively suppressed, reduction in channel width can be suppressed and reduction in channel resistance can be caused.

[0190] In various embodiments, a conductive material may be deposited on the pre-insulating layer 111PB, wherein the conductive material may fill the first trench 115. The deposition of the conductive material may be performed using a chemical vapor deposition (CVD) process, etc. The conductive material may include at least one of Mo, W, TiN, and / or Ru.

[0191] Therefore, it is possible to form Figure 8The cell gate electrode layer 112 is shown. Thereafter, a cell gate structure 110 may be formed by a planarization process on the gate electrode layer 112. The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating layer 111, a cell gate electrode layer 112, a cell gate capping conductive layer 113, and a cell gate capping layer 114. The cell gate electrode layer 112 may correspond to a word line WL.

[0192] Subsequently, a bit line structure 140ST extending in the second direction DR2 may be formed on the substrate 100 . The bit line structure 140ST may include a cell conductive line 140 , a cell line capping layer 144 , and a bit line spacer 150 .

[0193] In various embodiments, the storage contact 120 , the storage pad 160 , and the information storage unit 190 may be formed on the second portion 103 b of the cell active area ACT. The information storage unit 190 may include a lower electrode 191 , a capacitor dielectric layer 192 , and an upper electrode 193 .

[0194] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present disclosure. Therefore, the preferred embodiments of the present invention disclosed are used in a general and descriptive sense only, and not for the purpose of limitation.

[0195] This application claims priority and all rights arising from Korean Patent Application No. 10-2023-0075427 filed in the Korean Intellectual Property Office on June 13, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, include: A substrate including an element isolation layer defining a plurality of active regions; as well as a plurality of gate structures intersecting the plurality of active regions, Each of the plurality of gate structures comprises: a gate insulating layer on the active region, the gate insulating layer comprising a first region including a first material and a second region including a second material different from the first material; as well as a gate electrode layer, on the gate insulating layer, wherein the concentration of the second material in the first region is less than the concentration of the second material in the second region, A thickness of the gate insulating layer in the first region is smaller than a thickness of the gate insulating layer in the second region. 2 . The semiconductor device according to claim 1 , wherein a concentration of the first material in the first region is greater than a concentration of the first material in the second region. 3 . The semiconductor device according to claim 1 , wherein a concentration of the second material in the gate insulating layer is greater in a region adjacent to the gate electrode layer than in a region adjacent to the active region. 4 . The semiconductor device according to claim 1 , wherein a concentration of the first material in the gate insulating layer is smaller in a region adjacent to the gate electrode layer than in a region adjacent to the active region.

5. The semiconductor device according to claim 1, wherein the first material comprises at least one of silicon, carbon and nitrogen, and The second material includes oxygen. 6 . The semiconductor device according to claim 1 , wherein each of the gate structures further comprises a capping layer on a top surface of the gate electrode layer and a sidewall of the second region. 7 . The semiconductor device according to claim 6 , wherein a bottom surface of the cover layer is not in contact with a top surface of the first region and a top surface of the second region. 8 . The semiconductor device of claim 1 , further comprising a nanosheet surrounded by each of the gate structures.

9. A semiconductor device, include: a substrate including an element isolation layer defining a cell region and a peripheral region around the cell region and defining a first active region in the cell region; as well as a cell gate structure in the cell region, the cell gate structure being formed in a first trench on the substrate and intersecting the first active region, Each of the cell gate structures comprises: a first barrier layer comprising a first region comprising a first material and a second region comprising a second material, wherein the first barrier layer is in the first trench and extends along sidewalls and a bottom surface of the first trench; a first insulating layer comprising the second material on the sidewalls of the first barrier layer and extending along the sidewalls and the bottom surface of the first trench; a cell gate electrode layer, on a side wall of the first insulating layer, the cell gate electrode layer filling the first trench; and A capping layer is on a top surface of the cell gate electrode layer and a sidewall of the first insulating layer, wherein a concentration of the second material in the first barrier layer is less than a concentration of the second material in the first insulating layer. 10 . The semiconductor device according to claim 9 , wherein a thickness of the first barrier layer is smaller than a thickness of the first insulating layer with respect to a sidewall of the first trench. 11 . The semiconductor device according to claim 9 , wherein a concentration of the second material in the first barrier layer decreases as it is closer to the first active region, and increases as it is closer to the cell gate electrode layer. 12 . The semiconductor device according to claim 9 , wherein the first insulating layer does not include the first material.

13. The semiconductor device according to claim 9, wherein the first material comprises at least one of silicon, carbon and nitrogen, and The second material includes oxygen.

14. The semiconductor device according to claim 9, further comprising a plurality of peripheral gate structures in the peripheral region, the plurality of peripheral gate structures being formed on the substrate and intersecting the second active region, Each of the peripheral gate structures include: a second barrier layer on the second active region, the second barrier layer comprising a third region comprising the first material and a fourth region comprising the second material; a second insulating layer comprising the second material on the second barrier layer, and The peripheral gate electrode layer is arranged on the second insulating layer. 15 . The semiconductor device of claim 14 , wherein a concentration of the second material in the second barrier layer is lower than a concentration of the second material in the second insulating layer. 16 . The semiconductor device according to claim 14 , wherein a thickness of the second barrier layer is smaller than a thickness of the second insulating layer.

17. The semiconductor device according to claim 9, further comprising: include: a first source / drain region and a second source / drain region in the first active region; a bit line structure on the substrate and connected to the first source / drain region; as well as An information storage unit is on the substrate and connected to the second source / drain region.

18. A method for manufacturing a semiconductor device, include: forming an element isolation layer defining a plurality of active regions on a substrate; forming a first trench in the substrate that intersects at least a portion of the plurality of active regions; forming a barrier layer including a first material along sidewalls and a bottom surface of the first trench; forming an insulating layer on a sidewall of the barrier layer, the insulating layer comprising a second material different from the first material; as well as forming a gate electrode layer on the sidewall of the insulating layer and filling the interior of the first trench, Wherein relative to the sidewall of the first trench, the thickness of the barrier layer is less than or equal to half of the thickness of the insulating layer.

19. The method of claim 18, wherein a concentration of the first material in the barrier layer is greater in a region adjacent to the active region than in a region adjacent to the gate electrode layer, and A concentration of the second material in the barrier layer is greater in a region adjacent to the gate electrode layer than in a region adjacent to the active region.

20. The method of claim 18, wherein the barrier layer comprises at least one of silicon, silicon carbide, silicon nitride, silicon carbonitride, or silicon oxynitride, The insulating layer includes silicon oxide.

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