NORD flash memory, layout and writing method and reading method thereof

Abstract

The invention provides a NORD flash memory, a layout and a writing method and a reading method thereof, a common source line is arranged between adjacent word lines in the layout of the NORD flash memory, a first control gate and a second control gate which are parallel to each other are arranged on two sides of each word line, and only one of two bit cells sharing the word line is used, so that the layout of the NORD flash memory is changed, and the layout of the NORD flash memory is changed into the layout of the NORD flash memory. Although only half of the bit units are utilized, the area of the active region can be reduced by half by applying voltage between the source line and the bit line, so that the area of the device is basically unchanged; due to the fact that the pressurization mode of writing, erasing and reading data of the NORD flash memory is changed and only one of the two bit units sharing the word line is used, writing interference and reading interference of the NORD flash memory are improved, and the reliability of the NORD flash memory is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a NORD flash memory, a layout, and a writing method and a reading method thereof. Background Art

[0002] When a NORD flash memory device writes (program) or reads (read) a certain bit unit (bit), crosstalk will occur to other bit units (bits). In serious cases, the data in other bits will change, causing failure.

[0003] Figure 1 FIG. 1 is a schematic diagram of the structure of a NORD flash memory in the prior art. Figure 1 As shown, the NORD flash memory layout includes a plurality of word lines and a plurality of bit lines perpendicular to each other, such as word line WL0, word line WL1, word line WL2 and word line WL3, bit line BL0, bit line BL1, bit line BL2, bit line BL3, bit line BL4 and bit line BL5. Two control gates are respectively arranged on both sides of each word line WL, for example, control gate CG0 and control gate CG1 are respectively arranged on both sides of word line WL0, and floating gates are respectively formed under control gate CG0 and control gate CG1, and control gate CG0 is used to store a data unit, and control gate CG1 is also used to store a data unit. Control gate CG2 and control gate CG3 are respectively arranged on both sides of word line WL1, and floating gates are respectively formed under control gate CG2 and control gate CG3, and control gate CG2 is used to store a data unit, and control gate CG3 is also used to store a data unit. In the direction of bit line extension, in order to connect control gate CG0 and control gate CG1, contact plugs need to be set separately, that is, control gate CG0 and control gate CG1 are staggered in the direction of bit line extension, and a spacing area is set between the two contact plugs. Therefore, every two bit lines are located in the same active area. The width of the active area is equal to three times the width of the contact plug after the width of the two bit lines and the width of the spacing area. Since the word line WL and control gate CG voltages of the bit cells (bit) in the same row of the NORD flash memory layout are shared, and the bit line BL voltages of the bit cells in the same column are shared. When operating a certain bit cell, it will inevitably affect other bit cells in the same row or column. How to reduce the interference between bit cells is a current difficulty. Summary of the invention

[0004] The object of the present invention is to provide a NORD flash memory, a layout and a writing method and a reading method thereof, so as to solve the problem that when operating a certain bit unit, other bit units in the same row or column will inevitably be interfered.

[0005] In order to solve the above technical problems, the present invention provides a NORD flash memory layout, including multiple word lines extending along a first direction and multiple bit lines extending along a second direction, the first direction and the second direction are perpendicular, a common source line is arranged between adjacent word lines, and parallel first control gates and second control gates are arranged on both sides of each word line, and bit units are arranged under the first control gate and the second control gate, the bit units under the two control gates close to the source line are used to store data, and the bit units under the two control gates far from the source line are shielded.

[0006] Based on the same inventive concept, the present invention also provides a NORD flash memory, which is manufactured using the above-mentioned NORD flash memory layout, including multiple word lines extending along a first direction and bit lines extending along a second direction, a common source line is arranged between adjacent word lines, and parallel first and second control gates are arranged on both sides of each word line, and bit units are arranged under the first and second control gates, the bit units under the two control gates close to the source line are used to store data units, and the bit units under the two control gates far from the source line are shielded.

[0007] Optionally, two control gates away from the source line are in a normally open state to shield the bit cells under the two control gates away from the source line.

[0008] Optionally, the first direction is rows, and the second direction is columns.

[0009] Optionally, the bit line voltages of the bit cells in the same column are shared, and the word lines and control gate voltages of the bit cells sharing a common source line are shared.

[0010] Optionally, the voltage application method of the NORD flash memory layout structure is to apply a voltage between the bit line and the source line, and to apply a voltage to the word line and the control gate at the same time.

[0011] Based on the same inventive concept, the present invention also provides a method for reading a NORD flash memory, using any of the above-mentioned NORD flash memory, comprising:

[0012] A voltage is applied to any one of the control gates near both sides of the source line to read data, and the bit cells under the control gates away from both sides of the source line are shielded.

[0013] Based on the same inventive concept, the present invention also provides a method for writing a NORD flash memory, using any of the above-mentioned NORD flash memory, comprising:

[0014] When a voltage is applied to one of the control gates near the two sides of the source line to write data, the time for which the bit cell under the other control gate near the two sides of the source line is disturbed is in the order of seconds.

[0015] Optionally, a voltage is applied to one of the control gates near both sides of the source line to write data, and the time for which the bits located on the same control gate and on the adjacent bit lines are disturbed is in the order of milliseconds.

[0016] Optionally, a voltage is applied to one of the control gates close to both sides of the source line to write data, and the bit cells located on the same bit line and not on the same source line are not disturbed.

[0017] In the NORD flash memory layout provided by the present invention, the NORD flash memory layout includes a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction, the first direction and the second direction are perpendicular, a common source line is arranged between adjacent word lines, and a first control gate and a second control gate are arranged on both sides of each word line in parallel, and a bit unit is arranged under each of the first control gate and the second control gate, and the bit units under the two control gates close to the source line are used to store data, and the bit units under the two control gates far from the source line are shielded and not used to store data. The present invention uses only one of the two bit units of the common word line, although only half of the bit units are used, but the voltage applied between the source line and the bit line can reduce the active area by half, so the device area remains basically unchanged; due to the change of the pressurization method of writing, erasing and reading data of the NORD flash memory and the use of only one of the two bit units of the common word line, the write interference and read interference of the NORD flash memory are improved, so that the reliability of the NORD flash memory is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0019] Figure 1 It is a schematic diagram of the layout of the NORD flash memory in the prior art.

[0020] Figure 2 is a diagram of a NORD flash memory layout according to an embodiment of the present invention.

[0021] Figure 3 4 is a circuit diagram of a NORD flash memory layout according to an embodiment of the present invention.

[0022] Figure 4 It is a schematic diagram of the layout of the NORD flash memory layout when reading data according to an embodiment of the present invention.

[0023] Figure 5 It is a schematic diagram of the layout of the NORD flash memory layout when writing data according to an embodiment of the present invention.

[0024] Figure 6 It is a schematic diagram of the layout of the NORD flash memory layout when erasing data according to an embodiment of the present invention.

[0025] In the attached figure:

[0026] 10-active region; 11-word line; 11a-first word line; 11b-second word line; 12a-first control gate; 12b-second control gate; 12c-third control gate; 12d-fourth control gate; 13-bit line; 14-source line; 15-bit unit. DETAILED DESCRIPTION

[0027] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0028] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0029] Figure 2 is a diagram of a NORD flash memory layout according to an embodiment of the present invention. Figure 34 is a circuit diagram of a NORD flash memory layout according to an embodiment of the present invention. Figure 4 It is a schematic diagram of the layout of the NORD flash memory layout when reading data according to an embodiment of the present invention. Figure 5 It is a schematic diagram of the layout of the NORD flash memory layout when writing data according to an embodiment of the present invention. Figure 6 FIG. 1 is a schematic diagram of a NORD flash memory layout when erasing data according to an embodiment of the present invention. Figure 2 and Figure 4 As shown, this embodiment provides a NORD flash memory layout, including a plurality of word lines 11 extending along a first direction and a plurality of bit lines 13 extending along a second direction, the bit lines 13 are located on active areas 10, there is only one bit line 13 on each active area 10, and the word lines 11 span multiple active areas 10. The first direction is perpendicular to the second direction. The first direction is a row, and the second direction is a column. A common source line 14 is arranged between adjacent word lines 11, for example, word lines 11a and word lines 11b share a common source line 14. Parallel first control gates and second control gates are arranged on both sides of each word line 11, for example, parallel first control gates 12a (CG1) and second control gates 12b (CG2) are arranged on both sides of the first word line 11a (WL1), and parallel third control gates 12c (CG3) and fourth control gates 12d (CG4) are arranged on both sides of the second word line 11b (WL2). Bit cells 15 are arranged under the first control gate 12a, the second control gate 12b, the third control gate 12c and the fourth control gate 12d. The bit cells 15 under the two control gates close to the source line 14 are used to store data, and the bit cells 15 under the two control gates far from the source line 14 are shielded and not used to store data. For example, the bit cells 15 under the second control gate 12b and the third control gate 12c are used to store data, and the bit cells 15 under the first control gate 12a and the fourth control gate 12d are shielded and not used to store data.

[0030] This embodiment also provides a NORD flash memory, which is manufactured using the above-mentioned NORD flash memory layout, and includes a plurality of word lines 11 extending along a first direction and a plurality of bit lines 13 extending along a second direction, wherein the bit lines 13 are located on active areas 10, and there is only one bit line 13 on each active area 10, and the word lines 11 span across multiple active areas 10. The first direction is perpendicular to the second direction, and a common source line 14 is arranged between adjacent word lines 11, and parallel first and second control gates are arranged on both sides of each word line 11, and bit units are arranged under the first and second control gates, and the bit units 15 under the two control gates close to the source line 14 are used to store data units, and the bit units 15 under the two control gates far from the source line 14 are shielded and not used to store data.

[0031] like Figure 2 and Figure 3 As shown, the two control gates away from the source line 14 are in a normally open state to shield the bit cells 15 under the two control gates away from the source line 14 from storing data.

[0032] like Figures 4 to 6 As shown, the bit line 13 voltage of the bit cells 15 in the same column is shared, and the word line and the control gate voltage of the bit cells 15 sharing the same source line 14 are shared. For example, the first word line 11a and the second word line 11b of the common source line 14, the first control gate 12a and the second control gate 12b arranged in parallel on both sides of the first word line 11a, and the third control gate 12c and the fourth control gate 12d arranged in parallel on both sides of the second word line 11b share the voltage, wherein the word lines and control gates located above the source line SL are marked starting with T (top), the word lines and control gates located below the source line SL are marked starting with B (bottom), the control gates close to the source line SL are marked ending with S, and the control gates far from the source line SL are marked ending with B, therefore, the first control gate 12a is marked as TCG1_B, the first word line 11a is marked as TWL1, the second control gate 12b is marked as TCG1_S, the second word line 11b is marked as BWL1, the third control gate 12c is marked as BCG1_S, and the fourth control gate 12d is marked as BCG1_B. Therefore, the voltage application method of the NORD flash memory structure is to apply a voltage between the bit line 13 and the source line 14, and to apply a voltage to the word line 11 and the control gate at the same time. By applying a voltage between the bit line 13 and the source line 14, the bit cells that do not share the source line 14 do not interfere with each other, thereby improving the write interference and read interference of the NORD flash memory, and greatly improving the reliability of the NORD flash memory.

[0033] like Figure 4As shown, this embodiment also provides a method for reading a NORD flash memory, using the above-mentioned NORD flash memory, including: applying a voltage to any one of the control gates near the two sides of the source line 14 to read data, and shielding the bit cells under the control gates far away from the two sides of the source line 14, and the bit cells under the control gates far away from the two sides of the source line 14 are not used to store data and do not generate interference. Specifically, a 0V voltage is applied to the source line 14, a 0.6V voltage is applied to the bit line 13, and a 3-5V voltage is applied to the second word line 11b, a 0V voltage is applied to the third control gate 12c, and a 0-5V voltage is applied to the fourth control gate 12d. Since the fourth control gate 12d in this embodiment is in a normally open state, the bit cell C under the fourth control gate 12d is not used to store data. Therefore, even if a 0-5V voltage is applied to the fourth control gate 12d, the bit cell C under the fourth control gate 12d will not generate interference to the bit cell A under the third control gate 12c. Similarly, the bit cell D under the first control gate 12a will not interfere with the bit cell A under the third control gate 12c. Therefore, in the bit cells with a common source line and a common bit line in the NORD flash memory provided in this embodiment, when reading data, the bit cells far away from the common source line do not interfere with the bit cells with a common source line and a common bit line because the bit cells far away from the common source line are not used to store data.

[0034] like Figure 5 As shown, this embodiment also provides a method for writing a NORD flash memory layout, using the above-mentioned NORD flash memory, including: applying a voltage to one of the control gates near the two sides of the source line 14 to write data, and the time for the bit cell under the other control gate near the two sides of the source line 14 to be disturbed is in the order of seconds. Specifically, a 4.2V voltage is applied to the source line 14, a reference voltage (Vdp) is applied to the bit line 13, and a 1.5V voltage is applied to the second word line 11b, a 9V voltage is applied to the third control gate 12c, and a 5V voltage is applied to the fourth control gate 12d. Since the first control gate 12a and the fourth control gate 12d in this embodiment are in a normally open state, the bit cell D under the first control gate 12a and the bit cell C under the fourth control gate 12d are not used to store data. Therefore, even if a 5V voltage is applied to the fourth control gate 12d, the bit cell A under the third control gate 12c will not be disturbed by the bit cell C under the fourth control gate 12d. Similarly, the bit cell D under the first control gate 12a will not interfere with the bit cell A under the third control gate 12c. When reading the bit cell A under the third control gate 12c, among the bit cells on the same bit line 13, only the bit cell B under the second control gate 12b is interfered, and the interference time is in the order of seconds.

[0035] Please continue to refer to Figure 5, a voltage is applied to one of the control gates near the two sides of the source line to write data, and the time for which the bit located on the same control gate and on the adjacent bit line is disturbed is in the order of milliseconds. Specifically, a 4.2V voltage is applied to the source line 14, a reference voltage (Vdp) is applied to the bit line 13, a 1.5V voltage is applied to the second word line 11b, a 9V voltage is applied to the third control gate 12c, and a 5V voltage is applied to the fourth control gate 12d. Since the bit unit F and the bit unit A located on the same control gate and on the adjacent bit line in this embodiment share the source line but not the bit line, the voltage applied to the bit line where the bit unit F is located is 1.2V. Therefore, when writing data to the bit unit A, the bit unit F is disturbed, but the time for which the disturbance is in the order of milliseconds (msec).

[0036] Please continue to refer to Figure 5 , a voltage is applied to one of the control gates near the two sides of the source line 14 to write data, and the bit cells located on the same bit line 13 and on a non-common source line are not disturbed. Specifically, a 4.2V voltage is applied to the source line 14, a reference voltage (Vdp) is applied to the bit line 13, and a 1.5V voltage is applied to the second word line 11b, a 9V voltage is applied to the third control gate 12c, and a 5V voltage is applied to the fourth control gate 12d. Since the bit cell E and the bit cell A located on the same bit line 13 and on a non-common source line in this embodiment share a bit line but do not share a source line, the voltage applied to the source line where the bit cell E is located is 0V. Therefore, when writing data to the bit cell A, the bit cell E is not disturbed. Therefore, in the NORD flash memory provided in this embodiment, when writing data, the bit cells that share a source line and a bit line are disturbed in the order of seconds, the bit cells that share a source line but not a bit line are disturbed in the order of milliseconds, and the bit cells that share a bit line but not a source line are not disturbed.

[0037] like Figure 6 As shown, this embodiment also provides a method for erasing a NORD flash memory layout, using the above-mentioned NORD flash memory, including: applying a 0V voltage to the bit line 13 and the source line 14, applying an 8.5V voltage to the first word line 11a and the second word line 11b respectively, and applying a -7V voltage to the first control gate 12a, the second control gate 12b, the third control gate 12c and the fourth control gate 12d respectively, to erase data.

[0038] In the NORD flash memory provided in this embodiment, a voltage is applied between the source line and the bit line, which changes the pressurization method of writing data, reading data and erasing data, improves the write interference and read interference of the NORD flash memory, and greatly improves the reliability of the NORD flash memory.

[0039] From the above, it can be seen that in the NORD flash memory, layout and writing method and reading method provided by the embodiment of the present invention, the NORD flash memory layout includes a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction, the first direction and the second direction are perpendicular, a common source line is arranged between adjacent word lines, and a parallel first control gate and a second control gate are arranged on both sides of each word line, and a bit unit is arranged under the first control gate and the second control gate, and the bit unit under the two control gates close to the source line is used to store data, and the bit unit under the two control gates far from the source line is shielded and not used to store data. The present invention uses only one of the two bit units of the common word line, although only half of the bit units are used, but the voltage applied between the source line and the bit line can reduce the active area by half, so the device area remains basically unchanged; because the pressurization method of writing, erasing and reading data of the NORD flash memory is changed and only one of the two bit units of the common word line is used, the write interference and read interference of the NORD flash memory are improved, so that the reliability of the NORD flash memory is greatly improved.

[0040] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A NORD flash memory layout, characterized in that: The invention comprises a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction, wherein the first direction is perpendicular to the second direction, a common source line is arranged between adjacent word lines, a first control gate and a second control gate are arranged on both sides of each word line in parallel, bit units are arranged under the first control gate and the second control gate, the bit units under the two control gates close to the source line are used for storing data, and the bit units under the two control gates far from the source line are shielded.

2. A NORD flash memory, characterized in that: The NORD flash memory device is manufactured using the NORD flash memory layout of claim 1, comprising a plurality of word lines extending in a first direction and bit lines extending in a second direction, a common source line being arranged between adjacent word lines, parallel first control gates and second control gates being arranged on both sides of each word line, bit cells being arranged under the first control gates and the second control gates, the bit cells under the two control gates close to the source lines being used to store data cells, and the bit cells under the two control gates far from the source lines being shielded.

3. The NORD flash memory according to claim 2, characterized in that: The two control gates away from the source line are in a normally open state to shield the bit cells under the two control gates away from the source line.

4. The NORD flash memory according to claim 2, characterized in that: The first direction is rows, and the second direction is columns.

5. The NORD flash memory according to claim 4, characterized in that: The bit line voltage of the bit cells in the same column is shared, and the word line and the control gate voltage of the bit cells sharing a common source line are shared.

6. The NORD flash memory according to claim 2, characterized in that: The voltage application method of the NORD flash memory layout structure is to apply a voltage between the bit line and the source line, and to apply a voltage to the word line and the control gate at the same time.

7. A method for reading a NORD flash memory, characterized in that: The NORD flash memory device according to any one of claims 2 to 6 comprises: A voltage is applied to any one of the control gates near both sides of the source line to read data, and the bit cells under the control gates away from both sides of the source line are shielded.

8. A method for writing a NORD flash memory, characterized in that: The NORD flash memory device according to any one of claims 2 to 6 comprises: When a voltage is applied to one of the control gates near the two sides of the source line to write data, the time for which the bit cell under the other control gate near the two sides of the source line is disturbed is in the order of seconds.

9. The method for writing a NORD flash memory according to claim 8, characterized in that: When a voltage is applied to one of the control gates near both sides of the source line to write data, the time for which the bits located on the same control gate and on the adjacent bit lines are disturbed is in the order of milliseconds.

10. The method for writing to a NORD flash memory according to claim 8, characterized in that: A voltage is applied to one of the control gates near both sides of the source line to write data, and the bit cells located on the same bit line but not on the same source line are not disturbed.

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