Semiconductor memory device and method of manufacturing the same

Abstract

The invention relates to a semiconductor memory device and a method of manufacturing the same. A semiconductor memory device may include first gate structures each including alternately stacked first real gate lines and first insulating layers. The device may also include first dummy gate lines on the first gate structures, a separation insulating structure configured to extend between the first dummy gate lines and between the first gate structures, and a second gate structure on the first gate structures and the separation insulating structure, and a second dummy gate line having a width greater than that of each of the first dummy gate lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0075442, filed on Jun. 13, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments relate to electronic devices and methods of manufacturing electronic devices. More particularly, the disclosed embodiments relate to semiconductor memory devices and methods of manufacturing semiconductor memory devices. Background Art

[0004] The integration degree of semiconductor memory devices is generally determined by the area occupied by a unit memory cell. As the integration degree of semiconductor memory devices increases, the area occupied by a memory cell formed as a single layer on a substrate may have recently reached its limit, and three-dimensional semiconductor memory devices in which memory cells are stacked on top of each other on a substrate have appeared. Various structures and manufacturing methods have been developed to improve the operation and reliability of such semiconductor memory devices. Summary of the invention

[0005] In one embodiment, a semiconductor memory device may include first gate structures, each of which includes first real gate lines and first insulating layers that are alternately stacked. Each gate structure also includes first dummy gate lines located on the first gate structure, a separation insulating structure configured to extend between the first dummy gate lines and between the first gate structures, and a second gate structure located on both the first gate structure and the separation insulating structure and including a second dummy gate line having a greater width than each of the first dummy gate lines.

[0006] In one embodiment, a method for manufacturing a semiconductor memory device may include: forming a first stack including alternating stacks of first material layers and second material layers, forming a first sacrificial layer on the first stack, forming a second sacrificial layer on the first sacrificial layer, forming an opening extending through the second sacrificial layer and the first sacrificial layer into the first stack, forming a preliminary insulating structure within the opening, forming a separation insulating structure within the opening by etching the preliminary insulating structure and the second sacrificial layer so that the first sacrificial layer is exposed, and forming a second stack including alternating stacks of third material layers and fourth material layers on the separation insulating structure and the first sacrificial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a vertical cross-sectional view for describing a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view for describing a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 3A and Figure 3B is a vertical cross-sectional view for describing a semiconductor memory device according to an embodiment of the present disclosure.

[0010] FIG. 4A to FIG. 4E is a vertical cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to one embodiment of the present disclosure.

[0011] Figure 5A and Figure 5B is a vertical cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

[0013] Embodiments of the present disclosure provide a semiconductor memory device having a stable structure and improved characteristics, and a method of manufacturing a semiconductor memory device having a stable structure and improved characteristics.

[0014] Figure 1 is a diagram depicting a vertical cross-section of a semiconductor memory device 10 according to one embodiment of the present disclosure and showing various layers (also referred to as strata) of different types of materials, stacked on top of each other to embody the semiconductor memory device. A layer or stratum of material is essentially a thin sheet of material, regardless of how it is formed. As used herein, the word "line" should be interpreted as referring to a layer.

[0015] refer to Figure 1 , the semiconductor memory device 10 may include a first gate structure 110 , a first dummy gate line 120 , and a separation insulating structure 130 . The device 10 may also include a first gate structure 110 , a first dummy gate line 120 , a separation insulating structure 130 , and a second gate structure 140 .

[0016] The first gate structures 110 may each include a first insulating layer 110A and a first real gate line 110B layer stacked on top of each other. Such alternately stacked layers 110B and 110A are considered to be "alternately stacked" and "staggered" in this article. Therefore, "alternately stacked" and "staggered" can be used interchangeably hereinafter.

[0017] The first insulating layers 110A may each have a first thickness T1. The first real gate lines (which may also be referred to as layers) 110B may each have a second thickness T2. The first thickness T1 may be substantially the same as or different from the second thickness T2. For example, the second thickness T2 may be greater than the first thickness T1.

[0018] The first insulating layer 110A may each include an insulating material, such as an oxide. The first real gate line (layer) 110B may each include a conductive material, such as tungsten, molybdenum or polysilicon. The first real gate line (layer) 110B may each be a selection line or a word line. For example, the first real gate line 110B may each be a selection line.

[0019] The first dummy gate lines 120 may be respectively located on the first gate structure 110. The first dummy gate lines 120 may each have a third thickness T3. The third thickness T3 may be substantially the same as or different from the second thickness T2. For example, the third thickness T3 may be substantially the same as the second thickness T2. The first dummy gate lines 120 may each include a conductive material such as tungsten, molybdenum, or polysilicon. The first dummy gate lines 120 may each be a dummy selection line or a dummy word line. For example, the first dummy gate lines 120 may each be a dummy word line.

[0020] The separation insulating structure 130 may be located between the first gate structures 110. For example, the separation insulating structure 130 may extend between the first dummy gate lines (layers) 120 and between the first gate structures 110.

[0021] The separation insulating structure 130 may be tapered so that a first portion P1 located near the bottom has a first width D1 that is smaller than a second width D2 of a second portion P2, and as shown, the second portion P2 is closer to the second gate structure 140 than the first portion P1. The tapered separation insulating structure 130 may be located between the first gate structures 110, and may insulate at least one gate line 110B among the first real gate lines 110B at corresponding levels between the first gate structures 110. The first real gate lines 110B insulated by the separation insulating structure 130 may each be used as a source selection line.

[0022] The second gate structure 140 may be located above the first gate structure 110, that is, on top of the first gate structure 110. For example, the second gate structure 140 may be located above the first gate structure 110 and above the isolation insulating structure 130. The second gate structure 140 may include a second dummy gate line 140B1, which may be electrically connected to the first dummy gate line 120. The second dummy gate line 140B1 may be a dummy word line or a dummy selection line.

[0023] As used herein, the phrase "real gate line" should be interpreted in view of the phrase "dummy gate line", which refers to a conductor (i.e., line) electrically connected to the gate of a transistor that does not actually store data. Therefore, the "real gate line" should be interpreted as referring to a gate line that is not a dummy gate line. In other words, the "real gate line" can be interpreted as a conductor (i.e., line) electrically connected to the gate of a transistor that stores data, i.e., an actual gate line.

[0024] The second gate structure 140 may include a second real gate line 140B2 stacked on the second dummy gate line 140B1, and a second insulating layer 140A alternately stacked on the second dummy gate line 140B1 together with the second real gate line 140B2. In this case, the second insulating layer 140A may each include an insulating material, such as an oxide. The second real gate line 140B2 may each include a conductive material, such as tungsten, molybdenum or polysilicon. The second dummy gate line 140B1 may be a dummy selection line or a dummy word line. For example, the second dummy gate line 140B1 may be a dummy word line. The second real gate line 140B2 may each be a selection line or a word line. For example, the second real gate line 140B2 may each be a word line. For reference, the dummy gate lines 120 and 140B1 may be real gate lines 110B and 140B2. For example, the first dummy gate line 120 may be used as the first real gate line 110B, and the second dummy gate line 140B1 may be used as the second real gate line 140B2.

[0025] The lowermost second insulating layer 140A1 among the second insulating layers 140A may include a sacrificial layer 140A11 and an insulating layer 140A12 located on the sacrificial layer 140A11. In this case, the sacrificial layer 140A11 may be a layer used as a polishing stop layer and retained in the process of forming the separation insulating structure 130. The insulating layer 140A12 may be a layer formed on the sacrificial layer 140A11 and the separation insulating structure 130. Therefore, the lowermost second insulating layer 140A1 including the sacrificial layer 140A11 and the insulating layer 140A12 may be formed. The sacrificial layer 140A11 and the insulating layer 140A12 may each be an oxide layer, which may be formed by the same process or a separate and different process. An interface not shown may exist between the sacrificial layer 140A11 and the insulating layer 140A12. However, if the sacrificial layer 140A11 and the insulating layer 140A12 include the same material, there may be no interface.

[0026] The sacrificial layer 140A11 may be an oxide layer formed by a separate process before forming the separation insulating structure 130, and may be used as a polishing stop layer in the process of forming the separation insulating structure 130. If the sacrificial layer 140A11 is not formed separately, the sacrificial layer 140A11 may be formed at the same level as the first dummy gate line 120. Therefore, the nitride layer replaced with the first dummy gate line 120 in the subsequent process may be used as a polishing stop layer. In other words, the nitride layer may be formed to have a relatively large thickness from the beginning, and may be used as a polishing stop layer in the process of forming the separation insulating structure 130. In this case, the nitride layer may be etched to a certain thickness. Therefore, the third thickness T3 of each of the first dummy gate lines 120 and the second thickness T2 of each of the first real gate lines 110B may be different from each other.

[0027] In the process of forming the gate lines 120 and 110B, due to the difference between the thicknesses of the gate lines 120 and 110B formed of the conductive material, a seam may appear at the layer corresponding to the first dummy gate line 120. The fluorine series source gas may remain in the seam. Since smoke appears due to the fluorine series source gas, the surrounding layers may be damaged. However, in the present disclosure, the third thickness T3 and the second thickness T2 may be substantially the same, and since the sacrificial layer 140A11 is used as a polishing stop layer, the occurrence of seams or smoke can be reduced.

[0028] The lowermost second insulating layer 140A1 may contact (ie, mechanically contact or touch) the separation insulating structure 130. Figure 1 As shown, the top end of the separate insulating structure 130 may contact the lower surface of the insulating layer 140A12 and may extend through and physically contact the sacrificial layer 140A11. In other words, the separate insulating structure 130 may extend "upward" into the lowermost second insulating layer 140A1.

[0029] The upper surface of the separation insulating structure 130 may be located between the upper surface and the lower surface of the lowermost second insulating layer 140A1. The lowermost second insulating layer 140A1 may have a fourth thickness T4. The fourth thickness T4 may be substantially the same as or different from the first thickness T1 or the second thickness T2. For example, the fourth thickness T4 may be greater than the first thickness T1. The remaining second insulating layer 140A2 may have a thickness substantially the same as the first thickness T1.

[0030] In addition, since the sacrificial layer 140A11 is formed by a separate process, the fourth thickness T4 of the lowermost second insulating layer 140A1 and the first thickness T1 of each first insulating layer 110A and the thickness of each remaining second insulating layer 140A2 may be different from each other. However, since the sacrificial layer 140A11 is formed by a separate process, the thickness of the first dummy gate line 120 and the thickness of the first real gate line 110B may be substantially the same. In other words, since the sacrificial layer 140A11 (i.e., the oxide layer) is formed separately, the thickness of the nitride layer used to form the gate lines 120, 110B may be uniformly formed. In this case, the sacrificial layer 140A11, each first insulating layer 110A, and each second insulating layer 140A2 may include oxide.

[0031] According to the above description, the first real gate lines 110B at the same altitude level in the memory device 10 can be insulated from each other by the separation insulation structure 130. Similarly, the first dummy gate lines 120 at the same level can also be insulated from each other by the separation insulation structure 130. Therefore, each first real gate line 110B that has been insulated from each other or each first dummy gate line 120 that has been insulated from each other can be driven independently.

[0032] The gate lines located adjacent to the interface between the first gate structure 110 and the second gate structure 140 can be used as dummy gate lines 120 and 140B1. The remaining gate lines can be used as and considered as real gate lines 110B and 140B2. In addition, the dummy gate lines 120 and 140B1 can be electrically connected and can be driven by the same bias. Therefore, the risk of real gate lines 110B and 140B2 being bridged can be reduced.

[0033] In addition, in the process of forming the separation insulating structure 130, since the sacrificial layer 140A11 as an oxide layer can be used as a polishing stop layer, the thickness of the first dummy gate line 120 and the thickness of the first real gate line 110B can be substantially the same. Therefore, the occurrence of seams or smoke at substantially the same level as the first dummy gate line 120 can be reduced.

[0034] Figure 2 is another vertical cross-sectional view of a semiconductor memory device 20 according to another embodiment of the present disclosure. In the following, for the sake of brevity, descriptions of the contents are omitted.

[0035] refer to Figure 2The semiconductor memory device 20 may include a first gate structure 210, a first dummy gate line 220, a separation insulating structure 230, or a second gate structure 240, or the semiconductor memory device 20 may include a combination of the first gate structure 210, the first dummy gate line 220, the separation insulating structure 230, or the second gate structure 240. The semiconductor memory device 20 may further include a channel structure 250.

[0036] The first gate structures 210 may each have a first width W1. In this case, the first width W1 may be the width of the upper surface of each of the first gate structures 210, may be the width of the lower surface of each of the first gate structures 210, or may be the intermediate width between the upper surface and the lower surface of each of the first gate structures 210. The second gate structure 240 may have a second width W2 different from the first width W1. For example, the second width W2 may be greater than the first width W1. Therefore, the second gate structure 240 may have a greater width than each of the first gate structures 210 in the first gate structures 210.

[0037] The first dummy gate line 220 may be located on the first gate structure 210. The second gate structure 240 may be located on the first dummy gate line 220. The second gate structure 240 may include at least one second dummy gate line 240B1 and at least one second real gate line 240B2. The first dummy gate lines 220 may each have a width substantially the same as or different from that of the first gate structure 210. For example, the first dummy gate lines 220 may each have a first width W1. At least one second dummy gate line 240B1 may have a width substantially the same as or different from that of the second gate structure 240. For example, at least one second dummy gate line 240B1 may have a second width W2. Therefore, the second dummy gate line 240B1 may have a greater width than the first dummy gate line 220.

[0038] At least one second dummy gate line 240B1 may be positioned adjacent to the first dummy gate line 220. The first dummy gate line 220 and the at least one second dummy gate line 240B1 may be electrically connected. In this case, the first dummy gate line 220 and the at least one second dummy gate line 240B1 may be dummy selection lines or dummy word lines, and the at least one second real gate line 240B2 may be a selection line or a word line.

[0039] The channel structure 250 may be located within the first gate structure 210. For example, the channel structure 250 may extend through the first gate structure 210 and the second gate structure 240. The channel structure 250 may extend through the second gate structure 240, the first dummy gate line 220, and the first gate structure 210. The channel structures 250 may each include a channel layer 250A, a memory layer 250B surrounding the channel layer 250A, or an insulating core 250C within the channel layer 250A, or the channel structure 250 may include the channel layer 250A, the memory layer 250B, or the insulating core 250C combined. The separation insulating structure 230 may be located between the channel structures 250.

[0040] In one embodiment, the first dummy gate line 220 and the at least one second dummy gate line 240B1 may be vertically adjacent to each other. The first dummy gate line 220 and the at least one second dummy gate line 240B1 may also be electrically connected to each other. The first dummy gate line 220 and the at least one second dummy gate line 240B1 may be dummy selection lines or dummy word lines.

[0041] Figure 3A and Figure 3B 30 - 1 and 30 - 2 are vertical cross-sectional views of two slightly different semiconductor memory device embodiments identified by reference numerals 30 - 1 and 30 - 2 . In the following, descriptions of repeated elements are omitted for the sake of brevity.

[0042] refer to Figure 3A , the semiconductor memory device 30-1 may include a first gate structure 310, a first dummy gate line 320, a separation insulation structure 330, a second gate structure 340, and a tapered channel structure 350. The semiconductor memory device may further include a substrate 1, a source structure 300, an interconnection structure 3, an interlayer insulation layer IL, or a peripheral circuit PC, or the semiconductor memory device may further include a substrate 1, a source structure 300, an interconnection structure 3, an interlayer insulation layer IL, or a peripheral circuit PC in combination.

[0043] like Figure 3A As shown, the source structure 300 may be located below the first gate structure 310. The source structure 300 may also be connected to a tapered channel structure 350, which may extend through the first gate structure 310 into the source structure 300. A channel layer 350 portion of each of the tapered channel structures 350 may be connected to the source structure 300.

[0044] The peripheral circuit PC may be located in a substrate 1, which is located below and attached to the source structure 300. An isolation layer ISO may be located within the substrate 1. An active area may be defined by the isolation layer ISO. The peripheral circuit PC may include one or more transistors 2, one or more capacitors, and one or more registers. Figure 3A , the transistor 2 may include a first junction 2A, a second junction 2B, a gate insulating layer 2C, and a gate electrode 2D. The gate insulating layer 2C may be located between the gate electrode 2D and the substrate 1. The gate insulating layer 2C and the isolation layer ISO may each include an insulating material such as oxide or nitride.

[0045] The interconnection structure 3 may include a contact via 3A or a wiring 3B, or may include a contact via 3A or a wiring 3B combined. The interlayer insulating layer IL may be located on the substrate 1. The interconnection structure 3 may be located within the interlayer insulating layer IL. The interconnection structure 3 may be connected to the peripheral circuit PC. The contact via 3A may each connect each of the junctions 2A and 2B of the transistor 2 to the wiring 3B, or the wiring 3B may be connected to each other. The wiring 3B may each be connected to the contact via 3A, or the contact via 3A may each be connected to each other. The second contact via 3A or the second wiring 3B may each include a conductive material such as tungsten.

[0046] refer to Figure 3B , the semiconductor memory device 30-2 may include a first gate structure 310, a first dummy gate line 320, a separation insulation structure 330, a second gate structure 340, a channel structure 350, a substrate 1 or a peripheral circuit PC, or the semiconductor memory device 30-2 may include a first gate structure 310, a first dummy gate line 320, a separation insulation structure 330, a second gate structure 340, a channel structure 350, a substrate 1 or a peripheral circuit PC in combination. The semiconductor memory device may further include a first interconnect structure 360, a second interconnect structure 3, a first bonding pad 370, a second bonding pad 4, an interlayer insulating layer IL1 or an interlayer insulating layer IL2, or the semiconductor memory device may further include a first interconnect structure 360, a second interconnect structure 3, a first bonding pad 370, a second bonding pad 4, an interlayer insulating layer IL1 or an interlayer insulating layer IL2 in combination.

[0047] The first interconnect structure 360 ​​may be located below the first gate structure 310 and the second gate structure 340. The first interconnect structure 360 ​​may include a first contact via 360A and a first wiring 360B. The first contact vias 360A may be connected to the channel structure 350, respectively. The first wirings 360B may each be connected to the first contact vias 360A, and may each connect the first contact vias 360A to each other. The first contact vias 360A and the first wirings 360B may each include a conductive material, such as tungsten.

[0048] The first bonding pads 370 may be located under the first interconnection structure 360. The first bonding pads 370 may each be connected to at least one of the first contact vias 360A. The channel structure 350 and the peripheral circuit PC may be electrically connected through the first bonding pads 370 and the first interconnection structure 360.

[0049] The second bonding pads 4 may be located on the second interconnect structure 3. Each of the second bonding pads 4 may be connected to one or more corresponding second interconnect structures 3. For example, the second bonding pads 4 may be connected to at least one of the second "wirings" 3B, which are conductive paths or traces formed and embedded in the interlayer insulating layer IL1. Therefore, the peripheral circuit PC may be electrically connected to the channel structure 350 through one or more second interconnect structures 3 and one or more corresponding second bonding pads 4.

[0050] The corresponding first bonding pad 370 and second bonding pad 4 can of course be bonded to each other, that is, electrically connected to each other. Therefore, the first gate structure 310, the first dummy gate line 320, the separation insulation structure 330, the second gate structure 340, the channel structure 350, the first interconnect structure 360 ​​and the first bonding pad 370 can be included in the first wafer W1. The substrate 1, the peripheral circuit PC, the second interconnect structure 3 and the second bonding pad 4 can be included in the second wafer W2. Therefore, the semiconductor memory device 30-2 can have a structure in which the first wafer W1 and the second wafer W2 and their corresponding components are mechanically and electrically bonded to each other.

[0051] Before the first wafer and the second wafer are bonded to each other, as part of the process of manufacturing the semiconductor device, the substrate of the first wafer W1 may need to be removed. For the purpose of claim construction, the designation of structures as "on" (or above) and "under" (or below) is relative and is used herein only for ease of description. Therefore, the second wafer W2 can be located above the first wafer.

[0052] According to the above description, at least Figure 3A and Figure 3BThe semiconductor device depicted in the figure may therefore be or have a combined wafer structure. The channel structure 350 may belong to the first wafer W1 and be a part of the first wafer W1. The peripheral circuit PC may belong to the second wafer W2 and be a part of the second wafer W2. The substrate of the first wafer W1 may be removed during the manufacturing process of the semiconductor memory device 30-1 or 30-2. Therefore, by separately forming the first wafer W1 having the memory cell array and the second wafer W2 having the peripheral circuit PC, the degree of memory integration of the semiconductor memory devices 30-1 and 30-2 may be greatly improved. The separately formed wafers W1 and W2 may be combined with each other after they are formed.

[0053] FIG. 4A to FIG. 4E 1 is a vertical cross-sectional view illustrating steps of a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with the aforementioned contents are omitted.

[0054] refer to Figure 4A The first stack 410 may be formed by alternately stacking first material layers 410A and second material layers 410B (also referred to as forming staggered layers). Each first material layer 410A may be an insulating material, such as an oxide. Each second material layer 410B may be a sacrificial material, such as a nitride.

[0055] Each first material layer 410A may have a first thickness T1. Each second material layer 410B may have a second thickness T2. The first thickness T1 and the second thickness T2 may be substantially the same, or they may be different from each other. For example, the second thickness T2 may be greater than the first thickness T1.

[0056] After forming the first stack 410, a first sacrificial layer 420 may be formed on the first stack 410. The first sacrificial layer 420, which may have a third thickness T3, may be used as a polishing stop layer in a subsequent process. The third thickness T3 may be substantially the same as or different from the first thickness T1 and the second thickness T2. For example, the third thickness T3 may be less than the first thickness T1. The first sacrificial layer 420 may be a non-conductive material, such as an oxide.

[0057] Next, a second sacrificial layer 430 may be formed on the first sacrificial layer 420. The second sacrificial layer 430 may have a fourth thickness T4. The fourth thickness T4 may be substantially the same as or different from the first thickness T1, the second thickness T2, or the third thickness T3. For example, the fourth thickness T4 may be less than the second thickness T2. In a subsequent process, the second sacrificial layer 430 may be removed by being etched during the process of forming the separation insulating structure 440. The second sacrificial layer 430 may include a material having a high etching selectivity relative to the first sacrificial layer 420. For example, the second sacrificial layer 430 may include a sacrificial material such as nitride or polysilicon.

[0058] refer to Figure 4B , an opening OP may be formed in the first stack 410. For example, an opening OP extending into the first stack 410 may be formed through the second sacrificial layer 430 and the first sacrificial layer 420. The opening OP may include a first portion P1 having a first width D1 and a second portion P2 having a second width D2. The second width D2 may be substantially the same as or different from the first width D1. Figure 4B As shown, the second width D2 may be greater than the first width D1, in which case the vertical cross-sectional shape of the opening OP will be similar to a trapezoid because the shape of the opening OP is tapered.

[0059] Next, the corner CN of the second sacrificial layer 430, which is exposed during the formation of the opening OP, may be rounded. By rounding the edge of the top surface of the second sacrificial layer 430 exposed by forming the opening OP, the exposure or generation of a seam between the inner surface of the opening OP and the outer surface of a separation insulating structure (not shown) formed inside the opening OP in a subsequent process may be reduced or even prevented.

[0060] refer to Figure 4C , a preliminary insulating structure 440A may be formed within the opening OP, and the preliminary insulating structure 440A may be an insulating oxide. More specifically, the preliminary insulating structure 440A may be formed inside the opening OP so that a material including the insulating structure is in direct contact with the sidewall SW1 of the layer including the stack 410, the sidewall SW2 of the first sacrificial layer 420, and the sidewall SW3 of the second sacrificial layer 430, each of which is exposed by the formation of the opening OP. The preliminary insulating structure 440A may include an insulating material, such as an oxide.

[0061] refer to Figure 4D , a separation insulating structure 440 can be formed. For example, by etching or otherwise removing the top portion of the preliminary insulating structure 440A and the second sacrificial layer 430, so that the first sacrificial layer 420 is exposed, a separation insulating structure 440 can be formed in the opening OP. First, the second sacrificial layer 430 can also be etched while etching the preliminary insulating structure 440A. Next, the first sacrificial layer 420 can be etched to a certain thickness. In this case, the first sacrificial layer 420 can be used as a polishing stop layer. The level of the upper surface of the first sacrificial layer 420 and the level of the upper surface of the separation insulating structure 440 can be substantially the same. For reference, the thickness of the first sacrificial layer 420 etched to remove the seam formed in the preliminary insulating structure 440A can be adjusted.

[0062] The separation insulating structure 440 may be used to insulate one or more gate lines (not shown) formed substantially at the same level in a subsequent process from each other. For example, the separation insulating structure 440 may insulate gate lines (not shown) used as source selection lines and formed substantially at the same level from each other. Therefore, the gate lines (not shown) insulated from each other may be driven independently.

[0063] For reference, the second material layer 410B (i.e., the highest second material layer among all stacked second material layers 410B) may be formed to be relatively thick and may be used as a polishing stop layer in the process of forming the separation insulating structure 440. A sacrificial material that is the same as the sacrificial material of the second material layer 410B may be formed on the etched second material layer 410B (i.e., the highest portion) and the separation insulating structure 440. Therefore, the thickness of the second material layer 410B (i.e., the highest portion) may be greater than the thickness of the remaining second material layer 410B.

[0064] In the subsequent process, in the process of forming the conductive material in the opening from which the second material layer 410B has been removed, a seam may occur because only a portion of the conductive material is formed in the opening from which the relatively thick second material layer 410B (i.e., the highest portion) has been removed. Therefore, since smoke occurs at the level corresponding to the second material layer 410B (i.e., the highest portion), the surrounding layers may be damaged.

[0065] However, according to one embodiment of the present disclosure, the thickness of each second material layer 410B (i.e., the highest portion) can be formed to be substantially the same as the thickness of each remaining second material layer 410B by forming the first sacrificial layer 420 and the second sacrificial layer 430. Therefore, damage to the surrounding layers due to seams or smoke occurring at the level corresponding to the second material layer 410B as the highest portion can be reduced.

[0066] refer to Figure 4E , a second stack 450 including a second set of alternately stacked (interleaved) layers may be formed on the first stack 410. For example, the second stack 450 may be formed on the separation insulating structure 440 and the first sacrificial layer 420. The second stack 450 may include alternately stacked third material layers 450A and fourth material layers 450B. The third material layer 450A may include substantially the same material as the first material layer 410A. The fourth material layer 450B may include substantially the same material as the second material layer 410B. For example, the third material layers 450A may each include an insulating material, such as an oxide. The fourth material layers 450B may each include an insulating material, such as a nitride.

[0067] The lowermost third material layer 450A among the third material layers 450A may contact the separation insulating structure 440. For example, the lower surface of the lowermost third material layer 450A and the upper surface of the separation insulating structure 440 may contact each other. Because the third material layer 450A and the first sacrificial layer 420 are formed by separate processes, an interface may exist between the lowermost third material layer 450A and the first sacrificial layer 420. However, the present disclosure is not limited thereto. The lowermost third material layer 450A and the first sacrificial layer 420 may constitute a single layer.

[0068] The lowermost third material layer 450A may have a fifth thickness T5, and the remaining third material layers 450A may each have a sixth thickness T6. The fifth thickness T5 or the sixth thickness T6 may be substantially the same as or different from the first thickness T1 of the first material layer 410A. For example, the fifth thickness T5 may be less than the first thickness T1. The sum of the thickness of the retained first sacrificial layer 420 and the fifth thickness T5 may be greater than the first thickness T1 or the sixth thickness T6. The sixth thickness T6 may be substantially the same as the first thickness T1. The fourth material layers 450B may each have a seventh thickness T7. The seventh thickness T7 may be substantially the same as or different from the second thickness T2 of the second material layer 410B. For example, the seventh thickness T7 may be substantially the same as the second thickness T2.

[0069] For reference, if the third material layer 450A and the first sacrificial layer 420 are formed as a single layer by forming the third material layer 450A on the first sacrificial layer 420, the third material layer 450A may have a thickness different from that of the first insulating layer 410A or the second insulating layer 450A. However, the first sacrificial layer 420, the third material layer 450A, the first insulating layer 410A, and the second insulating layer 450A may each include an oxide. Despite the difference in thickness, bending of the oxide may occur relatively less.

[0070] According to the aforementioned manufacturing method, since the first sacrificial layer 420 (ie, the oxide layer) is used as a polishing stop layer, the thickness of the second material layer 410B can be uniformly formed. Therefore, damage to the surrounding layers due to the occurrence of seams or smoke at the level corresponding to the second material layer 410B (ie, the highest part) can be prevented.

[0071] In addition, the preliminary insulating structure 440A may be etched by using the first sacrificial layer 420 as a polish stop layer. Therefore, although a seam is formed in the preliminary insulating structure 440A, the seam may not exist in the separation insulating structure 440 by etching the first sacrificial layer 420 to a height at which the seam can be removed.

[0072] A single layer may be constructed by forming a third material layer 450A including oxide on the first sacrificial layer 420 (ie, oxide layer). The third material layer 450A may have a thickness different from that of each of the other material layers 410A and 450A. However, despite the thickness difference, bending of the oxide may occur relatively less.

[0073] As described above, due to the etching opening OP, the second sacrificial layer 430 (at Figure 4E The corners of the separation insulating structure 440 (not visible in FIG. 4 ) are rounded. Therefore, the formation of a seam in the preliminary insulating structure 440A during the formation of the preliminary insulating structure 440A can be prevented, minimized or reduced. Therefore, the occurrence of smoke in the semiconductor memory device due to the seam remaining in the separation insulating structure 440 can be prevented, minimized or reduced.

[0074] Figure 5A and Figure 5B is a vertical cross-sectional view illustrating steps of a method of manufacturing a semiconductor memory device according to one embodiment of the present disclosure. Hereinafter, descriptions of contents overlapping with the aforementioned contents are omitted.

[0075] refer to Figure 5A , a first stack 510 including a first material layer 510A and a second material layer 510B stacked alternately may be formed. Next, a first sacrificial layer 520 may be formed on the first stack 510. Next, a second sacrificial layer (not shown) may be formed on the first sacrificial layer 520. Next, after forming an opening (not shown) extending through the second sacrificial layer (not shown), the first sacrificial layer 520, and the first stack 510, a preliminary insulating structure (not shown) may be formed within the opening (not shown). Next, by etching the preliminary insulating structure (not shown) and the second sacrificial layer (not shown) so that the first sacrificial layer 520 is exposed, a separation insulating structure 540 may be formed within the opening (not shown). In this case, the first sacrificial layer 520 may be used as a polishing stop layer and may be etched to a certain thickness.

[0076] Next, the second stack 550 may be formed by alternately stacking third material layers 550A and fourth material layers 550B on the first sacrificial layer 520 and the separation insulating structure 540. In this case, the lowermost third material layer 550A among the third material layers 550A may contact the separation insulating structure 540.

[0077] Next, a channel structure 560 extending through the second stack 550, the first sacrificial layer 520, and the first stack 510 may be formed. The channel structures 560 may each include a channel layer 560A, a memory layer 560B surrounding the channel layer 560A, or an insulating core 560C within the channel layer 560A, or the channel structures 560 may each include the channel layer 560A, the memory layer 560B, or the insulating core 560C combined.

[0078] refer to Figure 5B , the second material layer 510B and the fourth material layer 550B may be replaced with gate lines 510C1, 510C2, 550C1, and 550C2. First, a slit (not shown) extending through the second stack 550, the first sacrificial layer 520, and the first stack 510 may be formed. Next, the gate lines 510C1, 510C2, 550C1, and 550C2 may be formed by forming a conductive material in an opening formed by removing the second material layer 510B and the fourth material layer 550B in the stacks 510 and 550 through the slit (not shown). For reference, if the second material layer 510B and the fourth material layer 550B each include a conductive material, the replacement process may be omitted. In such a case, the second material layer 510B and the fourth material layer 550B may be used as gate lines 510C1, 510C2, 550C1, and 550C2. For reference, a silicidation process for reducing the specific resistance of the second material layer 510B and the fourth material layer 550B may also be performed.

[0079] The gate lines 510C1, 510C2, 550C1, and 550C2 may respectively refer to the first real gate line 510C1, the first dummy gate line 510C2, the second dummy gate line 550C1, and the second real gate line 550C2. The first real gate line 510C1 or the second real gate line 550C2 may be a selection line or a word line. For example, the first real gate line 510C1 may be a selection line, and the second real gate line 550C2 may be a word line. The first dummy gate line 510C2 or the second dummy gate line 550C1 may be a dummy selection line or a dummy word line. For example, the first dummy gate line 510C2 and the second dummy gate line 550C1 may each be a dummy word line.

[0080] The first real gate lines 510C1 formed at substantially the same level may be insulated from each other by the separation insulation structure 540. In addition, the first dummy gate lines 510C2 formed at substantially the same level may be insulated from each other by the separation insulation structure 540. Therefore, the first real gate lines 510C1 insulated from each other or the first dummy gate lines 510C2 insulated from each other may be independently driven. The first dummy gate line 510C2 and the second dummy gate line 550C1 may be electrically connected.

[0081] For reference, if there is a difference between the thickness of each second material layer 510B and the thickness of each fourth material layer 550B in the process of forming the gate lines 510C1, 510C2, 550C1, and 550C2, a seam may appear at the level corresponding to the first dummy gate line 510C2. The fluorine series source gas may remain in the seam, and therefore, because smoke appears, the surrounding layers may be damaged. However, because the first sacrificial layer 520 is used as a polishing stop layer and the gate lines 510C1, 510C2, 550C1, and 550C2 can have a uniform thickness, the present disclosure can reduce the occurrence of gaps or smoke.

[0082] According to the foregoing description, the first real gate lines 510C1 and the first dummy gate lines 510C2 insulated from each other by the separation insulating structure 540 may be independently driven.

[0083] In addition, the first dummy gate line 510C2 and the second dummy gate line 550C1 may be electrically connected. The first dummy gate line 510C2 and the second dummy gate line 550C1 may be driven by using the same bias. Therefore, the risk of bridging between the first real gate line 510C1 and the second real gate line 550C2 may be reduced.

[0084] Although the embodiments according to the technical spirit of the present disclosure have been described above with reference to the accompanying drawings, the embodiments have been provided to describe only the embodiments according to the concepts of the present disclosure, and the present disclosure is not limited to the embodiments. A person with ordinary knowledge of the field to which the present disclosure relates may substitute, modify and change the embodiments in various ways without departing from the technical spirit of the present disclosure as written in the claims. Such substitutions, modifications and changes may be considered to belong to the scope of the present disclosure.

Claims

1. A semiconductor memory device, comprising: first gate structures, each comprising interlaced first real gate lines and a first insulating layer; first dummy gate lines respectively located on the first gate structures; a separate insulating structure formed within the first dummy gate lines and the first gate structures and configured to extend between the first dummy gate lines and between the first gate structures; as well as A second gate structure is located on the first gate structure and the separation insulating structure, the second gate structure includes a second dummy gate line having a greater width than each of the first dummy gate lines. 2 . The semiconductor memory device according to claim 1 , wherein the first dummy gate line and the second dummy gate line are electrically connected to each other.

3. The semiconductor memory device according to claim 1, wherein the second gate structure comprises: a second real gate line stacked on the second dummy gate line; as well as The second insulating layer and the second real gate lines are alternately stacked on the second dummy gate lines.

4. The semiconductor memory device according to claim 3, wherein: The first real gate line is a select line, and The second real gate line is a word line. 5 . The semiconductor memory device according to claim 3 , wherein the second gate structure has a width greater than a width of the first gate structure. 6 . The semiconductor memory device according to claim 3 , wherein the separate insulating structure extends into a lowermost second insulating layer among the second insulating layers. 7 . The semiconductor memory device according to claim 6 , wherein an upper surface of the separate insulating structure is located between an upper surface and a lower surface of the lowermost second insulating layer.

8. The semiconductor memory device according to claim 1, wherein the separation isolation structure comprises: a first portion having a first width, and A second portion has a second width, the second width being greater than the first width. 9 . The semiconductor memory device according to claim 8 , wherein the second portion is closer to the second gate structure than the first portion.

10. The semiconductor memory device according to claim 3, wherein: The first insulating layers each have a first thickness, and The first real gate lines each have a second thickness greater than the first thickness. 11 . The semiconductor memory device according to claim 10 , wherein the first dummy gate lines each have a third thickness substantially the same as the second thickness.

12. The semiconductor memory device according to claim 10, The lowermost second insulating layer among the second insulating layers has a fourth thickness greater than the first thickness.

13. The semiconductor memory device according to claim 3, wherein: The lowermost second insulating layer among the second insulating layers includes a sacrificial layer and an insulating layer located on the sacrificial layer, and The separate insulating structure passes through the sacrificial layer to contact a lower surface of the insulating layer. 14 . The semiconductor memory device of claim 1 , further comprising a channel structure extending through the second gate structure, the first dummy gate line, and the first gate structure.

15. The semiconductor memory device of claim 14, wherein the separate insulating structure is located between the channel structures.

16. A method of manufacturing a semiconductor device, comprising: forming a first stack including alternating stacks of first material layers and second material layers; forming a first sacrificial layer on top of the first stack; forming a second sacrificial layer on top of the first sacrificial layer; forming an opening extending through the second sacrificial layer, through the first sacrificial layer, and into the first stack; forming a preliminary insulating structure in the opening; By etching the preliminary insulating structure and the second sacrificial layer, the first sacrificial layer is exposed, and a separate insulating structure is formed in the opening; as well as A second stack including third material layers and fourth material layers alternately stacked is formed on the separate insulating structure and the first sacrificial layer. 17 . The method of claim 16 , further comprising etching corners of the second sacrificial layer, the corners formed and exposed by the forming of the opening. 18 . The method of claim 16 , wherein the forming of the separate insulating structure comprises etching the first sacrificial layer to a certain thickness. 19 . The method according to claim 16 , further comprising replacing the second material layer and the fourth material layer with a gate line. 20 . The method of claim 19 , wherein a lowermost third material layer among the third material layers contacts the first sacrificial layer and the separate insulating structure.

21. The method of claim 16, wherein the opening comprises: a first portion having a first width, and A second portion has a second width, the second width being greater than the first width.

22. The method of claim 16, wherein: The first material layers each have a first thickness, and The second material layers each have a second thickness greater than the first thickness. 23 . The method of claim 22 , wherein the first sacrificial layer has a third thickness that is less than the first thickness.

24. The method of claim 22, wherein the second sacrificial layer has a fourth thickness that is less than the second thickness. 25 . The method of claim 22 , wherein a lowermost third material layer among the third material layers has a fifth thickness that is smaller than the first thickness. 26 . The method of claim 25 , wherein remaining third material layers among the third material layers each have a sixth thickness substantially the same as the first thickness.

27. The method of claim 22, wherein the fourth material layers each have a seventh thickness that is substantially the same as the second thickness.

28. The method of claim 16, further comprising forming a channel structure extending through the second stack, the first sacrificial layer, and the first stack.

29. The method of claim 16, wherein the second sacrificial layer comprises a material having a high etch selectivity with respect to the first sacrificial layer.

30. The method of claim 29, wherein: The second sacrificial layer includes nitride, and The first sacrificial layer includes oxide.

31. The method of claim 16, wherein the first material layer, the separate insulating structure, or the third material layer each comprises an oxide. 32 . The method according to claim 16 , wherein the second material layer or the fourth material layer each comprises a nitride.

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