Semiconductor structure and preparation method thereof
The semiconductor structure with a shared drain region and inclined memristor arrangement in the 2T2R RRAM improves driving capability and enables miniaturization by allowing dual control of memristors, solving reset and size challenges.
Patent Information
- Application Number
- CN202411120345.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-15
- Publication Date
- 2024-12-13
AI Technical Summary
The existing 2T2R resistive random access memory (RRAM) structure faces challenges in resetting due to high reset operation voltage and difficulty in miniaturization, leading to insufficient transistor drive capability.
A semiconductor structure is designed with a shared drain region for two transistors and two memristors, allowing two word lines to control each memristor, and utilizing an inclined arrangement of resistive switching units to maintain the number of memristors while improving driving capability.
The structure enhances driving capability and enables miniaturization without sacrificing the number of memristors, addressing the reset difficulty and size limitations of the 2T2R structure.
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Figure CN119136562A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] Resistive Random Access Memory (RRAM) is a non-volatile memory that uses the variable resistance characteristics of materials to store information. It has the advantages of low power consumption, high density, fast read and write speed, and good durability.
[0003] However, in the existing 2T2R structure, one transistor controls one R, and there is difficulty in resetting. The required reset operation voltage is high, and it is difficult to miniaturize the size, which will face the problem of insufficient transistor drive. Summary of the invention
[0004] The present disclosure provides a semiconductor structure and a method for preparing the same, so as to at least solve the above technical problems existing in the prior art.
[0005] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:
[0006] A substrate, the substrate comprising a plurality of active regions arranged in an array along a first direction and a second direction;
[0007] A transistor unit is formed on each of the active regions, the transistor unit comprising a first transistor and a second transistor, the first transistor and the second transistor sharing a drain region;
[0008] A resistive switching unit is formed on each of the drain regions, and each of the resistive switching units includes a first memristor and a second memristor;
[0009] A plurality of word lines extending along the second direction, wherein in each of the transistor units, the first transistor is connected to one word line, and the second transistor is connected to another word line.
[0010] In one possible implementation manner, an extension direction of the resistive switching unit intersects with the first direction and forms a preset angle, and the preset angle ranges from 30° to 60°.
[0011] In one possible implementation, the first memristor and the second memristor both include a lower electrode, a resistive switching layer, and an upper electrode arranged from bottom to top, wherein the first memristor and the second memristor share a lower electrode.
[0012] In one embodiment, the semiconductor structure further includes:
[0013] A plurality of bit lines extending along the first direction, wherein in each row of resistive switching units on the active area arranged along the first direction, all the first memristors are connected to the same bit line, and all the second memristors are connected to another bit line.
[0014] In one embodiment, the semiconductor structure further includes:
[0015] A plurality of source lines extending along the first direction, wherein in each of the transistor units, the source region of the first transistor is connected to one source line, and the source region of the second transistor is connected to another source line; wherein, in two adjacent rows of transistor units on the active regions arranged along the first direction, the source regions of all the first transistors in one row and the source regions of all the second transistors in the other row are connected to the same source line.
[0016] According to a first aspect of the present disclosure, a method for preparing a semiconductor structure is provided, the method comprising:
[0017] Providing a substrate, the substrate comprising a plurality of active regions arranged in an array along a first direction and a second direction;
[0018] forming a transistor unit on each of the active regions, wherein the transistor unit comprises a first transistor and a second transistor, wherein the first transistor and the second transistor share a drain region;
[0019] forming a plurality of word lines extending along the second direction, wherein, in each of the transistor units, the first transistor is connected to one word line, and the second transistor is connected to another word line;
[0020] A resistive switching unit is formed on each of the drain regions, and each of the resistive switching units includes a first memristor and a second memristor.
[0021] In one possible implementation manner, an extension direction of the resistive switching unit intersects with the first direction and forms a preset angle, and the preset angle ranges from 30° to 60°.
[0022] In one possible implementation, the first memristor and the second memristor both include a lower electrode, a resistive switching layer, and an upper electrode arranged from bottom to top, wherein the first memristor and the second memristor share a lower electrode.
[0023] In one embodiment, the method further comprises:
[0024] After forming the resistive switching unit, a plurality of bit lines extending along the first direction are formed, wherein, in each row of resistive switching units on the active area arranged along the first direction, all the first memristors are connected to the same bit line, and all the second memristors are connected to another bit line.
[0025] In one embodiment, the method further comprises:
[0026] After forming the transistor unit, a plurality of source lines extending along the first direction are formed, wherein in each of the transistor units, the source region of the first transistor is connected to one source line, and the source region of the second transistor is connected to another source line; wherein, in two adjacent rows of transistor units on the active regions arranged along the first direction, the source regions of all the first transistors in one row and the source regions of all the second transistors in the other row are connected to the same source line.
[0027] The semiconductor structure and preparation method disclosed in the present invention share a drain region through two transistors, and then form two memristors (R) on the drain region, so two word lines can control any one of the memristors through two transistors. This will have one more R than the 2T1R structure. At the same time, any one of the memristors can be controlled by applying excitation through two source lines at the same time, and the driving capability is improved, solving the reset difficulty problem.
[0028] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:
[0030] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.
[0031] Figure 1 A top view of a semiconductor structure provided by an embodiment of the present disclosure;
[0032] Figure 2 For along Figure 1 A cross-sectional view along the dashed line A-A';
[0033] Figure 3 A schematic diagram of the structure of a storage unit provided in an embodiment of the present disclosure;
[0034] Figure 4A flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;
[0035] Figures 5a to 5i A schematic diagram of a semiconductor structure during the preparation process provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0036] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.
[0037] The present disclosure provides a semiconductor structure. Figure 1 A top view of a semiconductor structure provided by an embodiment of the present disclosure, Figure 2 For along Figure 1 Cross-sectional view along the dashed line AA'.
[0038] like Figure 1 to Figure 2 As shown, the semiconductor structure includes:
[0039] A substrate 10, the substrate 10 includes a plurality of active regions 11 arranged in an array along a first direction and a second direction;
[0040] A transistor unit is formed on each active area 11, and the transistor unit includes a first transistor 21 and a second transistor 22, and the first transistor 21 and the second transistor 22 share a drain area 211;
[0041] A resistive switching unit is formed on each drain region 211, and each resistive switching unit includes a first memristor 23 and a second memristor 24;
[0042] A plurality of word lines 70 extending along the second direction, wherein in each transistor unit, the first transistor 21 is connected to one word line 70 , and the second transistor 22 is connected to another word line 70 .
[0043] In one embodiment, the substrate 10 can be a single semiconductor material substrate (for example, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (for example, a germanium silicon substrate, etc.), or a silicon on insulator substrate (Silicon on Insulator, SOI), a germanium on insulator (Germanium on Insulator, GOI) substrate, etc.
[0044] The substrate 10 includes a plurality of active regions 11 arranged in an array along a first direction and a second direction, wherein adjacent active regions 11 are insulated and isolated by shallow trench isolation structures.
[0045] A memory cell is formed on each active region 11 . The memory cell has a 2T2R structure and includes a first transistor 21 , a second transistor 22 , a first memristor 23 and a second memristor 24 .
[0046] Figure 3 A schematic diagram of the structure of a storage unit provided in an embodiment of the present disclosure.
[0047] like Figure 3 As shown, the first transistor 21 and the second transistor 22 each include a gate 213 located on the substrate 10 and a drain region 211 and a source region 212 located in the substrate 10 on both sides of the gate 213 .
[0048] In the embodiment of the present disclosure, the first transistor 21 and the second transistor 22 share a drain region 211 .
[0049] Continue to see Figure 3 The first memristor 23 and the second memristor 24 are located on the drain region 211 and are electrically connected to the drain region 211 .
[0050] In the disclosed embodiment, two transistors share a drain region, and then two memristors (R) are formed on the drain region, so two word lines can control any one of the memristors through two transistors. This will have one more R than the 2T1R structure, and will improve the driving capability and solve the Reset difficulty problem.
[0051] See below for more information Figure 1 and Figure 2 , a detailed description of the semiconductor structure provided by the embodiment of the present disclosure is given.
[0052] In one embodiment, the semiconductor structure further includes: a first interlayer dielectric layer 41 , a second interlayer dielectric layer 42 , a third interlayer dielectric layer 43 , a fourth interlayer dielectric layer 44 and a fifth interlayer dielectric layer 45 which are sequentially stacked on the substrate 10 .
[0053] The material of the first interlayer dielectric layer 41 includes but is not limited to insulating materials such as silicon oxide, silicon nitride or silicon oxynitride; the second interlayer dielectric layer 42 can be a metal interlayer dielectric layer, such as aluminum oxide, zinc oxide and other materials; the third interlayer dielectric layer 43 can be a silicon carbide film (Nitride Doped Silicon Carbide, NDC); the material of the fourth interlayer dielectric layer 44 includes but is not limited to insulating materials such as silicon oxide, silicon nitride or silicon oxynitride; the material of the fifth interlayer dielectric layer 45 includes ultra-low K material.
[0054] like Figure 2 As shown, the first transistor 21 and the second transistor 22 are located in the first interlayer dielectric layer 41 .
[0055] like Figure 1 and Figure 3 As shown, in each transistor unit, the first transistor 21 is connected to one word line 70, and the second transistor 22 is connected to another word line 70. Specifically, as Figure 3 As shown, the word line WL is connected to the gate 213 of the transistor.
[0056] The semiconductor structure also includes: a first contact plug 51 located in the first interlayer dielectric layer 41; a metal connection layer 80 located in the second interlayer dielectric layer 42; and a second contact plug 52 located in the third interlayer dielectric layer 43; wherein the metal connection layer 80 is connected to the substrate 10 through the first contact plug 51, and is connected to the first memristor 23 and the second memristor 24 through the second contact plug 52.
[0057] The material of the metal connection layer 80 includes but is not limited to copper. The first contact plug 51 and the second contact plug 52 may be a double-layer structure, and the material of the first contact plug 51 and the second contact plug 52 may include titanium nitride in the outer layer and metal tungsten in the inner layer.
[0058] The first memristor 23 and the second memristor 24 are located in the fourth interlayer dielectric layer 44 and the fifth interlayer dielectric layer 45 .
[0059] In one embodiment, the first memristor 23 and the second memristor 24 both include a lower electrode 201 , a resistive switching layer 202 and an upper electrode 203 arranged from bottom to top, wherein the first memristor 23 and the second memristor 24 share a lower electrode 201 .
[0060] The first memristor 23 and the second memristor 24 share a lower electrode 201 , so that two transistors can control any one of the memristors.
[0061] The material of the lower electrode includes but is not limited to titanium nitride; the material of the resistive layer includes but is not limited to transition metal oxides, such as hafnium oxide, aluminum oxide, etc.; the material of the upper electrode includes but is not limited to titanium nitride.
[0062] In one embodiment, if Figure 1 As shown, the extending direction of the resistive switching unit intersects with the first direction and forms a preset angle, and the preset angle ranges from 30° to 60°. Preferably, the preset angle is 45°.
[0063] In this embodiment, the resistive switching unit is arranged in an inclined manner, so that one more R can be arranged in the same area. In order to improve the driving capability of the transistor, the present invention designs the structure of the shared SL in the prior art as a shared drain region, but this will make the original 2R become 1R. Therefore, in order not to sacrifice the number of R in the same area, an inclined placement is adopted so that the original 2R can be maintained in the same area; at the same time, the preset angle is set within this range, so that when the bit lines are set later, the bit lines respectively connected to the first memristor and the second memristor can be separated so as not to contact with each other and cause interference.
[0064] The semiconductor structure also includes: a plurality of source lines 30 (SL) extending along the first direction, wherein in each transistor unit, the source region 212 of the first transistor 21 is connected to one source line 30, and the source region 212 of the second transistor 22 is connected to another source line 30; wherein, in two adjacent rows of transistor units on the active area 11 arranged along the first direction, the source regions 212 of all the first transistors 21 in one row and the source regions 212 of all the second transistors 22 in the other row are connected to the same source line 30.
[0065] In the disclosed embodiment, since two memristors are formed on a common drain region, any memristor can be controlled by applying excitation through two source lines at the same time, thereby solving the reset difficulty problem.
[0066] like Figure 2 As shown, the source line 30 is located in the second interlayer dielectric layer 42 .
[0067] The semiconductor structure also includes: a plurality of bit lines 60 (BL) extending along the first direction, wherein, in each row of resistive switching units on the active area 11 arranged along the first direction, all first memristors 23 are connected to the same bit line 60 , and all second memristors 24 are connected to another bit line 60 .
[0068] Specifically, Figure 2 As shown, the first memristor 23 and the second memristor 24 are connected to the bit line 60 through the third contact plug 53 .
[0069] Table 1 below shows a comparison of parameters of a semiconductor structure in the prior art and a semiconductor structure in the present disclosure.
[0070] Table 1
[0071] Prior art The Disclosure Architecture 2T2R 2T2R Unit cell <![CDATA[55F 2 (430*250)]]> <![CDATA[55F 2 (410*262)]]> Drive Capability 170 / 40 (170*2) / 40, driving capacity doubled
[0072] As shown in Table 1, the semiconductor structure in the prior art and the structure in the present disclosure are both 2T2R structures, and the size of the storage unit (Unit cell) is 55F. 2In the case of , the driving capability in the prior art is less than the driving capability in the present disclosure, wherein, Figure 1 As shown, 170 nm refers to the width of the active region 11 along the second direction, and 40 nm refers to the width of the word line 70 along the first direction. The present disclosure can control any one R through two word lines, so the driving capability is doubled.
[0073] In the disclosed embodiment, the size of the semiconductor structure can be miniaturized and is not limited by the insufficient driving capability of the transistor caused by the miniaturization of the size.
[0074] Compared with the 2T1R structure, the 2T2R structure in the embodiment of the present disclosure can have one more R under the same driving capability.
[0075] Table 2 below shows the switching states of the word line, bit line and source line of one of the memristors under different circumstances.
[0076] Table 2
[0077] R BL1 BL2 WL2 WL3 SL1 SL2 Forming 1 0 1 1 0 0 Set 1 0 1 1 0 0 Reset 0 1 1 1 1 1
[0078] Among them, Table 2 above shows Figure 1 The switching states of the word line, bit line and source line of the memristor in the lower left corner in different situations, where 1 means on and 0 means off. It can be seen from the table that two word lines WL can simultaneously increase the excitation of one R to improve the driving capability.
[0079] The present disclosure also provides a method for preparing a semiconductor structure. Figure 4 Flow chart of the method for preparing a semiconductor structure provided by an embodiment of the present disclosure. Figure 4 As shown, the method for preparing the semiconductor structure includes:
[0080] Step 401: providing a substrate, wherein the substrate comprises a plurality of active regions arranged in an array along a first direction and a second direction;
[0081] Step 402: forming a transistor unit on each active region, wherein the transistor unit includes a first transistor and a second transistor, and the first transistor and the second transistor share a drain region;
[0082] Step 403: forming a plurality of word lines extending along the second direction, wherein in each transistor unit, a first transistor is connected to one word line, and a second transistor is connected to another word line;
[0083] Step 404: forming a resistive switching unit on each drain region, each resistive switching unit including a first memristor and a second memristor.
[0084] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is further described in detail below in conjunction with specific embodiments. Figures 5a to 5i A schematic diagram of a semiconductor structure during the preparation process provided in an embodiment of the present disclosure.
[0085] First, see Figure 5a , perform step 401, provide a substrate 10, the substrate 10 includes a plurality of active regions 11 arranged in an array along a first direction and a second direction.
[0086] In one embodiment, the substrate 10 can be a single semiconductor material substrate (for example, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (for example, a germanium silicon substrate, etc.), or a silicon on insulator substrate (Silicon on Insulator, SOI), a germanium on insulator (Germanium on Insulator, GOI) substrate, etc.
[0087] like Figure 1 As shown, the substrate 10 includes a plurality of active regions 11 arranged in an array along a first direction and a second direction, wherein adjacent active regions 11 are insulated and isolated by shallow trench isolation structures (not shown in the figure).
[0088] Next, continue to see Figure 5a , executing step 402, forming a transistor unit on each active area, the transistor unit including a first transistor 21 and a second transistor 22, the first transistor 21 and the second transistor 22 share a drain region.
[0089] For details, see Figure 3 The first transistor 21 and the second transistor 22 each include a gate 213 located on the substrate 10 and a drain region 211 and a source region 212 located in the substrate 10 on both sides of the gate 213. The first transistor 21 and the second transistor 22 share a drain region 211.
[0090] Next, continue to see Figure 5a , forming a first interlayer dielectric layer 41 , and forming a first contact plug 51 in the first interlayer dielectric layer 41 .
[0091] The material of the first interlayer dielectric layer 41 includes but is not limited to insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. The first contact plug 51 may be a double-layer structure. The material of the first contact plug 51 may include titanium nitride in the outer layer and metal tungsten in the inner layer.
[0092] Continue to see Figure 5a A second interlayer dielectric layer 42 is formed on the first interlayer dielectric layer 41 , and a metal connection layer 80 is formed in the second interlayer dielectric layer 42 .
[0093] The second interlayer dielectric layer 42 may be a metal interlayer dielectric layer, such as aluminum oxide, zinc oxide, etc. The material of the metal connection layer 80 includes but is not limited to metal copper.
[0094] Continue to see Figure 5a ,as well as Figure 1 and Figure 3 , forming a plurality of source lines 30 extending along the first direction, in each transistor unit, the source region 212 of the first transistor 21 is connected to one source line 30, and the source region 212 of the second transistor 22 is connected to another source line 30; wherein, in two adjacent rows of transistor units on the active area 11 arranged along the first direction, the source regions 212 of all the first transistors 21 in one row and the source regions 212 of all the second transistors 22 in the other row are connected to the same source line 30.
[0095] Continue to see Figure 5a , a third interlayer dielectric layer 43 is formed on the second interlayer dielectric layer 42 , and a second contact plug 52 is formed in the third interlayer dielectric layer 43 .
[0096] The third interlayer dielectric layer 43 may be a silicon carbide film, the second contact plug 52 may be a double-layer structure, and the material of the second contact plug 52 may include titanium nitride located in the outer layer and metal tungsten located in the inner layer.
[0097] Next, see Figure 1 and Figure 3 , executing step 403 to form a plurality of word lines 70 extending along the second direction, wherein in each transistor unit, the first transistor 21 is connected to one word line 70, and the second transistor 22 is connected to another word line 70. Specifically, Figure 3 As shown, the word line WL is connected to the gate 213 of the transistor.
[0098] Next, step 404 is performed to form a resistive switching unit on each drain region 211 , and each resistive switching unit includes a first memristor 23 and a second memristor 24 .
[0099] For details, see Figure 5b , a lower electrode material layer 201 ′ is formed on the third interlayer dielectric layer 43 .
[0100] In actual operation, the lower electrode material layer 201' can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods. Preferably, it can be formed by physical vapor deposition process.
[0101] Next, see Figure 5c , and etching the lower electrode material layer 201 ′ to form the lower electrode 201 .
[0102] In actual operation, a mask layer may be formed on the lower electrode material layer 201 ′, and then the mask layer may be patterned to form a lower electrode pattern on the mask layer, and the lower electrode material layer 201 ′ may be etched according to the lower electrode pattern to form the lower electrode 201 .
[0103] The etching process may be a wet etching process or a dry etching process.
[0104] Next, see Figure 5d and Figure 5e , forming a fourth interlayer dielectric layer 44 covering the lower electrode 201 , and then performing chemical mechanical polishing (CMP) on the fourth interlayer dielectric layer 44 to make the fourth interlayer dielectric layer 44 flush with the surface of the lower electrode 201 .
[0105] The fourth interlayer dielectric layer 44 can insulate and isolate adjacent lower electrodes 201 .
[0106] The material of the fourth interlayer dielectric layer 44 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.
[0107] Next, see Figure 5f , a resistive switching layer material layer 202 ′ and an upper electrode material layer 203 ′ are formed on the fourth interlayer dielectric layer 44 and the lower electrode 201 .
[0108] In actual operation, the resistive layer material layer 202' and the upper electrode material layer 203' can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods. Preferably, they can be formed by physical vapor deposition process.
[0109] Next, see Figure 5g , the resistive layer material layer 202 ′ and the upper electrode material layer 203 ′ are etched to form the resistive layer 202 and the upper electrode 203 .
[0110] In one embodiment, the first memristor 23 and the second memristor 24 both include a lower electrode 201 , a resistive switching layer 202 and an upper electrode 203 arranged from bottom to top, wherein the first memristor 23 and the second memristor 24 share a lower electrode 201 .
[0111] The first memristor 23 and the second memristor 24 share a lower electrode 201 , so that two transistors can control any one of the memristors.
[0112] The material of the lower electrode includes but is not limited to titanium nitride; the material of the resistive layer includes but is not limited to transition metal oxides, such as hafnium oxide, aluminum oxide, etc.; the material of the upper electrode includes but is not limited to titanium nitride.
[0113] In one embodiment, if Figure 1 As shown, the extending direction of the resistive switching unit intersects with the first direction and forms a preset angle, and the preset angle ranges from 30° to 60°. Preferably, the preset angle is 45°.
[0114] In this embodiment, the resistive switching unit is arranged in an inclined manner, so that one more R can be arranged in the same area. In order to improve the driving capability of the transistor, the present invention designs the structure of the shared SL in the prior art as a shared drain region, but this will make the original 2R become 1R. Therefore, in order not to sacrifice the number of R in the same area, an inclined placement is adopted so that the original 2R can be maintained in the same area; at the same time, the preset angle is set within this range, so that when the bit lines are set later, the bit lines respectively connected to the first memristor and the second memristor can be separated so as not to contact with each other and cause interference.
[0115] Next, see Figure 5h , forming a fifth interlayer dielectric layer 45 covering the first memristor 23 and the second memristor 24 .
[0116] The material of the fifth interlayer dielectric layer 45 includes ultra low-K material.
[0117] Next, see Figure 5i , forming a third contact plug 53 located in the fifth interlayer dielectric layer 45 , wherein the third contact plug 53 is located on the upper electrode 203 and is electrically connected to the upper electrode 203 .
[0118] In actual operation, a mask layer is formed on the fifth interlayer dielectric layer 45, and the mask layer is patterned to form a position for a third contact plug through hole on the mask layer. Then, the fifth interlayer dielectric layer 45 is etched along the position of the third contact plug through hole to form a third contact plug through hole. The third contact plug through hole exposes a portion of the upper electrode 203, and a third contact plug 53 is formed in the third contact plug through hole.
[0119] The third contact plug 53 may have a double-layer structure, and the material of the third contact plug 53 may include titanium nitride at an outer layer and metal tungsten at an inner layer.
[0120] Next, continue to see Figure 5i , forming a plurality of bit lines 60 extending along the first direction, wherein, in each row of resistive switching units on the active region 11 arranged along the first direction, all first memristors 23 are connected to the same bit line 60 , and all second memristors 24 are connected to another bit line 60 .
[0121] Specifically, the first memristor 23 and the second memristor 24 are connected to the bit line 60 through the third contact plug 53 .
[0122] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.
[0123] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0124] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A semiconductor structure, It is characterized in that The semiconductor structure comprises: A substrate, the substrate comprising a plurality of active regions arranged in an array along a first direction and a second direction; A transistor unit is formed on each of the active regions, the transistor unit comprising a first transistor and a second transistor, the first transistor and the second transistor sharing a drain region; A resistive switching unit is formed on each of the drain regions, and each of the resistive switching units includes a first memristor and a second memristor; A plurality of word lines extending along the second direction, wherein in each of the transistor units, the first transistor is connected to one word line, and the second transistor is connected to another word line.
2. The semiconductor structure according to claim 1, It is characterized in that The extending direction of the resistive switching unit intersects with the first direction and forms a preset angle, and the preset angle ranges from 30° to 60°.
3. The semiconductor structure according to claim 1, It is characterized in that The first memristor and the second memristor both include a lower electrode, a resistive switching layer, and an upper electrode arranged from bottom to top, wherein the first memristor and the second memristor share a lower electrode.
4. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further comprises: A plurality of bit lines extending along the first direction, wherein in each row of resistive switching units on the active area arranged along the first direction, all the first memristors are connected to the same bit line, and all the second memristors are connected to another bit line.
5. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further comprises: A plurality of source lines extending along the first direction, wherein in each of the transistor units, the source region of the first transistor is connected to one source line, and the source region of the second transistor is connected to another source line; wherein, in two adjacent rows of transistor units on the active regions arranged along the first direction, the source regions of all the first transistors in one row and the source regions of all the second transistors in the other row are connected to the same source line.
6. A method for preparing a semiconductor structure, It is characterized in that The method comprises: Providing a substrate, the substrate comprising a plurality of active regions arranged in an array along a first direction and a second direction; forming a transistor unit on each of the active regions, wherein the transistor unit comprises a first transistor and a second transistor, wherein the first transistor and the second transistor share a drain region; forming a plurality of word lines extending along the second direction, wherein, in each of the transistor units, the first transistor is connected to one word line, and the second transistor is connected to another word line; A resistive switching unit is formed on each of the drain regions, and each of the resistive switching units includes a first memristor and a second memristor.
7. The method according to claim 6, It is characterized in that The extending direction of the resistive switching unit intersects with the first direction and forms a preset angle, and the preset angle ranges from 30° to 60°.
8. The method according to claim 6, It is characterized in that The first memristor and the second memristor both include a lower electrode, a resistive switching layer, and an upper electrode arranged from bottom to top, wherein the first memristor and the second memristor share a lower electrode.
9. The method according to claim 6, It is characterized in that The method further comprises: After forming the resistive switching unit, a plurality of bit lines extending along the first direction are formed, wherein, in each row of resistive switching units on the active area arranged along the first direction, all the first memristors are connected to the same bit line, and all the second memristors are connected to another bit line.
10. The method according to claim 6, It is characterized in that The method further comprises: After forming the transistor unit, a plurality of source lines extending along the first direction are formed, wherein in each of the transistor units, the source region of the first transistor is connected to one source line, and the source region of the second transistor is connected to another source line; wherein, in two adjacent rows of transistor units on the active regions arranged along the first direction, the source regions of all the first transistors in one row and the source regions of all the second transistors in the other row are connected to the same source line.