Display device having connection electrode through bending area

Abstract

A display device having a connection electrode spanning a bending area may be provided. The connection electrode may be disposed on a device substrate including a bending region between a display region and a pad region. The connection electrode may connect the display area and the pad area across the bending area. The connection electrode may have a stacked structure of a lower connection electrode and an upper connection electrode. The light emitting device, the encapsulation element, and the touch electrode may be sequentially stacked on the display area of the device substrate. The upper connection electrode may include the same material as the touch electrode. Accordingly, in the display device, disconnection of the connection electrode due to bending stress and external impact may be prevented.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202011518204.6 (application date: December 21, 2020, invention name: display device with connecting electrodes spanning a curved area). Technical Field

[0002] The present invention relates to a display device in which a connection electrode crosses a bending region to connect a display region and a pad region. Background Art

[0003] Typically, electronic appliances such as monitors, televisions (TVs), laptop computers, and digital cameras include a display device that displays an image. For example, the display device may include at least one light emitting device. The light emitting device may emit light that displays a specific color. For example, the light emitting device may include a light emitting layer located between a first light emitting electrode and a second light emitting electrode.

[0004] The display device may include a bending area between the display area and the pad area. The light emitting device may be disposed on the display area. The pad to which an external signal is applied may be disposed on the pad area. The device substrate supporting the light emitting device and the pad may be bent in the bending area. The connecting electrode connecting the display area and the pad area may span the bending area. Therefore, in the display device, the connecting electrode may be disconnected due to bending stress or external impact. Summary of the invention

[0005] SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0006] An object of the present invention is to provide a display device which prevents disconnection of a connection electrode due to bending stress and external impact.

[0007] Another object of the present invention is to provide a display device in which a display area and a pad area can be stably connected by a connection electrode spanning a bending area.

[0008] Other advantages, purposes and features of the present invention will be described in part in the following description, and in part will become apparent to those skilled in the art after reviewing the following content, or may be learned from the practice of the present invention. The purposes and other advantages of the present invention can be realized and obtained through the structures particularly pointed out in the written description and claims and the drawings.

[0009] To achieve these objects and other advantages, and in accordance with the purposes of the present invention, as embodied and broadly described herein, a display device including a device substrate is provided. The device substrate includes a display area and a bending area. A light emitting device is disposed on the display area of ​​the device substrate. A packaging component is disposed on the light emitting device. A touch structure is disposed on the packaging component. The touch structure includes a touch electrode. A lower connecting electrode is disposed on the device substrate. The lower connecting electrode spans the bending area of ​​the device substrate. An anti-crack layer is disposed on the lower connecting electrode. The anti-crack layer includes an area overlapping the bending area. An upper connecting electrode is disposed on the anti-crack layer. The upper connecting electrode spans the bending area. The upper connecting electrode includes the same material as the touch electrode.

[0010] The upper connection electrode may include a region overlapping the lower connection electrode.

[0011] The crack prevention layer may include a connection contact hole exposing a portion of the lower connection electrode. The upper connection electrode may be connected to the lower connection electrode through the connection contact hole.

[0012] The connecting contact hole may be arranged outside the bending region.

[0013] The thin film transistor may be disposed between the device substrate and the light emitting device. The light emitting device may be connected to one of the thin film transistors through an intermediate contact electrode. The lower connection electrode may include the same material as the intermediate contact electrode.

[0014] The upper connection electrode may be connected to the lower connection electrode through the intermediate connection electrode. The intermediate connection electrode may include the same material as the first light emitting electrode of the light emitting device.

[0015] On the other hand, a display device includes a device substrate. The device substrate includes a curved area arranged between a display area and a pad area. A light-emitting device, a packaging component, an anti-crack layer and a connecting electrode are arranged on the device substrate. The light-emitting device is arranged on the display area. The packaging component covers the light-emitting device. A touch electrode is arranged on the packaging component. The touch electrode overlaps with the display area. The touch electrode is connected to a link line. The link line extends outside the display area along the surface of the packaging component. The anti-crack layer is separated from the packaging component. The anti-crack layer includes an area overlapping with the curved area. The connecting electrode connects the display area and the pad area across the curved area. The connecting electrode has a stacked structure of a lower connecting electrode and an upper connecting electrode. The lower connecting electrode is arranged between the device substrate and the anti-crack layer. The upper connecting electrode is arranged on the anti-crack layer. The touch electrode, the link line and the upper connecting electrode include the same material.

[0016] The link line may be in direct contact with the upper connection electrode.

[0017] The driving circuit may be disposed between the display area of ​​the device substrate and the light emitting device. The driving circuit may include a first thin film transistor and a second thin film transistor. The first thin film transistor may be connected to the light emitting device. The second thin film transistor may be connected to the first thin film transistor. The second semiconductor pattern of the second thin film transistor may include a material different from the first semiconductor pattern of the first thin film transistor.

[0018] The second semiconductor pattern of the second thin film transistor may include metal oxide.

[0019] The first overcoat may be disposed between the device substrate and the light emitting device. The first overcoat may cover the driving circuit. The second overcoat may be disposed between the first overcoat and the light emitting device. The anti-crack layer may include the same material as the second overcoat.

[0020] The gate driver may be disposed on the device substrate. The gate driver may be separated from the display area, the pad area, and the bending area. The gate driver may include at least a third thin film transistor. The third semiconductor pattern of the third thin film transistor may include the same material as the first semiconductor pattern of the first thin film transistor.

[0021] The touch buffer layer may be disposed between the package element and the touch electrode. The touch buffer layer may extend between the package element and the link line and between the crack prevention layer and the upper connection electrode.

[0022] The connection electrode may further include an intermediate connection electrode connecting the lower connection electrode and the upper connection electrode. The intermediate connection electrode may penetrate the anti-crack layer at the outer side of the bending area.

[0023] The substrate hole may penetrate the device substrate. The light emitting device may be separated from the substrate hole. The separation device may be disposed between the light emitting device and the substrate hole. The separation device may have at least one undercut structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present invention and together with the description serve to explain the principle of the present invention. In the drawings:

[0025] Figure 1 is a view schematically showing a display device according to an embodiment of the present invention;

[0026] Figure 2 is a view schematically showing a hole peripheral area of ​​a display device according to an embodiment of the present invention;

[0027] Figure 3A It is shown along Figure 1 A view of a cross section taken along line I-I';

[0028] Figure 3B is a view showing a cross section of a hole peripheral area in a display device according to an embodiment of the present invention;

[0029] Figure 3C It is shown along Figure 1 A view of a cross section taken along line II-II'; and

[0030] FIG. 4A to FIG. 17A , FIG. 4B to FIG. 17B and FIG. 4C to FIG. 17C are views sequentially illustrating a method of forming a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] Hereinafter, details related to the above-mentioned purpose, technical configuration and operation effect of the embodiments of the present invention will be clearly understood through the following detailed description with reference to the accompanying drawings, which illustrate some embodiments of the present invention. Here, the embodiments of the present invention are provided to allow the technical spirit of the present invention to be satisfactorily conveyed to those skilled in the art, so the present invention can be implemented in other forms and is not limited to the embodiments described below.

[0032] In addition, throughout the specification, the same or very similar elements may be represented by the same reference numerals, and in the drawings, the lengths and thicknesses of layers and regions may be exaggerated for convenience. It should be understood that when a first element is referred to as being "on" a second element, although the first element may be disposed on the second element to contact the second element, a third element may be interposed between the first element and the second element.

[0033] Here, terms such as "first" and "second" may be used to distinguish any one element from another element. However, without departing from the technical spirit of the present invention, the first element and the second element may be arbitrarily named according to the convenience of those skilled in the art.

[0034] The terms used in the specification of the present invention are only used to describe specific embodiments, and are not intended to limit the scope of the present invention. For example, unless the context clearly indicates otherwise, the elements described in the singular are intended to include multiple elements. In addition, in the specification of the present invention, it should also be understood that the terms "include" and "comprise" specify the presence of the described features, wholes, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which the example embodiments belong. It should also be understood that terms (e.g., terms defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0036] (Implementation Method)

[0037] Figure 1 is a view schematically showing a display device according to an embodiment of the present invention. Figure 2 is a view schematically showing a hole peripheral area of ​​a display device according to an embodiment of the present invention. Figure 3A It is shown along Figure 1 A view of a cross section taken along line I-I'. Figure 3B is a view showing a cross section of a hole peripheral area in a display device according to an embodiment of the present invention. Figure 3C It is shown along Figure 1 A view of a cross section taken along line II-II'.

[0038] Reference Figure 1 , Figure 2 and FIG. 3A to FIG. 3C , a display device according to an embodiment of the present invention may include a device substrate 100. The device substrate 100 may include an insulating material. For example, the device substrate 100 may include glass or plastic. The device substrate 100 may have a multilayer structure. For example, the device substrate 100 may include a structure in which a first substrate layer 101, a substrate insulating layer 102, and a second substrate layer 103 are sequentially stacked. The second substrate layer 103 may include the same material as the first substrate layer 101. For example, the first substrate layer 101 and the second substrate layer 103 may include a polymer material such as polyimide (PI). The substrate insulating layer 102 may include an insulating material. Therefore, in a display device according to an embodiment of the present invention, the device substrate 100 may have flexibility. Therefore, in a display device according to an embodiment of the present invention, damage to the device substrate 100 due to bending stress may be prevented.

[0039] The device substrate 100 may include a display area AA, a bending area BA, and a pad area PD. The image provided to the user may be implemented in the display area AA. For example, the display area AA may include a plurality of pixel areas PA. Each pixel area PA may display a specific color. For example, a light emitting device 600 may be disposed on each pixel area PA. The light emitting device 600 may emit light showing a specific color. For example, the light emitting device 600 may include a first light emitting electrode 610, a light emitting layer 620, and a second light emitting electrode 630 sequentially stacked on the device substrate 100.

[0040] The first light emitting electrode 610 may include a conductive material. The first light emitting electrode 610 may have a high reflectivity. For example, the first light emitting electrode 610 may include a metal such as aluminum (Al) and silver (Ag). The first light emitting electrode 610 may have a multilayer structure. For example, the first light emitting electrode 610 may have a structure in which a reflective electrode formed of a metal is disposed between transparent electrodes formed of a transparent conductive material such as ITO and IZO.

[0041] The light emitting layer 620 may generate light having a brightness corresponding to the voltage difference between the first light emitting electrode 610 and the second light emitting electrode 630. For example, the light emitting layer 620 may include a light emitting material layer (EML) 622 having a light emitting material. The light emitting material may include an organic material, an inorganic material, or a mixed material. For example, the display device according to the embodiment of the present invention may be an organic light emitting display device having a light emitting material layer 622 formed of an organic material. The light emitting layer 620 may have a multilayer structure. For example, the light emitting layer 620 may include at least one of a first light emitting common layer 621 between the first light emitting electrode 610 and the light emitting material layer 622 and a second light emitting common layer 623 between the light emitting material layer 622 and the second light emitting electrode 630. Each of the first light emitting common layer 621 and the second light emitting common layer 623 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). For example, in the display device according to the embodiment of the present invention, the first light emitting common layer 621 may include at least one of a hole injection layer (HIL) and a hole transport layer (HTL), and the second light emitting common layer 623 may include at least one of an electron transport layer (ETL) and an electron injection layer (EIL). Therefore, in the display device according to the embodiment of the present invention, the light emitting efficiency of the light emitting device 600 can be increased.

[0042] The second light emitting electrode 630 may include a conductive material. The second light emitting electrode 630 may include a material different from the first light emitting electrode 610. For example, the second light emitting electrode 630 may be a transparent electrode formed of a transparent conductive material such as ITO and IZO. The second light emitting electrode 630 may have a higher transmittance than the first light emitting electrode 610. Therefore, in the display device according to the embodiment of the present invention, the light generated from the light emitting layer 620 may be emitted through the second light emitting electrode 630.

[0043] A driving circuit may be provided in each pixel region PA. The driving circuit may generate a driving current provided to the light emitting device 600. The driving circuit may be connected to signal lines GL, DL, VDD, and VSS. For example, each pixel region PA may be defined by signal lines GL, DL, VDD, and VSS. The signal lines GL, DL, VDD, and VSS may transmit various signals for realizing an image. For example, the signal lines GL, DL, VDD, and VSS may include a gate line GL for applying a gate signal, a data line DL for applying a data signal, and power lines VDD and VSS for providing a power voltage. The driving circuit may generate a driving current corresponding to the data signal according to the gate signal. The operation of the light emitting device 600 may be maintained for one frame. For example, the driving circuit may include a first thin film transistor 210, a second thin film transistor 220, and a storage capacitor 230.

[0044] The first thin film transistor 210 may be electrically connected to the light emitting device 600. The first thin film transistor 210 may provide a driving current corresponding to a data signal to the light emitting device 600. For example, the first thin film transistor 210 may be disposed between the light emitting device 600 and one of the power supply lines VDD and VSS. The first thin film transistor 210 may include a first semiconductor pattern 211, a first gate insulating layer 212, a first gate electrode 213, a first interlayer insulating layer 214, a first source electrode 215, and a first drain electrode 216.

[0045] The first semiconductor pattern 211 may be disposed near the device substrate 100. The first semiconductor pattern 211 may include a semiconductor material. For example, the first semiconductor pattern 211 may include silicon. The first semiconductor pattern 211 may include a polycrystalline semiconductor. For example, the first semiconductor pattern 211 may include low temperature polycrystalline silicon (LTPS). The first semiconductor pattern 211 may include a first source region, a first drain region, and a first channel region. The first channel region may be disposed between the first source region and the first drain region. The first channel region may have a lower conductivity than the first source region and the first drain region. For example, the first source region and the first drain region may contain a higher content of conductive impurities than the first channel region.

[0046] The first gate insulating layer 212 may be disposed on the first semiconductor pattern 211. The first gate insulating layer 212 may extend beyond the first semiconductor pattern 211. For example, a side portion of the first semiconductor pattern 211 may be covered by the first gate insulating layer 212. The first gate insulating layer 212 may include an insulating material. For example, the first gate insulating layer 212 may include silicon oxide (SiO) and / or silicon nitride (SiN). Silicon oxide (SiO) may include silicon dioxide (SiO2). The first gate insulating layer 212 may include a material having a high dielectric constant. For example, the first gate insulating layer 212 may include a high-K material such as hafnium oxide (HfO).

[0047] The first gate electrode 213 may be disposed on the first gate insulating layer 212. The first gate electrode 213 may include a conductive material. For example, the first gate electrode 213 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The first gate electrode 213 may be insulated from the first semiconductor pattern 211 by the first gate insulating layer 212. The first gate electrode 213 may overlap with the first channel region of the first semiconductor pattern 211. For example, the first channel region of the first semiconductor pattern 211 may have a conductivity corresponding to a voltage applied to the first gate electrode 213.

[0048] The first interlayer insulating layer 214 may be disposed on the first gate electrode 213. The first interlayer insulating layer 214 may extend beyond the first gate electrode 213. For example, a side portion of the first gate electrode 213 may be covered by the first interlayer insulating layer 214. The first interlayer insulating layer 214 may extend along the first gate insulating layer 212. The first interlayer insulating layer 214 may include an insulating material. For example, the first interlayer insulating layer 214 may include silicon oxide (SiO).

[0049] The first source electrode 215 may be disposed on the first interlayer insulating layer 214. The first source electrode 215 may include a conductive material. For example, the first source electrode 215 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The first source electrode 215 may be insulated from the first gate electrode 213 by the first interlayer insulating layer 214. The first source electrode 215 may include a material different from the first gate electrode 213. The first source electrode 215 may be electrically connected to the first source region of the first semiconductor pattern 211. For example, the first gate insulating layer 212 and the first interlayer insulating layer 214 may include a first source contact hole partially exposing the first source region of the first semiconductor pattern 211. The first source electrode 215 may include a region overlapping the first source region of the first semiconductor pattern 211. For example, the first source electrode 215 may be in direct contact with the first source region of the first semiconductor pattern 211 in the first source contact hole.

[0050] The first drain electrode 216 may be disposed on the first interlayer insulating layer 214. The first drain electrode 216 may include a conductive material. For example, the first drain electrode 216 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The first drain electrode 216 may be insulated from the first gate electrode 213 by the first interlayer insulating layer 214. The first drain electrode 216 may include a material different from the first gate electrode 213. For example, the first drain electrode 216 may include the same material as the first source electrode 215. The first drain electrode 216 may be formed by the same process as the first source electrode 215. The first drain electrode 216 may be electrically connected to the first drain region of the first semiconductor pattern 211. The first drain electrode 216 may be separated from the first source electrode 215. For example, the first gate insulating layer 212 and the first interlayer insulating layer 214 may include a first drain contact hole partially exposing the first drain region of the first semiconductor pattern 211. The first drain electrode 216 may include a region overlapping the first drain region of the first semiconductor pattern 211. For example, the first drain electrode 216 may directly contact the first drain region of the first semiconductor pattern 211 in the first drain contact hole.

[0051] The second thin film transistor 220 may be electrically connected to the first thin film transistor 210. The second thin film transistor 220 may transmit a data signal to the first thin film transistor 210 according to a scan signal. For example, the second thin film transistor 220 may be disposed between the data line DL and the first gate electrode 213 of the first thin film transistor 210. The structure of the second thin film transistor 220 may be the same as that of the first thin film transistor 210. For example, the second thin film transistor 220 may include a second semiconductor pattern 221, a second gate insulating layer 222, a second gate electrode 223, a second interlayer insulating layer 224, a second source electrode 225, and a second drain electrode 226.

[0052] The second semiconductor pattern 221 may include a semiconductor material. The second semiconductor pattern 221 may include a material different from the first semiconductor pattern 211. For example, the second semiconductor pattern 221 may include an oxide semiconductor formed of a metal oxide such as IGZO. The second semiconductor pattern 221 may be disposed on a layer different from the first semiconductor pattern 211. For example, a separation insulating layer 140 may be disposed on the first thin film transistor 210, and the second semiconductor pattern 221 may be disposed on the separation insulating layer 140. Therefore, in the display device according to the embodiment of the present invention, damage to the second semiconductor pattern 221 caused by the process of forming the first semiconductor pattern 211 may be prevented. The second semiconductor pattern 221 may include a second source region, a second drain region, and a second channel region. The second channel region may be disposed between the second source region and the second drain region. The second source region and the second drain region may have a lower resistance than the second channel region. For example, the second source region and the second drain region may include a conductive portion of an oxide semiconductor. The second channel region may be a non-conductive region of an oxide semiconductor.

[0053] The second gate insulating layer 222 may be disposed on the second semiconductor pattern 221. The second gate insulating layer 222 may overlap with the second channel region of the second semiconductor pattern 221. The second source region and the second drain region of the second semiconductor pattern 221 may not overlap with the second gate insulating layer 222. For example, the second gate insulating layer 222 may expose the second source region and the second drain region of the second semiconductor pattern 221. The second source region and the second drain region of the second semiconductor pattern 221 may be disposed outside the second gate insulating layer 222. For example, the second source region and the second drain region of the second semiconductor pattern 221 may be conductive by an etchant used in a process of patterning the second gate insulating layer 222. The second gate insulating layer 222 may include an insulating material. The second gate insulating layer 222 may include the same material as the first gate insulating layer 212. For example, the second gate insulating layer may have a multi-layer structure.

[0054] The second gate electrode 223 may be disposed on the second gate insulating layer 222. For example, the second gate electrode 223 may overlap with the second channel region of the second semiconductor pattern 221. The second gate electrode 223 may include a conductive material. For example, the second gate electrode 223 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The second gate electrode 223 may include the same material as the first gate electrode 213. The second gate electrode 223 may be insulated from the second semiconductor pattern 221 by the second gate insulating layer 222. For example, the second channel region of the semiconductor pattern 221 may have a conductivity corresponding to a voltage applied to the second gate electrode 223.

[0055] The second interlayer insulating layer 224 may be disposed on the second gate electrode 223. The second interlayer insulating layer 224 may extend beyond the second gate electrode 223. For example, a side portion of the second gate electrode 223 and a second source region and a second drain region of the second semiconductor pattern 221 may be covered by the second interlayer insulating layer 224. The second interlayer insulating layer 224 may include an insulating material. The second interlayer insulating layer 224 may include the same material as the first interlayer insulating layer 214. For example, the second interlayer insulating layer 224 may include silicon oxide (SiO).

[0056] The second source electrode 225 may be disposed on the second interlayer insulating layer 224. The second source electrode 225 may include a conductive material. For example, the second source electrode 225 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The second source electrode 225 may include the same material as the first source electrode 215. The second source electrode 225 may be insulated from the second gate electrode 223 by the second interlayer insulating layer 224. The second source electrode 225 may include a material different from the second gate electrode 223. The second source electrode 225 may be electrically connected to the second source region of the second semiconductor pattern 221. For example, the second interlayer insulating layer 224 may include a second source contact hole partially exposing the second source region of the second semiconductor pattern 221. The second source electrode 225 may include a region overlapping the second source region of the second semiconductor pattern 221. For example, the second source electrode 225 may be in direct contact with the second source region of the second semiconductor pattern 221 in the second source contact hole.

[0057] The second drain electrode 226 may be disposed on the second interlayer insulating layer 224. The second drain electrode 226 may include a conductive material. For example, the second drain electrode 226 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The second drain electrode 226 may include the same material as the first drain electrode 216. The second drain electrode 226 may be insulated from the second gate electrode 223 by the second interlayer insulating layer 224. The second drain electrode 226 may include a material different from the second gate electrode 223. For example, the second drain electrode 226 may include the same material as the second source electrode 225. The second drain electrode 226 may be formed by the same process as the second source electrode 225. The second drain electrode 226 may be electrically connected to the second drain region of the second semiconductor pattern 221. The second drain electrode 226 may be separated from the second source electrode 225. For example, the second interlayer insulating layer 224 may include a second drain contact hole partially exposing the second drain region of the second semiconductor pattern 221. The second drain electrode 226 may include a region overlapping the second drain region of the second semiconductor pattern 221. For example, the second drain electrode 226 may directly contact the second drain region of the second semiconductor pattern 221 in the second drain contact hole.

[0058] The storage capacitor 230 may maintain the operation of the first thin film transistor 210 for one frame. For example, the storage capacitor 230 may be connected between the first gate electrode 213 and the first drain electrode 216 of the first thin film transistor 210. The storage capacitor 230 may include a first storage electrode 231 and a second storage electrode 232 stacked in sequence. The first storage electrode 231 and the second storage electrode 232 may include a conductive material. For example, the first storage electrode 231 and the second storage electrode 232 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

[0059] The storage capacitor 230 may be formed using a process for forming the first thin film transistor 210 or the second thin film transistor 220. For example, the storage capacitor 230 may be disposed between the device substrate 100 and the separation insulating layer 140. The storage capacitor 230 may be disposed side by side with the first thin film transistor 210. The first storage electrode 231 may include the same material as the first gate electrode 213. The first storage electrode 231 may be disposed on the same layer as the first gate electrode 213. For example, the first storage electrode 231 may be formed by the same process as the first gate electrode 213. The second storage electrode 232 may include the same material as the first source electrode 215 and the first drain electrode 216. The second storage electrode 232 may be formed by the same process as the first source electrode 215 and the first drain electrode 216. For example, the first interlayer insulating layer 214 may extend between the first storage electrode 231 and the second storage electrode 232. The second storage electrode 232 may include a material different from the first storage electrode 231.

[0060] The second thin film transistor 220 may be disposed on the storage capacitor 230. For example, the second semiconductor pattern 221 may overlap the second storage electrode 232 of the storage capacitor 230. Therefore, in the display device according to the embodiment of the present invention, light passing through the device substrate 100 and traveling toward the second semiconductor pattern 221 may be blocked by the storage capacitor 230. Therefore, in the display device according to the embodiment of the present invention, a change in the characteristics of the second thin film transistor 220 due to external light may be prevented. The storage capacitor 230 may be electrically connected to the second drain electrode 226 of the second thin film transistor 220. For example, the first interlayer insulating layer 214, the separation insulating layer 140, and the second interlayer insulating layer 224 may include a storage contact hole partially exposing the first storage electrode 231 of the storage capacitor 230. The second drain electrode 226 may extend in the storage contact hole. For example, the second drain electrode 226 may be in direct contact with the first storage electrode 231 in the storage contact hole.

[0061] The device buffer layer 110 may be disposed between the device substrate 100 and the driving circuit of each pixel area PA. The device buffer layer 110 may prevent contamination from the device substrate 100 during the formation of the driving circuit. For example, the device buffer layer 110 may completely cover the display area AA of the device substrate 100. The device buffer layer 110 may be disposed between the device substrate 100 and the first semiconductor pattern 211 of each pixel area PA. The device buffer layer 110 may include an insulating material. For example, the device buffer layer 110 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The device buffer layer 110 may have a multilayer structure. For example, the device buffer layer 110 may have a stacked structure of a first buffer layer 111 and a second buffer layer 112 including a material different from the first buffer layer 111.

[0062] The first lower passivation layer 120 and the second lower passivation layer 130 may be sequentially stacked between the first thin film transistor 210 and the separation insulating layer 140 of each pixel area PA. The first lower passivation layer 120 and the second lower passivation layer 130 may prevent the thin film transistor 210 from being damaged due to external impact and moisture. The first lower passivation layer 120 and the second lower passivation layer 130 may extend between the storage capacitor 230 and the separation insulating layer 140 of each pixel area PA. For example, the storage contact hole of each pixel area PA may penetrate the first lower passivation layer 120 and the second lower passivation layer 130. The first lower passivation layer 120 and the second lower passivation layer 130 may include an insulating material. For example, the first lower passivation layer 120 and the second lower passivation layer 130 may include an inorganic material such as silicon oxide (SiO) and silicon nitride (SiN). The second lower passivation layer 130 may include a material different from the first lower passivation layer 120. For example, the first lower passivation layer 120 may include silicon oxide (SiO), and the second lower passivation layer 130 may include silicon nitride (SiN). Therefore, in the display device according to the embodiment of the present invention, damage to the first thin film transistor 210 and the storage capacitor 230 due to external impact and moisture can be effectively prevented.

[0063] The third lower passivation layer 150 may be disposed between the second interlayer insulating layer 224 and the second source electrode 225 of each pixel region PA, and between the second interlayer insulating layer 224 and the second drain electrode 226 of each pixel region PA. The third lower passivation layer 150 may prevent the second thin film transistor 220 from being damaged due to external impact and moisture. For example, the third lower passivation layer 150 may extend beyond the second semiconductor pattern 221 along the second interlayer insulating layer 224. The third lower passivation layer 150 may include an insulating material. The third lower passivation layer 150 may include a material different from the second interlayer insulating layer 224. For example, the third lower passivation layer 150 may include silicon nitride (SiN). Therefore, in the display device according to an embodiment of the present invention, damage to the second semiconductor pattern 221 due to external impact and moisture may be effectively prevented.

[0064] The intermediate source electrode 265 and the intermediate drain electrode 266 may be disposed on the third lower passivation layer of each pixel area PA. The intermediate source electrode 265 and the intermediate drain electrode 266 may include a conductive material. For example, the intermediate source electrode 265 and the intermediate drain electrode 266 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo) and tungsten (W). The intermediate drain electrode 266 may include the same material as the intermediate source electrode 265. For example, the intermediate drain electrode 266 may be formed by the same process as the intermediate source electrode 265. The intermediate source electrode 265 and the intermediate drain electrode 266 may include the same material as the second source electrode 225 and the second drain electrode 226. For example, the intermediate drain electrode 266, the intermediate source electrode 265, the second source electrode 225 and the second drain electrode 226 may be formed simultaneously.

[0065] The intermediate source electrode 265 may be electrically connected to the first source electrode 215 of the first thin film transistor 210. For example, the first lower passivation layer 120, the second lower passivation layer 130, the separation insulating layer 140, the second interlayer insulating layer 224, and the third lower passivation layer 150 may include a first intermediate contact hole partially exposing the first source electrode 215 of the first thin film transistor 210. The intermediate source electrode 265 may include a region overlapping the first source electrode 215 of the first thin film transistor 210. For example, the intermediate source electrode 265 may directly contact the first source electrode 215 of the first thin film transistor 210 in the first intermediate contact hole.

[0066] The middle drain electrode 266 may be electrically connected to the first drain electrode 216 of the first thin film transistor 210. For example, the first lower passivation layer 120, the second lower passivation layer 130, the separation insulating layer 140, the second interlayer insulating layer 224, and the third lower passivation layer 150 may include a second middle contact hole partially exposing the first drain electrode 216 of the first thin film transistor 210. The middle drain electrode 266 may be spaced apart from the middle source electrode 265. The middle drain electrode 266 may include a region overlapping the first drain electrode 216 of the first thin film transistor 210. For example, the middle drain electrode 266 may be in direct contact with the first drain electrode 216 of the first thin film transistor 210 in the second middle contact hole.

[0067] The light emitting device 600 of each pixel area PA may be arranged on the driving circuit of the corresponding pixel area PA. For example, the first thin film transistor 210, the second thin film transistor 220 and the storage capacitor 230 of each pixel area PA may be arranged between the device substrate 100 and the first light emitting electrode 610 of the corresponding pixel area PA. Therefore, in the display device according to the embodiment of the present invention, the area occupied by each pixel area PA may be minimized. Therefore, in the display device according to the embodiment of the present invention, the resolution may be improved.

[0068] The first overcoat 160 and the second overcoat 170 may be sequentially stacked between the driving circuit and the light emitting device 600 of each pixel area PA. For example, the first light emitting electrode 610, the light emitting layer 620, and the second light emitting electrode 630 of each pixel area PA may be sequentially stacked on the second overcoat 170 of the corresponding pixel area PA. The first overcoat 160 and the second overcoat 170 may eliminate the thickness difference caused by the driving circuit. For example, the upper surface of the second overcoat 170 facing the light emitting device 600 of each pixel area PA may be a flat surface. The first overcoat 160 and the second overcoat 170 may include an insulating material. The first overcoat 160 and the second overcoat 170 may be made of a material having high fluidity. For example, the first overcoat 160 and the second overcoat 170 may include an organic insulating material. The second overcoat 170 may include a material different from the first overcoat 160. Therefore, in the display device according to an embodiment of the present invention, the thickness difference caused by the driving circuit may be effectively eliminated.

[0069] The intermediate contact electrode 510 may be disposed between the first overcoat 160 and the second overcoat 170 of each pixel area PA. The light emitting device 600 may be electrically connected to the first drain electrode 216 of the first thin film transistor 210 via the intermediate contact electrode 510. For example, the intermediate contact electrode 510 may be connected to the intermediate drain electrode 266 by penetrating the first overcoat 160, and the first light emitting electrode 610 of the light emitting device 600 may be connected to the intermediate contact electrode 510 by penetrating the second overcoat 170. The intermediate contact electrode 510 may include a region overlapping with the intermediate drain electrode 266 and a region overlapping with the first light emitting electrode 610. For example, the intermediate contact electrode 510 may be disposed between the intermediate drain electrode 266 and the first light emitting electrode 610. The intermediate contact electrode 510 may be in direct contact with the intermediate drain electrode 266. The first light emitting electrode 610 may be in direct contact with the intermediate contact electrode 510. The intermediate contact electrode 510 may include a conductive material. For example, the intermediate contact electrode 510 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The intermediate contact electrode 510 may include a material different from that of the intermediate drain electrode 266 and the first light emitting electrode 610 .

[0070] The bank insulating layer 180 may be disposed on the second overcoat layer 170 of each pixel region PA. The bank insulating layer 180 may include an insulating material. For example, the bank insulating layer 180 may include an organic insulating material. The bank insulating layer 180 may include a material different from the first overcoat layer 160 and the second overcoat layer 170. The bank insulating layer 180 may cover the edge of each first light emitting electrode 610. The light emitting layer 620 and the second light emitting electrode 630 of each pixel region PA may be stacked on a portion of the corresponding first light emitting electrode 610 exposed by the bank insulating layer 180. For example, the bank insulating layer 180 may define a light emitting region in each pixel region PA.

[0071] The light emitting layer 620 of each pixel region PA may extend on the bank insulating layer 180. Each pixel region PA may display a color different from that of an adjacent pixel region PA. For example, the light emitting material layer 622 of each pixel region PA may be separated from the light emitting material layer 622 of the adjacent pixel region PA. The light emitting material layer 622 of each pixel region PA may include an end portion in the corresponding pixel region PA. The light emitting material layer 622 may be formed by using a fine metal mask (FMM). The end portion of each light emitting material layer 622 may be disposed on the bank insulating layer 180. For example, a spacer may be disposed on the bank insulating layer 180. The spacer may prevent the bank insulating layer 180 and the light emitting material layer 622 formed on the adjacent pixel region PA from being damaged by the fine metal mask. The first light emitting common layer 621 and the second light emitting common layer 623 of each light emitting material layer 622 may extend along the surface of the bank insulating layer 180. For example, the first light emitting common layer 621 and the second light emitting common layer 623 of each pixel region PA may be connected to the first light emitting common layer 621 and the second light emitting common layer 623 of the adjacent pixel region PA. Therefore, in the display device according to the embodiment of the present invention, process efficiency can be improved.

[0072] The voltage applied to the second light emitting electrode 630 of each pixel area PA may be the same as the voltage applied to the second light emitting electrode 630 of the adjacent pixel area PA. For example, the second light emitting electrode 630 of each pixel area PA may be connected to the second light emitting electrode 630 of the adjacent pixel area PA. Therefore, the display device according to the embodiment of the present invention can adjust the brightness of each pixel area PA by the gate signal and the data signal applied to the corresponding pixel area PA. The second light emitting electrode 630 of each pixel area PA may be in direct contact with the second light emitting electrode 630 of the adjacent pixel area PA.

[0073] The encapsulation element 700 may be disposed on the light emitting device 600 of each pixel region PA. The encapsulation element 700 may prevent the light emitting device 600 from being damaged due to external impact and moisture. The encapsulation element 700 may have a multilayer structure. For example, the encapsulation element 700 may include a first encapsulation layer 710, a second encapsulation layer 720, and a third encapsulation layer 730 stacked in sequence. The first encapsulation layer 710, the second encapsulation layer 720, and the third encapsulation layer 730 may include an insulating material. The second encapsulation layer 720 may include a material different from the first encapsulation layer 710 and the third encapsulation layer 730. For example, the first encapsulation layer 710 and the third encapsulation layer 730 may include an inorganic insulating material, and the second encapsulation layer 720 may include an organic insulating material. Therefore, in the display device according to the embodiment of the present invention, damage to the light emitting device 600 due to external impact and moisture may be effectively prevented. The thickness difference caused by the light emitting device 600 of each pixel region PA may be eliminated by the encapsulation element 700. For example, the upper surface of the encapsulation element 700 opposite to the device substrate 100 may be a flat surface.

[0074] The encapsulation element 700 may extend beyond the display area AA. At least one of the encapsulation dams 106 may be disposed outside the display area AA. The encapsulation dam 106 may include an insulating material. For example, the encapsulation dam 106 may include an organic insulating material. The encapsulation dam 106 may be disposed on the first overcoat 160. For example, the encapsulation dam 106 may include the same material as the second overcoat 170. The encapsulation dam 106 may be formed by the same process as the second overcoat 170. Therefore, in the display device according to the embodiment of the present invention, the process efficiency may be improved. The encapsulation dam 106 may extend along the edge of the display area AA. For example, the encapsulation dam 106 may have a closed loop shape surrounding a portion of the device substrate 100. The flow of the second encapsulation layer 720 having relatively high fluidity may be blocked by the encapsulation dam 106. For example, the second encapsulation layer 720 may be disposed only on a portion of the device substrate 100 defined by the encapsulation dam 106. The third encapsulation layer 730 may be in direct contact with the first encapsulation layer 710 on the outside of the second encapsulation layer 720. For example, second encapsulation layer 720 may be surrounded by first encapsulation layer 710 and third encapsulation layer 730. First encapsulation layer 710 may extend beyond third encapsulation layer 730. For example, encapsulation dam 106 may be covered by first encapsulation layer 710.

[0075] Touch structures 810 and 820 may be disposed on package element 700. Touch structures 810 and 820 may detect touches of a user and / or a tool. For example, touch structures 810 and 820 may include touch electrodes 811 and 821 and bridge electrodes 812 and 822. Touch electrodes 811 and 821 may be disposed side by side. Bridge electrodes 812 and 822 may be connected between touch electrodes 811 and 821. Touch electrodes 811 and 821 and bridge electrodes 812 and 822 may include conductive materials. For example, touch electrodes 811 and 821 and bridge electrodes 812 and 822 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). Touch electrodes 811 and 821 and bridge electrodes 812 and 822 may overlap with display area AA of device substrate 100. The light emitting device 600 of each pixel area PA may be disposed outside the touch electrodes 811 and 821 and the bridging electrodes 812 and 822. For example, the touch electrodes 811 and 821 and the bridging electrodes 812 and 822 may overlap the bank insulating layer 180. The touch electrodes 811 and 821 and the bridging electrodes 812 and 822 may be separated from the light emitting device 600 of each pixel area PA. Therefore, in the display device according to the embodiment of the present invention, light emitted from each light emitting device 600 in a direction perpendicular to the upper surface of the device substrate 100 is not blocked by the touch electrodes 811 and 821 and the bridging electrodes 812 and 822. Therefore, in the display device according to the embodiment of the present invention, a reduction in the brightness of each pixel area PA due to the touch electrodes 811 and 821 and the bridging electrodes 812 and 822 may be prevented.

[0076] The touch structures 810 and 820 may include a first touch component 810 extending in a first direction, and a second touch component 820 extending in a second direction perpendicular to the first direction. Each first touch component 810 may include a first touch electrode 811 and a first bridge electrode 812. For example, each first bridge electrode 812 may connect the first touch electrode 811 in the first direction. Each second touch component 820 may include a second touch electrode 821 and a second bridge electrode 822. For example, each second bridge electrode 822 may connect the second touch electrode 821 in the second direction. The second touch electrode 821 may be disposed between the first touch electrodes 811. Each second bridge electrode 822 may intersect with one first bridge electrode 812. The second bridge electrode 822 may be insulated from the first bridge electrode 812. For example, the second bridge electrode 822 may be disposed on a layer different from the first bridge electrode 812. The touch insulating layer 830 may be disposed between the first bridge electrode 812 and the second bridge electrode 822. The touch insulating layer 830 may include an insulating material. For example, the touch insulating layer 830 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The second touch electrode 821 may be provided on the same layer as the first touch electrode 811. For example, the first touch electrode 811, the second touch electrode 821, and the second bridge electrode 822 may be provided on the touch insulating layer 830 covering the first bridge electrode 812. The touch insulating layer 830 may include a touch contact hole partially exposing each first bridge electrode 812. Each first touch electrode 811 may be connected to the corresponding first bridge electrode 812 via one of the touch contact holes.

[0077] The outermost touch electrodes 811 and 821 disposed in each touch assembly 810 and 820 may be connected to one of the link lines 850. The link line 850 may extend beyond the display area AA along the surface of the package element 700. The link line 850 may include a conductive material. For example, the link line 850 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The link line 850 may include the same material as the touch electrodes 811 and 821. For example, the link line 850 may be formed by the same process as the touch electrodes 811 and 821. The link line 850 may be disposed on the same layer as the touch electrodes 811 and 821. For example, the link line 850 may include an area disposed on the touch insulating layer 830. Each link line 850 may be in direct contact with one of the touch electrodes 811 and 821.

[0078] The touch buffer layer 800 may be disposed between the package element 700 and the touch structures 810 and 820. The touch buffer layer 800 may prevent damage to the package element 700 and the light emitting device 600 due to the process of forming the touch electrodes 811 and 821 and the bridge electrodes 812 and 822. For example, the surface of the package element 700 facing the touch structures 810 and 820 may be completely covered by the touch buffer layer 800. The touch buffer layer 800 may extend along the third package layer 730. For example, the touch buffer layer 800 may extend beyond the package dam 106. The touch buffer layer 800 may include an insulating material. For example, the touch buffer layer 800 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN).

[0079] The covering insulating layer 890 may be disposed on the touch structures 810 and 820. The covering insulating layer 890 may prevent the touch structures 810 and 820 from being damaged due to external impact and moisture. For example, the touch structures 810 and 820 may be completely covered by the covering insulating layer 890. Therefore, in the display device according to the embodiment of the present invention, the external impact may be mitigated by the covering insulating layer 890. The covering insulating layer 890 may include an insulating material. For example, the covering insulating layer 890 may include an inorganic insulating material and / or an organic insulating material. The covering insulating layer 890 may extend beyond the touch structures 810 and 820. For example, the covering insulating layer 890 may include an area overlapping with the light emitting device 600. The covering insulating layer 890 may extend beyond the display area AA. For example, the encapsulation dam 106 may be covered by the covering insulating layer 890.

[0080] The bending area BA may be an area where the device substrate 100 is bent. The bending area BA may have a relatively thin thickness. For example, the device buffer layer 110, the first gate insulating layer 212, the first interlayer insulating layer 214, the first lower passivation layer 120, the second lower passivation layer 130, the separation insulating layer 140, the second interlayer insulating layer 224, and the third lower passivation layer 150 may expose the bending area BA of the device substrate 100. For example, the bending area BA of the device substrate 100 may be in direct contact with the first overcoat layer 160.

[0081] The crack prevention layer 410 may be disposed on the first overcoat 160 of the bending area BA. The crack prevention layer 410 may prevent the device substrate 100 from being damaged due to external impact. For example, the crack prevention layer 410 may include an area overlapping the bending area BA and an area disposed outside the bending area BA. The crack prevention layer 410 may include an insulating material. For example, the crack prevention layer 410 may include an organic insulating material. The crack prevention layer 410 may include the same material as the second overcoat 170. For example, the crack prevention layer 410 may be formed by the same process as the second overcoat 170. Therefore, in the display device according to the embodiment of the present invention, the process efficiency may be improved. The crack prevention layer 410 may be separated from the encapsulation element 700. The encapsulation dam 106 may be disposed between the encapsulation element 700 and the crack prevention layer 410. For example, the encapsulation dam 106 may be separated from the crack prevention layer 410. Therefore, in the display device according to the embodiment of the present invention, the damage of the crack prevention layer 410 due to the bending stress does not affect the display area AA.

[0082] The pads 104 and 804 may be arranged on the pad region PD. The pads 104 and 804 may be arranged side by side in the first direction. The pads 104 and 804 may include a display pad 104 electrically connected to the signal lines GL, DL, VDD, and VSS and a touch pad 804 electrically connected to the touch structures 810 and 820. The pad region PD may be connected to the display region AA through the connecting electrode 900. For example, each display pad 104 may be connected to one of the signal lines GL, DL, VDD, and VSS through one of the connecting electrodes 900, and each touch component 810 and 820 may be connected to one of the touch pads 804 through one of the connecting electrodes 900 and one of the link lines 850.

[0083] The pad area PD may be disposed on one side of the display area AA. For example, the pad area PD may be disposed side by side with the display area AA in the second direction. The bending area BA may be disposed between the display area AA and the pad area PD. For example, the connection electrode 900 may span the bending area BA. The connection electrode 900 may be disposed on the first overcoat 160. For example, the first overcoat 160 may extend on the pad area PD.

[0084] Each connection electrode 900 may have a multilayer structure. For example, each connection electrode 900 may have a stacked structure of a lower connection electrode 910 and an upper connection electrode 920. The lower connection electrode 910 may be disposed between the device substrate 100 and the upper connection electrode 920. For example, the upper connection electrode 920 may include an area overlapping with the lower connection electrode 910. The lower connection electrode 910 and the upper connection electrode 920 may include a conductive material. For example, the lower connection electrode 910 and the upper connection electrode 920 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo) and tungsten (W). Therefore, in a display device according to an embodiment of the present invention, disconnection of each connection electrode 900 due to bending stress and external impact may be prevented.

[0085] The lower connection electrode 910 may be disposed between the first overcoat layer 160 and the crack prevention layer 410. For example, the first overcoat layer 160 may extend between the bending area BA of the device substrate 100 and the lower connection electrode 910. The lower connection electrode 910 may include the same material as the intermediate contact electrode 510. For example, the lower connection electrode 910 may be formed by the same process as the intermediate contact electrode 510.

[0086] The upper connection electrode 920 may be disposed on the crack prevention layer 410. The upper connection electrode 920 may include the same material as the touch electrodes 811 and 821, which are the uppermost conductive layers disposed in each pixel area PA. For example, the touch buffer layer 800 may extend between the crack prevention layer 410 and the upper connection electrode 920. The upper connection electrode 920 may be in direct contact with one of the link lines 850. For example, the touch electrodes 811 and 821, the link line 850, and the upper connection electrode 920 of each connection electrode 900 may be formed simultaneously. Therefore, in the display device according to the embodiment of the present invention, damage to the upper connection electrode 920 due to the process of patterning the conductive layer can be prevented. In addition, in the display device according to the embodiment of the present invention, accidental connection between adjacent upper connection electrodes 920 due to a conductive residual layer generated by a subsequent process can be prevented. Therefore, in the display device according to the embodiment of the present invention, the display area AA can be stably connected to the pad area PD.

[0087] The upper connection electrode 920 may be connected to the lower connection electrode 910. For example, the intermediate connection electrode 930 may be disposed between the lower connection electrode 910 and the upper connection electrode 920 of each connection electrode 900. The intermediate connection electrode 930 may include a conductive material. For example, the intermediate connection electrode 930 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The intermediate connection electrode 930 may penetrate the anti-crack layer 410. For example, the anti-crack layer 410 may include a connection contact hole partially exposing the lower connection electrode 910 of each connection electrode 900, and the intermediate connection electrode 930 of each connection electrode 900 may include a region disposed in one of the connection holes. The intermediate connection electrode 930 may include the same material as the first light emitting electrode 610 of each light emitting device 600. For example, the touch buffer layer 800 on the bending area BA may partially expose each intermediate connection electrode 930, and the upper connection electrode 920 of each connection electrode 900 may be in direct contact with the area of ​​the corresponding intermediate connection electrode 930 exposed by the touch buffer layer 800. The connection contact hole may be provided outside the bending area BA. For example, the intermediate connection electrode 930 of each connection electrode 900 may penetrate the anti-crack layer 410 outside the bending area BA. Therefore, in the display device according to the embodiment of the present invention, deformation and damage of the intermediate connection electrode 930 due to bending stress and external impact may be prevented. Therefore, in the display device according to the embodiment of the present invention, the display area AA may be stably connected to the pad area PD.

[0088] The hole peripheral area HA may be disposed between the pixel areas PA. The hole peripheral area HA may be disposed in the display area AA. The hole peripheral area HA may include a hole area CA in which the substrate hole CH is disposed and a separation area SA surrounding the hole area CA. The substrate hole CH may penetrate the device substrate 100. At least one separation device 300 may be disposed on the separation area SA. For example, the substrate hole CH may be disposed between the light emitting devices 600, and the separation device 300 may be disposed between the light emitting device 600 and the substrate hole CH. The separation device 300 may partially separate the light emitting layer 620 and the second light emitting electrode 630 of each light emitting device 600. For example, the separation device 300 may include at least one undercut structure UC. Therefore, the display device according to the embodiment of the present invention can prevent moisture introduced through the substrate hole CH from penetrating into the pixel area PA. The separation device 300 may be formed by a process of forming a driving circuit and a light emitting device 600 of each pixel area PA. For example, the separation device 300 may have a stacked structure of a device buffer layer 110, a first gate insulating layer 212, a first interlayer insulating layer 214, a first lower passivation layer 120, a second lower passivation layer 130, a separation insulating layer 140, a second interlayer insulating layer 224, and a third lower passivation layer 150. The separation device 300 may further include a separation cover 420 on the third lower passivation layer 150. The separation cover 420 may include the same material as the second overcoat 170. For example, the separation cover 420 may be formed simultaneously with the second overcoat 170. The separation device 300 may be separated from the driving circuit and the light emitting device 600 of each pixel area PA. Therefore, in the display device according to the embodiment of the present invention, the penetration of moisture through the separation device 300 may be prevented.

[0089] The device substrate 100 may include a gate driver region GIP. The gate driver may be disposed on the gate driver region GIP. The gate driver region GIP may be separated from the display region AA, the bending region BA, and the pad region PD. For example, the gate driver region GIP may be disposed side by side with the display region AA in the first direction. The gate driver region GIP may be electrically connected to the display region AA through a gate line (GL). For example, the gate driver may apply a gate signal to each pixel region PA of the display region AA. The gate driver may include at least one third thin film transistor 250. The third thin film transistor 250 on the gate driver region GIP may have the same structure as the first thin film transistor 210 and the second thin film transistor 220 of each pixel region PA. For example, the third thin film transistor 250 may include a third semiconductor pattern 251, a third gate insulating layer 252, a third gate electrode 253, a third interlayer insulating layer 254, a third source electrode 255, and a third drain electrode 256. The third thin film transistor 250 may be formed simultaneously with the driving circuit of each pixel region PA. For example, the third semiconductor pattern 251, the third gate insulating layer 252, the third gate electrode 253, and the third interlayer insulating layer 254 of the third thin film transistor 250 may be formed by the process of forming the first semiconductor pattern 211, the first gate insulating layer 212, the first gate electrode 213, and the first interlayer insulating layer 214 of each pixel area PA. The third semiconductor pattern 251 of the third thin film transistor 250 may include the same material as the first semiconductor pattern 211 of each pixel area PA. For example, the third semiconductor pattern 251 of the third thin film transistor 250 may include LTPS. The third gate insulating layer 252 of the third thin film transistor 250 may include the same material as the first gate insulating layer 212 of each pixel area PA. The third gate electrode 253 of the third thin film transistor 250 may include the same material as the first gate electrode 213 of each pixel area PA. The third interlayer insulating layer 254 of the third thin film transistor 250 may include the same material as the first interlayer insulating layer 214 of each pixel area PA. The third source electrode 255 and the third drain electrode 256 of the third thin film transistor 250 may be formed by a process different from the first source electrode 215 and the first drain electrode 216 of each pixel area PA. For example, the third source electrode 255 and the third drain electrode 256 of the third thin film transistor 250 may be formed by the same process as the middle source electrode 265 and the middle drain electrode 266 of each pixel area PA. The first lower passivation layer 120, the second lower passivation layer 130, the separation insulating layer 140, the second interlayer insulating layer 224, and the third lower passivation layer 150 of each pixel area PA may extend between the third interlayer insulating layer 254 and the third source electrode 255 and between the third interlayer insulating layer 254 and the third drain electrode 256.The first overcoat layer 160, the second overcoat layer 170, and the bank insulating layer 180 may extend on the third thin film transistor 250. Therefore, in the display device according to the embodiment of the present invention, process efficiency may be improved.

[0090] Figures 4A to 17A , Figure 4B-Figure 17B and Figure 4C-Figure 17C are views sequentially illustrating a method of forming a display device according to an embodiment of the present invention.

[0091] Will refer to Figure 1 , Figures 3A to 17A , Figure 3B-Figure 17B and Figure 3C-Figure 17C A method for forming a display device according to an embodiment of the present invention is described. First, as FIG. 4A to FIG. 4C As shown, the method for forming a display device according to an embodiment of the present invention may include: preparing a device substrate 100 including a pixel area PA, a gate driver area GIP, a hole peripheral area HA, a bending area BA and a pad area PD; forming a device buffer layer 110 on the device substrate 100; forming a third semiconductor pattern 251, a third gate insulating layer 252, a third gate electrode 253 and a third interlayer insulating layer 254 on the gate driver area GIP of the device buffer layer 110; forming a first thin film on the pixel area PA of the device buffer layer 110; The device substrate 100 includes a first thin film transistor 210 and a storage capacitor 230; a step of stacking a first lower passivation layer 120, a second lower passivation layer 130 and a separation insulating layer 140 on the device substrate 100 on which the first thin film transistor 210, the storage capacitor 230 and the third interlayer insulating layer 254 are formed; a step of forming a second semiconductor pattern 221, a second gate insulating layer 222 and a second gate electrode 223 on the separation insulating layer 140 of the pixel area PA; and a step of stacking a second interlayer insulating layer 224 and a third lower passivation layer 150 on the device substrate 100 on which the second gate electrode 223 is formed.

[0092] The hole peripheral area HA may include a hole area CA in which the substrate hole CH is formed by a subsequent process and a separation area SA disposed outside the hole area CA.

[0093] The device substrate 100 may be formed into a multi-layer structure. For example, the step of preparing the device substrate 100 may include the step of sequentially stacking a substrate insulating layer 102 and a second substrate layer 103 on a first substrate layer 101 .

[0094] The device buffer layer 110 may be formed as a multilayer structure. For example, the step of forming the device buffer layer 110 may include: a step of forming a first buffer layer 111 on the device substrate 100; and a step of forming a second buffer layer 112 on the first buffer layer 111. The second buffer layer 112 may be formed of a material different from the first buffer layer 111. The device buffer layer 110 may be formed on the entire surface of the device substrate 100. For example, the pixel area PA, the gate driver area GIP, the hole peripheral area HA, the bending area BA, and the pad area PD of the device substrate 100 may be covered by the device buffer layer 110.

[0095] The step of forming the first thin film transistor 210 may include: the step of forming the first semiconductor pattern 211 on the device buffer layer 110; the step of forming the first gate insulating layer 212 covering the first semiconductor pattern 211; the step of forming the first gate electrode 213 on the first gate insulating layer 212; the step of forming the first interlayer insulating layer 214 covering the first gate electrode 213; and the step of forming the first source electrode 215 and the first drain electrode 216 on the first interlayer insulating layer 214. The storage capacitor 230 may be formed as a stacked structure of the first storage electrode 231 and the second storage electrode 232. The storage capacitor 230 may be formed simultaneously with the first thin film transistor 210. For example, the step of forming the first thin film transistor 210 and the storage capacitor 230 may include: the step of forming the first gate electrode 213 and the first storage electrode 231 on the first gate insulating layer 212; and the step of forming the first source electrode 215, the first drain electrode 216, and the second storage electrode 232 on the first interlayer insulating layer 214.

[0096] The third semiconductor pattern 251, the third gate insulating layer 252, the third gate electrode 253, and the third interlayer insulating layer 254 may be formed by using the process of forming the first thin film transistor 210. For example, the third semiconductor pattern 251, the third gate insulating layer 252, the third gate electrode 253, and the third interlayer insulating layer 254 may be formed simultaneously with the first semiconductor pattern 211, the first gate insulating layer 212, the first gate electrode 213, and the first interlayer insulating layer 214, respectively. For example, the third semiconductor pattern 251 may include the same material as the first semiconductor pattern 211. The first gate insulating layer 212 and the first interlayer insulating layer 214 may be stacked on the hole peripheral area HA, the bending area BA, and the pad area PD of the device substrate 100.

[0097] The second gate insulating layer 222 may expose the second source region and the second drain region of the second semiconductor pattern 221 through a patterning process. The second source region and the second drain region of the second semiconductor pattern 221 may be conductive through a process of patterning the second gate insulating layer 222. For example, the second source region and the second drain region of the second semiconductor pattern 221 may be in direct contact with an etchant used in a process of patterning the second gate insulating layer 222.

[0098] like FIG. 5A to FIG. 5C As shown, the method of forming the display device according to the embodiment of the present invention may include the step of forming a second source contact hole and a second drain contact hole by patterning the second interlayer insulating layer 224 and the third lower passivation layer 150 .

[0099] The second source contact hole may partially expose the second source region of the second semiconductor pattern 221 in the pixel area PA. The second drain contact hole may partially expose the second drain region of the second semiconductor pattern 221 in the pixel area PA. The second interlayer insulating layer 224 and the third lower passivation layer 150 on the bending area BA and the pad area PD of the device substrate 100 may be removed by the process of forming the second source contact hole and the second drain contact hole. For example, the step of forming the second source contact hole and the second drain contact hole may include the step of exposing the separation insulating layer 140 on the bending area BA and the pad area PD of the device substrate 100.

[0100] like FIG. 6A to FIG. 6C As shown, a method for forming a display device according to an embodiment of the present invention may include: forming a first middle contact hole, a second middle contact hole, a storage contact hole, a third source contact hole and a third drain contact hole by patterning a third interlayer insulating layer 254, a first lower passivation layer 120, a second lower passivation layer 130, a separation insulating layer 140, a second interlayer insulating layer 224 and a third lower passivation layer 150.

[0101] The first intermediate contact hole may partially expose the first source electrode 215. The second intermediate contact hole may partially expose the first drain electrode 216. The storage contact hole may partially expose the first storage electrode 231. The third source contact hole may partially expose the third source region of the third semiconductor pattern 251. The third drain contact hole may partially expose the third drain region of the third semiconductor pattern 251. For example, the first intermediate contact hole, the second intermediate contact hole, the storage contact hole, the third source contact hole, and the third drain contact hole may be formed simultaneously.

[0102] like 7A to 7CAs shown, a method for forming a display device according to an embodiment of the present invention may include: forming an intermediate source electrode 265, an intermediate drain electrode 266, a second source electrode 225, a second drain electrode 226, a third source electrode 255 and a third drain electrode 256 on a device substrate 100 having a first intermediate contact hole, a second intermediate contact hole, a storage contact hole, a third source contact hole and a third drain contact hole.

[0103] The intermediate source electrode 265 may be connected to the first source electrode 215 via the first intermediate contact hole. The intermediate drain electrode 266 may be connected to the first drain electrode 216 via the second intermediate contact hole. The second source electrode 225 may be connected to the second source region of the second semiconductor pattern 221 via the second source contact hole. The second drain electrode 226 may be connected to the second drain region of the second semiconductor pattern 221 via the second drain contact hole, and to the first storage electrode 231 via the storage contact hole. The third source electrode 255 may be connected to the third source region of the third semiconductor pattern 251 via the third source contact hole. The third drain electrode 256 may be connected to the third drain region of the third semiconductor pattern 251 via the third drain contact hole. The intermediate source electrode 265, the intermediate drain electrode 266, the second source electrode 225, the second drain electrode 226, the third source electrode 255, and the third drain electrode 256 may be formed simultaneously. For example, the steps of forming the intermediate source electrode 265, the intermediate drain electrode 266, the second source electrode 225, the second drain electrode 226, the third source electrode 255 and the third drain electrode 256 may include: the steps of forming a conductive layer on the device substrate 100 on which the first intermediate contact hole, the second intermediate contact hole, the storage contact hole, the third source contact hole and the third drain contact hole are formed; and the steps of patterning the conductive layer by using a mask pattern.

[0104] like FIG. 8A to FIG. 8C As shown, a method for forming a display device according to an embodiment of the present invention may include: a step of forming at least one separation device 300 on a separation area SA of a device substrate 100 on which an intermediate source electrode 265, an intermediate drain electrode 266, a second source electrode 225, a second drain electrode 226, a third source electrode 255 and a third drain electrode 256 are formed.

[0105] The step of forming the separation device 300 may include: patterning the device buffer layer 110, the first gate insulating layer 212, the first interlayer insulating layer 214, the first lower passivation layer 120, the second lower passivation layer 130, the separation insulating layer 140, the second interlayer insulating layer 224, and the third lower passivation layer 150 stacked on the separation area SA of the device substrate 100. The device buffer layer 110, the first gate insulating layer 212, the first interlayer insulating layer 214, the first lower passivation layer 120, the second lower passivation layer 130, the separation insulating layer 140, the second interlayer insulating layer 224, and the third lower passivation layer 150 on the hole area CA, the bending area BA, and the pad area PD of the device substrate 100 may be removed by the process of forming the separation device 300. For example, the step of forming the separation device 300 may include: exposing the hole area CA, the bending area BA, and the pad area PD of the device substrate 100. A side of the separation device 300 disposed closest to the hole area CA may have a relatively gentle slope.

[0106] like 9A to 9C As shown, the method of forming a display device according to an embodiment of the present invention may include: a step of forming a first overcoat 160 on a pixel area PA, a gate driver area GIP, a bending area BA, and a pad area PD of a device substrate 100 on which a separation device 300 is formed; and a step of forming a first electrode contact hole in the first overcoat 160.

[0107] The bending area BA and the pad area PD of the device substrate 100 may be in direct contact with the first overcoat 160. The first electrode contact hole may partially expose the intermediate drain electrode 266 of the pixel area PA. The first overcoat 160 may not be formed on the separation device 300. For example, the step of forming the first electrode contact hole may include the step of removing the first overcoat 160 on the hole peripheral area HA of the device substrate 100.

[0108] like FIG. 10A to FIG. 10C As shown, the method of forming the display device according to the embodiment of the present invention may include the steps of forming the intermediate contact electrode 510 and the lower connection electrode 910 on the device substrate 100 having the first electrode contact hole formed therein.

[0109] The intermediate contact electrode 510 may be formed on the pixel area PA. The intermediate contact electrode 510 may be connected to the intermediate drain electrode 266 via the first electrode contact hole. The lower connection electrode 910 may include an area overlapping the bending area BA. For example, the lower connection electrode 910 may span the bending area BA. The lower connection electrode 910 may be formed simultaneously with the intermediate contact electrode 510. For example, the steps of forming the intermediate contact electrode 510 and the lower connection electrode 910 may include: a step of forming a conductive layer on the device substrate 100 having the first electrode contact hole formed therein; and a step of patterning the conductive layer.

[0110] like FIG. 11A to FIG. 11C As shown, the method of forming a display device according to an embodiment of the present invention may include the steps of forming a second overcoat layer 170 , an encapsulation dam 106 , a crack prevention layer 410 and a separation cover 420 on a device substrate 100 having intermediate contact electrodes 510 and lower connection electrodes 910 formed thereon.

[0111] The second overcoat 170 may include a second electrode contact hole partially exposing the intermediate contact electrode 510. The crack prevention layer 410 may include a connection contact hole exposing a portion of the lower connection electrode 910. The crack prevention layer 410 may be separated from the encapsulation dam 106. The separation cover 420 may be formed on the separation area SA. For example, the separation cover 420 may constitute a separation device 300. The separation device 300 may be separated from the second overcoat 170, the encapsulation dam 106, and the crack prevention layer 410. The second overcoat 170, the encapsulation dam 106, the crack prevention layer 410, and the separation cover 420 may be formed simultaneously. For example, the steps of forming the second overcoat 170, the encapsulation dam 106, the crack prevention layer 410, and the separation cover 420 may include: a step of forming an organic insulating material layer on the device substrate 100 on which the intermediate contact electrode 510 and the lower connection electrode 910 are formed; and a step of patterning the organic insulating material layer by using a mask pattern.

[0112] like FIG. 12A to FIG. 12C As shown, the method for forming a display device according to an embodiment of the present invention may include: forming a light-emitting electrode layer 610a on a pixel area PA, a bending area BA and a pad area PD of a device substrate 100 on which a second overcoat 170, an encapsulation dam 106, an anti-crack layer 410 and a separation cover 420 are formed.

[0113] The light emitting electrode layer 610a may not be formed on the hole peripheral area HA of the device substrate 100. For example, the step of forming the light emitting electrode layer 610a may include: a step of forming a conductive layer on the device substrate 100 formed with the second overcoat layer 170, the encapsulation dam 106, the crack prevention layer 410, and the separation cover 420; and a step of removing the light emitting electrode layer 610a on the hole peripheral area HA of the device substrate 100. The conductive residual layer on the hole peripheral area HA of the device substrate 100 left in the process of forming the intermediate contact electrode 510 and the lower connection electrode 910 may be removed by the process of forming the light emitting electrode layer 610a.

[0114] The light emitting electrode layer 610a may include a first electrode region 611 and a second electrode region 612 thinner than the first electrode region 611. The first electrode region 611 may overlap with the first light emitting electrode 610 and the intermediate connection electrode 930 formed by subsequent processes. For example, the second electrode contact hole and the connection contact hole may be filled with the first electrode region 611.

[0115] like FIG. 13A to FIG. 13C As shown, the method of forming the display device according to the embodiment of the present invention may include: forming at least one undercut structure UC in the separation device 300 .

[0116] The step of forming the undercut structure UC of the separation device 300 may include the step of partially etching some of the device buffer layer 110, the first gate insulating layer 212, the first interlayer insulating layer 214, the first lower passivation layer 120, the second lower passivation layer 130, the separation insulating layer 140, the second interlayer insulating layer 224, and the third lower passivation layer 150 constituting the separation device 300 (using its etching selectivity). For example, the step of forming the undercut structure UC of the separation device 300 may include the step of etching the edges of the second lower passivation layer 130 and the third lower passivation layer 150 formed of silicon nitride (SiN). The step of forming the undercut structure UC of the separation device 300 may be performed by using the light emitting electrode layer 610a as a mask pattern. Therefore, in the method of forming the display device according to the embodiment of the present invention, the undercut structure UC of the separation device 300 may be formed without affecting the pixel area PA, the bending area BA, and the pad area PD of the device substrate 100. Therefore, in the method of forming the display device according to the embodiment of the present invention, the process efficiency can be improved.

[0117] like FIG. 14A to FIG. 14C As shown, the method of forming the display device according to the embodiment of the present invention may include the steps of forming a first light emitting electrode 610 and an intermediate connection electrode 930 on a device substrate 100 .

[0118] The first light emitting electrode 610 may be formed on the pixel area PA of the device substrate 100. The intermediate connection electrode 930 may include an area in the connection contact hole that penetrates the crack prevention layer 410. For example, the steps of forming the first light emitting electrode 610 and the intermediate connection electrode 930 may include the step of removing the second electrode region 612 of the light emitting electrode layer 610a. Therefore, in the method of forming the display device according to the embodiment of the present invention, the first light emitting electrode 610 and the intermediate connection electrode 930 may be formed without forming a new mask pattern.

[0119] like FIG. 15A to FIG. 15C As shown, the method of forming the display device according to the embodiment of the present invention may include the step of forming a light emitting device 600 on the pixel area PA of the device substrate 100 .

[0120] The step of forming the light emitting device 600 may include: forming a bank insulating layer 180 covering the edge of the first light emitting electrode 610; and stacking a light emitting layer 620 and a second light emitting electrode 630 on a portion of the first light emitting electrode 610 exposed by the bank insulating layer 180. The light emitting layer 620 and the second light emitting electrode 630 may not be formed on the hole area CA, the bending area BA, and the pad area PD of the device substrate 100. For example, the step of forming the light emitting layer 620 and the second light emitting electrode 630 may include: exposing the hole area CA, the bending area BA, and the pad area PD of the device substrate 100. In the separation area SA of the device substrate 100, the light emitting layer 620 and the second light emitting electrode 630 may be partially separated by the separation device 300 having the undercut structure UC.

[0121] like FIG. 16A to FIG. 16C As shown, the method for forming a display device according to an embodiment of the present invention may include: a step of forming a packaging element 700 covering the light-emitting device 600 on the pixel area PA; a step of forming a touch buffer layer 800 on the packaging element 700; and a step of partially exposing the intermediate connection electrode 930 by patterning the touch buffer layer 800.

[0122] The package element 700 may not be formed on the hole area CA, the bending area BA, and the pad area PD of the device substrate 100. The touch buffer layer 800 may not be formed on the hole area CA of the device substrate 100. For example, the step of partially exposing the intermediate connection electrode 930 may include the step of removing the package element 700 and the touch buffer layer 800 on the hole area CA of the device substrate 100.

[0123] like Figure 1 and FIG. 17A to FIG. 17C As shown, the method of forming the display device according to the embodiment of the present invention may include the steps of forming touch structures 810 and 820 , link lines 850 , and upper connection electrodes 920 on the device substrate 100 formed with the touch buffer layer 800 .

[0124] The touch structures 810 and 820 may include a first touch electrode 811, a first bridging electrode 812, a second touch electrode 821, and a second bridging electrode 822. The second bridging electrode 822 may be insulated from the first bridging electrode 812. For example, the steps of forming the touch structures 810 and 820 may include: a step of forming the first bridging electrode 812 on the touch buffer layer 800; a step of forming a touch insulating layer 830 covering the first bridging electrode 812; a step of forming a touch contact hole partially exposing the first bridging electrode 812; and a step of forming the first touch electrode 811 connected to the first bridging electrode 812, the second touch electrode 821 arranged side by side with the first touch electrode 811, and the second bridging electrode 822 having an area overlapping the first bridging electrode 812.

[0125] The touch insulating layer 830 may not be formed on the hole area CA, the bending area BA, and the pad area PD of the device substrate 100. For example, forming the touch insulating layer 830 may include exposing the hole area CA, the bending area BA, and the pad area PD of the device substrate 100.

[0126] The link line 850 may be in direct contact with the upper connection electrode 920. The touch electrodes 811 and 821, the link line 850, and the upper connection electrode 920 may be formed of the same material. For example, the steps of forming the touch electrodes 811 and 821, the link line 850, and the upper connection electrode 920 may include: forming a conductive layer on the device substrate 100 on which the touch insulation layer 830 is formed; and patterning the conductive layer.

[0127] The upper connection electrode 920 may be connected to a portion of the intermediate connection electrode 930 exposed by the touch buffer layer 800. The upper connection electrode 920 may span the bending area BA. For example, the upper connection electrode 920 may include an area overlapping the lower connection electrode 910. The lower connection electrode 910, the upper connection electrode 920, and the intermediate connection electrode 930 may constitute a connection electrode 900 that electrically connects the display area AA to the pad area PD across the bending area BA. Therefore, in the method of forming a display device according to an embodiment of the present invention, disconnection of the connection electrode 900 due to bending stress and external impact may be effectively prevented.

[0128] like Figure 1 and FIG. 3A to FIG. 3C As shown, a method for forming a display device according to an embodiment of the present invention may include: a step of forming a covering insulating layer 890 covering the touch structures 810 and 820, the link line 850 and the upper connecting electrode 920; a step of defining the pads 104 and 804 in the pad area PD by patterning the covering insulating layer 890; and a step of forming a substrate hole CH at the hole area CA of the device substrate 100.

[0129] Therefore, the display device and the forming method thereof according to the embodiment of the present invention may include a connection electrode 900 that connects the display area AA to the pad area PD across the bending area BA, wherein the connection electrode 900 may have a stacked structure of a lower connection electrode 910 and an upper connection electrode 920, and wherein the upper connection electrode 920 may be formed simultaneously with the touch electrodes 811 and 821 that are the uppermost conductive layer disposed in the pixel area PA. Therefore, in the display device and the forming method thereof according to the embodiment of the present invention, damage to the upper connection electrode 920 due to the process of patterning the conductive layer can be prevented. In addition, in the display device and the forming method thereof according to the embodiment of the present invention, accidental connection between adjacent upper connection electrodes 920 due to a conductive residual layer generated by a subsequent process can be prevented. In addition, in the display device and the forming method thereof according to the embodiment of the present invention, the conductive residual layer on the hole peripheral area HA can be removed by the process of forming the first light emitting electrode 610 and the intermediate connection electrode 930. Therefore, in the display device and the forming method thereof according to the embodiment of the present invention, disconnection of the connection electrode 900 due to bending stress and external impact can be prevented, and the display area AA can be stably connected to the pad area PD. Furthermore, in the display device and the method of forming the same according to the embodiments of the present invention, process efficiency can be improved.

[0130] As a result, the display device and the method for forming the same according to the embodiment of the present invention may include a connection electrode across the bending area, wherein the connection electrode may have a stacked structure of a lower connection electrode and an upper connection electrode, and the upper connection electrode may include the same material as the touch electrode on the package element covering the light-emitting device. Therefore, in the display device and the method for forming the same according to the embodiment of the present invention, the disconnection of the connection electrode due to bending stress and external impact can be prevented. Therefore, in the display device and the method for forming the same according to the embodiment of the present invention, the display area AA can be stably connected to the pad area PD through the connection electrode.

[0131] CROSS-REFERENCE TO RELATED APPLICATIONS

[0132] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0180184, filed on December 31, 2019, and Korean Patent Application No. 10-2020-0162230, filed on November 27, 2020, which are hereby incorporated by reference as if fully set forth herein.

Claims

1. A display device, comprising: A device substrate, the device substrate comprising a display area and a bending area; a first thin film transistor, the first thin film transistor comprising a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode in the display area; a second thin film transistor, the second thin film transistor comprising a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode in the display region, the second semiconductor pattern being disposed on a layer different from the first semiconductor pattern in the display region; A light emitting device, wherein the light emitting device is disposed on the display area of ​​the device substrate; a first overcoat layer, the first overcoat layer being disposed between the second thin film transistor and the light emitting device in the display area; a second outer covering layer, the second outer covering layer being disposed between the first outer covering layer and the light emitting device in the display area; a lower connecting electrode, the lower connecting electrode being arranged on the bending region on the device substrate, the lower connecting electrode spanning the bending region; A crack prevention layer, the crack prevention layer being on the lower connecting electrode in the bending region; and wherein the anti-cracking layer comprises the same material as the outer covering layer, The first overcoat layer is further disposed between the crack prevention layer and the device substrate in the bending region, and The lower connection electrode is disposed between the first overcoat layer and the crack prevention layer.

2. The display device according to claim 1, further comprising: a lower insulating layer disposed between the device substrate and the second semiconductor pattern; wherein the first semiconductor pattern and the first gate electrode are disposed between the device substrate and the lower insulating layer, and The second semiconductor pattern and the second gate electrode are disposed between the lower insulating layer and the first overcoat layer.

3. The display device according to claim 1, wherein: The first semiconductor pattern includes low temperature polysilicon (LTPS), and the second semiconductor pattern includes metal oxide.

4. The display device according to claim 1, wherein: The display area of ​​the device substrate includes a hole peripheral area including a substrate hole penetrating the device substrate.

5. The display device according to claim 1, further comprising: an intermediate contact electrode, the intermediate contact electrode being disposed between the first overcoat and the second overcoat in the display region; The intermediate contact electrode is electrically connected to the light emitting device and the first drain electrode of the first thin film transistor.

6. The display device according to claim 5, wherein: The lower connecting electrode includes the same material as the intermediate contact electrode.

7. The display device according to claim 1, further comprising: A packaging component, wherein the packaging component is disposed on the light emitting device; as well as A touch electrode, wherein the touch electrode is arranged on the packaging component in the display area; The touch electrode is electrically connected to the lower connection electrode through one of the link lines.

8. The display device according to claim 7, wherein: The crack prevention layer includes a connection contact hole exposing a portion of the lower connection electrode, and wherein the one of the link lines is electrically connected to the lower connection electrode through the connection contact hole.

9. The display device according to claim 7, further comprising: a covering insulating layer, wherein the covering insulating layer is arranged on the touch electrode in the display area; Wherein, the cover insulating layer is arranged on the anti-crack layer in the bending area.

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