Semiconductor device and electronic apparatus

Abstract

The invention improves the transconductance (gm) of the field effect transistor. A semiconductor device according to the present invention is provided with: an island-shaped semiconductor unit having an upper surface portion and a side surface portion; a field effect transistor including a gate electrode disposed on the semiconductor unit and a gate insulating film interposed therebetween; an insulating layer covering the field effect transistor; and a contact electrode disposed on the insulating layer so as to overlap the semiconductor cell outside the gate electrode when viewed in a plan view. The contact electrode is connected to an upper surface portion and a side surface portion of the semiconductor unit.

Description

Technical Field

[0001] The present technology (technology according to the present disclosure) relates to a semiconductor device and an electronic device, and particularly to a technology that is effective when applied to a semiconductor device having a fin field effect transistor and an electronic device including the semiconductor device. Background Art

[0002] As a semiconductor device, for example, a solid-state imaging device called a CMOS image sensor is known. The CMOS image sensor includes a pixel circuit (readout circuit) that converts a signal charge photoelectrically converted by a photoelectric conversion element into a pixel signal and outputs the pixel signal. The pixel circuit includes pixel transistors such as an amplification transistor, a selection transistor, and a reset transistor.

[0003] Meanwhile, as a field effect transistor mounted on a semiconductor device, a fin field effect transistor (Fin-FET) is known, in which a gate electrode is provided in an island-shaped semiconductor portion (fin portion), a gate insulating film is interposed therebetween, and a pair of main electrode regions serving as a source region and a drain region are provided in the semiconductor portion on both sides of the gate length direction of the gate electrode. Since such a fin field effect transistor can improve short channel characteristics and shorten the gate length to achieve necessary operations, it is possible to miniaturize the planar size and is useful for high integration.

[0004] The wiring on the insulating layer is electrically connected to the pair of main electrode regions of the fin field effect transistor via a contact electrode provided in the insulating layer and covering the field effect transistor. The contact electrode is connected to an upper surface portion of the semiconductor portion.

[0005] Patent Document 1 discloses a solid-state imaging device in which an amplifying transistor included in a pixel circuit is configured by a fin field-effect transistor.

[0006] Furthermore, Non-Patent Document 1 discloses a field effect transistor having an SOI-Fin structure.

[0007] Reference List

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2021-034435

[0010] Non-patent literature

[0011] Non-patent document 1: W.Xiong, et al., “Full / partial depletion effects in FinFETs”, IEEE International SOI Conference, 10 / 4, 2004 Summary of the invention

[0012] Problems to be solved by the present invention

[0013] By the way, as the fin field effect transistor is miniaturized, the width in the lateral direction of the semiconductor portion and the diameter (width of the thickness) of the contact electrode tend to decrease, and the contact resistance between the semiconductor portion and the contact electrode increases. In the production of miniaturizing the diameter (width) of the contact electrode, the influence of the contact resistance on the parasitic resistance increases, and the transconductance (gm) of the fin field effect transistor decreases.

[0014] The purpose of this technique is to improve the transconductance (gm) of a transistor.

[0015] Solution to the problem

[0016] A semiconductor device according to one aspect of the present technology includes:

[0017] a semiconductor portion having an island shape, the island shape having an upper surface portion and a side surface portion;

[0018] a field effect transistor having a gate electrode disposed on the semiconductor portion, with a gate insulating film interposed between the gate electrode and the semiconductor portion;

[0019] an insulating layer covering the field effect transistor; and

[0020] A contact electrode is provided on the insulating layer to overlap the semiconductor portion outside the gate electrode in a plan view. Then, the contact electrode is connected to an upper surface portion and a side surface portion of the semiconductor portion.

[0021] A semiconductor device according to another aspect of the present technology includes:

[0022] a semiconductor portion having an island shape, the island shape having an upper surface portion and a side surface portion;

[0023] a field effect transistor having a gate electrode disposed on the semiconductor portion, with a gate insulating film interposed between the gate electrode and the semiconductor portion;

[0024] an insulating layer covering the field effect transistor; and

[0025] A contact electrode is provided on the insulating layer to overlap the semiconductor portion outside the gate electrode in a plan view. Then, the contact electrode is connected to an upper surface portion and a side surface portion of the semiconductor portion and is formed in the same layer as the gate electrode.

[0026] An electronic device according to another aspect of the present technology includes: a semiconductor device; an optical system that forms an image of image light from a subject on the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 : is a schematic plan view showing a configuration example of a semiconductor device according to a first embodiment of the present technology.

[0028] Figure 2 It shows that along Figure 1 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a1 - a1 in FIG.

[0029] Figure 3 It shows that along Figure 1 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b1 - b1 in FIG.

[0030] Figure 4 is shown along Figure 1 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c1 - c1 in FIG.

[0031] Figure 5 Schematic plan views showing steps of a method for manufacturing a semiconductor device according to a first embodiment of the present technology.

[0032] Fig. 6A is shown along Figure 5 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a5-a5 in FIG.

[0033] Figure 6B is shown along Figure 5 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b5-b5 in FIG.

[0034] Figure 7 It shows Figure 5 Schematic plan view of the following steps.

[0035] Fig. 8A is shown along Figure 7 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a7-a7 in FIG.

[0036] Figure 8B is shown along Figure 7 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b7-b7 in FIG.

[0037] Fig. 9 It shows Figure 7 Schematic plan view of the following steps.

[0038] Fig. 10A It is shown along Fig. 9 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a9-a9 in FIG.

[0039] Fig. 10B It is shown along Fig. 9 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b9-b9 in FIG.

[0040] Fig.11 It shows Fig. 9 Schematic plan view of the following steps.

[0041] Fig. 12A is shown along Fig.11 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a11 - a11 in FIG.

[0042] Fig. 12B It is shown along Fig.11 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c11-c11 in FIG.

[0043] Fig.13 It is shown Fig.11 Schematic plan view of the following steps.

[0044] Fig.14A It shows that along Fig.13 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a13 - a13 in FIG.

[0045] Fig. 14B It is shown along Fig.13 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c13-c13 in FIG.

[0046] Fig.15 It is shown Fig.13 Schematic plan view of the following steps.

[0047] Fig.16A It shows that along Fig.15 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a15-a15 in FIG.

[0048] Fig. 16B It is shown along Fig.15 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c15-c15 in FIG.

[0049] Fig.17 It is shown Fig.15 Schematic plan view of the following steps.

[0050] Fig.18Ais shown along Fig.17 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a17 - a17 in FIG.

[0051] Fig.18B It is shown along Fig.17 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c17-c17 in FIG.

[0052] Fig.19 It is shown Fig.17 Schematic plan view of the following steps.

[0053] Fig. 20A It is shown along Fig.19 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a19-a19 in FIG.

[0054] Fig. 20B It is shown along Fig.19 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c19-c19 in FIG.

[0055] Fig.21 It is shown Fig.19 Schematic plan view of the following steps.

[0056] Fig.22A is shown along Fig.21 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a21 - a21 in FIG.

[0057] Fig. 22B is shown along Fig.21 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c21 - c21 in FIG.

[0058] Fig.23 is a schematic plan view showing a schematic configuration of a semiconductor device according to a second embodiment of the present technology.

[0059] Fig.24 is shown along Fig.23 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a23 - a23 in FIG.

[0060] Fig.25 It shows that along Fig.23 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c23-c23 in FIG.

[0061] Fig.26 : is a schematic plan view showing two semiconductor portions and two field effect transistors arranged in series in the semiconductor device according to the first embodiment of the present technology.

[0062] Fig. 27 It is a schematic longitudinal sectional view showing a modification example of the second embodiment of the present technology.

[0063] Fig.28 is a schematic plan view showing a schematic configuration of a semiconductor device according to a third embodiment of the present technology.

[0064] Fig.29 It shows that along Fig.28 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c28-c28 in FIG.

[0065] Fig.30 It is a schematic plan view showing a first modification example of the third embodiment of the present technology.

[0066] Fig.31 It is a schematic plan view showing a second modification example of the third embodiment of the present technology.

[0067] Fig.32 It is a schematic cross-sectional view showing a third modification example of the third embodiment of the present technology.

[0068] Fig.33 is a schematic plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment of the present technology.

[0069] Fig.34 It shows that along Fig.33 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b33-b33 in FIG.

[0070] Fig.35 It shows that along Fig.33 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c33-c33 in FIG.

[0071] Fig.36 : is a schematic plan layout diagram showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology.

[0072] Fig.37 is a block diagram showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology.

[0073] Fig.38 : is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit of a solid-state imaging device according to a fifth embodiment of the present technology.

[0074] Fig.39 It shows Fig.36 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure of a pixel array unit in FIG.

[0075] Fig.40is a schematic plan view showing a configuration example of a semiconductor device according to a sixth embodiment of the present technology.

[0076] Fig.41 It shows that along Fig.40 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a40 - a40 in FIG.

[0077] Fig.41A It is shown in an enlarged manner Fig.41 Schematic longitudinal cross-sectional view of a portion of.

[0078] Fig.42 is shown along Fig.40 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b40 - b40 in FIG.

[0079] Fig.43 It shows that along Fig.40 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c40-c40 in FIG.

[0080] Fig.44 Schematic plan views showing steps of a method for manufacturing a semiconductor device according to a sixth embodiment of the present technology.

[0081] Fig.45A It is shown along Fig.44 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a44 - a44 in FIG.

[0082] Fig.45B It is shown along Fig.44 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b44-b44 in FIG.

[0083] Fig.46 It is shown Fig.44 Schematic plan view of the following steps.

[0084] Fig.47A It shows that along Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a46 - a46 in FIG.

[0085] Fig.47B It is shown along Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b46-b46 in FIG.

[0086] Fig.47C It shows that along Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c46-c46 in FIG.

[0087] Fig.48AIt is shown Fig.46 The following steps are shown in the figure. Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line A46-A46 in FIG.

[0088] Fig.48B It is shown Fig.46 The following steps are shown in the figure. Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line b46-b46 in FIG.

[0089] Fig.48C It is shown Fig.46 The following steps are shown in the figure. Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line c46-c46 in FIG.

[0090] Fig.49A It is shown Fig.48A The following steps are shown in the figure. Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a46-a46 in FIG.

[0091] Fig.49B It shows that Fig.48B The following steps are shown in the figure. Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line b46-b46 in FIG.

[0092] Fig.49C It is shown Fig.48C The following steps are shown in the figure. Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line c46-c46 in FIG.

[0093] Fig.50 It is shown Fig.49A Schematic plan view of the following steps.

[0094] Fig.51A is shown along Fig.50 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a50 - a50 in FIG.

[0095] Fig.51B It is shown along Fig.50 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b50 - b50 in FIG.

[0096] Fig.51C is shown along Fig.50A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c50-c50 in FIG.

[0097] Fig.51D It is enlarged Fig.51A Schematic longitudinal cross-sectional view of a portion of.

[0098] Fig.51E It is enlarged Fig.51C Schematic longitudinal cross-sectional view of a portion of.

[0099] Fig.52 It is shown Fig.50 Schematic plan view of the following steps.

[0100] Fig.53A It is shown along Fig.52 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a52 - a52 in FIG.

[0101] Fig.53B It is shown along Fig.52 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c52-c52 in FIG.

[0102] Fig.54A It is shown in Fig.53A Schematic cross-sectional view of a granular oxide modified by heat treatment in cross section.

[0103] Fig.54B It is shown in Fig.53B Schematic cross-sectional view of a granular oxide modified by heat treatment in cross section.

[0104] Fig.55 It is shown Fig.52 Schematic plan view of the following steps.

[0105] Fig.56A It is shown along Fig.55 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a55-a55 in FIG.

[0106] Fig.56B It is shown along Fig.55 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c55-c55 in FIG.

[0107] Fig.57 It is shown Fig.55 Schematic plan view of the following steps.

[0108] Fig.58A is shown along Fig.57 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a57-a57 in FIG.

[0109] Fig.58B It is shown along Fig.57 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c57-c57 in FIG.

[0110] Fig.59 It is shown Fig.57 Schematic plan view of the following steps.

[0111] Fig.60A is shown along Fig.59 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a59-a59 in FIG.

[0112] Fig.60B is shown along Fig.59 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b59-b59 in FIG.

[0113] Fig.60C is shown along Fig.59 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c59-c59 in FIG.

[0114] Fig.61 It is shown Fig.59 The following steps are shown in the figure. Fig.59 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a59-a59 in FIG.

[0115] Fig.62 It is shown Fig.61 The following steps are shown in the figure. Fig.59 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a59-a59 in FIG.

[0116] Fig.63 It is shown Fig.62 Schematic plan view of the following steps.

[0117] Fig.64 is shown along Fig.63 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a63-a63 in FIG.

[0118] Fig.65 It is shown Fig.63 The following steps are shown in the figure. Fig.63 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the cutting line a63-a63.

[0119] Fig.66 It is shown Fig.65 The following steps are shown in the figure. Fig.63A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the cutting line a63-a63.

[0120] Fig.67 It is shown Fig.66 The following steps are shown in the figure. Fig.63 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the cutting line a63-a63.

[0121] Fig.68 It is shown Fig.67 The following steps are shown in the figure. Fig.63 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the cutting line a63-a63.

[0122] Fig.69 It is a schematic plan view showing a first modification example of the sixth embodiment of the present technology.

[0123] Fig.70A It shows that along Fig.69 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a69-a69 in FIG.

[0124] Fig.70B It shows that along Fig.69 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c69-c69 in FIG.

[0125] Fig.71 It is a schematic plan view showing a second modification example of the sixth embodiment of the present technology.

[0126] Fig.72 is shown along Fig.71 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a71 - a71 in FIG.

[0127] Fig.73 : is a schematic longitudinal sectional view showing a third modification example of the sixth embodiment of the present technology.

[0128] Fig.74 is a schematic plan view showing a configuration example of a semiconductor device according to a seventh embodiment of the present technology.

[0129] Fig.75 is shown along Fig.74 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a74-a74 in FIG.

[0130] Fig.76 is a schematic plan view showing a configuration example of a semiconductor device according to an eighth embodiment of the present technology.

[0131] Fig.77 It is a schematic plan view showing a modified example of the eighth embodiment of the present technology.

[0132] Fig.78 : is a schematic longitudinal sectional view showing a configuration example of a solid-state imaging device according to a ninth embodiment of the present technology.

[0133] Fig.79 : is a schematic plan view showing a configuration example of a semiconductor device according to a tenth embodiment of the present technology.

[0134] Fig.80 is shown along Fig.79 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a79-a79 in FIG.

[0135] Fig.81 is shown along Fig.79 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b79-b79 in FIG.

[0136] Fig.82 is shown along Fig.79 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c79-c79 in FIG.

[0137] Fig.83 Schematic plan views showing steps of a method for manufacturing a semiconductor device according to a tenth embodiment of the present technology.

[0138] Fig.84 is a diagram showing steps of a method for manufacturing a semiconductor device according to a tenth embodiment of the present technology ((a) is a diagram showing steps along Fig.83 A schematic cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a83-a83 in FIG. 1 , (b) is a schematic cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a83-a83 in FIG. Fig.83 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b83-b83 in FIG. 1 , and (c) is a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b83-b83 in FIG. Fig.83 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c83-c83 in FIG. 1 ).

[0139] Fig.85 It is shown Fig.83 and Fig.84 The following steps are shown in Figure (a) Fig.83 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure with the cutting line a83-a83 in the same position, (b) is a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure with the cutting line a83-a83 in the same position, and (c) is a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure with the cutting line a83-a83 in the same position. Fig.83 (c) is a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure with the cutting line b83-b83 in the same position, and (d) is a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure with the cutting line b83-b83 in the same position, and (e) is a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure with the cutting line b83-b83 in the longitudinal cross-sectional structure Fig.83 (a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure with the cutting line c83-c83 in the same position).

[0140] Fig.86 It is shown Fig.85 Schematic plan view of the following steps.

[0141] Fig.87 It is shown Fig.86 A longitudinal cross-sectional structure diagram of the Fig.86 A schematic longitudinal section of the longitudinal section structure taken along the cutting line a86-a86 in FIG. 1, (b) is a diagram showing the longitudinal section structure along the cutting line a86-a86 in FIG. Fig.86 A schematic longitudinal section of the longitudinal section structure taken along the cutting line b86-b86 in FIG. 1 , and (c) is a schematic longitudinal section of the longitudinal section structure taken along the cutting line b86-b86 in FIG. Fig.86 Schematic longitudinal section of the longitudinal cross-sectional structure taken along the cutting line c86-c86 in FIG. 1 ).

[0142] Fig.88 It is shown Fig.86 Schematic plan view of the following steps.

[0143] Fig.89 It is shown Fig.88 The longitudinal cross-sectional structure of the diagram (a) is a diagram showing the longitudinal cross-sectional structure of the Fig.88 A schematic longitudinal section of the longitudinal section structure taken along the cutting line a88-a88 in FIG. 1 , and (b) is a schematic longitudinal section of the longitudinal section structure taken along the cutting line a88-a88 in FIG. Fig.88 Schematic longitudinal section of the longitudinal cross-sectional structure taken along the cutting line c88-c88 in FIG. 1 ).

[0144] Fig.90 It is shown Fig.88 Schematic plan view of the following steps.

[0145] Fig.91 It is shown Fig.90 A longitudinal cross-sectional structure diagram of the Fig.90 A schematic longitudinal section of the longitudinal section structure taken along the cutting line a90-a90 in FIG. 1 , and (b) is a schematic longitudinal section of the longitudinal section structure taken along the cutting line a90-a90 in FIG. Fig.90 Schematic longitudinal section of the longitudinal cross-sectional structure taken along the cutting line c90-c90 in FIG. 1 ).

[0146] Fig.92 It is shown Fig.90 Schematic plan view of the following steps.

[0147] Fig.93 It shows Fig.92 The longitudinal cross-sectional structure of FIG. 1 is shown in FIG. 1 , (a) is a diagram showing the longitudinal cross-sectional structure of FIG. Fig.92 A schematic longitudinal section of the longitudinal section structure taken along the cutting line a92-a92 in FIG. 1 , and (b) is a schematic longitudinal section of the longitudinal section structure taken along the cutting line a92-a92 in FIG. Fig.92 Schematic longitudinal section of the longitudinal cross-sectional structure taken along the cutting line c92-c92 in FIG. 1 ).

[0148] Fig.94 It is shown Fig.92 Schematic plan view of the following steps.

[0149] Fig.95 It is shown Fig.94 The longitudinal cross-sectional structure of FIG. 1 is shown in FIG. 1 , (a) is a diagram showing the longitudinal cross-sectional structure of FIG. Fig.94 A schematic longitudinal section of the longitudinal section structure taken along the cutting line a94-a94 in FIG. 1, (b) is a diagram showing the longitudinal section structure along the cutting line a94-a94 in FIG. Fig.94 A schematic longitudinal section of the longitudinal section structure taken along the cutting line b94-b94 in FIG. 1 , and (c) is a schematic longitudinal section of the longitudinal section structure taken along the cutting line b94-b94 in FIG. Fig.94 Schematic longitudinal section of the longitudinal cross-sectional structure taken along the cutting line c94-c94 in FIG.

[0150] Fig.96 It is shown Fig.94 The following steps are shown in the figure. Fig.94 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a94-a94 in FIG.

[0151] Fig.97 It is shown Fig.96 The following steps are shown in the figure. Fig.94 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a94-a94 in FIG.

[0152] Fig.98 It is shown Fig.97 Schematic plan view of the following steps.

[0153] Fig.99 is shown along Fig.98 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a98-a98 in FIG.

[0154] Fig.100 It is shown Fig.98 The following steps are shown in the figure. Fig.98 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a98-a98 in FIG.

[0155] Fig.101 It is shown Fig.100 The following steps are shown in the figure and are Fig.98 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a98-a98 in FIG.

[0156] Fig.102 It is shown Fig.101 The following steps are shown in the figure. Fig.98A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a98-a98 in FIG.

[0157] Fig.103 It is a diagram showing a configuration example of an electronic device according to the 106th embodiment of the present technology. DETAILED DESCRIPTION

[0158] Hereinafter, embodiments of the present technology will be described in detail with reference to the accompanying drawings.

[0159] In the description of the drawings referred to in the following description, the same or similar parts are marked with the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane size, the thickness ratio of each layer, etc. are different from the actual ones. Therefore, the specific thickness and size should be determined in consideration of the following description.

[0160] In addition, of course, the drawings also include portions having different dimensional relationships and ratios. In addition, the effects described in this specification are merely examples and are not limiting, and other effects may be provided.

[0161] In addition, the following embodiments illustrate devices and methods for embodying the technical concept of the present technology, and do not specify the following configurations. That is, various modifications can be made to the technical concept of the present technology within the technical scope described in the claims.

[0162] In addition, in the following description, the definition of directions such as the up and down directions is only for the convenience of description and does not limit the technical concept of the present technology. For example, it is a matter of course that when an object is observed by rotating the object by 90°, the upper side and the lower side are converted into the left side and the right side and read, and when the object is observed by rotating the object by 180°, the upper side and the lower side are reversed and read.

[0163] In addition, in the following embodiments, as the conductivity type of the semiconductor, the case where the first conductivity type is p-type and the second conductivity type is n-type will be described exemplarily, but the conductivity types can be selected in the opposite relationship, and the first conductivity type can be n-type and the second conductivity type can be p-type.

[0164] In addition, in the following embodiments, among the three directions orthogonal to each other in space, the first direction and the second direction orthogonal to each other in the same plane are defined as the X direction and the Y direction, respectively, and the third direction orthogonal to the first direction and the second direction is defined as the Z direction. Then, in the following embodiments, the thickness direction of the semiconductor parts 3 and 33 to be described later is described as the Z direction.

[0165] [First embodiment]

[0166] In the first embodiment, an example in which the present technology is applied to a semiconductor device having a fin field effect transistor will be described.

[0167] <<Structure of semiconductor device>>

[0168] First, refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 The overall configuration of the semiconductor device 1A is described. Figure 1 For the convenience of description, Figures 2 to 4 Schematic diagram of the wirings 18a, 18b, and 18c shown in FIG.

[0169] like Figures 1 to 4 As shown, the semiconductor device 1A according to the first embodiment of the present technology includes an island-shaped semiconductor portion 3 and a field effect transistor Qa, in which a channel forming portion (channel region) 12 is provided in the island-shaped semiconductor portion 3 .

[0170] In addition, if Figures 1 to 4 As shown, the semiconductor device 1A according to the first embodiment of the present technology also includes: an insulating layer 14 including a semiconductor portion 3 and a field effect transistor Qa; and contact electrodes 17a, 17b and 17c, which are arranged in the insulating layer 14 so as to overlap with the island-shaped semiconductor portion 3 in a plan view.

[0171] Here, in Figure 1 In the figure, the contact electrode 17c is omitted.

[0172] <Semiconductor Division>

[0173] like Figures 1 to 4 As shown, the semiconductor portion 3 is formed into a rectangular parallelepiped shape having, for example, an upper surface portion 3a, a lower surface portion (bottom surface portion) 3b and four side surface portions 3c1, 3c2, 3c3 and 3c4. Then, as an example, the semiconductor portion 3 extends in the Y direction, the thickness direction is the Z direction, the longitudinal direction is the Y direction, and the lateral direction is the X direction. The upper surface portion 3a and the lower surface portion 3b are located on opposite sides in the thickness direction (Z direction) of the semiconductor portion 3. Among the four side portions 3c1, 3c2, 3c3 and 3c4, two side portions 3c1 and 3c2 are positioned opposite to each other in the lateral direction (X direction), and the remaining two side portions 3c3 and 3c4 are positioned opposite to each other in the longitudinal direction (Y direction).

[0174] Here, in the first embodiment, the semiconductor portion 3 corresponds to a specific example of the "semiconductor portion" of the present technology. Then, the four side surface portions 3c1, 3c2, 3c3, and 3c4 of the semiconductor portion 3 correspond to a specific example of the "side surface portion of the semiconductor portion" of the present technology. Then, the four side portions 3c1, 3c2, 3c3, and 3c4 may be referred to as a first side portion 3c1, a second side portion 3c2, a third side portion 3c3, and a fourth side portion 3c4, respectively.

[0175] Furthermore, in the first embodiment, the lateral direction of the semiconductor portion 3 corresponds to a specific example of the “first direction of the semiconductor portion” of the present technology, and the longitudinal direction of the semiconductor portion 3 corresponds to a specific example of the “second direction of the semiconductor portion” of the present technology. Then, the side surfaces 3c3 and 3c4 in the longitudinal direction (second direction) of the semiconductor portion 3 correspond to a specific example of the “end portions in the second direction intersecting with the first direction of the semiconductor portion” of the present technology.

[0176] Although not limited thereto, the semiconductor portion 3 is composed of, for example, silicon (Si) as a semiconductor material (for example, as a crystalline single crystal) and, for example, i-type (intrinsic type) as a conductivity type. That is, the semiconductor portion 3 is composed of i-type single crystal silicon. In addition to Si, germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), etc. can also be used as the material of the semiconductor portion 3.

[0177] <Insulation layer>

[0178] like Figures 1 to 4 As shown, the insulating layer 14 has a multilayer structure, which includes: a first insulating film (substrate insulating film) 2, which is arranged to contact the lower surface portion 3b on the side of the lower surface portion 3b opposite to the upper surface portion 3a of the semiconductor portion 3; a second insulating film (surrounding insulating film) 4, which is arranged on the first insulating film 2 so as to surround the semiconductor portion 3; and a third insulating film (covering insulating film) 13, which is arranged on the second insulating film 4 so as to cover the semiconductor portion 3 and the gate electrode 7 to be described later. The first insulating film 2, the second insulating film 4, and the third insulating film 13 are composed of, for example, a silicon dioxide (SiO2) film. That is, the semiconductor device 1A of the first embodiment has a silicon-on-insulator (SOI) structure in which the semiconductor portion 3 of silicon (Si) is arranged on the first insulating film 2. In addition, the insulating layer 14 includes the semiconductor portion 3 and the field effect transistor Qa.

[0179] <Field Effect Transistor>

[0180] Field effect transistor Qa is not limited thereto, but is configured to have, for example, an n-channel conductivity type. Then, field effect transistor Qa includes a metal oxide semiconductor field effect transistor (MOSFET) having a silicon oxide (SiO2) film as a gate insulating film. Field effect transistor Qa may be a p-channel conductivity type. In addition, a metal insulator semiconductor FET (MISFET) using a silicon nitride film or a laminated film (composite film) such as a silicon nitride (Si3N4) film and a silicon oxide film may be used as a gate insulating film.

[0181] like Figures 1 to 4 As shown, the field effect transistor Qa includes a channel forming portion 12 arranged in the semiconductor portion 3, and a gate electrode 7 arranged on the upper surface portion 3a and two side surface portions 3c1 and 3c2 of the semiconductor portion 3, wherein the gate insulating film 6 is inserted in the channel forming portion 12 of the semiconductor portion 3 in the lateral direction (X direction) of the semiconductor portion 3.

[0182] In addition, the field effect transistor Qa further includes a pair of main electrode regions 11a and 11b disposed outside the semiconductor portion 3 separately from each other in the channel length direction (gate length direction) of the channel forming portion 12, with the channel forming portion 12 interposed therebetween. In other words, the field effect transistor Qa includes a pair of main electrode regions 11a and 11b disposed on both sides of the gate length direction (longitudinal direction) of the gate electrode 7 in the semiconductor portion 3. The pair of main electrode regions 11a and 11b serve as a source region and a drain region.

[0183] Furthermore, the field effect transistor Qa further includes a sidewall spacer 9 provided on the sidewall of the gate electrode 7 .

[0184] Here, for convenience of description, one main electrode region 11 a of the pair of main electrode regions 11 a and 11 b may be referred to as a source region 11 a , and the other main electrode region 11 b may be referred to as a drain region 11 b .

[0185] In addition, the distance between the pair of main electrode regions 11a and 11b is the channel length (L) of the channel forming portion 12 (the gate length (Lg) of the gate electrode 7), and the direction of the channel length is referred to as the channel length direction (gate length direction). Then, the direction of the channel width (W) (gate width (Wg)) of the channel forming portion 12 is referred to as the channel width direction (gate width direction). Then, in the first embodiment, as an example, since the pair of main electrode regions 11a and 11b are separated in the Y direction with the channel forming portion 12 interposed therebetween, the channel length direction is the Y direction.

[0186] In the field effect transistor Qa, a channel (inversion layer) electrically connecting the source region (main electrode region) 11a and the drain region (another main electrode region) 11b is formed (induced) in the channel forming portion 12 by the voltage applied to the gate electrode 7, and current (drain current) flows from the drain region 11b side through the channel forming portion 12 to the source region 11a side.

[0187] <Gate Electrode, Gate Insulating Film, and Sidewall Spacer>

[0188] like Figure 2 and Figure 3 As shown, the gate electrode 7 includes, but is not limited to, for example, a head (first portion) 7a and two leg portions (second portion) 7b1 and 7b2, the head (first portion) 7a being disposed on the upper surface portion 3a side of the semiconductor portion 3, the gate insulating film 6 being interposed between the head portions, the leg portions 7b1 and 7b2 being integrally formed with the head 7a and disposed on the outer side of each of the two side portions 3c1 and 3c2 located on the opposite sides in the lateral direction (X direction) of the semiconductor portion 3, and the gate insulating film 6 being interposed between the two side portions 7c1 and 7c2. That is, the gate electrode 7 is disposed on the upper surface portion 3a and the two side surface portions 3c1 and 3c2 of the semiconductor portion 3, and has a C-shaped cross-sectional shape orthogonal to the longitudinal direction (Y direction). The gate electrode 7 is composed of, for example, a polycrystalline silicon film into which impurities for reducing the resistance value are introduced.

[0189] The head 7a of the gate electrode 7 is located above the second insulating film 4 and is covered with the third insulating film 13. The leg portions 7b1 and 7b2 of the gate electrode 7 are provided in the film of the second insulating film 4.

[0190] The gate insulating film 6 is provided between the semiconductor portion 3 and the gate electrode 7 over the upper surface portion 3a and both side surface portions 3c1 and 3c2 of the semiconductor portion 3. The gate insulating film 6 is composed of, for example, a silicon oxide film.

[0191] The sidewall spacer 9 is provided on the sidewall of the head portion 7a of the gate electrode 7 so as to surround the head portion 7a of the gate electrode 7, and extends on the second insulating film 4 of the insulating layer 14 and the semiconductor portion 3 in a plan view. Then, the sidewall spacer 9 is formed so as to be aligned with the gate electrode 7. The sidewall spacer 9 can be formed by, for example, forming an insulating film (spacer material) covering the gate electrode 7 by a CVD method, and performing anisotropic dry etching such as RIE (reactive ion etching) on ​​the insulating film.

[0192] The sidewall spacer 9 is composed of a material having a selectivity ratio with respect to the second insulating film 4 included in the insulating layer 14 and the semiconductor portion 3. In the first embodiment, the sidewall spacer 9 is composed of, for example, a silicon nitride film having selectivity with respect to the silicon oxide film of the second insulating film 4 and the silicon of the semiconductor portion 3. The sidewall spacer 9 ensures that the gate electrode 7 is in contact with each of the pair of main electrode regions 11a and 11b described later (see Figure 2 ) between the two.

[0193] <Main Electrode Area>

[0194] like Figure 2 As shown, each of the pair of main electrode regions 11a and 11b includes: an n-type extension region 8 including an n-type semiconductor region disposed in the semiconductor portion 3 so as to be aligned with the gate electrode 7; and an n-type contact region 10 including an n-type semiconductor region disposed in the semiconductor portion 3 so as to be aligned with the sidewall spacer 9 of the sidewall of the gate electrode 7. That is, the pair of main electrode regions 11a and 11b having the n-type extension region 8 and the n-type contact region 10 are disposed in the semiconductor portion 3 so as to be aligned with the gate electrode 7.

[0195] like Figure 2 and Figure 4 As shown, the n-type contact region 10 is provided in the region of the n-type extension region 8. Each of the n-type extension region 8 and the n-type contact region 10 has a thickness in the thickness direction (Z direction) of the semiconductor portion 3 and in the height direction of the semiconductor portion 3. Then, the n-type extension region 8 is formed to be deeper than the n-type contact region 10 (in other words, thicker than the n-type contact region 10). In the first embodiment, although not limited thereto, the n-type extension region 8 extends from the upper surface portion 3a side of the semiconductor portion 3 to the lower surface portion 3b side, and has a depth in contact with the first insulating film 2 on the lower surface portion 3b side of the semiconductor portion 3.

[0196] like Figures 2 to 4 As shown, the field effect transistor Qa of the first embodiment is configured as a so-called fin type in which a gate electrode 7 is provided in an island-shaped semiconductor portion 3 as a fin portion with a gate insulating film 6 interposed therebetween.

[0197] In the fin field effect transistor Qa, the length between a pair of main electrode regions 11a and 11b is the channel length L (≈gate length Lg), and in the region where the gate electrode 7 overlaps three-dimensionally with the semiconductor portion 3, the value obtained by multiplying the length including the lateral width W2 on the upper surface portion 3a side of the semiconductor portion 3 and the height of the side surface portions 3b1 and 3b2 of the semiconductor portion 3 (the length surrounding the semiconductor portion 3) by the number of semiconductor portions 3 is the channel width W (≈gate width).

[0198] Therefore, in the fin field effect transistor Qa, since the channel width W is increased by increasing the width W2 of the semiconductor portion 3 in the lateral direction (Y direction) and increasing the height of the semiconductor portion 3 in the thickness direction (Z direction), the effective channel area (channel length L×channel width W) can be increased. Then, the fin field effect transistor Qa can increase the channel area (channel length L×channel width W) by increasing the number of semiconductor portions 3. In the first embodiment, the case where the field effect transistor Qa is provided in one semiconductor portion 3 has been described, but a plurality of semiconductor portions 3 may be provided.

[0199] Examples of the field effect transistor Qa include an enhancement type (normally off type) in which a drain current flows by applying a gate voltage equal to or higher than a threshold voltage to the gate electrode 7, and an inhibition type (normally off type) in which a drain current flows without applying a voltage to the gate electrode 7. In the first embodiment, although not limited to this, for example, an enhancement type is used. In the case of the enhancement type, in the field effect transistor Qa, a channel (inversion layer) electrically connecting a pair of main electrode regions 11a and 11b is formed (induced) in the channel forming portion 12 by a voltage applied to the gate electrode 7, and a current (drain current) flows from the drain region side (for example, the main electrode region 11b side) through the channel of the channel forming portion 12 to the source region side (for example, the main electrode region 11a side).

[0200] <Contact Electrode and Wiring>

[0201] like Figure 2 and Figure 3As shown, the gate electrode 7 is electrically connected to the wiring 18c of the wiring layer provided on the insulating layer 14 via the contact electrode 17c provided on the insulating layer 14 (specifically, the third insulating film 13) and the isolation metal film 16c provided on the semiconductor layer 3. In addition, one of the main electrode regions 11a and 11b is electrically connected to the wiring 18a of the wiring layer provided on the insulating layer 14 via the contact electrode 17a provided on the insulating layer 14 (specifically, the third insulating film 13) and the barrier metal film 16a provided on the semiconductor layer 3. Moreover, the other main electrode region 11b of the pair of main electrode regions 11a and 11b is electrically connected to the wiring 18b of the wiring layer provided on the insulating layer 14 via the contact electrode 17b provided on the insulating layer 14 (specifically, the third insulating film 13) and the barrier metal film 16b provided on the semiconductor layer 3. The material of the contact electrodes 17a, 17b, and 17c can be, for example, tungsten (W), which is a high melting point metal. As the barrier metal films 16a, 16b and 16c, for example, a composite film (Ti / TiN) including a titanium (Ti) film and a titanium nitride (TiN) film can be used. As the material of the wirings 18a, 18b, 18c, for example, metal materials such as aluminum (Al) and copper (Cu), alloy materials mainly composed of Al and Cu, etc. can be used.

[0202] In the first embodiment, the contact electrodes 17a, 17b, 17c and the barrier metal films 16a, 16b, 16c are described separately, but the contact electrodes 17a, 17b, 17c including the barrier metal films 16a, 16b, 16c may be used. In addition, although the barrier metal films 16a, 16b, 16c may be omitted, as in the first embodiment, it is preferred that the barrier metal films 16a, 16b, 16c are interposed between the semiconductor portion 3 and the gate electrode 7 and the contact electrodes 17a, 17b, 17c.

[0203] <Connection between Contact Electrode and Semiconductor Section>

[0204] like Figure 2 and Figure 4 As shown, the contact electrode 17a is provided in a groove portion 15a extending along the thickness direction (Z direction) of the insulating layer 14, penetrating the third insulating film 13 from the upper surface side of the third insulating film 13 of the insulating layer 14 and entering the film of the second insulating film 4. Similarly, the contact electrode 17b is also provided in a groove portion 15b extending along the thickness direction (Z direction) of the insulating layer 14, penetrating the third insulating film 13 from the upper surface side of the third insulating film 13 of the insulating layer 14 and invading the film of the second insulating film 4. In addition, the contact electrodes 17a and 17b are not limited to this, and may have a depth that separates the insulating layer 14 from the first insulating film 2 in the thickness direction (Z direction) of the insulating layer 14.

[0205] like Figure 2 and Figure 4 As shown, the contact electrodes 17a and 17b are connected to the upper surface portion 3a and the side portions of the semiconductor portion 3. Specifically, the contact electrode 17a is connected to the upper surface portion 3a and the three side portions 3c1, 3c2, and 3c3 of the semiconductor portion 3, respectively, and is electrically connected to one main electrode region 11a on one end side (main electrode region 11a side) in the longitudinal direction (Y direction) of the semiconductor portion 3. In addition, the contact electrode 17b is connected to the upper surface portion 3a and the three side portions 3c1, 3c2, and 3c4 of the semiconductor portion 3, respectively, and is electrically connected to the other main electrode region 11b on the other end side (main electrode region 11b side) in the longitudinal direction (Y direction) of the semiconductor portion 3.

[0206] In addition, although in the first embodiment, the contact electrode 17a is connected to the upper surface portion 3a and the three side portions 3c1, 3c2, and 3c3 of the semiconductor portion 3 via the barrier metal film 16a, the present invention is not limited thereto. In addition, the contact electrode 17b is connected to the upper surface portion 3a and the three side portions 3c1, 3c2, and 3c4 of the semiconductor portion 3 via the barrier metal film 16b.

[0207] <Contact Electrode Width>

[0208] like Figure 1 , Figure 2 , Figure 3 As shown, in the lateral direction (X direction) of the semiconductor portion 3, the width W1a of the contact electrode 17a is wider than the width W2 of the semiconductor portion 3. Then, the width W1a of the contact electrode 17a is narrower than the width W3 of the head portion 7a of the gate electrode 7 and the sidewall spacer 19 provided on both sides of the gate electrode 7 (the width of the gate electrode + the width of the sidewall spacer × 2).

[0209] Likewise, in the lateral direction (X direction) of the semiconductor portion 3, the width W1b of the contact electrode 17b is wider than the width W2 of the semiconductor portion 3. Furthermore, the width W1b of the contact electrode 17b is narrower than the width W2 of the gate electrode 7 and the sidewall spacers 19 provided on both sides of the gate electrode 7.

[0210] <<Method for manufacturing a semiconductor device>>

[0211] Figure 5 is a schematic plan view showing steps of a method for manufacturing a semiconductor device 1A, Fig. 6A is shown along Figure 5 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a5-a5 in FIG. Figure 6B is shown along Figure 5 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b5-b5 in FIG.

[0212] Figure 7 It shows Figure 5 Schematic plan view of the following steps, Fig. 8A is shown along Figure 7 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a7-a7 in FIG. Figure 8B is shown along Figure 7 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b7-b7 in FIG.

[0213] Fig. 9 It shows Figure 7 Schematic plan view of the following steps, Fig. 10A It shows that along Fig. 9 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a9-a9 in FIG. Fig. 10B It shows that along Fig. 9 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b9-b9 in FIG.

[0214] Fig.11 It shows Fig. 9 Schematic plan view of the following steps, Fig. 12A is shown along Fig.11 A schematic longitudinal sectional view of the longitudinal sectional structure taken along the cutting line a11-a11 in FIG. Fig. 12B is shown along Fig.11 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c11-c11 in FIG.

[0215] Fig.13 It is shown Fig.11 Schematic plan view of the following steps, Fig.14A It is shown along Fig.13 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a13-a13 in FIG. Fig. 14B It is shown along Fig.13 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c13-c13 in FIG.

[0216] Fig.15 It is shown Fig.13 Schematic plan view of the following steps, Fig.16A It is shown along Fig.15 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a15-a15 in FIG. Fig. 16B It is shown along Fig.15 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c15-c15 in FIG.

[0217] Fig.17 It is shown Fig.15 Schematic plan view of the following steps, Fig.18A is shown along Fig.17 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a17-a17 in FIG. Fig.18B is shown along Fig.17 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c17-c17 in FIG.

[0218] Fig.19 It is shown Fig.17 Schematic plan view of the following steps, Fig. 20A is shown along Fig.19 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a19-a19 in FIG. Fig. 20B is along Fig.19 Schematic longitudinal cross-sectional view taken along the cutting line c19-c19 in FIG.

[0219] Fig.21 It is shown Fig.19 Schematic plan view of the following steps, Fig.22A is shown along Fig.21 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a21-a21 in FIG. 1 , and Fig. 22B is shown along Fig.21 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c21 - c21 in FIG.

[0220] First, if Figure 5 , Fig. 6A and Figure 6B As shown, an island-shaped semiconductor portion 3 is formed on the first insulating film 2. The semiconductor portion 3 is formed into, for example, a rectangular parallelepiped shape having an upper surface portion 3a, a lower surface portion (bottom portion) 3b, and four side portions 3c1, 3c2, 3c3, and 3c4. For example, the semiconductor portion 3 can be formed by patterning a semiconductor layer provided on the first insulating film 2 into a predetermined shape using a known etching technique or a thinning technique such as a CMP method. Although not limited to this, the semiconductor portion 3 is composed of, for example, silicon as a semiconductor material, for example, as a crystalline single crystal, and, for example, as an i-type (intrinsic type) of conductivity type. The first insulating film 2 supports the semiconductor portion 3 on the lower surface portion 3b side of the semiconductor portion 3. As the first insulating film 2, for example, a silicon oxide film formed by a chemical vapor deposition (CVD) method is used.

[0221] Then, if Figure 7 , Fig. 8A , Figure 8BAs shown, the second insulating film 4 and the grooved portions 5a, 5b are formed. The second insulating film 4 is formed outside the semiconductor portion 3 so as to surround the semiconductor portion 3. The second insulating film 4 can be formed by forming, for example, a silicon oxide film on the entire surface of the first insulating film 2 including the semiconductor portion 3 using a known film formation method (for example, a CVD method), and then selectively removing the silicon oxide film on the semiconductor portion 3 using, for example, a CMP method.

[0222] After forming the second insulating film 4, the grooved portions 5a and 5b are formed so that the side surface portions 3c1 and 3c2 are exposed to the outside of each of the two side surface portions 3c1 and 3c2 located on the opposite sides in the X direction of the semiconductor portion 3. The grooved portions 5a and 5b can be formed by selectively etching the second insulating film 4 outside each side portion 3c1 and 3c2 of the semiconductor portion 3 using, for example, a known photolithography technique and a dry etching technique. The etching of the second insulating film 4 is performed under conditions that can obtain an etching ratio relative to the semiconductor portion 3. The grooved portions 5a, 5b are formed in a shape in which the length in the same direction as the length direction (Y direction) of the semiconductor portion 3 is shorter than the length in the length direction of the semiconductor portion 3. In addition, the grooved portions 5a, 5b are preferably formed in such a way that the depth in the Z direction is equal to or greater than the height of the semiconductor portion 3 in the Z direction.

[0223] Then, if Fig. 9 , Fig. 10A and Fig. 10B As shown, a gate insulating film 6 and a gate electrode 7 are formed. Fig. 10A and Fig. 10B As shown, in the lateral direction (X direction) of the semiconductor portion 3, the gate insulating film 6 is formed on the upper surface portion 3a and the two side surface portions 3c1 and 3c2 of the semiconductor portion 3. The gate insulating film 6 can be formed by a thermal oxidation method or a deposition method. In the first embodiment, a silicon oxide film as the gate insulating film 6 is formed by a thermal oxidation method. As a result, the gate insulating film 6 can be selectively formed in the portion of the semiconductor portion 3 exposed from the second insulating film 4.

[0224] like Fig. 10A and Fig. 10BAs shown, the gate electrode 7 is formed to face (be adjacent to) the upper surface portion 3a and each of the two side surface portions 3c1 and 3c2 of the semiconductor portion 3, with the gate insulating film 6 interposed therebetween. The gate electrode 7 includes: a head portion (first portion) 7a, which is provided on the upper surface portion 3a side of the semiconductor portion 3 via the gate insulating film 6; and two leg portions (second portions) 7b1 and 7b2, which are integrally formed with the head portion 7a and are provided on the outer side of each of the two side surface portions 3c1 and 3c2 located on the opposite sides in the lateral direction (X direction) of the semiconductor portion 3, with the gate insulating film 6 interposed therebetween. The head portion 7a protrudes upward from the second insulating film 4. The two leg portions 7b1, 7b2 are provided on the grooved portions 5a, 5b, respectively.

[0225] The gate electrode 7 can be formed by forming a gate electrode film (electrode material) on the entire surface of the second insulating film 4 including the inside of each of the two grooved portions 5a and 5b and the semiconductor portion 3, and then patterning the gate electrode film using a known planarization technique, a photolithography technique, a dry etching technique, etc. As the gate electrode film, for example, a polycrystalline silicon film into which impurities for reducing the resistance value are introduced can be used.

[0226] Impurities in the polysilicon film may be introduced during or after film formation. When the polysilicon film is embedded in the trenches 5a and 5b as in the first embodiment, it is preferable to introduce impurities during film formation from the viewpoint of uniformity of impurity concentration.

[0227] Next, if Fig.11 , Fig. 12A and Fig. 12B As shown, a pair of extension regions 8 including an n-type semiconductor region are formed on each semiconductor portion 3 on both sides of the gate electrode 7 in the gate length direction (Y direction). By using the gate electrode 7 and the second insulating film 4 as an impurity introduction mask, arsenic ions (As 2+) as n-type impurities can be introduced. + ) or phosphorus ion (P + ) ions are implanted into each semiconductor portion 3 on both sides of the gate length direction (Y direction) of the gate electrode 7, and then the semiconductor portion 3 is heat-treated to activate the impurities to form an extension region 8. A pair of n-type extension regions 8 are formed at a depth in contact with the first insulating film 2 on the lower surface portion 3b side of the semiconductor portion 3.

[0228] In this step, each of a pair of n-type extension regions 8 is formed on each semiconductor portion 3 on both sides of the gate electrode 7 in the gate length direction (Y direction) so as to be aligned with the gate electrode 7 .

[0229] Then, if Fig.13 , Fig.14A and Fig. 14BAs shown in FIG. 1 , a sidewall spacer 9 is formed on the sidewall of the head 7a of the gate electrode 7 protruding upward from the second insulating film 4. The sidewall spacer 9 can be formed as follows: a silicon nitride film selective to, for example, a silicon oxide film as an insulating film is formed on the entire surface of the second insulating film 4 by a CVD method in such a manner as to cover the head 7a of the gate electrode 7, and anisotropic dry etching such as RIE is performed on the silicon nitride film. The sidewall spacer 9 is formed on the sidewall of the head 8a of the gate electrode 7 in such a manner as to surround the head 7a of the gate electrode 7, and is formed in such a manner as to be aligned with the gate electrode 7. In addition, the sidewall spacer 9 is formed on the second insulating film 4 and the semiconductor portion 3 so as to intersect with the semiconductor portion 3.

[0230] Next, after forming the sidewall spacer 9, as shown in Fig.13 , Fig.14A and Fig. 14B As shown in FIG. 1 , a pair of n-type contact regions 10 including an n-type semiconductor region are formed on each semiconductor portion 3 on both sides of the gate electrode 7 in the gate length direction (Y direction). By using the second insulating film 4, the gate electrode 7 and the sidewall spacer 9 as an impurity introduction mask, arsenic ions (As ) as n-type impurities can be introduced. + ) or phosphorus ion (P + ) ions are implanted into each semiconductor portion 3 on both sides of the gate length direction (Y direction) of the gate electrode 7, and then the semiconductor portion 3 is heat-treated to activate the impurities to form a pair of n-type contact regions 10. The pair of n-type contact regions 10 are formed separately in the region of the pair of extension regions 8. Then, a pair of n-type contact regions 10 are formed on each semiconductor portion 3 on both sides of the gate length direction (Y direction) of the gate electrode 7 so as to be aligned with the sidewall spacer 9.

[0231] In this step, a pair of main electrode regions 11 a and 11 b including the n-type extension region 8 and the n-type contact region 10 are formed in the semiconductor portion 3 .

[0232] Furthermore, in this step, the channel forming portion 12 is formed in the semiconductor portion 3 between the pair of main electrode regions 11 a and 11 b .

[0233] Then, through this step, a field effect transistor Qa including the gate insulating film 6 , the gate electrode 7 , the sidewall spacer 9 , the pair of main electrode regions 11 a and 11 b , the channel forming portion 12 , and the like is formed in the semiconductor portion 3 .

[0234] Next, if Fig.15 , Fig.16A and Fig. 16BAs shown, a third insulating film 13 covering the semiconductor portion 3 and the gate electrode 7 is formed on the side of the second insulating film 4 opposite to the first insulating film 2 side. The third insulating film 13 can be formed by, for example, forming a silicon oxide film as an insulating film on the entire surface of the second insulating film 4 including the head 7a of the gate electrode 7, and then flattening the surface of the silicon oxide film by a CMP method or the like.

[0235] In this step, the insulating layer 14 including the first insulating film 2, the second insulating film 4, and the third insulating film 13 and including the semiconductor portion 3 and the field effect transistor Qa is formed.

[0236] Next, if Fig.17 , Fig.18A and Fig.18B As shown in FIG. 1 , each of the groove portions 15a and 15b entering the second insulating film 4 from the surface of the third insulating film 13 of the insulating layer 14 is formed on both end sides of the semiconductor portion 3 in the longitudinal direction (Y direction), and a groove portion 15c reaching the head portion 7a of the gate electrode 7 from the surface of the third insulating film 13 of the insulating layer 14 is formed. Each of the groove portions 15a, 15b, and 15c is formed by selectively etching the insulating layer 14 using a known photolithography technique and anisotropic dry etching technique.

[0237] The groove portion 15a is formed so that the upper surface portion 3a and three side surface portions 3c1, 3c2 and 3c3 of one of the two semiconductor portions 3 on both sides of the gate length direction (Y direction) of the gate electrode 7 are exposed. In addition, the groove portion 15b is formed so that the upper surface portion 3a and three side surface portions 3c1, 3c2 and 3c4 of the other of the two semiconductor portions 3 on both sides of the gate length direction (Y direction) of the gate electrode 7 are exposed. The width W4 of each groove portion 15a, 15b in the lateral direction (X direction) of the semiconductor portion 3 determines the width W1 of the contact electrodes 17a, 17b described later.

[0238] Then, if Fig.19 , Fig. 20A and Fig. 20B As shown, a barrier metal film 16a is formed on the upper surface portion 3a and the three side portions 3c1 and 3c2, and a barrier metal film 16b is formed on the upper surface portion 3a and the three side portions 3c1 in 3c3 of the semiconductor portion 3 exposed from the groove portion 15a, 3c2 and 3c4 of the semiconductor portion 3 exposed from the groove portion 15b, and a barrier metal film 16c is formed on the head portion 7a of the gate electrode 7 exposed from the groove portion 15c. The barrier metal films 16a, 16b and 16c are composed of, for example, a composite film (Ti / TiN) including a titanium (Ti) film and a titanium nitride (TiN) film. The barrier metal films 16a, 16b and 16c can be selectively formed by an ALD method.

[0239] Then, if Fig.21 , Fig.22A and Fig. 22B As shown, contact electrodes 17a, 17b and 17c are formed in the grooved portions 15a, 15b and 15c, respectively. The contact electrodes 17a, 17b and 17c can be formed as a tungsten film as a high melting point metal film on the entire surface of the insulating layer 14 (including the inside of the grooved portions 15a, 15b and 15c), and the tungsten film on the insulating layer 14 is selectively removed so that the tungsten film remains inside the grooved portions 15a, 15b and 15c, respectively.

[0240] In this step, the contact electrode 17a is connected to the upper surface portion 3a and three side portions 3c1, 3c2, and 3c3 of one of the two semiconductor portions 3 on both sides of the gate length direction (Y direction) of the gate electrode 7 through the barrier metal film 16a, and is electrically and mechanically connected to one of the main electrode regions 11a and 11b.

[0241] In addition, in this step, the contact electrode 17b is connected to the upper surface portion 3a and three side portions 3c1, 3c2, and 3c4 of the other semiconductor portion 3 of the two semiconductor portions 3 on both sides of the gate length direction (Y direction) of the gate electrode 7 via the barrier metal film 16b, and is electrically and mechanically connected to the other main electrode region 11b of a pair of main electrode regions 11a and 11b.

[0242] In this step, the contact electrode 17 c is connected to the head portion 7 a of the gate electrode 7 via the barrier metal film 16 c , and is electrically and mechanically connected to the gate electrode 7 .

[0243] Next, wirings 18a, 18b, 18c are formed on the wiring layer of the insulating layer 14 to be electrically / mechanically connected to the contact electrodes 17a, 17b, 17c, respectively. Figures 1 to 4 Status shown.

[0244] <<Main Effects of First Embodiment>>

[0245] Next, main effects of the first embodiment will be described.

[0246] The semiconductor device 1A of the first embodiment includes contact electrodes 17a and 17b, which are provided so as to overlap with the semiconductor portion 3 on both sides of the gate length direction (Y direction) of the gate electrode 7 in a plan view. Furthermore, the contact electrode 17a is connected to the upper surface portion 3a and three side portions 3c1, 3c2, and 3c3 of the semiconductor portion 3, and the semiconductor portion 3 includes one main electrode region 11a of a pair of main electrode regions 11a and 11b, and the pair of main electrode regions 11a and 11b are provided on both sides of the gate length direction (Y direction) of the gate 7. Therefore, compared with the case where the contact electrode 17a is connected only to the upper surface portion 3a of the semiconductor portion 3 in the past, the contact area between the semiconductor portion 3 (main electrode region 11a) and the contact electrode 17a is increased, and the contact resistance between the semiconductor portion 3 (main electrode region 11a) and the contact electrode 17a can be reduced. Therefore, according to the semiconductor device 1A of the first embodiment 1, the transconductance (gm) of the field effect transistor Qa can be improved.

[0247] In addition, the contact electrode 17b is also connected to the upper surface portion 3a and the three side portions 3c1, 3c2, and 3c4 of the semiconductor portion 3, and the semiconductor portion 3 is provided with the other main electrode region 11b of a pair of main electrode regions 11a and 11b, and the pair of main electrode regions 11a and 11b are provided in the semiconductor portion 5 on both sides of the gate length direction of the gate electrode 7. Therefore, compared with the conventional case where the contact electrode 17b is connected only to the upper surface portion 3a of the semiconductor portion 3, the contact area between the semiconductor portion 3 (the other main electrode region 11b) and the contact electrode 17b is increased, and the contact resistance between the semiconductor portion 3 (the other main electrode region 11b) and the contact electrode 17b can be reduced. Therefore, according to the semiconductor device 1A of the first embodiment 1, the transconductance (gm) of the field effect transistor Qa can be improved.

[0248] In addition, the contact resistance between the semiconductor portion 3 (one main electrode region 11a) and the contact electrode 17a can be reduced, and the contact resistance between the semiconductor portion 3 (the other main electrode region 11b) and the contact electrode 17b can be reduced, thereby further improving the transconductance (gm) of the field effect transistor Qa.

[0249] In addition, even if the lateral (X-direction) width W2 of the semiconductor portion 3 and the width W1 (diameter, thickness) of the contact electrodes 17a and 17b decrease as the field effect transistor Qa is miniaturized, the increase in the contact resistance between the semiconductor portion 3 and the contact electrodes 17a and 17b can be suppressed, and the reduction in transconductance (gm) can be suppressed while miniaturizing the field effect transistor Qa.

[0250] In addition, in the first embodiment described above, the contact electrodes 17a and 17b are formed at a depth separated from the first insulating film 2 of the insulating layer 14, but may be formed at a depth reaching the first insulating film 2. In this case, the contact resistance between the semiconductor portion 3 and the contact electrodes 17a and 17b, specifically, the contact resistance between the pair of main electrode regions 11a and 11b and the contact electrodes 17a and 17b can be further reduced.

[0251] In addition, in the above-mentioned first embodiment, the case where the two contact electrodes 17a and 17b are respectively connected to the upper surface portion 3a and the three side portions (3c1, 3c2, 3c3 (or 3c4)) of the semiconductor portion 3 is described. However, one of the two contact electrodes 17a and 17b may be connected to the upper surface portion 3a and the three side portions (3c1, 3c2, 3c3 (or 3c4)) of the semiconductor portion 3, and the other may be connected only to the upper surface portion 3a of the semiconductor portion 3.

[0252] [Second embodiment]

[0253] like Figure 23 to Figure 25 As shown, the semiconductor device 1B according to the second embodiment of the present technology basically has a configuration similar to that of the semiconductor device 1A according to the above-described first embodiment, and the connection form of the contact electrode to the side surface portion of the semiconductor portion 3 is different.

[0254] That is, Figures 1 to 4 As shown, the contact electrode 17a of the first embodiment is connected to the three side surfaces 3c1, 3c2, and 3c3 of the semiconductor portion 3. In addition, the contact electrode 17b is also connected to the three side surfaces 3c1, 3c2, and 3c4 of the semiconductor portion 3.

[0255] On the other hand, Figure 23 to Figure 25 As shown, the contact electrode 17a of the second embodiment is located at a position closer to the gate electrode 7 than one side portion 3c3 of the side portions 3c3 and 3c4 in the longitudinal direction (Y direction) of the semiconductor portion 3. Then, the contact electrode 17a of the second embodiment is connected to each of two side portions 3c1 and 3c2 located on opposite sides in the lateral direction (X direction) of the semiconductor portion 3 among the three side portions 3c1, 3c2, and 3c3 of the semiconductor portion 3. That is, the contact electrode 17a of the second embodiment is connected to the upper surface portion 3a of the semiconductor portion 3, and as the side portions of the semiconductor portion 3, is connected to each of two side portions 3c1 and 3c2 located in the lateral direction (X direction) of the semiconductor portion 3 except the side portion 3c3 which is one end portion in the longitudinal direction (Y direction) of the semiconductor portion 3.

[0256] In the contact electrode 17b of the second embodiment, similarly to the contact electrode 17a of the second embodiment, the contact electrode is located on the gate electrode 7 side relative to the other side portion 3c4 located at the two opposite ends of the side portions 3c3 and 3c4 in the longitudinal direction (Y direction) of the semiconductor portion 3. Furthermore, the contact electrode 17b of the second embodiment is connected to the two side portions 3c1 and 3c2 located at the opposite sides of the lateral direction (X direction) of the semiconductor portion 3, among the three side portions 3c1, 3c2, and 3c4 of the semiconductor portion 3. That is, the contact electrode 17b of the second embodiment is also connected to the upper surface portion 3a of the semiconductor portion 3, and is connected to the two side portions 3c1 and 3c2 in the short direction (X direction) of the semiconductor portion 3, except for the side portion 3c4 at the end in the long direction (Y direction) of the semiconductor portion 3, as the side portions of the semiconductor portion 3.

[0257] like Fig.26 As shown in, in the semiconductor device 1B according to the second embodiment, two semiconductor portions 3 (3A1 and 3A2) are arranged in series in the Y direction at a predetermined interval in a direction in which the longitudinal direction (Y direction) of each is the same direction. That is, in the two semiconductor portions 3 (3A1 and 3A2), the side surface portion 3c3 located on one end side in the longitudinal direction of one semiconductor portion 3A1 and the side surface portion 3c4 located on the other end side in the longitudinal direction of the other semiconductor portion 3A2 are adjacent to each other and are arranged in series in the Y direction. Then, a field effect transistor Qa is provided in each of the two semiconductor portions 3 (3A1 and 3A2).

[0258] Here, if Fig.26 As shown, the contact electrode 17a located on the side surface portion 3c3 side of one semiconductor portion 3 (3A1) is positioned closer to the gate electrode 7 provided in the one semiconductor portion 3 (3A1) than the side surface portion 3c3 in the longitudinal direction of the one semiconductor portion 3 (3A1). Then, the contact electrode 17b located on the side surface portion 3c4 side of the other semiconductor portion 3 (3A2) is positioned closer to the gate electrode 7 provided in the other semiconductor portion 3 (3A2) than the side surface portion 3c4 in the longitudinal direction of the other semiconductor portion 3 (3A2).

[0259] Therefore, according to the semiconductor device 1B of the second embodiment, the interval (distance) Ly between the side surface portion 3c3 of one semiconductor portion 3 (3A1) and the side surface portion 3c4 of another semiconductor portion 3 (3A2) can be narrowed in a plan view, so that the field effect transistors Qa can be arranged more densely. As a result, the transconductance (Gm) of the field effect transistors Qa can be improved, and the semiconductor device 1B can be highly integrated.

[0260] like Figure 23 to Figure 25 As shown, in the second embodiment, similarly to the first embodiment, in the lateral direction (X direction) of the semiconductor portion 3, the width W1a of the contact electrode 17a is wider than the width W2 of the semiconductor portion 3. Then, the width W1a of the contact electrode 17a is narrower than the width W3 including the gate electrode 7 and the sidewall spacers 19 provided on both sides of the gate electrode 7.

[0261] In the second embodiment, similarly to the first embodiment, in the lateral direction (X direction) of the semiconductor portion 3, the width W1b of the contact electrode 17b is wider than the width W2 of the semiconductor portion 3. Furthermore, the width W1b of the contact electrode 17b is narrower than the width W3 of the gate electrode 7 and the sidewall spacers 19 provided on both sides of the gate electrode 7.

[0262] That is, the two contact electrodes 17a and 17b are respectively located on the inner side (gate electrode 7 side) of the end portions (side surface portion 3c3 and side surface portion 3c4) in the longitudinal direction (Y direction) of the semiconductor portion 3, and the widths W1a and W1b of the contact electrodes 17a and 17b are narrower than the width W3 of the gate electrode 7 and the sidewall spacers 19 provided on both sides of the gate electrode 7. Therefore, according to the semiconductor device 1B of the second embodiment, the transconductance (gm) of the field effect transistor Qa can be improved without increasing the area occupied by the field effect transistor Qa.

[0263] It should be noted that in Fig.26 In the above-mentioned first embodiment, Figure 1 Similarly, for convenience of description, illustration of layers higher than the insulating layer 14 is omitted.

[0264] <<Modification of Second Embodiment>>

[0265] In the above second embodiment, if Fig.25 As shown in FIG. 1 , the structure in which the contact electrodes 17a and 17b are connected to the upper surface portion 3a and the side surface portions 3c1 and 3c2 of the semiconductor portion 3 is described. Fig. 27 As shown, the contact electrode 17 a may also be connected to the lower surface portion 3 b of the semiconductor portion 3 .

[0266] That is, the contact electrode 17a of this modification example is connected to the upper surface portion 3a and each of the two side portions 3c1 and 3c2 of the semiconductor portion 3, and is also connected to the lower surface portion 3b of the semiconductor portion 3. In addition, the barrier metal film 16a is respectively connected to the upper surface portion 3a and the two side portions 3c1 and 3c2 of the semiconductor portion 3, and is also connected to the lower surface portion 3b of the semiconductor portion 3.

[0267] The contact electrode 17a of this variation is formed by forming a groove portion 15a on the insulating layer 14 to expose the two side portions 3c1, 3c2 and the lower surface portion 3b of the semiconductor portion 3, and a barrier metal film 16a is formed on the surface portion of the semiconductor portion 3 exposed from the groove portion 15a. Then, a conductive film is buried in the groove portion 15a to surround the lower surface portion 3b side of the semiconductor portion 3.

[0268] According to the variation of the second embodiment, the contact area between the semiconductor portion 3 (one main electrode region 11a) and the contact electrode 17a can be increased compared to the second embodiment, and the contact resistance between the semiconductor portion 3 (one main electrode region 11a) and the contact electrode 17a can be further reduced.

[0269] In addition, Fig. 27 In the description, the contact electrode 17a is taken as an example, but it is preferred that the contact electrode 17b has the same structure as the contact electrode 17a.

[0270] In addition, Fig. 27 In the description, the structure in which the contact electrode 17a covers the entire lower surface portion 3b of the semiconductor portion 3 is taken as an example, but the central portion of the lower surface portion 3b of the semiconductor portion 3 in the lateral direction (X direction) may not be selectively covered by the contact electrode.

[0271] [Third Embodiment]

[0272] like Fig.28 and Fig.29 As shown, a semiconductor device 1C according to the third embodiment of the present technology basically has a configuration similar to that of the semiconductor device 1B according to the above-described second embodiment, and has a different connection form in which a contact electrode is connected to a side surface portion of a semiconductor portion 3 .

[0273] That is, Figure 23 to Figure 25 As shown, the contact electrode 17a of the second embodiment is connected to the two side surfaces 3c1 and 3c2 of the semiconductor portion 3. In addition, the contact electrode 17b is connected to the two side surfaces 3c1 and 3c2 of the semiconductor portion 3.

[0274] On the other hand, Fig.28 and Fig.29 As shown, the contact electrodes 17a and 17b of the third embodiment are connected to either of the two side surfaces 3c1 and 3c2 on the opposite sides of the semiconductor portion 3 in the lateral direction (X direction), respectively, as the side surfaces of the semiconductor portion 3. Fig.28 and Fig.29 In the description, the contact electrodes 17 a and 17 b are connected to the side surface portion 3 c 1 of the semiconductor portion 3 , but they may be connected to the side surface portion 3 c 2 on the opposite side to the side surface portion 3 c 1 of the semiconductor portion 3 .

[0275] That is, the contact electrodes 17a, 17b of embodiment 3 are connected to the upper surface portion 3a of the semiconductor portion 3, and are connected as the side portions of the semiconductor portion 3, selectively connected to a side portion 3c1 located in the lateral direction (X direction) of the semiconductor portion 3, except for the side portions 3c3 and 3c4 which are the ends in the longitudinal direction (Y direction) of the semiconductor portion 3 and another side portion 3c2 located in the lateral direction (X direction) of the semiconductor portion 3.

[0276] like Fig.28 and Fig.29 As shown, the semiconductor device 1C according to the third embodiment further includes a through contact electrode 24, which penetrates the insulating layer 14 in the thickness direction of the insulating layer 14 and is provided adjacent to the contact electrode 17a on the outer side in the lateral direction (X direction) of the semiconductor portion 3 when viewed from above. The through contact electrode 24 is, for example but not limited to, arranged on the outer side of the other side portion 3c2 of the two side portions 3c1 and 3c2 that are opposite to each other in the lateral direction of the semiconductor portion 3.

[0277] Then, if Fig.29 As shown in the figure, the through contact electrode 24 is arranged in the groove portion 23, which penetrates the insulating layer 14 in the thickness direction (Z direction) of the insulating layer 14 and extends on the layer 22 arranged on the upper surface side of the insulating layer 14 and the layer 21 arranged on the lower surface side opposite to the upper surface side of the insulating layer 14.

[0278] Here, if Fig.28 and Fig.29 As shown, the contact electrode 17a is selectively connected to one side portion 3c1 on the opposite side of the through contact electrode 24 of the semiconductor portion 3, of the two side portions 3c1 and 3c2 located on both sides of the semiconductor portion 3 in the lateral direction (X direction). Therefore, as in the above-mentioned second embodiment, compared with the case where the contact electrode 17a is connected to the two side portions 3c1 and 3c2 located on both sides of the semiconductor portion 3 in the lateral direction, the interval (distance) Lx between the contact electrode 17a and the through contact electrode 24 can be increased, and the insulating film between the contact electrode 17a and the through contact electrode 24 is used as a dielectric film, which can reduce the parasitic capacitance. Therefore, according to the semiconductor device 1C of the third embodiment, the same effect as the above-mentioned second embodiment can be obtained, and the parasitic capacitance of using the insulating film between the contact electrode 17a and the through contact electrode 24 as a dielectric film can be reduced.

[0279] In addition, although not shown in the figure, even in the case where a through contact electrode 24 is provided adjacent to the contact electrode 17b on the lateral (X direction) outer side of the semiconductor portion 3 when viewed from above, the through contact electrode is selectively connected to one side portion 3c1 of the semiconductor portion 3 on the side of the through contact electrode 24, of the two side portions 3c1 and 3c2 located on both sides in the lateral (X direction) direction of the semiconductor portion 3. This can reduce the parasitic capacitance of the insulating film between the contact electrode 17b and the through contact electrode 24 as a dielectric film.

[0280] It should be noted that in Fig.28 In the above-mentioned first embodiment, Figure 1 Similarly, for convenience of description, illustration of layers higher than the insulating layer 14 is omitted.

[0281] <<Modification of the Third Embodiment>>

[0282] <First Modification>

[0283] like Fig.30 As shown, in the semiconductor device 1C1 according to the first modified example of the third embodiment, two semiconductor parts 3 (3A3 and 3A4) are arranged in parallel at a predetermined interval in the X direction, wherein the longitudinal direction (Y direction) of each semiconductor part is the same direction. That is, in the two semiconductor parts 3 (3A3 and 3A4), the other side surface part 3c2 of the two side surface parts 3c1 and 3c2 located in the lateral direction of one semiconductor part 3 (3A3) and the one side surface part 3c1 of the two side surface parts 3c1 and 3c2 located in the lateral direction of the other semiconductor part 3 (3A4) are adjacent to each other and arranged in parallel. Then, a field effect transistor Qa is provided in each of the two semiconductor parts 3 (3A3 and 3A4).

[0284] Here, if Fig.30As shown, in the two semiconductor portions 3 (3A3 and 3A4), the other side surface portion 3c2 located in the lateral direction (X direction) of one semiconductor portion 3A3 and the one side surface portion 3c1 located in the lateral direction (X direction) of the other semiconductor portion 3A4 are arranged to be adjacent to each other (facing each other). Then, the contact electrode 17a located on the side of one semiconductor portion 3C3 is selectively connected to one side surface portion 3c1 of the two side surface portions 3c1 and 3c2 located on both lateral sides of one semiconductor portion 3A3, and the contact electrode 17a located on the side of the other semiconductor portion 3A4 is also selectively connected to one side surface portion 3c1 of the two side surface portions 3c1 and 3c2 located on both lateral sides of the other semiconductor portion 3A4. Therefore, compared with the case where the contact electrode 17a is connected to the two side surfaces 3c1 and 3c2 located on both sides of the semiconductor portion 3 in the lateral direction as in the second embodiment, the interval (distance) Lx1 between the contact electrode 17a on the semiconductor portion 3A3 side on one side and the contact electrode 17a on the semiconductor portion 3A4 side on the other side becomes larger, so that the insulating film between the contact electrode 17a on the semiconductor portion 3A3 side on one side and the contact electrode 17a on the semiconductor portion 3A4 side on the other side can be used as a dielectric film, thereby reducing parasitic capacitance. Therefore, according to the semiconductor device 1C1 of the first variation of the third embodiment, the same effect as the second embodiment can be obtained, and the parasitic capacitance of using the insulating film between the contact electrode 17a on the semiconductor portion 3A3 side and the contact electrode 17a on the semiconductor portion 3A4 side on the other side as a dielectric film can be reduced.

[0285] In addition, if Fig.30 As shown, since the interval between the contact electrode 17b on the semiconductor portion 3A3 side on one side and the contact electrode 17b on the semiconductor portion 3A4 side on the other side is also increased, the parasitic capacitance can be reduced by using the insulating film between the contact electrode 17a on the semiconductor portion 3A3 side on one side and the contact electrode 17b on the semiconductor portion 3A4 side on the other side as a dielectric film.

[0286] It should be noted that in Fig.30 In the above-mentioned first embodiment, Figure 1 Similarly, for convenience of description, illustration of layers higher than the insulating layer 14 is omitted.

[0287] <Second Modification>

[0288] like Fig.31 As shown, a semiconductor device 1C2 according to the second modification example of the third embodiment basically has the same structure as the semiconductor device 1C1 according to the first modification example of the third embodiment described above, but the following structures are different.

[0289] That is, Fig.31As shown, similarly to the first modified example of the third embodiment described above, each of the contact electrodes 17a and 17b on the side of one semiconductor portion 3 (3A3) of the two semiconductor portions 3 (3A3 and 3A4) is selectively connected to one side portion 3c1 of the two side portions 3c1 and 3c2 located on both sides in the lateral direction of the one semiconductor portion 3 (3A3). Moreover, unlike the first modified example of the third embodiment described above, the contact electrodes 17a and 17b on the side of the other semiconductor portion 3 (3A4) of the two semiconductor portions 3 (3A3, 3A4) are selectively connected to the other side portion 3c2 of the two side portions 3c1 and 3c2 located on both sides in the lateral direction of the other semiconductor portion 3 (3A4).

[0290] Therefore, compared with the first variant of the above-mentioned third embodiment, the interval (distance) Lx2 between the contact electrode 17a on one semiconductor portion 3A3 side and the contact electrode 17a on the other semiconductor portion 3A4 side is wider. Therefore, the insulating film between the contact electrode 17a on one semiconductor portion 3A3 side and the contact electrode 17a on the other semiconductor portion 3A4 side can be used as a dielectric film, which can further reduce the parasitic capacitance.

[0291] In addition, if Fig.31 As shown, since the interval between the contact electrode 17b on the semiconductor portion 3A3 side on one side and the contact electrode 17b on the semiconductor portion 3A4 side on the other side is also widened, the parasitic capacitance of the insulating film between the contact electrode 17b on the semiconductor portion 3A3 side on one side and the contact electrode 17b on the semiconductor portion 3A4 side on the other side can be further reduced by using the insulating film between the contact electrode 17b on the semiconductor portion 3A3 side on one side and the contact electrode 17b on the semiconductor portion 3A4 side on the other side as a dielectric film.

[0292] It should be noted that in Fig.31 In the above-mentioned first embodiment, Figure 1 Similarly, for convenience of description, illustration of layers higher than the insulating layer 14 is omitted.

[0293] <Third Modification>

[0294] like Fig.32 As shown, similarly to the modification of the second embodiment described above, the contact electrode 17 a may be connected to the lower surface portion 3 b of the semiconductor portion 3 .

[0295] That is, the contact electrode 17a of the third modification example is connected to the upper surface portion 3a of the semiconductor portion 3, to one side portion 3c1 of the two side portions 3c1 and 3c2, and to the lower surface portion 3b of the semiconductor portion 3. In addition, the barrier metal film 16a is also connected to the upper surface portion 3a of the semiconductor portion 3, to one side portion 3c1 of the two side portions 3c1 and 3c2, and to the lower surface portion 3b of the semiconductor portion 3.

[0296] In addition, Fig.32In the description, the contact electrode 17a is taken as an example, but the contact electrode 17b may also have Fig.32 The contact electrode 17a shown has the same structure.

[0297] [Fourth Embodiment]

[0298] like Figure 33 to Figure 35 As shown, the semiconductor device 1D according to the fourth embodiment of the present technology basically has a configuration similar to that of the semiconductor device 1C according to the third embodiment described above, and is different in the following configuration.

[0299] That is, Figure 33 to Figure 35 As shown, a semiconductor device 1D according to a fourth embodiment of the present technology includes: two semiconductor portions 3 (3A5 and 3A6) arranged parallel to a lateral direction aligned with the X direction; and a field effect transistor Qd, wherein a gate electrode 7 is provided on each of the two semiconductor portions 3 (3A5 and 3A6) with a gate insulating film 6 interposed therebetween.

[0300] The field effect transistor Qd basically has a configuration similar to that of the above-described field effect transistor Qa, and is different in the configuration of the gate electrode 7. The other structures are substantially the same as those of the above-described field effect transistor Qa.

[0301] like Figure 33 to Figure 35 As shown, the gate electrode 7 of the field effect transistor Qd includes a head portion 7a, which is arranged on the upper surface portion 3a side of each of the two semiconductor portions 3 (3A5 and 3A6), a gate insulating film 6 is interposed between the head portions and extends in the lateral direction (X direction) above the two semiconductor portions 3 (3A5 and 3A6), and three leg portions 7b1, 7b2 and 7b3, which are integrally formed with the head portion 7a and are arranged side by side in the lateral direction of each of the two semiconductor portions 3 (3A5 and 3A6).

[0302] like Fig.34 As shown, the leg portion 7b1 is provided outside one side portion 3c1 located on both lateral sides of one semiconductor portion 3 (3A5) of the two semiconductor portions 3 (3A5 and 3A6) among the two side portions 3c1 and 3c2 with the gate insulating film 6 interposed therebetween.

[0303] The leg portion 7b2 is provided outside the other side surface portion 3c2 located on both sides of the other semiconductor portion 3 (3A6) of the two semiconductor portions 3 (3A5 and 3A6) in the lateral direction of the other semiconductor portion 3 (3A6) of the two side surface portions 3c1 and 3c2 with the gate insulating film 6 interposed therebetween.

[0304] The leg portion 7b3 is provided between the two semiconductor portions 3 (3A5 and 3A6). Then, in the two semiconductor portions 3 (3A5 and 3A6), the leg portion 7b3 is adjacent to the other side portion 3c2 (with the gate insulating film 6 interposed therebetween) of the two side portions 3c1 and 3c2 located on both sides in the lateral direction of one semiconductor portion 3 (3A5), and is adjacent to one side portion 3c1 (with the gate insulating film 6 interposed therebetween) of the two side portions 3c1 and 3c2 located on both sides in the lateral direction of the other semiconductor portion 3 (3A6).

[0305] Here, the semiconductor device 1D of the fourth embodiment includes contact electrodes 17 a and 17 b similarly to the semiconductor device 1C of the third embodiment. However, the contact electrodes 17 a and 17 b of the fourth embodiment are connected to the side surfaces of the two semiconductor portions 3 ( 3A5 and 3A6 ), respectively.

[0306] Specifically, Fig.33 and Fig.35 As shown, in the two semiconductor portions 3 (3A5 and 3A6), the contact electrode 17a of the fourth embodiment is selectively connected to the other side portion 3c2 of the two side portions 3c1 and 3c2 located on both sides in the lateral direction of one semiconductor portion 3 (3A5) and one side portion 3c1 of the two side portions 3c1 and 3c2 located on both sides in the lateral direction of the other semiconductor portion 3 (3A6). Then, in the contact electrode 17b of the fourth embodiment, similar to the contact electrode 17a of the fourth embodiment, in the two semiconductor portions 3 (3A5, 3A6), the other side portion 3c2 located in the lateral direction of one semiconductor portion 3 (3A5) and one side portion 3c1 located in the lateral direction of the other semiconductor portion 3 (3A6) are selectively connected.

[0307] That is, each of the contact electrodes 17a, 17b of the fourth embodiment is connected to the upper surface portion 3a of each of the two semiconductor portions 33 (3A5, 3A6), and as a side surface portion of each of the two semiconductor portions 3 (3A5, 3A6), is selectively connected to another side surface portion 3c2 located in the lateral direction of one semiconductor portion 3 (3A5) and a side surface portion 3c1 located in the lateral direction of the other semiconductor portion 3 (3A6).

[0308] Also in the semiconductor device 1D according to the fourth embodiment, effects similar to those of the semiconductor device 1C according to the above-described third embodiment can be obtained.

[0309] It should be noted that in Fig.33 In the above-mentioned first embodiment, Figure 1 Similarly, for convenience of description, illustration of layers higher than the insulating layer 14 is omitted.

[0310] [Fifth Embodiment]

[0311] In the fifth embodiment, reference is made to Figure 36 to Figure 39 An example in which the present technology is applied to a solid-state imaging device called a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor as a light detection device included in a semiconductor device is described.

[0312] <<Overall Configuration of Solid-State Imaging Device>>

[0313] First, the overall configuration of the solid-state imaging device 1E will be described.

[0314] like Fig.36 As shown, the solid-state imaging device 1E according to the fifth embodiment of the present technology mainly includes a semiconductor chip 102 having a two-dimensional planar shape of a square in a plan view. That is, the solid-state imaging device 1E is mounted on the semiconductor chip 102, and the semiconductor chip 102 can be regarded as the solid-state imaging device 1E. Fig.103 As shown, the solid-state imaging device 1E (201) acquires image light (incident light 206) from an object via an optical lens 202, converts the light amount of the incident light 206 formed on the imaging surface into an electrical signal in pixels, and outputs the electrical signal as a pixel signal (image signal).

[0315] like Fig.36 As shown, the semiconductor chip 102 on which the solid-state imaging device 1E is mounted includes: a rectangular pixel array unit 102A, which is arranged in the central part in a two-dimensional plane including an X direction and a Y direction orthogonal to each other; and a peripheral part 102B, which is arranged outside the pixel array unit 102A to surround the pixel array unit 102A. The semiconductor chip 102 is formed by breaking a semiconductor wafer including a semiconductor layer 130 described later according to each chip forming area in the manufacturing process. Therefore, even in the wafer state before the semiconductor wafer is divided into small pieces, the configuration of the solid-state imaging device 1E described below is basically similar. That is, the present technology can be applied to the state of the semiconductor chip and the state of the semiconductor wafer.

[0316] The pixel array unit 102A receives, for example, Fig.103 The optical lens (optical system) 202 shown in FIG. 1 is a light receiving surface of light that is focused by the optical lens (optical system) 202 shown in FIG. Then, in the pixel array unit 102A, a plurality of pixels 103 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 103 are repeatedly arranged in the X direction and the Y direction orthogonal to each other in the two-dimensional plane.

[0317] like Fig.36As shown, a plurality of pads 114 are arranged in the peripheral portion 102B. For example, each of the plurality of pads 114 is arranged along each of four sides in a two-dimensional plane of the semiconductor chip 102. Each of the plurality of pads 114 serves as an input / output terminal for electrically connecting the semiconductor chip 102 and an external device.

[0318] <Logic Circuit>

[0319] The semiconductor chip 102 includes Fig.37 The logic circuit 113 shown in FIG. Fig.37 As shown, the logic circuit 113 includes a vertical drive circuit 104, a column signal processing circuit 105, a horizontal drive circuit 106, an output circuit 107, a control circuit 108, etc. The logic circuit 113 includes, for example, a complementary MOS (CMOS) circuit including an n-channel conductive type metal oxide semiconductor field effect transistor (MOSFET) and a p-channel conductive type MOSFET as field effect transistors.

[0320] The vertical drive circuit 104 includes, for example, a shift register. The vertical drive circuit 104 sequentially selects a desired pixel drive line 110, supplies a pulse for driving the pixel 103 to the selected pixel drive line 110, and drives each pixel 103 row by row. That is, the vertical drive circuit 104 sequentially and selectively scans each pixel 103 of the pixel array unit 102A in the vertical direction in units of rows, and supplies a pixel signal from the pixel 103 to the column signal processing circuit 105 through the vertical signal line 111 based on a signal charge generated according to the amount of light received by the photoelectric conversion unit (photoelectric conversion element) of each pixel 103.

[0321] The column signal processing circuit 105 is arranged, for example, for each column of the pixels 103, and performs signal processing such as noise removal for each pixel column on the signals output from the pixels 103 of one row. For example, the column signal processing circuit 105 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion for removing pixel-specific fixed pattern noise.

[0322] The horizontal drive circuit 106 includes, for example, a shift register. The horizontal drive circuit 106 sequentially outputs horizontal scanning pulses to the column signal processing circuits 105 to sequentially select each of the column signal processing circuits 105 and causes each of the column signal processing circuits 105 to output a pixel signal subjected to signal processing to the horizontal signal line 112.

[0323] The output circuit 107 performs signal processing on pixel signals sequentially supplied from each column signal processing circuit 105 through the horizontal signal line 112 and outputs the pixel signals. As the signal processing, for example, buffering, black level adjustment, column variation correction, various digital signal processing, etc. can be used.

[0324] The control circuit 108 generates a clock signal or a control signal used as a reference for the operation of the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, etc. based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock signal. Then, the control circuit 108 outputs the generated clock signal and control signal to the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, etc.

[0325] <Circuit Configuration of Pixel>

[0326] Fig.36 and Fig.37 Each of the plurality of pixels 103 shown in FIG. 1 includes Fig.38 . The photoelectric conversion region 121 and the pixel circuit (readout circuit) 115 shown in . The photoelectric conversion region 121 includes a photoelectric conversion unit 124, a transfer transistor TR, and a charge holding region (floating diffusion) FD. The pixel circuit 115 is electrically connected to the charge holding region FD of the photoelectric conversion region 121. In the fifth embodiment, as an example, one pixel circuit 115 is assigned to one pixel 103, but the circuit configuration is not limited thereto, and one pixel circuit 115 can be shared by a plurality of pixels 103. For example, a circuit configuration can be adopted in which one pixel circuit 115 is shared by four pixels 103 (one pixel block) arranged in 2×2, with two pixels arranged in each of the X direction and the Y direction.

[0327] For example, Fig.38 The photoelectric conversion unit 124 shown in FIG. 1 includes a pn junction photodiode (PD) and generates signal charge according to the amount of light received. In the photoelectric conversion unit 124, the cathode side is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (eg, ground).

[0328] Fig.38 The transfer transistor TR shown in FIG. transfers the signal charge photoelectrically converted by the photoelectric conversion unit 124 to the charge holding region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 124, and the drain region of the transfer transistor TR is electrically connected to the charge holding region FD. Then, the gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line of the pixel drive line 110 (see FIG. Fig.37 ).

[0329] Fig.38The charge holding region FD shown in FIG. 1 temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion unit 124 via the transfer transistor TR.

[0330] The photoelectric conversion unit 124, the transfer transistor TR, and the photoelectric conversion region 121 including the charge holding region FD are mounted on the semiconductor layer 130 (see Fig.39 ) on top, as a second semiconductor layer described later.

[0331] Fig.38 The pixel circuit 115 shown in reads the signal charge held in the charge holding area FD, converts the read signal charge into a pixel signal, and outputs the pixel signal. In other words, the pixel circuit 115 converts the signal charge photoelectrically converted by the photoelectric conversion unit 124 into a pixel signal based on the signal charge and outputs the pixel signal. The pixel circuit 115 includes, but is not limited to, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and a switch transistor FDG, for example, as a pixel transistor. Each of these pixel transistors (AMP, SEL, RST, and FDG) and the above-mentioned transfer transistor TR is configured as a field effect transistor by, for example, a MOSFET. In addition, these transistors can be MISFETs.

[0332] Among the pixel transistors included in the pixel circuit 115, each of the selection transistor SEL, the reset transistor RST, and the switching transistor FDG functions as a switching element, and the amplifier transistor AMP functions as an amplification element. That is, the pixel circuit 115 includes field effect transistors for different applications.

[0333] It should be noted that the selection transistor SEL and the switching transistor FDG may be omitted as necessary.

[0334] like Fig.38 As shown, in the amplifier transistor AMP, the source region is electrically connected to the drain region of the selection transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. Then, the gate electrode of the amplifier transistor AMP is electrically connected to the charge holding region FD and the source region of the switching transistor FDG.

[0335] The source of the selection transistor SEL is electrically connected to the vertical signal line 111 (VSL), and its drain region is electrically connected to the source region of the amplifier transistor AMP. Then, the gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line of the pixel drive line 110 (see Fig.37 ).

[0336] The reset transistor RST has a source region electrically connected to the drain region of the switching transistor FDG, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. Then, the gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line among the pixel drive lines 110 (see Fig.37 ).

[0337] The switching transistor FDG has a source region electrically connected to the charge holding region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. Then, the gate electrode of the switching transistor FDG is electrically connected to the switching transistor driving line of the pixel driving line 110 (see Fig.37 ).

[0338] It should be noted that when the selection transistor SEL is omitted, the source region of the amplifier transistor AMP is electrically connected to the vertical signal line 111 (VSL). In addition, when the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplifier transistor AMP and the charge holding region FD.

[0339] When the transfer transistor TR is turned on, the transfer transistor TR transfers the signal charge generated by the photoelectric conversion unit 124 to the charge holding region FD.

[0340] When the reset transistor RST is turned on, the reset transistor RST resets the potential (signal charge) of the charge holding region FD to the potential of the power supply line Vdd. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 115.

[0341] The amplifier transistor AMP generates a signal having a voltage corresponding to the level of the signal charge held in the charge holding region FD as a pixel signal. The amplifier transistor AMP constitutes a source follower type amplifier, and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated by the photoelectric conversion unit 124. When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the charge holding region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 105 via the vertical signal line 111 (VSL).

[0342] The switching transistor FDG controls charge retention by the charge retention region FD, and adjusts a multiplication factor of a voltage according to the potential amplified by the amplification transistor AMP.

[0343] During the operation of the solid-state imaging device 1E according to the fifth embodiment, the signal charge generated in the photoelectric conversion unit 124 of the pixel 103 is held (accumulated) in the charge holding region FD via the transfer transistor TR of the pixel 103. Then, the signal charge held in the charge holding region FD is read by the pixel circuit 115 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 115. The horizontal line selection control signal is supplied from the vertical shift register to the gate electrode of the selection transistor SEL of the pixel circuit 115. Then, by setting the selection control signal to a high (H) level, the selection transistor SEL is turned on, and a current corresponding to the potential of the charge holding region FD amplified by the amplifier transistor AMP flows through the vertical signal line 111. In addition, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 115 to a high (H) level, the reset transistor RST is turned on, and the signal charge accumulated in the charge holding region FD is reset.

[0344] <<Longitudinal Cross-Sectional Structure of Solid-State Imaging Device>>

[0345] Next, we will refer to Fig.39 A longitudinal cross-sectional structure of the semiconductor chip 102 (solid-state imaging device 1E) is described. Fig.39 It shows Fig.36 A schematic longitudinal cross-sectional view of a longitudinal cross-sectional structure in a pixel array unit, and relative to Fig.36 It is upside down to make the drawing easier to see.

[0346] <Semiconductor Chip>

[0347] like Fig.39 As shown, the semiconductor chip 102 includes: a semiconductor layer 130 having a first surface S1 and a second surface S2 located at opposite sides in a thickness direction (Z direction); and an insulating layer 131 disposed on the first surface S1 side of the semiconductor layer 130 .

[0348] Furthermore, on the second surface S2 side of the semiconductor layer 130 , the semiconductor chip 102 includes a planarization layer 141 , a color filter layer 142 , a lens layer 143 , and the like which are sequentially laminated from the second surface S2 side.

[0349] Furthermore, the semiconductor chip 102 includes an insulating layer 14 provided on the side of the insulating layer 131 opposite to the semiconductor layer 130 side. The insulating layer 14 of the fifth embodiment has the same structure as that of the first embodiment described above as an example. Figures 2 to 4 The configuration of the insulating layer 14 shown in FIG. 1 is similar to that of FIG. 1 , and includes an island-shaped semiconductor portion 3 and a field effect transistor Qa in which a gate electrode 7 is provided in the semiconductor portion 3 with a gate insulating film 6 interposed therebetween.

[0350] The semiconductor chip 102 further includes contact electrodes 17a and 17b, which are provided on the insulating layer 14 so as to overlap with the island-shaped semiconductor portion 3 in a plan view. The contact electrodes 17a and 17b of the fifth embodiment are different from those of the first embodiment. Figures 2 to 4 The contact electrodes 17a, 17b shown are identical.

[0351] The semiconductor layer 130 is made of, for example, single crystal silicon.

[0352] The planarization layer 141 is composed of, for example, a silicon oxide film. Then, the planarization layer 141 covers the entire second surface S2 side of the semiconductor layer 130 in the pixel array unit 102A so that the second surface S2 (light incident surface) side of the semiconductor layer 130 is an uneven plane.

[0353] In the color filter layer 142 , color filters such as red (R), green (G), and blue (B) are provided for each pixel 103 , and incident light incident from the light incident surface side of the semiconductor chip 102 is color-separated.

[0354] In the lens layer 143 , a microlens is provided for each pixel 103 , and the microlens collects the irradiated light and efficiently causes the collected light to enter the photoelectric conversion region 121 .

[0355] The semiconductor layer 130 is arranged to overlap with the semiconductor portion 5. That is, the semiconductor chip 102 has a two-step structure in which the semiconductor layer 130 and the semiconductor portion 3 are stacked in each thickness direction (Z direction).

[0356] In the fifth embodiment, although not shown in detail, Fig.38 Each of the photoelectric conversion unit 124, the transfer transistor TR, and the charge holding region FD shown in FIG. Fig.39 In the semiconductor layer 130 shown in FIG.

[0357] At the same time, including Fig.38 Each pixel transistor (AMP, SEL, RST and FDG) in the pixel circuit 115 includes Fig.39 The field effect transistor Qa shown in FIG. Then, in Fig.39 , an amplifier transistor AMP including a field effect transistor Qa is shown as an example.

[0358] <<Main Effects of the Fifth Embodiment>>

[0359] In the solid-state imaging device 1E according to the fifth embodiment, each of the pixel transistors (AMP, SEL, RST, and FDG) included in the pixel circuit 115 includes a field effect transistor Qa provided in the semiconductor portion 3. Moreover, the contact electrode 17a of the contact electrodes 17a and 17b provided on both end sides of the semiconductor portion 3 in the length direction in a manner overlapping the semiconductor portion 3 is connected to the upper surface portion 3a of the semiconductor portion 3, and is respectively connected to the side portions of the semiconductor portion 3, that is, the three side portions 3c1, 3c2, and 3c3, as in the above-mentioned first embodiment. In addition, the contact electrodes 17b provided on both end sides of the semiconductor portion 3 in the length direction in a manner overlapping the semiconductor portion 3 are also connected to the upper surface portion 3a of the semiconductor portion 3, as in the above-mentioned first embodiment, and are respectively connected to the three side portions 3c1, 3c2, and 3c4 as the side portions of the semiconductor portion 3.

[0360] Therefore, according to the solid-state imaging device 1E of the fifth embodiment, similarly to the above-described first embodiment, the transconductance (gm) of each of the pixel transistors (AMP, SEL, RST, and FDG) included in the pixel circuit 115 can be improved.

[0361] In addition, even if the lateral (Y direction) width W2 of the semiconductor portion 3 and the width W1 (diameter, thickness) of the contact electrodes 17a and 17b decrease as the pixel transistors (AMP, SEL, RST, FDG) included in the pixel circuit 115 are miniaturized, the increase in the contact resistance between the semiconductor portion 3 and the contact electrodes 17a and 17b can be suppressed, and the reduction in transconductance (gm) can be suppressed while miniaturizing the pixel transistors (AMP, SEL, RST, FDG).

[0362] Here, in the amplifier transistor AMP, it is important to suppress the degradation of noise resistance such as 1 / f noise or RTS noise compared to the pixel transistors (SEL, RST, and FDG) used as switching elements. Therefore, in the case where the present technology is applied to the connection between the semiconductor portion 3 and the contact electrode provided with the amplifier transistor AMP included in the pixel circuit 115, the effectiveness is particularly high.

[0363] In the fifth embodiment, the connection method of the first embodiment is described as a connection method for connecting the contact electrodes 17a and 17b to the semiconductor unit 3. However, the connection methods in the other embodiments and modified examples described above can also be applied to the fifth embodiment.

[0364] In addition, at least one of the pixel transistors (AMP, SEL, RST, or FDG) included in the pixel circuit 115 may be configured by a field effect transistor Qa provided in the semiconductor portion 3 .

[0365] [Sixth Embodiment]

[0366] In a sixth embodiment, a semiconductor device having a contact electrode formed in the same layer as a gate electrode of a field effect transistor will be described.

[0367] First, refer to Fig.40 , Fig.41 , Fig.41A , Fig.42 as well as Fig.43 The overall configuration of the semiconductor device 1F is described. Fig.40 In order to facilitate the description, the Fig.41 , Fig.42 and Fig.43 2 is a diagram of upper layers (buffer insulating film 42, third insulating film 46, contact electrodes 49a, 49b and 49c, wirings 50a, 50b and 50c, etc.) other than sidewall spacers 41a, 41b and 41c shown in FIG.

[0368] like Figure 40 to Figure 43 As shown, the semiconductor device 1F according to the sixth embodiment of the present technology includes an island-shaped semiconductor portion 33 and a field effect transistor Qf, in which a channel forming portion (channel region) 45 is provided in the island-shaped semiconductor portion 33 .

[0369] In addition, if Figure 40 to Figure 43 As shown, the semiconductor device 1F according to the sixth embodiment of the present technology further includes: an insulating layer 47 including the semiconductor portion 33 and the field effect transistor Qf; and contact electrodes 38a and 38b provided on the insulating layer 47 so as to overlap with the island-shaped semiconductor portion 33 in a plan view.

[0370] In addition, if Figure 41 to Figure 43 As shown in , the semiconductor device 1F according to the sixth embodiment of the present technology further includes contact electrodes 49 a and 49 b provided in the insulating layer 47 so as to overlap with the contact electrodes 38 a and 38 b , respectively.

[0371] Here, in the sixth embodiment, the contact electrodes 38a and 38b correspond to a specific example of the “contact electrode” or the “first contact electrode” of the present technology, and the contact electrodes 49a and 49b correspond to a specific example of the “second contact electrode” of the present technology.

[0372] <Semiconductor Division>

[0373] like Figure 40 to Figure 43As shown in , the semiconductor portion 33 has, for example, a rectangular parallelepiped shape, which has an upper surface portion 33a, a lower surface portion (bottom surface portion) 33b and four side surface portions 33c1, 33c2, 33c3 and 33c4. Then, as an example, the semiconductor portion 33 extends in the Y direction, the thickness direction is the Z direction, the longitudinal direction is the Y direction, and the lateral direction is the X direction. The upper surface portion 33a and the lower surface portion 33b are located on opposite sides in the thickness direction (Z direction) of the semiconductor portion 33. Among the four side surface portions 33c1, 33c2, 33c3 and 33c4, two side surface portions 33c1 and 33c2 are located on opposite sides in the X direction, and the remaining two side surface portions 33c3 and 33c4 are located on opposite sides in the Y direction.

[0374] Here, in the sixth embodiment, the semiconductor portion 33 corresponds to a specific example of the "semiconductor portion" of the present technology. Then, the four side surface portions 33c1, 33c2, 33c3, and 33c4 of the semiconductor portion 33 correspond to a specific example of the "side surface portion of the semiconductor portion" of the present technology. Then, the four side surface portions 33c1, 33c2, 33c3, and 33c4 may be referred to as a first side surface portion 33c1, a second side surface portion 33c2, a third side surface portion 33c3, and a fourth side surface portion 33c4, respectively.

[0375] Furthermore, in the sixth embodiment, the lateral direction of the semiconductor portion 33 corresponds to a specific example of the “first direction of the semiconductor portion” of the present technology, and the longitudinal direction of the semiconductor portion 33 corresponds to a specific example of the “second direction of the semiconductor portion” of the present technology. Then, the side surface portions 33c3 and 33c4 located on the end side in the longitudinal direction (second direction) of the semiconductor portion 33 correspond to a specific example of the “end in the second direction intersecting with the first direction of the semiconductor portion” of the present technology.

[0376] Although not limited thereto, similar to the above-mentioned semiconductor portion 3, the semiconductor portion 33 is composed of, for example, silicon (Si) as a semiconductor material (for example, as a crystalline single crystal) and, for example, i-type (intrinsic type) as a conductivity type. That is, the semiconductor portion 33 is composed of i-type single crystal silicon. In addition to Si, germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), etc. can also be used as the material of the semiconductor portion 33.

[0377] <Insulation layer>

[0378] like Figure 40 to Figure 43As shown in , the insulating layer 47 has a multilayer structure, which includes but is not limited to a first insulating film (substrate insulating film) 32 disposed on the side of the lower surface portion 33b opposite to the upper surface portion 33a of the semiconductor portion 33 to contact the lower surface portion 33b; a second insulating film (surrounding insulating film) 34 disposed on the first insulating film 32 to surround the semiconductor portion 33; and a third insulating film (covering insulating film) 46 disposed on the second insulating film 34 to cover the semiconductor portion 33 and the field effect transistor Qf. Then, the insulating layer 47 of the sixth embodiment further includes but is not limited to the buffer insulating film 42. Each of the first insulating film 32, the second insulating film 34, the third insulating film 46 and the buffer insulating film 42 is composed of, for example, a silicon oxide (SiO2) film. That is, the semiconductor device 1F of the first embodiment has a silicon-on-insulator (SOI) structure in which the semiconductor portion 33 of silicon (Si) is disposed on the first insulating film 32. In addition, the insulating layer 47 includes the semiconductor portion 33 and the field effect transistor Qf.

[0379] <Contact Electrode>

[0380] like Fig.41 and Fig.43 As shown in FIG. 1 , the contact electrode 38a is provided on the side of one side surface portion 33c3 of two side surface portions 33c3 and 33c4 located in the longitudinal direction (Y direction) of the semiconductor portion 33 so as to overlap with the semiconductor portion 33 in a plan view. The contact electrode 38a includes: a head portion 38A1 protruding upward from the second insulating film 34 included in the insulating layer 47 and covered by the buffer insulating film 42 and the third insulating film 46 included in the insulating layer 47; and a leg portion 38A2 formed integrally with the head portion 38A1 and provided in the groove portion 35a between the second insulating film 34 and the semiconductor portion 33.

[0381] like Fig.41 As shown, the contact electrode 38b is provided on the other side surface portion 33c4 side of the two side surface portions 33c3 and 33c4 located in the longitudinal direction (Y direction) of the semiconductor portion 33 so as to overlap with the semiconductor portion 33 in a plan view. The contact electrode 38b includes: a head portion 38b1 protruding upward from the second insulating film 34 included in the insulating layer 47 and covered by the buffer insulating film 42 and the third insulating film 46 included in the insulating layer 47; and a leg portion 38b2 formed integrally with the head portion 38b1 and provided in the groove portion 35b between the second insulating film 34 and the semiconductor portion 33.

[0382] <Field Effect Transistor>

[0383] The field effect transistor Qf is not limited thereto, but is configured to have, for example, an n-channel conductivity type. Then, the field effect transistor Qf includes a MOSFET using a silicon oxide (SiO2) film as a gate insulating film. The field effect transistor Qf can be a p-channel conductivity type. In addition, a MISFET whose gate insulating film is a stacked film (composite film) of a silicon nitride film or a silicon nitride (Si3N4) film, a silicon oxide film, etc. can also be used.

[0384] like Figure 41 to Figure 43 As shown, the field effect transistor Qf includes a channel forming portion 45 arranged in the semiconductor portion 33, and a gate electrode 37 arranged on the upper surface portion 33a and two side surface portions 33c3 and 33c4 of the semiconductor portion 33, wherein the gate insulating film 36 is inserted in the channel forming portion 45 of the semiconductor portion 33 in the lateral direction (X direction) of the semiconductor portion 33.

[0385] In addition, the field effect transistor Qf further includes a pair of main electrode regions 44a and 44b, which are arranged outside the semiconductor portion 33 to be separated from each other in the channel length direction (gate length direction) of the channel forming portion 45, with the channel forming portion 45 interposed therebetween. In other words, the field effect transistor Qf includes a pair of main electrode regions 44a and 44b arranged in the semiconductor portion 33 on both sides of the gate length direction of the gate electrode 37. The pair of main electrode regions 44a and 44b serve as a source region and a drain region.

[0386] Here, for convenience of description, one main electrode region 44 a of the pair of main electrode regions 44 a and 44 b may be referred to as a source region 44 a , and the other main electrode region 44 b may be referred to as a drain region 44 b .

[0387] In addition, the distance between the pair of main electrode regions 44a and 44b is the channel length (L) of the channel forming portion 45 (the gate length (Lg) of the gate electrode 7), and the direction of the channel length is referred to as the channel length direction (gate length direction). Then, the direction of the channel width (W) (gate width (Wg)) of the channel forming portion 45 is referred to as the channel width direction (gate width direction). Thus, in the sixth embodiment, as an example, the pair of main electrode regions 44a and 44b are separated in the Y direction via the channel forming portion 45, and therefore the channel length direction is the Y direction.

[0388] In the field effect transistor Qf, a channel (inversion layer) electrically connecting the source region (main electrode region) 44a and the drain region (another main electrode region) 44b is formed (induced) in the channel forming portion 45 by the voltage applied to the gate electrode 37, and a current (drain current) flows from the drain region 44b side through the channel forming portion 45 to the source region 45a side.

[0389] <Gate Electrode>

[0390] like Fig.41 and Fig.42 As shown, the gate electrode 37 includes, but is not limited to, for example, a head (first portion) 37a provided on the upper surface portion 33a side of the semiconductor portion 33, with the gate insulating film 36 interposed therebetween; and two leg portions (second portions) 37b1 and 37b2, which are integrally formed with the head 37a and provided on the outer side of each of the two side surface portions 33c1 and 33c2 located on the opposite sides in the lateral direction (X direction) of the semiconductor portion 33, with the gate insulating film 36 interposed therebetween. That is, the gate electrode 37 is provided on the upper surface portion 33a and the two side surface portions 33c1 and 33c2 of the semiconductor portion 33, and has a C-shaped cross-sectional shape orthogonal to the longitudinal direction (Y direction) of the semiconductor portion 33. The gate electrode 37 is composed of, for example, a polysilicon film into which impurities for reducing the resistance value are introduced.

[0391] Here, the semiconductor portion 33 is preferably sandwiched between the legs of the gate electrode 37 from both sides in the lateral direction (X direction) of the semiconductor portion 33. Therefore, when the number of semiconductor portions 33 is "n", the leg of the gate electrode 37 is generally "n+1". In the sixth embodiment, since the gate electrode 37 is provided in one semiconductor portion 33, the gate electrode 37 has two legs 37b1 and 37b2.

[0392] like Fig.41 and Fig.42 As shown, the head 37a of the gate electrode 37 protrudes upward from the second insulating film 34 included in the insulating layer 47, and is further covered by the buffer insulating film 42 and the third insulating film 46 included in the insulating layer 47. Then, the two leg portions 37b1 and 37b2 of the gate electrode 37 are separately disposed in the grooved portions 35c1 and 35c2 between the second insulating film 34 and the semiconductor portion 33.

[0393] <Gate Insulating Film>

[0394] Over the upper surface portion 33a and both side surface portions 33c1 and 33c2 of the semiconductor portion 33, a gate insulating film 36 is provided between the semiconductor portion 33 and the gate electrode 37. The gate insulating film 36 is composed of, for example, a silicon oxide film.

[0395] <Sidewall Spacer>

[0396] like Figure 40 to Figure 43As shown in FIG. 1 , the sidewall spacer 41a is provided on the sidewall of the head 38A1 of the contact electrode 38a so as to surround the periphery of the head 38A1. In addition, the sidewall spacer 41b is provided on the sidewall of the head 38b1 of the contact electrode 38b so as to surround the periphery of the head 38b1. Moreover, the sidewall spacer 41c is provided on the sidewall of the head 37a of the gate electrode 37 so as to surround the periphery of the head 37a.

[0397] The sidewall spacer 41a extends on the second insulating film 34 of the insulating layer 47 and on the semiconductor portion 33, and is formed to be aligned with the head portion 38A1 of the contact electrode 38a (see FIG. 1 ). Fig.40 , Fig.41 and Fig.43 ).

[0398] The sidewall spacer 41b extends on the second insulating film 34 of the insulating layer 47 and on the semiconductor portion 33, and is formed to be aligned with the head portion 38b1 of the contact electrode 38b (see FIG. Fig.40 and Fig.41 ).

[0399] The sidewall spacer 41c extends on the second insulating film 34 of the insulating layer 47 and on the semiconductor portion 33, and is formed to be aligned with the head portion 37a of the gate electrode 37 (see FIG. 1 ). Fig.40 , Fig.41 and Fig.42 ).

[0400] For example, an insulating film (spacer material) may be formed on the second insulating film 34 by a CVD method to cover the head portions 37a, 38A1, and 38b of the gate electrode 37 and the contact electrodes 38a and 38b, and then anisotropic dry etching such as reactive ion etching (RIE) may be applied to the insulating film to form each of the sidewall spacers 41a, 41b, and 41c. That is, the sidewall spacers 41a, 41b, and 41c of Embodiment 6 are formed on the same layer.

[0401] Here, “sidewall spacers 41 a , 41 b , and 41 c are formed in the same layer” means “sidewall spacers 41 a , 41 b , and 41 c are formed by the same step and the same material”.

[0402] The side wall spacers 41a, 41b and 41c are composed of a material having a selectivity ratio with respect to the second insulating film 34, the semiconductor layer 33, the gate electrode 37, and the contact electrodes 38a and 38b. In the sixth embodiment, the side wall spacers 41a, 41b and 41c are composed of, for example, a silicon nitride film having selectivity with respect to each of the silicon oxide film of the insulating layer 47, the single crystal silicon of the semiconductor portion 3, and the polycrystalline silicon of the gate electrode 37 and the contact electrodes 38a and 38b. The side wall spacers 41a, 41b and 41c respectively ensure that the n-type semiconductor regions 43a and 43b (see FIG. 1 ) included in a pair of main electrode regions 44a and 44b described later are spaced apart from each other. Fig.41 ) between the two.

[0403] <Buffer Insulating Film>

[0404] like Figure 41 to Figure 43 As shown in FIG. 1 , the buffer insulating film 42 included in the insulating layer 47 covers the head 37a of the gate electrode 37 and the heads 38A1 and 38b1 of each of the two contact electrodes 38a and 38b, and covers each of the sidewall spacers 41a, 41b, and 41c. The buffer insulating film 42 is used as a buffer film when ion-implanting impurities in the step of forming n-type semiconductor regions 43a and 43b described later, and is composed of, for example, a silicon oxide film.

[0405] <Main Electrode Area>

[0406] like Fig.41 As shown, one main electrode region 44a of a pair of main electrode regions 44a and 44b is provided on the side of one side portion 33c3 of two side portions 33c3 and 33c4 located in the longitudinal direction (Y direction) of the semiconductor portion 33. Then, the one main electrode region 44a includes the n-type semiconductor region 39a, the n-type semiconductor region 40a having an impurity concentration lower than that of the n-type semiconductor region 39a, and the n-type semiconductor region 43a having an impurity concentration higher than that of the n-type semiconductor region 39a.

[0407] like Fig.41 and Fig.43 As shown in FIG. 1 , n-type semiconductor region 39a has a three-dimensional structure extending from upper surface portion 33a to lower surface portion 33b along three side surface portions 33c1, 33c2, and 33c3 of semiconductor portion 33. N-type semiconductor region 39a may be formed by diffusing impurities from contact electrode 38a into semiconductor portion 33.

[0408] like Fig.41As shown, in a top view, an n-type semiconductor region 40a is disposed in contact with an n-type semiconductor region 39a in the semiconductor portion 33 located between the contact electrode 38a and the gate electrode 37. Then, the n-type semiconductor region 40a is formed to be aligned with the head portion 37a of the gate electrode 37 and to extend from the upper surface portion 33a to the lower surface portion 33b of the semiconductor portion 33. The n-type semiconductor region 40a serves as an extension region.

[0409] like Fig.41 As shown, the n-type semiconductor region 43a is provided on the upper surface portion 33a side of the semiconductor portion 33 and in the surface layer portion of the n-type semiconductor region 40a so as to contact the n-type semiconductor region 40a and the n-type semiconductor region 39a. Then, the n-type semiconductor region 43a is formed to be aligned with the side wall spacer 41a of the side wall of the head portion 38A1 of the contact electrode 38a and the side wall spacer 41c of the side wall of the head portion 37a of the gate electrode 37.

[0410] In the sixth embodiment, each of the n-type semiconductor region 39 a and the n-type semiconductor region 40 a is configured to have a depth of, for example, contact with the first insulating film 32 included in the insulating layer 47 , but is not limited thereto.

[0411] like Fig.41 As shown, the other main electrode region 44b of the pair of main electrode regions 44a and 44b is provided on the other side portion 33c4 side of the two side portions 33c3 and 33c4 located in the longitudinal direction (Y direction) of the semiconductor portion 33. Then, the other main electrode region 44b includes the n-type semiconductor region 39b, the n-type semiconductor region 40b having an impurity concentration lower than that of the n-type semiconductor region 39b, and the n-type semiconductor region 43b having an impurity concentration higher than that of the n-type semiconductor region 39b.

[0412] Although not shown in detail, similar to the n-type semiconductor region 39a, the n-type semiconductor region 39b has a three-dimensional structure extending from the upper surface portion 33a to the lower surface portion 33b along three side surface portions 33c1, 33c2, and 33c4 of the semiconductor portion 33. The n-type semiconductor region 39b can be formed by diffusing impurities from the contact electrode 38b into the semiconductor portion 33.

[0413] like Fig.41 As shown, in a plan view, an n-type semiconductor region 40b is provided to be in contact with an n-type semiconductor region 39b in the semiconductor portion 33 between the contact electrode 38b and the gate electrode 37. Then, the n-type semiconductor region 40b is formed to be aligned with the head portion 37a of the gate electrode 37 and to extend from the upper surface portion 33a to the lower surface portion 33b of the semiconductor portion 33. The n-type semiconductor region 40b serves as an extension region.

[0414] like Fig.41 As shown, the n-type semiconductor region 43b is provided on the upper surface portion 33a of the semiconductor portion 33 and in the surface layer portion of the n-type semiconductor region 40b so as to contact the n-type semiconductor region 40b and the n-type semiconductor region 39b. Then, the n-type semiconductor region 43b is formed in a manner aligned with the side wall spacer 41b of the side wall of the head 38b1 of the contact electrode 38b and the side wall spacer 41c of the side wall of the head 37a of the gate electrode 37.

[0415] In the sixth embodiment, for example, each of the n-type semiconductor region 39 b and the n-type semiconductor region 40 b is configured to have a depth in contact with the first insulating film 32 included in the semiconductor layer 47 , but is not limited thereto.

[0416] like Figure 40 to Figure 43 As shown in , the field effect transistor Qf of the sixth embodiment is configured as a so-called fin type in which a gate electrode 37 is provided in an island-shaped semiconductor portion 33 as a fin portion with a gate insulating film 36 interposed therebetween, similarly to the above-described field effect transistor Qa.

[0417] In the fin field effect transistor Qf, the length between a pair of main electrode regions 44a and 44b is the channel length L (≈gate length Lg), and in the region where the gate electrode 37 overlaps three-dimensionally with the semiconductor portion 33, the value obtained by multiplying the length including the lateral width W2 on the upper surface portion 33a side of the semiconductor portion 33 and the height of the side surface portions 3b1 and 3b2 of the semiconductor portion 33 (the length surrounding the semiconductor portion 3) by the number of semiconductor portions 33 is the channel width W (≈gate width).

[0418] Therefore, in the fin field effect transistor Qf, since the channel width W is increased by increasing the width W1 of the semiconductor portion 33 in the lateral direction (Y direction) and increasing the height of the semiconductor portion 33 in the thickness direction (Z direction), the effective channel area (channel length L×channel width W) can be increased. Then, the fin field effect transistor Qf can increase the channel area (channel length L×channel width W) by increasing the number of semiconductor portions 33. In the sixth embodiment, the case where the field effect transistor Qf is provided in one semiconductor portion 33 has been described, but a plurality of semiconductor portions 33 may exist.

[0419] Examples of the field effect transistor Qf include an enhancement type (normally off type) in which a drain current flows by applying a gate voltage equal to or higher than a threshold voltage to the gate electrode 37 and an inhibition type (normally off type) in which a drain current flows without applying a voltage to the gate electrode 37. In the sixth embodiment, although not limited to this, for example, an enhancement type is used. In the case of the enhancement type, in the field effect transistor Qf, a channel (inversion layer) electrically connecting a pair of main electrode regions 44a and 44b is formed (induced) in the channel forming portion 45 by a voltage applied to the gate electrode 37, and a current (drain current) flows from the drain region side (for example, the main electrode region 44b side) to the source region side (for example, the main electrode region 44a side) through the channel of the channel forming portion 45.

[0420] <Contact Electrode and Wiring>

[0421] like Fig.41 and Fig.42 As shown, the gate electrode 37 is electrically connected to the wiring 50c in the wiring layer provided on the insulating layer 47 via the contact electrode 49c provided in the groove portion 48c of the insulating layer 47 (specifically, the third insulating film 46). Fig.41 and Fig.43 As shown, the contact electrode 38a is electrically connected to the wiring 50a in the wiring layer provided on the insulating layer 47 via the contact electrode 49a (specifically, the third insulating film 46) provided in the groove portion 48a of the insulating layer 47. Fig.41 As shown, the contact electrode 38 b is electrically connected to a wiring 50 b in a wiring layer provided on the insulating layer 47 via a contact electrode 49 b (specifically, the third insulating film 46 ) provided in a groove portion 48 b of the insulating layer 47 .

[0422] like Fig.41 As shown, the contact electrode 49a is arranged to overlap with the contact electrode 38a in a plan view, and is electrically and mechanically connected to the contact electrode 38a. Similarly, the contact electrode 49b is arranged to overlap with the contact electrode 38b in a plan view, and is electrically and mechanically connected to the contact electrode 38b. In addition, the contact electrode 49c is arranged to overlap with the gate electrode 37 in a plan view, and is electrically and mechanically connected to the gate electrode 37.

[0423] For example, tungsten (W), a high melting point metal, can be used as the material of the contact electrodes 49a, 49b, and 49c. As the material of the wirings 50a, 50b, and 50c, for example, metal materials such as aluminum (Al) and copper (Cu), and alloy materials mainly composed of Al and Cu can be used.

[0424] <Connection between Contact Electrode and Semiconductor Section>

[0425] like Fig.41 and Fig.43 As shown in FIG. 1 , each of the contact electrodes 38 a and 38 b is connected to the upper surface portion 33 a and the side surface portion of the semiconductor portion 33 .

[0426] Specifically, Fig.41 and Fig.43 As shown in FIG. 1 , in the contact electrode 38a, on one end side (side surface portion 33c3 side) in the longitudinal direction of the semiconductor portion 33, the head portion 38A1 is connected to the upper surface portion 33a of the semiconductor portion 33, and the leg portion 38A2 is connected to the three side surface portions 33c1, 33c2, and 33c3 of the semiconductor portion 33. Then, the contact electrode 38a is electrically and mechanically connected to one main electrode region 44a provided on one end side (side surface portion 33c3 side) in the longitudinal direction of the semiconductor portion 33, of the pair of main electrode regions 44a and 44b.

[0427] Furthermore, although not shown in detail, similarly to the contact electrode 38a, in the contact electrode 38b as well, on the other end side (side side portion 33c4 side) in the longitudinal direction of the semiconductor portion 33, the head portion 38b1 is connected to the upper surface portion 33a of the semiconductor portion 33, and the leg portion 38b2 is connected to the three side portions 33c1, 33c2, and 33c4 of the semiconductor portion 33. Then, the contact electrode 38b is electrically and mechanically connected to the other main electrode region 44b provided on the other end side (side side portion 33c4 side) in the longitudinal direction of the semiconductor portion 33 in the pair of main electrode regions 44a, 44b.

[0428] <Material of contact electrode>

[0429] Fig.40 , Fig.41 and Fig.43 Each of the contact electrodes 38a and 38b shown in is composed of a polycrystalline semiconductor material. In the sixth embodiment, although not limited thereto, each of the contact electrodes 38a and 38b is composed of, for example, silicon (Si) as a semiconductor material, for example, a single crystal as a crystalline, for example, an n-type (intrinsic type) as a conductivity type. That is, each of the contact electrodes 38a and 38b is composed of n-type polycrystalline silicon as a semiconductor material. Then, each of the contact electrodes 38a and 38b is formed in the same layer as the gate electrode 37.

[0430] Here, “each of contact electrodes 38 a and 38 b is formed in the same layer as gate electrode 37 ” means “each of contact electrodes 38 a and 38 b is formed by the same step and the same material as gate electrode 37 ”. That is, in the step of patterning the gate material to form gate electrode 37 , each of contact electrodes 38 a and 38 b is formed together with gate electrode 37 .

[0431] Note that, as described above, the semiconductor portion 33 is composed of i-type single-crystal silicon. Also, as described above, the gate electrode 37 is composed of polycrystalline silicon.

[0432] <Thickness of Contact Electrode and Gate Electrode>

[0433] like Fig.41A As shown, in the contact electrode 38a, the thickness Th1 at the portion (head 38A1) overlapping with the semiconductor portion 33 in a plan view is substantially the same as the thickness Th3 at the portion (head 37a) overlapping with the semiconductor portion 33 of the gate electrode 37 in a plan view. In addition, in the contact electrode 38b, the thickness Th2 at the portion (head 38b1) overlapping with the semiconductor portion 33 in a plan view is substantially the same as the thickness Th3 at the portion (head 37a) overlapping with the semiconductor portion 33 of the gate electrode 37 in a plan view. That is, the thicknesses Th1, Th2, and Th3 of the contact electrodes 38a and 38b and the gate electrode 37 are substantially the same at the portions (head 38A1, head 38b1, head 37a) overlapping with the gate electrode 37 in a plan view.

[0434] In this way, by forming contact electrodes 38a and 38b in the same layer as the gate electrode 37, the thicknesses Th1 and Th2 at the corresponding portions (head portions 38A1 and 38b1) where the contact electrodes 38a and 38b overlap with the semiconductor portion 33 in a plan view can be made equal to the thickness Th3 at the portion (head portion 37a) where the gate electrode 37 overlaps with the semiconductor portion 33 in a plan view.

[0435] <Contact electrode width + sidewall spacer>

[0436] like Fig.40 As shown, in the lateral direction (X direction) of the semiconductor portion 33, the width W1a of the contact electrode 38a is wider than the width W2 of the semiconductor portion 33. Then, the width W5a (the width of the head 38A1 of the contact electrode 38a + the width of the sidewall spacer 41a × 2) including the head 38A1 of the contact electrode 38a and the sidewall spacer 41a respectively provided on both sides of the head 38A1 of the contact electrode 38a is narrower than the width W3 (the width of the head 38A1 of the gate electrode 37 + the width of the sidewall spacer 41c × 2) including the head 37a of the gate electrode 37 and the sidewall spacer 41c respectively provided on both sides of the gate electrode 37.

[0437] Similarly, in the lateral direction (X direction) of the semiconductor portion 33, the width W1b of the contact electrode 38b is also wider than the width W2 of the semiconductor portion 33. Furthermore, the width W5b (the width of the head 38A1 of the contact electrode 38a + the width of the sidewall spacer 41a × 2) of the head 38b1 of the contact electrode 38b and the sidewall spacers 41b respectively provided on both sides of the head 38b1 of the contact electrode 38b is also narrower than the width W3 (the width of the head 38A1 of the gate electrode 38a + the width of the sidewall spacer 41c × 2) of the head 37a of the gate electrode 37 and the sidewall spacers 41c respectively provided on both sides of the gate electrode 37.

[0438] <Oxide>

[0439] Here, although Fig.43 Not shown, but as Fig.54A and Fig.54B A plurality of oxides 33Y of a granular (spherical) insulator shown in FIG. 1 are dispersed at the interface portion between the semiconductor portion 33 and the contact electrodes 38a and 38b. Although the oxides 33Y will be described in detail later, Fig.51D and Fig.51E The natural oxide film 33X shown in FIG is changed by fluidization of heat treatment. The natural oxide film 33X composed of silicon oxide (SiO2) containing a large amount of impurities has a low melting point and is fluidized by heat treatment. As described above, by changing the natural oxide film 33X into a granular (spherical) oxide 33Y, the contact characteristics between the semiconductor portion 33 and the contact electrodes 38a and 38b can be further improved.

[0440] <Other Configuration>

[0441] like Fig.41 As shown in FIG. 1 , the gate insulating film 36 is provided between the gate electrode 37 side of the contact electrode 38a and the semiconductor portion 33. In addition, the gate insulating film 36 is also provided between the gate electrode 37 side of the contact electrode 38b and the semiconductor portion 33. Although not shown in detail, the gate insulating film 36 between the contact electrodes 38a and 38b and the semiconductor portion 33 extends over the upper surface portion 33a and the two side surface portions 33c1 and 33c2 of the semiconductor portion 33, similar to FIG. Fig.42 A gate insulating film 36 is provided between the gate electrode 37 shown in FIG.

[0442] Then, the gate insulating film 36 is provided on both side surface portions 33c1 and 33c2 of the semiconductor portion 33 between the contact electrodes 38a and 38b and the gate electrode 37, but is not provided on the upper surface portion 33a, although not limited thereto.

[0443] <<Method for manufacturing a semiconductor device>>

[0444] Next, refer to Figures 44 to 68 A method for manufacturing the semiconductor device 1F will be described.

[0445] In the sixth embodiment, the formation of the field effect transistor Qf and the formation of the contact electrodes 38 a and 38 b included in the method for manufacturing the semiconductor device will be specifically described.

[0446] First, if Fig.44 (Schematic plan view), Fig.45A (along Fig.44 A schematic longitudinal cross-sectional view taken along the cutting line A44-A44 in FIG. Fig.45B (along Fig.44 As shown in the schematic longitudinal cross-sectional view taken along the cutting line b44-b44 in FIG, an island-shaped semiconductor portion 33 is formed on the first insulating film 32. The semiconductor portion 33 is formed into, for example, a rectangular parallelepiped shape having an upper surface portion 33a, a lower surface portion (bottom surface portion) 33b, and four side surface portions 33c1, 33c2, 33c3, and 33c4. For example, the semiconductor portion 33 can be formed by patterning a semiconductor layer disposed on the first insulating film 32 into a predetermined shape using a known photolithography technique, an etching technique, or the like. Although not limited thereto, the semiconductor portion 33 is composed of, for example, silicon as a semiconductor material, for example, as a crystalline single crystal, and, for example, as an i-type (intrinsic type) of a conductive type. The first insulating film 32 supports the semiconductor portion 33 on the lower surface portion 33b side of the semiconductor portion 33. As the first insulating film 32, for example, a silicon oxide film formed by a chemical vapor deposition (CVD) method is used.

[0447] Next, if Fig.46 (Schematic plan view), Fig.47A (shown along Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line A46-A46 in FIG. Fig.47B (shown along Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b46-b46 in FIG. Fig.47C (shown along Fig.46), a second insulating film 34 and grooved portions 35a, 35b, 35c1, and 35c2 are formed in the second insulating film 34. The second insulating film 34 is formed on the outside of the semiconductor portion 33 so as to surround the semiconductor portion 33. The second insulating film 34 can be formed by forming, for example, a silicon oxide film on the entire surface of the first insulating film 32 including the semiconductor portion 33 using a known film forming method (for example, a CVD method), and then selectively removing the surface layer portion side of the silicon oxide film using, for example, a CMP method, so that the upper surface portion 33a of the semiconductor portion 33 is exposed to reduce the film thickness.

[0448] Each of the grooved portions 35a, 35b, 35c1, and 35c2 can be formed by selectively etching the second insulating film 34 using a known photolithography technique and a dry etching technique.

[0449] Specifically, the groove portion 35a is formed so that three side surface portions 33c1, 33c2 and 33c3 of the semiconductor portion 33 are exposed on one side surface portion 33c3 side of two side surface portions 33c3 and 33c4 located on opposite sides in the longitudinal direction (Y direction) of the semiconductor portion 33.

[0450] Further, the groove portion 35b is formed so that three side surface portions 33c1, 33c2 and 33c4 of the semiconductor portion 33 are exposed on one side of the other side surface portion 33c4 of the two side surface portions 33c3 and 33c4 located on opposite sides in the longitudinal direction (Y direction) of the semiconductor portion 33.

[0451] Furthermore, the cutout portions 35c1 and 35c2 are formed so that the side surface portions 33c1 and 33c2 are exposed to the outside of each of the two side surface portions 33c1 and 33c2 on opposite sides at the center portion in the longitudinal direction (Y direction) of the semiconductor portion 33 .

[0452] The etching of the second insulating film 34 is performed under the condition that an etching rate with respect to the semiconductor portion 33 can be obtained. The grooved portions 35a and 35b are preferably formed so that the depth in the same direction as the thickness direction (Z direction) of the semiconductor portion 33 is equal to or greater than the height in the thickness direction of the semiconductor portion 33. In other words, the grooved portions 35a and 35b are preferably formed at a depth reaching the first insulating film 32.

[0453] In this step, three side surface portions 33c1, 33c2, and 33c3 of the semiconductor portion 33 are exposed in the groove portion 35a, three side surface portions 33c1, 33c2, and 33c4 of the semiconductor portion 33 are exposed in the groove portion 35b, side surface portion 33c1 of the semiconductor portion 33 is exposed in the groove portion 35c1, and side surface portion 33c2 of the semiconductor portion 33 is exposed in the groove portion 35c2. The upper surface portion 33a of the semiconductor portion 33 is exposed from one end side to the other end side in the longitudinal direction (Y direction) of the semiconductor portion 33.

[0454] Next, if Fig.48A (shown with Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure with the cutting line A46-A46 in the same position), Fig.48B (shown with Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure with the cutting line b46-b46 in the same position) and Fig.48C (shown with Fig.46 As shown in the schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure in which the cutting line c46-c46 in the figure is at the same position, a gate insulating film 36 is formed on the semiconductor portion 33. In the lateral direction (X direction) of the semiconductor portion 33, a gate insulating film 36 is formed on the upper surface portion 33a and the two side surface portions 33c1 and 33c2 of the semiconductor portion 33. The gate insulating film 36 can be formed by a thermal oxidation method or a deposition method. In the sixth embodiment, a silicon oxide film as the gate insulating film 36 is formed by a thermal oxidation method. Therefore, the gate insulating film 36 can be selectively formed in the portion of the semiconductor portion 33 exposed from the second insulating film 34.

[0455] Note that in this step, Fig.48A As shown, a gate insulating film 36 is also formed on each of two side surface portions 33 c 3 and 33 c 4 in the longitudinal direction (Y direction) of the semiconductor portion 33 .

[0456] Then, if Fig.49A (shown in Fig.46 As shown in the schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the cutting line a46-b46 in FIG. Fig.49B (shown in Fig.46 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the cutting line b46-b46 in FIG. Fig.49C (shown in Fig.46), the gate insulating film 36 is patterned to selectively remove the gate insulating film 36 on one end side (grooved portion 35a side) and the other end side (grooved portion 35b side) in the longitudinal direction (Y direction) of the semiconductor portion 33, and the upper surface portion 33a and the three side surface portions 33c1, 33c2 and 33c3 are selectively exposed on one end side in the longitudinal direction of the semiconductor portion 33, and the upper surface portion 33a and the three side surface portions 33c1, 33c2 and 33c4 are selectively exposed on the other end side in the longitudinal direction of the semiconductor portion 33. The patterning of the gate insulating film 36 can be performed using a known photolithography technique, a dry etching technique, or the like.

[0457] In this step, the gate insulating film 36 has a strip shape, wherein the end in the same direction as the longitudinal direction of the semiconductor portion 33 is located on the inner side of the end in the longitudinal direction of the semiconductor portion 33 at the center portion in the longitudinal direction (Y direction) of the semiconductor portion 33 in a plan view, and extends on the upper surface portion 33a and two side surface portions 33c1 and 33c2 of the semiconductor portion 33.

[0458] Next, if Fig.50 (Schematic plan view), Fig.51A (along Fig.50 A schematic longitudinal cross-sectional view taken along the cutting line a50-a50 in FIG. Fig.51B (shown along Fig.50 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b50-b50 in FIG. 1 is shown, and Fig.51C (shown along Fig.50 ), for example, a polysilicon film (non-doped polysilicon film) 37X to which impurities for reducing the resistance value are not introduced is formed as an electrode forming material. The polysilicon film 37X is formed on the entire surface including the semiconductor portion 33 and the second insulating film 34 by, for example, a CVD method so as to fill the inside of each of the four grooved portions 35a, 35b, 35c1, and 35c2.

[0459] Here, due to the movement between steps after the gate insulating film 36 of the semiconductor portion 33 is selectively removed, etc. Fig.51D ( Fig.51A A schematic cross-sectional view in which a portion (one end side of the semiconductor portion) is enlarged) and Fig.51E ( Fig.51CAs shown in the schematic cross-sectional view in which a portion is enlarged, an extremely thin natural oxide film 33X is formed in the gate insulating film removal region (upper surface portion 33a and side surface portions 33c1 to 33c4) of the semiconductor portion 33. Fig.51D and 51E As shown, in the gate insulating film removal area on one end side in the longitudinal direction (Y direction) of the semiconductor portion 33, an extremely thin natural oxide film 33X having a film thickness of, for example, about 2 nm is retained at the interface portion between the polysilicon film 37X on one end side in the longitudinal direction of the semiconductor portion 33 and the upper surface portion 33a and the three side surface portions 33c1, 33c2 and 33c3.

[0460] In addition, in the gate insulating film removal area on the other end side in the longitudinal direction (Y direction) of the semiconductor portion 33, the natural oxide film 33X remains at the interface portion between the polysilicon film 37X and the upper surface portion 33a and the three side surface portions 33c1, 33c2 and 33c4 on the other end side in the longitudinal direction of the semiconductor portion 33.

[0461] These natural oxide films 33X extend in a planar shape (film shape) on the upper surface portion 33 a and the three side surface portions 33 c 1 , 33 c 2 , and 33 c 3 (or 33 c 4 ) of the semiconductor portion 33 .

[0462] Then, if Fig.52 (Schematic plan view), Fig.53A (Along Fig.52 A schematic longitudinal cross-sectional view taken along the cutting line a52-a52 in FIG. Fig.53B (shown along Fig.52 Cutting line c52- c5 2), a mask RM1 is formed as an impurity introduction mask which selectively covers the gate electrode formation region of the polysilicon film 37X. Then, as shown in FIG. Fig.53A and Fig.53B As shown, the mask RM1 is used as an impurity introduction mask, and, for example, fluorine ions (F - ) is implanted as an impurity into the polysilicon film 37X outside the mask RM1. The mask RM1 can be formed by a known photolithography technique.

[0463] The purpose of the fluorine ion implantation is to promote the granulation (spheroidization) of the natural oxide film 33X by heat treatment. 15 / cm 2 The fluorine ion implantation is performed under the condition of an acceleration energy of about 15 keV.

[0464] Next, after removing the mask RM1, a heat treatment is performed to make the fluorine ions (F) implanted into the polysilicon film 37X - )activation.

[0465] In this step, if Fig.51D and Fig.51E As shown, fluoride ion (F - ) diffuses into the polysilicon film 37X, and fluorine ions (F - ) also diffuses into the natural oxide film 33X. Then, the fluorine ions (F - ) of the natural oxide film 33X fluidized, and as Fig.54A and Fig.54B As shown, it is turned into a granular (spherical) oxide 33Y at the interface portion between the semiconductor portion 33 (the upper surface portion 33a and the side surface portions 33c1, 33c2, 33c3, and 33c4) and the polysilicon film 37X.

[0466] Then, if Fig.55 (Top view), Fig.56A ( Fig.55 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure of the cutting line a55-a55) and Fig.56B ( Fig.55 As shown in the schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure along the cutting line c55-c55 of FIG, a mask RM2 is formed on the polysilicon film 37X. The mask RM2 is an impurity introduction mask having an opening Ap1 in the gate electrode formation region of the polysilicon film 37X. Then, as shown in FIG. Fig.56A As shown, mask RM2 is used as an impurity introduction mask, for example, phosphorus ions (P + ) is selectively implanted as an n-type impurity into the gate electrode formation region of the polysilicon film 37X through the opening Ap1 of the mask RM2. The mask RM2 can be formed by a known photolithography technique.

[0467] The phosphorus ion (P + ) is implanted to reduce the resistance value of the gate electrode formation region of the polysilicon film 37X. For example, at a dose of about 5×10 15 / cm 2 The phosphorus ion (P + ) is implanted. Arsenic ions (As + ) can be used as n-type impurities.

[0468] Through this process, phosphorus ions (P) are selectively introduced into the gate electrode formation region of the polysilicon film 37X. + ).

[0469] Next, after removing the mask RM2, as Fig.57 (Schematic diagram), Fig.58A (Longitudinal cross-sectional diagram, showing Fig.57 The longitudinal cross-sectional structure taken along the cutting line a57-a57 in FIG. Fig.58B As shown in FIG. 58 (a longitudinal cross-sectional schematic diagram showing a longitudinal cross-sectional structure taken along the cutting line c58-c58 in FIG. 58), a mask RM3 is formed as an impurity introduction mask selectively covering the gate electrode formation region of the polysilicon film 37X. Fig.57 , Fig.58A , Fig.58B As shown, the mask RM3 is used as an impurity introduction mask, and for example, phosphorus ions are implanted as n-type impurities into the polysilicon film 37X outside the mask RM3. The mask RM3 can be formed by a known photolithography technique.

[0470] The phosphorus ion (P + ) is implanted to reduce the resistance value of the contact electrode formation region of the polysilicon film 37X and to form n-type semiconductor regions 39a and 39b described later on both end sides in the long side direction (Y direction) of the semiconductor portion 33. In the ion implantation step shown in FIG. 56, phosphorus ions (P + ) high concentration of phosphorus ions (P + ) is implanted. For example, at a dose of about 1×10 16 / cm 2 The measurement was performed under the condition of an acceleration energy of about 1 keV. + ) can be used as n-type impurities.

[0471] Through this process, phosphorus ions (P) are introduced into the contact electrode formation region of the polysilicon film 37X. + ).

[0472] Next, the polysilicon film 37X is patterned to form the gate electrode 37 and the contact electrodes 38a and 38b, as shown in FIG. Fig.59 (Schematic plan view), Fig.60A (shown along Fig.59 As shown in the schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a59-a59 in FIG. Fig.60B (shown along Fig.59 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b59-b59 in FIG. Fig.60C (shown along Fig.59 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line c59-c59 in FIG. 1 ). That is, the contact electrodes 38a and 38b are formed of the same layer (same step and same material) as the gate electrode 37. The patterning of the polysilicon film 37X can be performed using a known photolithography technique, dry etching technique, or the like.

[0473] In this step, the gate electrode 37 is formed so as to face the upper surface portion 33a and each of the two side surface portions 33c1 and 33c2 of the semiconductor portion 33, with the gate insulating film 36 interposed therebetween. Specifically, the gate electrode 37 includes: a head portion (first portion) 37a, which is disposed on the upper surface portion 33a side of the semiconductor portion 33, with the gate insulating film 36 interposed therebetween; and two leg portions (second portions) 37b1 and 37b2, which are integrally formed with the head portion 37a and are disposed outside each of the two side portions 3c1 and 3c2 located on opposite sides in the lateral direction (X direction) of the semiconductor portion 33, with the gate insulating film 36 interposed therebetween. The head portion 37a protrudes upward from the second insulating film 34. Each of the two leg portions 37b1 and 37b2 is individually disposed in each of the grooved portions 35a and 35b.

[0474] Furthermore, in this step, in a plan view, the contact electrode 38a is formed to overlap the semiconductor portion 33 on the side of one side surface portion 33c3 of the two side surface portions 33c3 and 33c4 located in the longitudinal direction (Y direction) of the semiconductor portion 33. Then, the contact electrode 38a includes: a head portion 38A1 protruding upward from the second insulating film 34; and a leg portion 38A2 formed integrally with the head portion 38A1 and provided in the groove portion 35a between the second insulating film 34 and the semiconductor portion 33. Then, in the contact electrode 38a, on one end side (side surface portion 33c3 side) in the longitudinal direction of the semiconductor portion 33, the head portion 38A1 is connected to the upper surface portion 33a of the semiconductor portion 33, and the leg portion 38A2 is connected to the three side surface portions 33c1, 33c2, and 33c3 of the semiconductor portion 33.

[0475] Furthermore, in this step, the contact electrode 38b is formed to overlap with the semiconductor portion 33 on one side of the other side surface portion 33c4 located in the longitudinal direction (Y direction) of the semiconductor portion 33, out of the two side surface portions 33c3 and 33c4, in a plan view. Then, the contact electrode 38b includes a head portion 38b1 protruding upward from the second insulating film 34, and a leg portion 38b2 integrated with the head portion 38b1 and provided in the groove portion 35b between the second insulating film 34 and the semiconductor portion 33. Then, in the contact electrode 38b, on the other end side (side portion 33c4 side) in the longitudinal direction of the semiconductor portion 33, the head portion 38b1 is connected to the upper surface portion 33a of the semiconductor portion 33, and the leg portion 38b2 is connected to the three side surface portions 33c1, 33c2, and 33c4 of the semiconductor portion 33.

[0476] In addition, in this step, the gate insulating film 36 is selectively retained (inserted) between the gate 37 side of the contact electrode 38a and the semiconductor portion 33 on the upper surface portion 33a and the two side surface portions 33c1 and 33c2 of the semiconductor portion 33, and the gate insulating film 36 is selectively retained (inserted) between the gate 37 side of the contact electrode 38b and the semiconductor portion 33 on the upper surface portion 33a and the two side surface portions 33c1 and 33c2 of the semiconductor portion 33.

[0477] Furthermore, in this step, during the patterning of the polysilicon film 37X, the gate insulating film 36 on the upper surface portion 33a of the semiconductor portion 33 between the gate electrode 37 and the contact electrode 38a and the gate insulating film 36 on the upper surface portion 33a of the semiconductor portion 33 between the gate electrode 37 and the contact electrode 38b are selectively removed by overetching. In the case where the film thickness is large, the gate insulating film 36 between the gate electrode 37 and the contact electrodes 38a and 38b may remain.

[0478] Next, after removing the mask RM3, heat treatment is performed to activate the impurities (phosphorus ions (P + )) to make the gate electrode 37 conductive (to reduce the resistance value of the gate electrode 37), and to activate the impurities (phosphorus ions (P + )) to make the contact electrodes 38a and 38b conductive (to reduce the resistance value of each of the contact electrodes 38a and 38b).

[0479] In this step, impurities (phosphorus ions (P + )) diffuses (leaks) to both end portions in the longitudinal direction (Y direction) of the semiconductor portion 33, and as Fig.61 As shown (shown in Fig.59 In the schematic longitudinal sectional view of the longitudinal sectional structure at the same position of the cutting line a59-a59 in FIG, an n-type semiconductor region 39a is formed on one end side (side surface portion 33c3 side) in the longitudinal direction (Y direction) of the semiconductor portion 33, and an n-type semiconductor region 39b is formed on the other end side (side surface portion 33c4 side).

[0480] The n-type semiconductor region 39a is formed from the upper surface portion 33a to the lower surface portion 33b along the three side surface portions 33c1, 33c2 and 33c3 of the semiconductor portion 33. In addition, the n-type semiconductor region 39b is formed from the upper surface portion 33a to the lower surface portion 33b along the three side surface portions 33c1, 33c2 and 33c4 of the semiconductor portion 33.

[0481] In addition, during the heat treatment of this step, a natural oxide film 33X (see Fig.51D and Fig.51E ) is fluidized and becomes a granular oxide 33Y (see Fig.54A and Fig.54B ) phenomenon.

[0482] Next, if Fig.62 (shown in Fig.59 As shown in the schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a59-a59 in FIG, a pair of n-type semiconductor regions 40a and 40b having an impurity concentration lower than that of the n-type semiconductor regions 39a and 39b is formed in each semiconductor portion 33 on both sides of the gate length direction (Y direction) of the gate electrode 37. Each of the pair of n-type semiconductor regions 40a and 40b serves as an extension region.

[0483] Each of the pair of n-type semiconductor regions 40a and 40b can be impurity-introduced by using the gate electrode 37, the contact electrodes 38a and 38b, and the second insulating film 34 as an impurity introduction mask to introduce, for example, arsenic ions (As + ) is injected as an n-type impurity into each semiconductor portion 33 on both sides of the gate length direction (Y direction) of the gate electrode 37, and then the semiconductor portion is subjected to heat treatment for activating the impurity.

[0484] For example, at a dose of approximately 3 × 10 14 / cm 2 The arsenic ion (As) is accelerated at an energy of about 80 keV. + ) is implanted. Phosphorus ions (P + ) can be used as n-type impurities.

[0485] In this step, each of a pair of n-type semiconductor regions 40 a and 40 b is formed on each of the semiconductor portions 33 located on both sides of the gate electrode 37 in the gate length direction (Y direction) to be aligned with the head 37 a of the gate electrode 37 .

[0486] In addition, one n-type semiconductor region 40a of a pair of n-type semiconductor regions 40a and 40b is formed in the semiconductor portion 33 in contact with the n-type semiconductor region 39a, and the other n-type semiconductor region 40b is formed in the semiconductor portion 33 in contact with the n-type semiconductor region 39b.

[0487] In addition, in the heat treatment of this step, a natural oxide film 33X (see Fig.51D and Fig.51E ) is fluidized and becomes a granular oxide 33Y (see Fig.54A and Fig.54B ) phenomenon.

[0488] Next, if Fig.63 (Schematic plan view) and Fig.64 (shown along Fig.63 As shown in the schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a63-a63 in the drawing, a sidewall spacer 41c is formed on the side wall of the head 37a of the gate electrode 37 protruding upward from the second insulating film 34, and sidewall spacers 41a and 41b are formed on the side walls of the corresponding heads 38A1 and 38b1 of the contact electrodes 38a and 38b protruding upward from the second insulating film 34.

[0489] The sidewall spacers 41a, 41b, 41c can be formed, for example, as follows: a silicon nitride film having selectivity for a silicon oxide film, for example, as an insulating film, is formed on the entire surface of the second insulating film 34 by a CVD method in a manner that covers the heads 38A1, 38b1 of the contact electrodes 38a, 38b and the head 37a of the gate electrode 37, and the silicon nitride film is subjected to anisotropic dry etching such as RIE.

[0490] The sidewall spacer 41a is formed to surround the head 38A1 of the contact electrode 38a and is formed to be aligned with the head 38A1 of the contact electrode 38a. The sidewall spacer 41b is formed to surround the head 38b1 of the contact electrode 38b and is formed to be aligned with the head 38b1 of the contact electrode 38b. The sidewall spacer 41c is formed to surround the head 37a of the gate electrode 37 and is formed to be aligned with the head 37a of the gate electrode 37.

[0491] The sidewall spacers 41 a , 41 b , and 41 c are formed on the second insulating film 34 and the semiconductor portion 33 so as to intersect the semiconductor portion 33 .

[0492] Next, if Fig.65 (shown in Fig.63 As shown in the schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position as the cutting line a63-a63 in FIG, a buffer insulating film 42 is formed. The buffer insulating film 42 is formed to cover the head 37a of the gate electrode 37, the heads 38A1 and 38b1 of the two contact electrodes 38a and 38b, and the side wall spacers 41a, 41b, and 41c, respectively, and is formed to cover the semiconductor portion 33 between the head 37a of the gate electrode 37 and the contact electrodes 38a and 38b. The buffer insulating film 42 is used as a buffer film when ion implanting impurities in the step of forming n-type semiconductor regions 43a and 43b described later. As the buffer insulating film 42, for example, a silicon oxide film can be used.

[0493] Next, if Fig.66 (shown in Fig.63As shown in a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the cutting line a63-a63 in the figure, a pair of n-type semiconductor regions 43a and 43b having a higher impurity concentration than the n-type semiconductor regions 39a and 39b are formed in each semiconductor portion 33 on both sides of the gate length direction (Y direction) of the gate electrode 37.

[0494] Each of the pair of n-type semiconductor regions 43a and 43b can be formed by using the gate electrode 37, the contact electrodes 38a and 38b, the sidewall spacers 41a, 41b and 41c, and the second insulating film 34 as an impurity introduction mask to introduce, for example, phosphorus ions (P + ) are injected into the semiconductor portion 33 between the sidewall spacer 41c of the side wall of the gate electrode 37 and the sidewall spacer 41a of the side wall of the contact electrode 38a, and into the semiconductor portion 33 between the sidewall spacer 41c of the side wall of the gate electrode 37 and the sidewall spacer 41b of the contact electrode 38b through the buffer insulating film 42, and then the semiconductor portion is subjected to heat treatment for activating the impurities.

[0495] For example, at a dose of approximately 8 × 10 15 / cm 2 The phosphorus ion (P + ) is implanted. Arsenic ions (As + ) can be used as n-type impurities.

[0496] In this step, due to the phosphorus ion (P + ) is implanted into the semiconductor portion 33 through the buffer insulating film 42, so that damage to the semiconductor portion 33 due to ion implantation can be suppressed.

[0497] Furthermore, in this step, the n-type semiconductor region 43a is formed to be aligned with the sidewall spacer 41c of the sidewall of the gate electrode 37 and the sidewall spacer 41a of the sidewall of the contact electrode 38a. Furthermore, the n-type semiconductor region 43b is formed to be aligned with the sidewall spacer 41c of the sidewall of the gate electrode 37 and the sidewall spacer 41b of the sidewall of the contact electrode 38b.

[0498] Furthermore, in this step, a main electrode region 44a including n-type semiconductor region 39a, n-type semiconductor region 40a and n-type semiconductor region 43a and a main electrode region 44b including n-type semiconductor region 39b, n-type semiconductor region 40b and n-type semiconductor region 43b are formed.

[0499] Furthermore, in this step, the channel forming portion 45 is formed in the semiconductor portion 3 between the pair of main electrode regions 44 a and 44 b .

[0500] Furthermore, in this step, a field effect transistor Qf including the gate insulating film 36 , the gate electrode 37 , the pair of main electrode regions 44 a and 44 b , the channel forming portion 45 , and the like is formed in the semiconductor portion 33 .

[0501] In addition, in the heat treatment of this step, a natural oxide film 33X (see Fig.51D and Fig.51E ) is fluidized and becomes a granular oxide 33Y (see Fig.54A and Fig.54B ) phenomenon.

[0502] Next, if Fig.67 (shown in Fig.63 As shown in the schematic longitudinal sectional view of the longitudinal sectional structure at the same position as the cutting line a63-a63 in FIG, a third insulating film 46 is formed on the entire surface of the buffer insulating film 42 to cover the gate electrode 37 and the contact electrodes 38a and 38b. The third insulating film 46 can be formed by forming, for example, a silicon oxide film as an insulating film on the entire surface of the buffer insulating film 42 including the gate electrode 37 and the heads 37a, 38A1 and 38b1 of the contact electrodes 38a and 38b and then planarizing the surface of the silicon oxide film by a CMP method or the like.

[0503] In this step, the insulating layer 47 including the first insulating film 32 , the second insulating film 34 , the buffer insulating film 42 , and the third insulating film 46 and including the semiconductor portion 33 and the field effect transistor Qf is formed.

[0504] Next, if Fig.68 As shown (shown in Fig.63 A schematic longitudinal sectional view of the longitudinal sectional structure at the same position of the cutting line a63-a63 in FIG. 4 shows a schematic longitudinal sectional view of the longitudinal sectional structure at the same position of the cutting line a63-a63 in FIG. 4 ), groove portions 48a, 48b are respectively reached from the surface of the insulating layer 47 (the surface of the third insulating film 46) to the heads 38a1, 38b1 of the contact electrodes 38a, 38b, to form a groove portion 48c that reaches the head 37a of the gate electrode 37 from the surface of the insulating layer 47 (the surface of the third insulating film 46).

[0505] Then, thereafter, if Fig.68 As shown, contact electrodes 49a, 49b, and 49c are individually formed in the cutout portions 48a, 48b, and 48c, respectively.

[0506] Each of the grooved portions 48 a , 48 b , and 48 c can be formed by etching the insulating layer 14 using a known photolithography technique and an anisotropic dry etching technique.

[0507] The contact electrodes 49a, 49b, and 49c can, for example, be formed by forming a tungsten film as a high-melting-point metal film on the entire surface of the insulating layer 47 including the grooved portions 48a, 48b, and 48c, and then selectively removing the tungsten film on the insulating layer 47 so that the tungsten film remains in the grooved portions 48a, 48b, and 48c, respectively.

[0508] In this step, the contact electrode 49a is electrically and mechanically connected to the contact electrode 38a, and is electrically connected to one main electrode region 44a of the field effect transistor Qf via the contact electrode 38a. In addition, the contact electrode 49b is electrically and mechanically connected to the contact electrode 38b, and is electrically connected to the other main electrode region 44b of the field effect transistor Qf via the contact electrode 38b. Then, the contact electrode 49c is electrically and mechanically connected to the gate electrode 37 of the field effect transistor Qf.

[0509] Next, wirings 50a, 50b, and 50c that are individually electrically and mechanically connected to the contact electrodes 49a, 49b, and 49c are formed in the wiring layer on the insulating layer 47, thereby obtaining Figure 40 to Figure 43 The status shown in .

[0510] Note that in the case where the gate insulating film 36 remains on the upper surface portion 33a of the semiconductor portion 33 between the sidewall spacer 41c of the sidewall of the gate electrode 37 and the sidewall spacer 41a of the sidewall of the contact electrode 38a, and on the upper surface portion 33a of the semiconductor portion 33 between the sidewall spacer 41c of the sidewall of the gate electrode 37 and the sidewall spacer 41b of the sidewall of the contact electrode 38b, the buffer insulating film 42 may be omitted. In this case, the insulating layer 47 does not include the buffer insulating film 42.

[0511] In the manufacturing method of the sixth embodiment, fluorine ions (F) are implanted into the polysilicon film 37X to promote the transformation from the natural oxide film 33X to the granular oxide 33Y. - ), but the fluorine ion (F) may be omitted when the impurities are introduced to a certain extent to ensure that the natural oxide film 33X is fluidized by heat treatment. - ) injection.

[0512] In addition, in the manufacturing method according to the sixth embodiment, the heat treatment for activating the impurities in the n-type semiconductor regions 40a and 40b and the heat treatment for activating the impurities in the n-type semiconductor regions 43a and 43b are performed in separate steps. However, the heat treatment for activating the impurities in the n-type semiconductor regions 40a and 40b can be performed in the same step as the heat treatment for activating the impurities in the n-type semiconductor regions 43a and 43b.

[0513] <<Main Effects of the Sixth Embodiment>>

[0514] As described above, the semiconductor device 1F according to the sixth embodiment includes the contact electrodes 38a and 38b, which are arranged to overlap the semiconductor portion 33 on both sides of the gate length direction (Y direction) of the gate electrode 37 in a plan view. Then, the contact electrode 38a is connected to each of the three side surface portions 33c1, 33c2, and 33c3 on the upper surface portion 33a of the semiconductor portion 33 and one end side in the longitudinal direction (Y direction) of the semiconductor portion 33. Similarly, the contact electrode 38b is also connected to each of the three side surface portions 33c1, 33c2, and 33c4 on the upper surface portion 33a of the semiconductor portion 33 and the other end side in the longitudinal direction (Y direction) of the semiconductor portion 33.

[0515] Therefore, according to the semiconductor device 1F of the sixth embodiment, similarly to the above-described first embodiment, the transconductance (gm) of the field effect transistor Qf can be improved.

[0516] In addition, even when the width W2 of the semiconductor portion 33 in the lateral direction (XY direction) and the widths W1a and W1b (diameter and thickness width) of the contact electrodes 38a and 38b are reduced as the field effect transistor Qf is miniaturized, the increase in contact resistance between the semiconductor portion 33 and the contact electrodes 38a and 38b can be suppressed, so that the reduction in transconductance (gm) can be suppressed while miniaturizing the field effect transistor Qf.

[0517] In addition, the widths W1a and W1b of the contact electrodes 38a and 38b can be made wider than the width W2 of the semiconductor portion 33, and the difficulty of connecting the contact electrodes 38a and 38b with the contact electrodes 49a and 49b can be reduced. Therefore, even if the width W2 of the semiconductor portion 33 is narrowed due to miniaturization, the semiconductor portion 33 can be easily electrically connected to the contact electrodes 49a and 49b. Therefore, even if the semiconductor portion 33 is miniaturized, the connection failure between the semiconductor portion 33 and the upper wirings 50a and 50b due to mask misalignment can be suppressed, and the manufacturing yield of the semiconductor device 1F can be improved.

[0518] Furthermore, since in the semiconductor device 1F according to the sixth embodiment, the contact electrodes 38a and 38b are formed in the same layer as the gate electrode 37, the contact electrodes 38a and 38b can be provided at a low cost compared to the case where the contact electrodes 38a and 38b are formed in a layer different from the gate electrode 37. Therefore, according to the semiconductor device 1F of the sixth embodiment, it is possible to reduce costs and improve the transconductance (gm) of the field effect transistor Qf.

[0519] In addition, since the contact electrodes 38a and 38b are formed in the same layer as the gate electrode 37, the thicknesses Th1 and Th2 of the corresponding portions (head 38A1, head 38b1) of the contact electrodes 38a and 38b overlapping with the semiconductor portion 33 in a plan view and the thickness Th3 of the portion (head 37a) of the gate electrode 37 overlapping with the semiconductor portion 33 in a plan view can be formed to be substantially the same.

[0520] As a result, the thickness of the insulating layer 47 on the contact electrodes 38a, 38b is approximately the same as the thickness of the insulating layer 47 on the gate electrode 37, thereby shortening the over-etching time when forming the groove parts in the insulating layer 47 corresponding to the contact electrodes 38a, 38b and the gate electrode 37, and suppressing the deviation of the width (diameter, thickness) of the groove parts 48a, 48b, 48c caused by over-etching.

[0521] In addition, in the manufacturing method of the semiconductor device 1F according to the sixth embodiment, the natural oxide film 33X formed on the semiconductor portion 33 is fluidized and converted into a granular (spherical) oxide 33Y by heat treatment, so that the contact characteristics between the semiconductor portion 33 and the contact electrodes 38a and 38b can be further improved.

[0522] In addition, in the method for manufacturing the semiconductor device 1F according to the sixth embodiment, the semiconductor portion 33 on which the gate insulating film 36 is formed is covered by the polysilicon film 37X except for the two end sides in the longitudinal direction (Y direction), and thereafter, the polysilicon film 33X is patterned to form the gate electrode 37 and the contact electrodes 38a and 38b so that the gate insulating film 36 can be maintained on the side of the gate electrode 37 between the contact electrodes 38a and 38b and the semiconductor portion 33.

[0523] <<Modification of Sixth Embodiment>>

[0524] In the above-mentioned sixth embodiment, as the side surface connection form in which the contact electrodes 38a and 38b are connected to the side surface portions of the semiconductor portion 33, the side surface connection form in which the contact electrodes 38a and 38b are connected to the three side surface portions 33c1, 33c2, and 33c3 (or 33c4) of the semiconductor portion 33 has been described. However, the present technology is not limited to the side surface connection form of the above-mentioned sixth embodiment.

[0525] That is, as a side surface connection form, it is only necessary to connect each of the contact electrodes 38 a and 38 b to at least one of the three side surface portions 33 c 1 , 33 c 2 , or 33 c 3 (or 33 c 4 ) of the semiconductor portion 33 .

[0526] Furthermore, each of the contact electrodes 38 a and 38 b only needs to be connected to at least one of the two side surface portions 33 c 1 or 33 c 2 in the lateral direction (X direction) of the semiconductor portion 33 .

[0527] Furthermore, each of the contact electrodes 38 a and 38 b only needs to be connected to at least one of the two side surface portions in the lateral direction of the semiconductor portion 33 .

[0528] <First Modification>

[0529] For example, as a side surface connection form, such as Fig.69 , Fig.70A and Fig.70B As shown, the contact electrodes 38a and 38b may be connected to any one of the two side surface portions 33c1 and 33c2 located in the lateral direction (X direction) of the semiconductor portion 33, and may be connected to the side surface portion 33c3 (or the side surface portion 33c4) located in the longitudinal direction (Y direction) of the semiconductor portion 33. In this case, the contact electrodes 38a and 38b are connected to the upper surface portion 33a of the semiconductor portion 33, and to two side surface portions of the three side surface portions 33c1, 33c2, and 33c3 (or 33c4) of the semiconductor portion 33.

[0530] exist Fig.69 , Fig.70A and Fig.70B In the figure, as an example, the structure in which the contact electrodes 38a and 38b are connected to one side surface portion 33c3 of the two side surface portions 33c1 and 33c2 located in the lateral direction of the semiconductor portion 33 is illustrated, but of course the contact electrodes 38a and 38b can be connected to the other side surface portion 33c2.

[0531] Also in the semiconductor device 1F1 according to the first modification of the sixth embodiment, the same effects as those of the semiconductor device 1F according to the sixth embodiment can be obtained.

[0532] In addition, although Fig.69 , but in the first modification of the sixth embodiment, Fig.28 and Fig.29The through contact electrode 24 shown in the figure is arranged to be adjacent to the contact electrode 38a on the outer side of the other side portion 33c2 (the side portions 3c1 and 3c2 in the third embodiment) of the two side portions 33c1 and 33c2 in the lateral direction (X direction) of the semiconductor portion 33 in a plan view, similar to the above-mentioned third embodiment, because the contact electrode 38a (the contact electrode 17a in the third embodiment) is selectively connected to one side surface portion 33c1 on the opposite side of the other side surface portion 33c2 on the through contact electrode 24 side of the semiconductor portion 33, compared with the above-mentioned sixth embodiment, the spacing (distance) Lx between the contact electrode 38a and the through contact electrode 24 is increased, and therefore, the parasitic capacitance of the insulating film between the contact electrode 38a and the through contact electrode 24, which is a dielectric film, can be reduced, similar to the above-mentioned third embodiment.

[0533] In addition, similarly to the third embodiment, even if a contact electrode 38b (17b in the third embodiment) is provided adjacent to the contact electrode 38b (17b in the third embodiment) on the outer side of the semiconductor portion 33 in the lateral direction (X direction) when viewed from above, Fig.28 and Fig.29 In the case of the through contact electrode 24 shown, the through contact electrode is selectively connected to a side portion 33c1 on the opposite side of another side portion 3c2 on the through contact electrode 24 side of the semiconductor portion 33, of the two side portions 3c1 and 3c2 located on both sides in the lateral direction (X direction) of the semiconductor portion 33, thereby reducing the parasitic capacitance of the insulating film between the contact electrode 38b and the through contact electrode 24 as a dielectric film.

[0534] It should be noted that Fig.69 In the sixth embodiment described above, Fig.40 Similarly, for convenience of description, illustration of layers above the sidewall spacers 41a, 41b, and 41c is omitted.

[0535] <Second Modification>

[0536] In addition, as a side surface connection form, such as Fig.71 and Fig.72 As shown, the contact electrodes 38a and 38b may be connected to any one of the two side surface portions 33c1 and 33c2 located in the lateral direction (X direction) of the semiconductor portion 33, and may not be connected to the side surface portion located in the longitudinal direction (Y direction) of the semiconductor portion 33. In this case, the contact electrodes 38a and 38b are connected to the upper surface portion 33a of the semiconductor portion 33, and are connected to one of the three side surface portions 33c1, 33c2, and 33c3 (or 33c4) of the semiconductor portion 33.

[0537] It should be noted that Fig.71 In the sixth embodiment described above, Fig.40 Similarly, for convenience of description, illustration of layers above the sidewall spacers 41a, 41b, and 41c is omitted.

[0538] In the semiconductor device 1F2 according to the second modification of the sixth embodiment, the same effects as those of the semiconductor device 1F according to the sixth embodiment can be obtained.

[0539] In addition, in the second modification of the sixth embodiment, Fig.26 Similar to the arrangement shown in FIG. 1 , in the case where two semiconductor portions 33 are arranged in series in the Y direction at a predetermined interval in the same direction as the longitudinal direction (Y direction) of each semiconductor portion, the interval Ly between the two semiconductor portions 33 (see FIG. Fig.26 ) can be narrowed so that the field effect transistors Qf can be arranged more densely.

[0540] Note that Fig.71 and Fig.72 , in a plan view, the side surface portion of the head portion 38a1 of the contact electrode 38a is flush with the side surface portion 33c3 on the one end side in the longitudinal direction (Y direction) of the semiconductor portion 33. However, in the case of a side surface connection form in which the contact electrode 38a is not connected to the side surface portion 33c3 of the semiconductor portion 33, similar to the above-mentioned second embodiment, the contact electrode 38a is preferably positioned closer to the gate electrode 37 than the side surface portion 33c3 of the semiconductor portion 33. Further, similarly, in the case of a side surface connection form in which the contact electrode 38b is not connected to the side surface portion 33c4 of the semiconductor portion 33, it is preferred that the contact electrode 38b is located closer to the gate electrode 37 than the side surface portion 33c4 of the semiconductor portion 33.

[0541] <Third Modification>

[0542] In the sixth embodiment described above, if Fig.41 and Fig.43 As shown in FIG. , a configuration has been described in which each of the contact electrodes 38a and 38b is connected to the upper surface portion 3a and the three side surface portions 3c1, 3c2, and 33c3 (or 33c4) of the semiconductor portion 33. However, as Fig.73 As shown, the contact electrode 38 a may also be connected to the lower surface portion 33 b of the semiconductor portion 33 .

[0543] That is, the contact electrode 38 a of the third modification example is connected to the upper surface portion 33 a and each of the three side surface portions 33 c 1 , 33 c 2 , and 33 c 3 of the semiconductor portion 33 , and is also connected to the lower surface portion 33 b of the semiconductor portion 33 .

[0544] According to the semiconductor device 1F3 of the variant example 3 of the sixth embodiment, compared with the semiconductor device 1F of the sixth embodiment described above, the contact area between the semiconductor portion 33 (main electrode region 44a) and the contact electrode 38a is increased, and the contact resistance between the semiconductor portion 33 (main electrode region 11a) and the contact electrode 38a can be further reduced.

[0545] In addition, Fig.73 In the embodiment, as an example, a configuration is illustrated in which the central portion of the lower surface portion 33b in the lateral direction (X direction) of the semiconductor portion 33 is not selectively covered by the contact electrode 38a. Fig. 27 In the modification shown in , the contact electrode 38 a may continuously cover the lower surface portion 33 b of the semiconductor portion 33 along the lateral direction of the semiconductor portion 33 .

[0546] Note that Fig.73 , the contact electrode 38a is illustrated as an example, but the contact electrode 38b preferably has a configuration similar to that of the contact electrode 38a.

[0547] [Seventh Embodiment]

[0548] like Fig.74 and Fig.75 As shown, the semiconductor device 1G according to the seventh embodiment of the present technology basically has a configuration similar to that of the semiconductor device 1F according to the above-described sixth embodiment, and is different in the following configurations.

[0549] That is, Fig.41 , Fig.42 as well as Fig.43 As shown in FIG. 1 , in the semiconductor device 1F according to the sixth embodiment described above, the wiring 50a is electrically connected to the contact electrode 38a via the contact electrode 49a, and the wiring 50b is electrically connected to the contact electrode 38b via the contact electrode 49b. In addition, the wiring 50c is electrically connected to the gate electrode 37 via the contact electrode 49c. That is, there are two connection portions between the wirings 50a, 50b, 50c and the contact electrodes 38a, 38b, and the gate electrode 37, respectively.

[0550] Meanwhile, in the semiconductor device 1G according to the seventh embodiment, the wiring 50a is directly connected to the contact electrode 38a, and the wiring 50b is directly connected to the contact electrode 38b. In addition, the wiring 50c is directly connected to the gate electrode 37. That is, in the seventh embodiment, there is a connection portion between each of the wirings 50a, 50b, 50c and each of the contact electrodes 38a, 38b and the gate electrode 37.

[0551] Then, in the semiconductor device 1G according to the seventh embodiment, similarly to the sixth embodiment described above, since each of the contact electrodes 38a and 38b is formed in the same layer as the gate electrode 37, the thicknesses Th1 and Th2 of the respective portions (the head portions 38a1 and 38b1) of the contact electrodes 38a and 38b overlapping the semiconductor portion 33 in a plan view and the thickness Th3 of the portion (the head portion 37a) of the gate electrode 37 overlapping the semiconductor portion 33 in a plan view can be made substantially the same, and therefore, the wirings 50a, 50b, and 50c can be directly connected to the contact electrode 38a, the contact electrode 38b, and the gate electrode 37, respectively.

[0552] As a result, the resistance (wiring resistance) of each of the conductive path between the electrical connection wiring 50a and one end side (one main electrode region 44a) in the longitudinal direction (Y direction) of the semiconductor portion 33, the conductive path between the electrical connection wiring 50b and the other end side (the other main electrode region 44b) in the longitudinal direction of the semiconductor portion 33, and the conductive path between the electrical connection wiring 50c and the gate electrode 37 can be reduced. Therefore, according to the semiconductor device 1G of the seventh embodiment, the operating speed of the field effect transistor Qf can be improved.

[0553] Note that also in the semiconductor device 1G according to the seventh embodiment, the first to third modifications of the sixth embodiment described above can be applied to a connection form in which the contact electrodes 38 a and 38 b are connected to the side surface portions of the semiconductor portion 33 .

[0554] It should be noted that Fig.74 In the sixth embodiment described above, Fig.40 Similarly, for convenience of description, illustration of layers above the sidewall spacers 41a, 41b, and 41c is omitted.

[0555] [Eighth Embodiment]

[0556] like Fig.76 As shown, the semiconductor device 1H according to the eighth embodiment of the present technology basically has a configuration similar to that of the semiconductor device 1F according to the above-described sixth embodiment, and is different in the following configurations.

[0557] That is, Fig.76As shown, in the semiconductor device 1H according to the eighth embodiment, in the direction in which the longitudinal direction (Y direction) of each semiconductor portion is the same direction, two semiconductor portions 33 (33A1 and 33A2) are arranged in parallel at a predetermined interval in the X direction. That is, in the two semiconductor portions 33 (33A1 and 3A2), the other side surface portion 3c2 of the two side surface portions 33c1 and 33c2 located in the lateral direction (X direction) of one semiconductor portion 33 (3A1) and the one side surface portion 33c1 of the two side surface portions 33c1 and 33c2 located in the lateral direction (X direction) of the other semiconductor portion 33 (33A2) are adjacent to each other in the X direction and arranged in parallel. Then, a field effect transistor Qf is provided in each of the two semiconductor portions 33 (33A3 and 33A4).

[0558] In addition, the contact electrode 38a extends on the two semiconductor portions 33 (33A1 and 33A2) on one end side in the longitudinal direction of each of the two semiconductor portions 33 (33A1 and 33A2). Then, the contact electrode 38a is connected to the upper surface portion 33a of each of the two semiconductor portions 33 (33A1 and 33A2), and is connected to the three side surface portions 33c1, 33c2 and 33c3 of each of the two semiconductor portions 33 (33A1 and 33A2). That is, in the eighth embodiment, one contact electrode 38a is shared by the two semiconductor portions 33 (33A1 and 33A2).

[0559] In the semiconductor device 1H according to the eighth embodiment as well, effects similar to those of the semiconductor device 1F according to the above-described sixth embodiment can be obtained.

[0560] In addition, since the contact electrode 38a is formed in the same layer as the gate electrode 37, when the polysilicon film 37X as the electrode forming material is patterned, the contact electrode 38a shared by the two semiconductor portions 33 (33A1 and 33A2) can be easily formed by only changing the shape of the mask.

[0561] It should be noted that Fig.76 , a case where two semiconductor portions 33 ( 33A1 and 33A2 ) share one contact electrode 38 a is shown as an example, but two semiconductor portions 33 ( 33A1 and 33A2 ) may share one contact electrode 38 b .

[0562] Furthermore, in the eighth embodiment, the first to third modifications of the sixth embodiment described above may be applied to a connection form in which the contact electrode 38 a is connected to the side surface portion of each of the two semiconductor portions 33 ( 33A1 and 33A2 ).

[0563] It should be noted that Fig.76 In the sixth embodiment described above, Fig.40 Similarly, for convenience of description, illustration of layers above the sidewall spacers 41a, 41b, and 41c is omitted.

[0564] <<Modification of Eighth Embodiment>>

[0565] like Fig.77 As shown, one end side of the two semiconductor portions in the longitudinal direction can be connected to each other. Also in this modification, because the contact electrode 38a is formed in the same layer as the gate electrode 37, when the polysilicon film 37X as the electrode forming material is patterned, the contact electrode 38a shared by the two semiconductor portions 33 (33A1 and 33A2) can be easily formed by only changing the shape of the mask.

[0566] Also in the semiconductor device 1H1 according to the modification example of the eighth embodiment, effects similar to those of the semiconductor device 1F according to the above-described sixth embodiment can be obtained.

[0567] It should be noted that Fig.77 In the sixth embodiment described above, Fig.40 Similarly, for convenience of description, illustration of layers above the sidewall spacers 41a, 41b, and 41c is omitted.

[0568] [Ninth Embodiment]

[0569] In the ninth embodiment, reference is made to Fig.78 The present technology is described as being applied to an example of a solid-state imaging device called a back-illuminated CMOS image sensor as a light detection device included in a semiconductor device.

[0570] like Fig.78 As shown, the solid-state imaging device 1I according to the ninth embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1E according to the above-described fifth embodiment, and the following configurations are different.

[0571] That is, Fig.78 As shown, the solid-state imaging device 1I according to the ninth embodiment includes a field effect transistor Qf and contact electrodes 38a and 38b instead of the above-mentioned fifth embodiment. Fig.39 The field effect transistor Qa and contact electrodes 17a and 17b are shown. The other structures are substantially the same as those of the fifth embodiment described above. Fig.76 Meanwhile, referring to the fifth embodiment Figure 36 to Figure 38 Give a description.

[0572] In the ninth embodiment, although not shown in detail, the fifth embodiment described above Fig.38Each of the photoelectric conversion unit 124, the transfer transistor TR, and the charge holding region FD shown in FIG. Fig.78 In the semiconductor layer 130 shown in .

[0573] At the same time, including Fig.38 Each of the pixel transistors (AMP, SEL, RST, and FDG) in the pixel circuit 115 shown in FIG. 1 includes Fig.78 The field effect transistor Qf shown in FIG. Then, in Fig.78 , an amplifier transistor AMP including a field effect transistor Qf is shown as an example.

[0574] <<Main Effects of the Ninth Embodiment>>

[0575] In the solid-state imaging device 1I according to the ninth embodiment, each of the pixel transistors (AMP, SEL, RST, and FDG) included in the pixel circuit 115 includes a field effect transistor Qf provided in the semiconductor portion 33. Then, the contact electrodes 38a and 38b are provided on both end sides in the longitudinal direction (Y direction) of the semiconductor portion 33 so as to overlap with the semiconductor portion 33. Similar to the sixth embodiment described above, the contact electrode 38a is connected to the upper surface portion 33a of the semiconductor portion 33, and is connected to each of the three side surface portions 3c1, 3c2, and 3c3 as the side surface portions of the semiconductor portion 33. In addition, the contact electrode 38b is also connected to the upper surface portion 33a of the semiconductor portion 33 similarly to the sixth embodiment described above, and is also connected to each of the three side surface portions 3c1, 3c2, and 3c4 as the side surface portions of the semiconductor portion 33.

[0576] Therefore, according to the solid-state imaging device 1I of the ninth embodiment, similarly to the above-described sixth embodiment, the transconductance (gm) of each of the pixel transistors (AMP, SEL, RST, and FDG) included in the pixel circuit 115 can be improved.

[0577] In addition, even when the width W2 in the lateral direction (Y direction) of the semiconductor portion 33 and the widths W1a and W1b (diameter and thickness width) of the contact electrodes 38a and 38b are reduced as the pixel transistors (AMP, SEL, RST and FDG) included in the pixel circuit 115 are miniaturized, the increase in contact resistance between the semiconductor portion 33 and the contact electrodes 38a and 38b can be suppressed, so that the reduction in transconductance (gm) can be suppressed while miniaturizing the pixel transistors (AMP, SEL, RST and FDG).

[0578] Here, in the amplifier transistor AMP, it is important to suppress the degradation of noise resistance such as 1 / f noise or RTS noise compared to the pixel transistors (SEL, RST, and FDG) used as switching elements. Therefore, in the case where the present technology is applied to the connection between the semiconductor portion 33 provided with the amplifier transistor AMP included in the pixel circuit 115 and the contact electrodes 38a and 38b, the effectiveness is particularly high.

[0579] It should be noted that in the above-mentioned ninth embodiment, the case of applying the connection form of the above-mentioned sixth embodiment as the connection form for connecting the contact electrodes 38a and 38b to the semiconductor portion 33 has been described, but the connection forms of the first to third variants of the above-mentioned sixth embodiment can of course be applied.

[0580] Furthermore, at least one of the pixel transistors (AMP, SEL, RST, or FDG) included in the pixel circuit 115 may be configured by a field effect transistor Qf provided in the semiconductor portion 33 .

[0581] [10th embodiment]

[0582] like Figures 79 to 82 As shown, the semiconductor device 1J according to the tenth embodiment of the present technology basically has a configuration similar to that of the semiconductor device 1F according to the above-described sixth embodiment, and is different in the following configuration.

[0583] That is, Figures 79 to 82 As shown, the semiconductor device 1J according to the tenth embodiment of the present technology includes an insulating layer 47J instead of the insulating layer 47J in the sixth embodiment described above. Fig.41 The insulating layer 47 is shown in FIG.

[0584] Specifically, the insulating layer 47 of the sixth embodiment described above has a multilayer structure including the first insulating film (substrate insulating film) 32 , the second insulating film (surrounding insulating film) 34 , and the third insulating film (cover insulating film) 46 .

[0585] At the same time, if Figures 79 to 82 As shown, the insulating layer 47J of the tenth embodiment has a multilayer structure including the first insulating film 32 and the third insulating film 46 in addition to the second insulating film 34 (see Fig.41 ). Then, the semiconductor portion 33 and the field effect transistor Qf are covered by the third insulating film 46.

[0586] Furthermore, in the semiconductor device 1J according to the tenth embodiment of the present technology, the shapes of the sidewall spacers 41a, 41b, and 41c are different from those of the sixth embodiment described above. Figure 40 to Figure 43 The shapes of the sidewall spacers 41a, 41b and 41c shown in FIG. 5 are different.

[0587] Specifically, Figures 79 to 82 As shown, in the sidewall spacers 41a, 41b and 41c of the tenth embodiment, the height of the semiconductor portion 33 along the thickness direction (Z direction) is different between the semiconductor portion 33 and the outside of the semiconductor portion 33, and the height on the outside of the semiconductor portion 33 is higher than the height on the semiconductor portion 33.

[0588] In the semiconductor device 1J according to the tenth embodiment of the present technology, n-type semiconductor regions 43a and 43b are arranged to have a depth reaching the lower surface portion 33b from the upper surface portion 33a side of the semiconductor portion 33. The other structures are substantially the same as those of the sixth embodiment described above.

[0589] In addition, in the tenth embodiment, the terms in the sixth embodiment are recorded continuously from the relationship with the above-mentioned sixth embodiment, and the insulating film is recorded as the third insulating film 46, but it is not limited to this, and it can also be recorded as the second insulating film 46 or simply recorded as the insulating film 46.

[0590] In addition, Fig.87 , 89 , 91, and 92 show contact electrode forming regions 37Xa, 37Xb, and a gate electrode forming region 37Xc in the polysilicon film 37X. The contact electrode forming regions 37Xa, 37Xb, and the gate electrode forming region 37Xc are formed by patterning the polysilicon film 37X by a manufacturing method described later to form contact electrodes 38a, 38b, and a gate electrode 37.

[0591] <<Method for manufacturing a semiconductor device>>

[0592] Next, refer to Figure 83 to Figure 102 A method for manufacturing the semiconductor device 1J according to the tenth embodiment is described.

[0593] Also in the tenth embodiment, similar to the above-described sixth embodiment, description will be made focusing on the formation of the field effect transistor Qf and the formation of the contact electrodes 38 a and 38 b included in the method for manufacturing the semiconductor device.

[0594] First, if Fig.83 and Fig.84 As shown in (a), (b) and (c), an island-shaped semiconductor portion 33 is formed on the first insulating film 32. The island-shaped semiconductor portion 33 is formed by a method similar to the above-mentioned sixth embodiment. That is, the semiconductor portion 33 is formed into, for example, a rectangular parallelepiped shape having an upper surface portion 33a, a lower surface portion (bottom surface portion) 33b and four side surface portions 33c1, 33c2, 33c3 and 33c4. The semiconductor portion 33 is supported by the first insulating film 32.

[0595] Next, similarly to the sixth embodiment described above, the gate insulating film 36 is formed on the semiconductor portion 33, and then the gate insulating film 36 is patterned to selectively remove the gate insulating film 36 on one end side (side surface portion 33c3 side) and the other end side (side surface portion 33c4 side) in the longitudinal direction (Y direction) of the semiconductor portion 33, as shown in FIG. Fig.85 ((a), (b) and (c))Similar to the sixth embodiment described above, the upper surface portion 33a and the three side surface portions 33c1, 33c2 and 33c3 are selectively exposed on one end side in the longitudinal direction of the semiconductor portion 33, and the upper surface portion 33a and the three side surface portions 33c1, 33c2 and 33c4 are selectively exposed on the other end side in the longitudinal direction of the semiconductor portion 33. Patterning of the gate insulating film 36 can be performed using a known photolithography technique, a dry etching technique, or the like.

[0596] Then, if Fig.86 , Fig.87 As shown in (a), (b), and (c), a polysilicon film (undoped polysilicon film) 37X is formed as an electrode forming material on the entire surface of the first insulating film 32 without introducing impurities for reducing the resistance value. The polysilicon film 37X is formed on the first insulating film 32 by, for example, a CVD method to cover the semiconductor portion 33.

[0597] Here, referring to the sixth embodiment Fig.51D and Fig.51E , also in the tenth embodiment, by moving between steps after the gate insulating film 36 of the semiconductor portion 33 is selectively removed, etc., an extremely thin natural oxide film 33X is formed in the gate insulating film removal region (the upper surface portion 33a and the side surface portions 33c1 to 33c4) of the semiconductor portion 33. Therefore, also in the tenth embodiment, in the gate insulating film removal region on one end side in the longitudinal direction (Y direction) of the semiconductor portion 33, an extremely thin natural oxide film 33X having a film thickness of, for example, about 2 nm remains at the interface portion between the polysilicon film 37X on one end side in the longitudinal direction of the semiconductor portion 33 and the upper surface portion 33a and the three side surface portions 33c1, 33c2, and 33c3.

[0598] In addition, in the gate insulating film removal area on the other end side in the longitudinal direction (Y direction) of the semiconductor portion 33, the natural oxide film 33X remains at the interface portion between the polysilicon film 37X and the upper surface portion 33a and the three side surface portions 33c1, 33c2 and 33c4 on the other end side in the longitudinal direction of the semiconductor portion 33.

[0599] These natural oxide films 33X extend in a planar shape (film shape) on the upper surface portion 33 a and the three side surface portions 33 c 1 , 33 c 2 , and 33 c 3 (or 33 c 4 ) of the semiconductor portion 33 .

[0600] Next, similarly to the sixth embodiment described above, a mask RM1 serving as an impurity introduction mask is selectively formed in the gate electrode formation region of the polysilicon film 37X, and then, the mask RM1 is used as an impurity introduction mask, for example, as shown in FIG. Fig.88 , Fig.89 As shown, outside the mask RM1, fluorine ions (F - ) as impurities ((a), (b)). The implantation of fluorine ions is performed under the same conditions as those in the sixth embodiment.

[0601] In this step, the gate electrode forming region 37Xc of the polysilicon film 37X is covered with a mask RM1, and the mask RM1 is used to block the fluorine ions (F - ) is injected into the gate electrode forming region 37Xc. On the other hand, the contact electrode forming regions 37Xa and 37Xb of the polysilicon film 37X are not covered by the mask RM1, and the fluorine ions (F - ) is injected (introduced) into the contact electrode formation regions 37Xa, 37Xb.

[0602] Next, after removing the mask RM1, the fluorine ions (F) implanted into the polysilicon film 37X are implanted. - )Activation heat treatment.

[0603] In this step, refer to the sixth embodiment described above. Fig.51D , Fig.51E , Fig.54A and Fig.54B , similar to the tenth embodiment described above, fluoride ions (F - ) diffuses into the polysilicon film 37X, and fluorine ions (F - ) spread to Fig.51D and Fig.51E Then, the fluorine ions (F - ) of the natural oxide film 33X fluidized, and as Fig.54A and Fig.54B As shown, it is turned into a granular (spherical) oxide 33Y at the interface portion between the semiconductor portion 33 (the upper surface portion 33a and the side surface portions 33c1, 33c2, 33c3, and 33c4) and the polysilicon film 37X.

[0604] Then, if Fig.90 and Fig.91As shown in (a), (b), a mask RM2 is formed on the polysilicon film 37X, and the mask RM2 is an impurity introduction mask having an opening Ap1 in the gate electrode formation region 37Xc of the polysilicon film 37X. Then, the mask RM2 is used as an impurity introduction mask, as shown in FIG. Fig.91 As shown in (a) and (b), for example, phosphorus ions (P + ) is selectively implanted as an n-type impurity into the gate electrode formation region 37Xc of the polysilicon film 37X through the opening Ap1 of the mask RM2. Phosphorus ions (P + The implantation of arsenic ions (As) is performed under conditions similar to those of the sixth embodiment described above. + ) can be used as n-type impurities.

[0605] In this step, the contact electrode forming regions 37Xa and 37Xb of the polysilicon film 37X are covered with a mask RM2, and phosphorus ions (P + ) are introduced into the contact electrode forming regions 37Xa and 37Xb. On the other hand, phosphorus ions (P + ).

[0606] Next, after removing the mask RM2, as Fig.92 and Fig.93 As shown in (a) and (b), a mask RM3 is formed as an impurity introduction mask for selectively covering the gate electrode forming region 37Xc of the polysilicon film 37X. Then, as shown in Fig.92 and Fig.93 As shown in ((a) and (b)), the mask RM3 is used as an impurity introduction mask, and, for example, phosphorus ions are implanted as n-type impurities into the polysilicon film 37X outside the mask RM3.

[0607] The phosphorus ion (P + ) is implanted to reduce the resistance value of the contact electrode formation region of the polysilicon film 37X and to form n-type semiconductor regions 39a and 39b described later on both end sides of the semiconductor portion 33 in the long side direction (Y direction). Phosphorus ions (P + The implantation of arsenic ions (As) is performed under conditions similar to those of the sixth embodiment described above. + ) can be used as n-type impurities.

[0608] In this step, the contact electrode forming regions 37Xa and 37Xb of the polysilicon film 37X are not covered by the mask RM3, and phosphorus ions (P +) are injected (introduced) into the contact electrode forming regions 37Xa and 37Xb. On the other hand, the gate electrode forming region 37Xc of the polysilicon film 37X is covered by the mask RM3, and the mask RM3 is used to prevent the injection (introduction) of phosphorus ions (P) into the gate electrode forming region 37Xc. + ).

[0609] Next, the polysilicon film 37X is patterned as shown in FIG. Fig.94 and Fig.95 As shown in (a), (b) and (c)), a gate electrode 37 including a gate electrode forming region 37Xc of a polysilicon film 37X is formed, and a contact electrode 38a including a contact electrode forming region 37Xa of a polysilicon film 37X and a contact electrode 38b including a contact electrode forming region 37Xb of a polysilicon film 37X are formed. That is, the contact electrodes 38a and 38b are composed of the same layer (same steps and same materials) as the gate electrode 37. The patterning of the polysilicon film 37X can be performed using a known photolithography technique, a dry etching technique, or the like.

[0610] In this step, the gate electrode 37 is formed to face the upper surface portion 33a and each of the two side surface portions 33c1 and 33c2 of the semiconductor portion 33, with the gate insulating film 36 interposed therebetween. Specifically, the gate electrode 37 includes: a head (first portion) 37a, which is disposed on the upper surface portion 33a side of the semiconductor portion 33, with the gate insulating film 36 interposed therebetween; and two leg portions (second portions) 37b1 and 37b2, which are integrally formed with the head 37a and are disposed on the outer side of each of the two side portions 3c1 and 3c2 located on the opposite sides in the lateral direction (X direction) of the semiconductor portion 33, with the gate insulating film 36 interposed therebetween. The head 37a protrudes upward from the semiconductor portion 33. The two leg portions 37b1 and 37b2 are respectively disposed on the outer side of the semiconductor portion 33 to clamp the semiconductor portion 33.

[0611] Furthermore, in this step, in a plan view, the contact electrode 38a is formed to overlap the semiconductor portion 33 on the side of one side surface portion 33c3 of the two side surface portions 33c3 and 33c4 located in the longitudinal direction (Y direction) of the semiconductor portion 33. Then, the contact electrode 38a includes a head portion 38A1 protruding upward from the semiconductor portion 33 and a leg portion 38A2 formed integrally with the head portion 38A1 and disposed so as to surround one end side (side surface portion 33c3 side) in the longitudinal direction of the semiconductor portion 33. Then, in the contact electrode 38a, on one end side (side surface portion 33c3 side) in the longitudinal direction of the semiconductor portion 33, the head portion 38A1 is connected to the upper surface portion 33a of the semiconductor portion 33, and the leg portion 38A2 is connected to the three side surface portions 33c1, 33c2, and 33c3 of the semiconductor portion 33.

[0612] Furthermore, in this step, the contact electrode 38b is formed so as to overlap with the semiconductor portion 33 on one side of the other side surface portion 33c4 located in the longitudinal direction (Y direction) of the semiconductor portion 33 among the two side surface portions 33c3 and 33c4 in a plan view. Moreover, the contact electrode 38b has a head portion 38b1 protruding upward from the semiconductor portion 33, and a leg portion 38b2 which is integrated with the head portion 38b1 and is provided on the other end side (side surface portion 33c4 side) in the long side direction of the semiconductor portion 33. Then, in the contact electrode 38b, on the other end side (side surface portion 33c4 side) in the longitudinal direction of the semiconductor portion 33, the head portion 38b1 is connected to the upper surface portion 33a of the semiconductor portion 33, and the leg portion 38b2 is connected to the three side surface portions 33c1, 33c2, and 33c4 of the semiconductor portion 33.

[0613] In addition, in this step, the gate insulating film 36 is selectively retained (inserted) between the gate 37 side of the contact electrode 38a and the semiconductor portion 33 on the upper surface portion 33a and the two side surface portions 33c1 and 33c2 of the semiconductor portion 33, and the gate insulating film 36 is selectively retained (inserted) between the gate 37 side of the contact electrode 38b and the semiconductor portion 33 on the upper surface portion 33a and the two side surface portions 33c1 and 33c2 of the semiconductor portion 33.

[0614] Then, in the 10th embodiment, unlike the above-mentioned 6th embodiment, the gate insulating film 36 also remains in the semiconductor portion 33 between the gate electrode 37 and the contact electrodes 38a and 38b. That is, in the 10th embodiment, even after the gate electrode 37 and the two contact electrodes 38a and 38b are formed by patterning the polysilicon film 37X, the upper surface portion 33a and the two side surface portions 33c1 and 33c2 of the semiconductor portion 33 are covered by the gate insulating film 36 above the two contact electrodes 38a and 38b.

[0615] Note that in this step, when the film thickness of the gate insulating film 36 is thin, the gate insulating film 36 in the semiconductor portion 33 between the gate electrode 37 and the contact electrode 38a and the semiconductor portion 33 between the gate electrode 37 and the contact electrode 38b can be selectively removed by over-etching during the patterning of the polysilicon film 33X.

[0616] Next, after removing the mask RM3, heat treatment is performed to activate the impurities (phosphorus ions (P + )) to make the gate electrode 37 conductive (to reduce the resistance value of the gate electrode 37), and to activate the impurities (phosphorus ions (P +)) to make the contact electrodes 38a and 38b conductive (to reduce the resistance value of each of the contact electrodes 38a and 38b).

[0617] In this step, impurities (phosphorus ions (P + )) diffuses (leaks) to both ends of the semiconductor portion 33 in the longitudinal direction (Y direction), and as Fig.96 As shown, the n-type semiconductor region 39a is formed on one end side (side surface portion 33c3 side) in the longitudinal direction (Y direction) of the semiconductor portion 33, and the n-type semiconductor region 39b is formed on the other end side (side surface portion 33c4 side).

[0618] The n-type semiconductor region 39a is formed three-dimensionally (3D) from the upper surface portion 33a to the lower surface portion 33b along the three side surface portions 33c1, 33c2 and 33c3 of the semiconductor portion 33. In addition, the n-type semiconductor region 39b is also formed three-dimensionally (3D) from the upper surface portion 33a to the lower surface portion 33b along the three side surface portions 33c1, 33c2 and 33c4 of the semiconductor portion 33. Each of the n-type semiconductor regions 39a and 39b is formed in the semiconductor portion 33 at a depth reaching the first insulating film 32 on the lower surface portion 33b side from the upper surface portion 33a side of the semiconductor portion 33.

[0619] In addition, during the heat treatment of this step, a natural oxide film 33X (see Fig.51D and Fig.51E ) is fluidized and becomes a granular oxide 33Y (see Fig.54A and Fig.54B ) phenomenon.

[0620] Next, if Fig.97 As shown, a pair of n-type semiconductor regions 40a and 40b having an impurity concentration lower than that of n-type semiconductor regions 39a and 39b is formed in each semiconductor portion 33 on both sides of the gate length direction (Y direction) of the gate electrode 37. Each of the pair of n-type semiconductor regions 40a and 40b serves as an extension region.

[0621] Each of the pair of n-type semiconductor regions 40a and 40b can be introduced with, for example, arsenic ions (As) as n-type impurities by using the gate electrode 37 and the contact electrodes 38a and 38b as impurity introduction masks. + ) is implanted into each semiconductor portion 33 on both sides of the gate length direction (Y direction) of the gate electrode 37, and then the semiconductor portion is subjected to a heat treatment for activating the impurities. For example, unlike the sixth embodiment described above, arsenic ion (As) is implanted under the conditions of a dose of about 1×1014 / cm2 and an acceleration energy of about 80 to 150 keV. +) is implanted. Phosphorus ions (P + ) can be used as n-type impurities.

[0622] In this step, each of a pair of n-type semiconductor regions 40 a and 40 b is formed on each of the semiconductor portions 33 located on both sides of the gate electrode 37 in the gate length direction (Y direction) to be aligned with the head 37 a of the gate electrode 37 .

[0623] In addition, one semiconductor region 40a of a pair of n-type semiconductor regions 40a and 40b is formed in the semiconductor portion 33 in contact with the n-type semiconductor region 39a, and the other semiconductor region 40b is formed in the semiconductor portion 33 in contact with the n-type semiconductor region 39b.

[0624] Furthermore, each of the n-type semiconductor regions 40 a and 40 b is formed in the semiconductor portion 33 at a depth reaching the first insulating film 32 on the lower surface portion 33 b side from the upper surface portion 33 a side of the semiconductor portion 33 .

[0625] In addition, in the heat treatment of this step, a natural oxide film 33X (see Fig.51D and Fig.51E ) is fluidized and becomes a granular oxide 33Y (see Fig.54A and Fig.54B ) phenomenon.

[0626] Next, if Fig.98 and Fig.99 As shown, the sidewall spacer 41c is formed on the sidewall of the gate electrode 37, and the sidewall spacers 41a and 41b are formed on the sidewalls of the contact electrodes 38a and 38b, respectively.

[0627] For example, each of the sidewall spacers 41a, 41b and 41c can be formed as follows: a silicon nitride film is formed as an insulating film on the entire surface of the first insulating film 32 by a CVD method to cover the contact electrodes 38a and 38b and the gate electrode 37, and then anisotropic dry etching such as RIE is applied to the silicon nitride film.

[0628] The sidewall spacer 41a is formed to surround the contact electrode 38a and is formed to be aligned with the contact electrode 38a. The sidewall spacer 41b is formed to surround the contact electrode 38b and is formed to be aligned with the contact electrode 38b. The sidewall spacer 41c is formed to surround the gate electrode 37 and is formed to be aligned with the gate electrode 37.

[0629] The sidewall spacers 41a, 41b, and 41c are formed on the first insulating film 32 and the semiconductor portion 33 so as to intersect the semiconductor portion 33. The sidewall spacer 41a is formed adjacent to the head 38A1 of the contact electrode 38a on the semiconductor portion 33, and is formed adjacent to the head 38A1 and the leg 38A2 of the contact electrode 38a on the outside of the semiconductor portion 33. The sidewall spacer 41b is formed adjacent to the head 38b1 of the contact electrode 38b on the semiconductor portion 33, and is formed adjacent to the head 38b1 and the leg 38b2 of the contact electrode 38b on the outside of the semiconductor portion 33. The sidewall spacer 41c is formed adjacent to the head 37a of the gate electrode 37 on the semiconductor portion 33, and is formed adjacent to the head 37a and the leg 37b1, 37b2 of the gate electrode 37 on the outside of the semiconductor portion 33. That is, in each sidewall spacer 41a, 41b and 41c, the length of the semiconductor portion 33 along the thickness direction (Z direction) is different between the portion overlapping with the semiconductor portion 33 and the portion not overlapping with the semiconductor portion 33 in a plan view, and the length of the portion not overlapping with the semiconductor portion 33 is greater than the length of the portion overlapping with the semiconductor portion 33.

[0630] Then, if Fig.100 As shown, a buffer insulating film 42 is formed. The buffer insulating film 42 is formed to cover the head 37a of the gate electrode 37, the heads 38A1 and 38b1 of the two contact electrodes 38a and 38b, and the sidewall spacers 41a, 41b, and 41c, respectively, and is formed to cover the semiconductor portion 33 between the head 37a of the gate electrode 37 and the contact electrodes 38a and 38b. The buffer insulating film 42 is used as a buffer film when ion implanting impurities in the step of forming n-type semiconductor regions 43a and 43b described later. As the buffer insulating film 42, for example, a silicon oxide film can be used.

[0631] Next, if Fig.101 As shown, a pair of n-type semiconductor regions 43 a and 43 b having a higher impurity concentration than the n-type semiconductor regions 39 a and 39 b are formed in each semiconductor portion 33 on both sides of the gate length direction (Y direction) of the gate electrode 37 .

[0632] Each of the pair of n-type semiconductor regions 43a and 43b can be formed by using the gate electrode 37, the contact electrodes 38a and 38b, and the sidewall spacers 41a, 41b and 41c as impurity introduction masks to introduce, for example, phosphorus ions (P +) are injected into the semiconductor portion 33 between the sidewall spacer 41c of the side wall of the gate electrode 37 and the sidewall spacer 41a of the side wall of the contact electrode 38a, and into the semiconductor portion 33 between the sidewall spacer 41c of the side wall of the gate electrode 37 and the sidewall spacer 41b of the contact electrode 38b through the buffer insulating film 42, and then the semiconductor portion is subjected to heat treatment for activating the impurities.

[0633] Phosphorus ion (P + ) is implanted under conditions different from those of the sixth embodiment described above. For example, at a dose of about 8×10 15 / cm 2 The phosphorus ion (P + ) is implanted. Arsenic ions (As + ) can be used as n-type impurities.

[0634] In this step, due to the phosphorus ion (P + ) is implanted into the semiconductor portion 33 through the buffer insulating film 42, so that damage to the semiconductor portion 33 due to ion implantation can be suppressed.

[0635] Furthermore, in this step, the n-type semiconductor region 43a is formed to be aligned with the sidewall spacer 41c of the sidewall of the gate electrode 37 and the sidewall spacer 41a of the sidewall of the contact electrode 38a. Furthermore, the n-type semiconductor region 43b is formed to be aligned with the sidewall spacer 41c of the sidewall of the gate electrode 37 and the sidewall spacer 41b of the sidewall of the contact electrode 38b.

[0636] Furthermore, in this step, unlike the above-described sixth embodiment, the n-type semiconductor regions 43 a and 43 b extend from the upper surface side to the lower surface side of the semiconductor portion 33 , and are formed at a depth reaching the first insulating film 32 .

[0637] Furthermore, in this step, a main electrode region 44a including n-type semiconductor region 39a, n-type semiconductor region 40a and n-type semiconductor region 43a and a main electrode region 44b including n-type semiconductor region 39b, n-type semiconductor region 40b and n-type semiconductor region 43b are formed.

[0638] Furthermore, in this step, the channel forming portion 45 is formed in the semiconductor portion 33 between the pair of main electrode regions 44 a and 44 b .

[0639] Furthermore, in this step, a field effect transistor Qf including the gate insulating film 36 , the gate electrode 37 , the pair of main electrode regions 44 a and 44 b , the channel forming portion 45 , and the like is formed in the semiconductor portion 33 .

[0640] In addition, in the heat treatment of this step, a natural oxide film 33X (see Fig.51D and Fig.51E ) is fluidized and becomes a granular oxide 33Y (see Fig.54A and Fig.54B ) phenomenon.

[0641] Next, if Fig.102 As shown, a third insulating film 46 (second insulating film 46 or insulating film 46) is formed on the entire surface of the buffer insulating film 42 to cover the semiconductor portion 33, the gate electrode 37, and the contact electrodes 38a and 38b. The third insulating film 46 can be formed by forming, for example, a silicon oxide film as an insulating film on the entire surface of the buffer insulating film 42 including the gate electrode 37 and the heads 37a, 38A1, and 38b1 of the contact electrodes 38a and 38b, and then planarizing the surface of the silicon oxide film by a CMP method or the like.

[0642] In this step, the insulating layer 47J including the first insulating film 32 , the buffer insulating film 42 , and the third insulating film 46 and including the semiconductor portion 33 and the field effect transistor Qf is formed.

[0643] Next, by performing the same steps as those of the sixth embodiment, the grooves 48a, 48b, 48c, the contact electrodes 49a, 49b, 49c, and the wirings 50a, 50b, 50c are formed. Figures 79 to 82 Status shown.

[0644] Note that in the case where the gate insulating film 36 remains in the semiconductor portion 33 between the gate electrode 37 and the contact electrodes 38a and 38b as in the tenth embodiment, the buffer insulating film 42 may be omitted. In this case, the insulating layer 47J does not include the buffer insulating film 42.

[0645] In the manufacturing method of the tenth embodiment, fluorine ions (F) are implanted into the polysilicon film 37X to promote the transformation from the natural oxide film 33X to the granular oxide 33Y. - ), but the fluorine ion (F) may be omitted when the impurities are introduced to a certain extent to ensure fluidization of the natural oxide film 33X by heat treatment. - ) injection.

[0646] In addition, in the manufacturing method of the tenth embodiment, the heat treatment for activating impurities of the n-type semiconductor regions 40a and 40b and the heat treatment for activating impurities of the n-type semiconductor regions 43a and 43b are performed in separate steps, but the heat treatment for activating impurities of the n-type semiconductor regions 40a and 40b may be performed in the same step as the heat treatment for activating impurities of the n-type semiconductor regions 43a and 43b.

[0647] <<Main Effects of the Tenth Embodiment>>

[0648] Similar to the semiconductor device 1F according to the sixth embodiment described above, the semiconductor device 1J according to the tenth embodiment includes contact electrodes 38a and 38b, which are arranged to overlap with the semiconductor portion 33 on both sides of the gate length direction (Y direction) of the gate electrode 37 in a plan view. Then, the contact electrode 38a is connected to each of the upper surface portion 33a of the semiconductor portion 33 and the three side surface portions 33c1, 33c2, and 33c3 on one end side in the longitudinal direction (Y direction) of the semiconductor portion 33. Similarly, the contact electrode 38b is also connected to each of the upper surface portion 33a of the semiconductor portion 33 and the three side surface portions 33c1, 33c2, and 33c4 on the other end side in the longitudinal direction (Y direction) of the semiconductor portion 33.

[0649] Therefore, also in the semiconductor device 1J according to the tenth embodiment, effects similar to those of the semiconductor device 1F according to the above-described sixth embodiment can be obtained.

[0650] Furthermore, in the method for manufacturing the semiconductor device 1J according to the tenth embodiment, unlike the method for manufacturing the semiconductor device 1F according to the sixth embodiment described above, the step of forming the second insulating film 34 and the step of forming the grooved portions 35c1, 35c2, 35a, and 35b in the second insulating film 34 are omitted. Therefore, according to the method for manufacturing the semiconductor device 1J of the tenth embodiment, the number of manufacturing steps can be reduced compared to the method for manufacturing the semiconductor device 1F according to the sixth embodiment described above, and the transconductance (gm) of the field effect transistor Qf can be improved at low cost.

[0651] In addition, when groove portions 35c1, 35c2, 35a and 35b are formed in the second insulating film 34, damage in the process of the semiconductor portion 33 caused by etching can be eliminated, and therefore, changes in the characteristics of the field effect transistor Qf can be suppressed and the field effect transistor Qf can be manufactured with higher reliability.

[0652] In addition, according to the manufacturing method of the semiconductor device 1J of the tenth embodiment, as in the sixth embodiment, the gate electrode 37, the contact electrode 38a, and the head portions 37a, 38A1, and 38b1 of the contact electrode 38b have substantially the same height, so when the groove portions 48a, 48b, and 48c are formed on the insulating film 46 by dry etching, the overetching amount can be reduced, so that the opening width of each groove portion can be reduced, and the variation can be reduced. As a result, the variation of the contact resistance, wiring resistance, and wiring capacitance can be suppressed, and a semiconductor device 1J having excellent robustness can be provided.

[0653] Note that the field effect transistor Qf and the contact electrodes 38a and 38b according to the tenth embodiment can be applied to the solid-state imaging device 1I according to the above-described ninth embodiment. In this case as well, effects similar to those of the solid-state imaging device 1I according to the above-described ninth embodiment can be obtained.

[0654] In addition, in the semiconductor device 1J according to the tenth embodiment, similar to the semiconductor device 1G according to the above-mentioned seventh embodiment, the contact electrodes 49a, 49b and 49c can be omitted, and each of the wirings 50a, 50b and 50c can be directly connected to each of the contact electrodes 38a and 38b and the gate electrode 37.

[0655] [Eleventh Embodiment]

[0656] <<Application Examples of Electronic Equipment>>

[0657] The present technology (technology according to the present disclosure) can be applied to, for example, various electronic devices such as an imaging device such as a digital still camera or a digital video camera, a mobile phone with an imaging function, or another device with an imaging function.

[0658] Fig.103 is a diagram illustrating a schematic configuration of an electronic device (for example, a camera) according to a tenth embodiment of the present technology.

[0659] like Fig.103 As shown, the electronic device 200 includes a solid-state imaging device 201, an optical lens 202, a shutter device 203, a drive circuit 204, and a signal processing circuit 205. The electronic device 200 shows an embodiment in which the solid-state imaging device 1E according to the fifth embodiment of the present technology or the solid-state imaging device 1I according to the ninth embodiment is used as the solid-state imaging device 201 in an electronic device (e.g., a camera).

[0660] The optical lens 202 forms an image of the image light (incident light 206) from the object on the imaging surface of the solid-state imaging device 201. As a result, the signal charge is accumulated in the solid-state imaging device 201 within a certain period of time. The shutter device 203 controls the light irradiation period and the light shielding period of the solid-state imaging device 201. The drive circuit 204 provides a drive signal for controlling the transmission operation of the solid-state imaging device 201 and the shutter operation of the shutter device 203. The signal of the solid-state imaging device 201 is transmitted by the drive signal (timing signal) provided from the drive circuit 204. The signal processing circuit 205 performs various types of signal processing on the signal (pixel signal (image signal)) output from the solid-state imaging device 201. The video signal after signal processing is stored in a storage medium such as a memory, or is output to a monitor.

[0661] With this configuration, in the electronic device 200 according to the eleventh embodiment, the transconductance of the pixel transistor is improved in the solid-state imaging device 201, so that the image quality can be improved.

[0662] It should be noted that the electronic device 200 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera and can also be applied to other electronic devices. For example, the present invention can be applied to an imaging device such as a camera module of a mobile device such as a mobile phone or a tablet terminal.

[0663] In addition, in addition to the above-mentioned solid-state imaging device as an image sensor, the present technology can be applied to all light detection devices including distance measurement sensors called time-of-flight (ToF) sensors that measure distances, etc. A distance measuring sensor is a sensor that emits irradiation light toward an object, detects reflected light obtained by reflecting the irradiation light on the surface of the object, and calculates the distance to the object based on the flight time from the emission of the irradiation light to the reception of the reflected light. The above-mentioned structure of the element isolation region can be adopted as the structure of the element isolation region of the distance measuring sensor.

[0664] [Other embodiments]

[0665] In the above-described embodiment, description has been made of the case where the field effect transistor is provided in the rectangular parallelepiped semiconductor portion extending in the Y direction. However, the present technology is not limited to the rectangular parallelepiped semiconductor portion.

[0666] For example, the present technology can also be applied to a semiconductor device having a field effect transistor in which a channel forming portion and a gate electrode are provided at a corner of a semiconductor portion having an L-shaped planar shape.

[0667] In addition, in the above-mentioned first to tenth embodiments, the island-shaped semiconductor portions 3 and 33 provided on the first insulating films 2 and 32 have been described as the semiconductor portion to which the contact electrode is connected. However, the present technology is not limited to the island-shaped semiconductor portions 3 and 33 provided on the insulating films 2 and 22.

[0668] For example, the present technology can also be applied to a case where a contact electrode is connected to an island-shaped semiconductor portion that protrudes integrally from a substrate portion composed of a semiconductor.

[0669] It should be noted that the present technology can have the following configurations. (1)

[0671] A semiconductor device comprising:

[0672] a semiconductor portion having an island shape, the island shape having an upper surface portion and a side surface portion;

[0673] A field effect transistor having a gate electrode disposed on a semiconductor portion, with a gate insulating film interposed between the gate electrode and the semiconductor portion;

[0674] an insulating layer covering the field effect transistor; and

[0675] a contact electrode disposed on the insulating layer so as to overlap the semiconductor portion outside the gate electrode in a plan view,

[0676] The contact electrodes are connected to the upper surface portion and the side surface portion of the semiconductor portion. (2)

[0678] The semiconductor device according to (1), wherein the gate electrode is provided on an upper surface portion and a side surface portion in a first direction of the semiconductor portion, and

[0679] The contact electrode is positioned closer to the gate electrode than an end portion of the semiconductor portion in a second direction intersecting the first direction. (3)

[0681] The semiconductor device according to (2), wherein the contact electrode is connected to at least one of two of the side surface portions of the semiconductor portion located on opposite sides in the first direction. (4)

[0683] The semiconductor device according to any one of (1) to (3), wherein the semiconductor portion further includes a lower surface portion opposite to the upper surface portion, and

[0684] A contact electrode is also connected to the lower surface portion. (5)

[0686] The semiconductor device according to any one of (2) to (4), wherein the field effect transistor further includes a sidewall spacer provided on a sidewall of the gate electrode, and

[0687] The width of the contact electrode is narrower than a width including the gate electrode and the sidewall spacers on both sides of the gate electrode in a first direction of the semiconductor portion. (6)

[0689] The semiconductor device according to any one of (1) to (7), further including a through contact electrode penetrating the insulating layer and provided on an outer side of the semiconductor portion in the first direction so as to be adjacent to the contact electrode,

[0690] Here, the contact electrode is connected to a side surface portion of the semiconductor portion on a side opposite to a side of the through contact electrode. (7)

[0692] The semiconductor device according to any one of (1) to (6), wherein the field effect transistor further includes a pair of main electrode regions provided on the semiconductor portion on both sides of the gate electrode in the gate length direction, and

[0693] The contact electrode is electrically connected to one of the pair of main electrode regions. (8)

[0695] The semiconductor device according to any one of (1) to (7), further comprising: a photoelectric conversion unit; and a pixel circuit that converts the signal charge photoelectrically converted by the photoelectric conversion unit into a pixel signal,

[0696] At least one of the plurality of pixel transistors included in the pixel circuit is configured by a field effect transistor. (9)

[0698] The semiconductor device according to (8), further includes a semiconductor layer which is arranged to overlap with the semiconductor portion in a plan view and is provided with the photoelectric conversion unit. (10)

[0700] A semiconductor device, comprising: a semiconductor portion, the semiconductor portion having an island shape, the island shape having an upper surface portion and a side surface portion;

[0701] A field effect transistor having a gate electrode disposed on a semiconductor portion, with a gate insulating film interposed between the gate electrode and the semiconductor portion;

[0702] an insulating layer covering the field effect transistor; and

[0703] a contact electrode disposed on the insulating layer so as to overlap the semiconductor portion outside the gate electrode in a plan view,

[0704] Among them, the contact electrode is connected to the upper surface portion and the side surface portion of the semiconductor portion, and is formed in the same layer as the gate electrode. (11)

[0706] The semiconductor device according to (10), wherein the semiconductor portion is composed of a single crystal, and

[0707] The contact electrode is composed of a polycrystalline semiconductor material. (12)

[0709] The semiconductor device according to (10) or (11), wherein a plurality of insulators are interspersed between the semiconductor portion and the contact electrode. (13)

[0711] The semiconductor device according to any one of (10) to (12), wherein the gate insulating film is selectively provided on the upper surface portion and the side surface portion between the gate electrode side of the contact electrode and the semiconductor portion. (14)

[0713] The semiconductor device according to any one of (10) to (13), wherein portions of the gate electrode and the contact electrode overlapping with the semiconductor portion in a plan view have the same thickness. (15)

[0715] The semiconductor device according to any one of (10) to (14), wherein the gate electrode is provided over an upper surface portion and a side surface portion in the first direction of the semiconductor portion, and

[0716] The contact electrode is positioned closer to the gate electrode than an end portion of the semiconductor portion in a second direction intersecting the first direction. (16)

[0718] The semiconductor device according to (15), wherein the contact electrode is connected to at least one of two side surface portions located on opposite sides in the first direction of the semiconductor portion. (17)

[0720] The semiconductor device according to any one of (1) to (16), wherein the semiconductor portion further includes a lower surface portion opposite to the upper surface portion, and

[0721] A contact electrode is also connected to the lower surface portion. (18)

[0723] The semiconductor device according to any one of (10) to (17), wherein the contact electrode is a first contact electrode,

[0724] The semiconductor device further includes a second contact electrode overlapping the first contact electrode in a plan view while being connected to the first contact electrode. (19)

[0726] The semiconductor device according to any one of (10) to (18), wherein a wiring provided on a side opposite to a side of the semiconductor portion of the insulating layer is connected to the contact electrode. (20)

[0728] An electronic device, comprising:

[0729] Semiconductor devices;

[0730] an optical lens that forms an image of image light from a subject on an imaging surface of the semiconductor device; and

[0731] a signal processing circuit that performs signal processing on a signal output from the semiconductor device,

[0732] Semiconductor devices include:

[0733] a semiconductor portion having an island shape, the island shape having an upper surface portion and a side surface portion;

[0734] A field effect transistor having a gate electrode provided on an upper surface portion and a side surface portion of a semiconductor portion, with a gate insulating film interposed between the gate electrode and the side surface portion;

[0735] an insulating layer covering the field effect transistor; and

[0736] a contact electrode disposed on the insulating layer so as to overlap the semiconductor portion outside the gate electrode in a plan view,

[0737] The contact electrodes are connected to the upper surface portion and the side surface portion of the semiconductor portion.

[0738] The scope of the present technology is not limited to the exemplary embodiments shown and described, but also includes all embodiments that provide equivalent effects to the effects of the intended present technology. In addition, the scope of the present technology is not limited to the combination of the features of the present invention defined by the claims, but can be defined by any desired combination of specific features in all disclosed corresponding features.

[0739] Reference Symbols List

[0740] 1A, 1B, 1C, 1D, 1F, 1F1, 1F2, 1F3, 1G, 1H, 1J semiconductor devices

[0741] 1E, 1I solid-state imaging device

[0742] 2First insulating film (substrate insulating film)

[0743] 3Semiconductor part (first semiconductor layer)

[0744] 3a Upper surface

[0745] 3b Lower surface

[0746] 3c1, 3c2, 3c3, 3c4 side parts

[0747] 4. Second insulating film (surrounding insulating film)

[0748] 5a, 5b trenching part (gate electrode trenching part)

[0749] 6 Gate insulation film

[0750] 7. Gate electrode

[0751] 7a Head (Part 1)

[0752] 7b1, 7b2, 7b3 Legs (Part 2)

[0753] 7X Gate Material

[0754] 8 Extended area

[0755] 9 Sidewall spacers

[0756] 10 Contact area

[0757] 11a, 11b Main electrode area

[0758] 12Channel formation portion

[0759] 13Third insulating film (cover insulating film)

[0760] 14 Insulation layer (including insulation layer)

[0761] 15a, 15b, 15c Grooved parts

[0762] 16a, 16b, 16c Barrier metal film

[0763] 17a, 17b, 17c contact electrodes

[0764] 22nd floor

[0765] 23 Grooving

[0766] 24 Through contact electrode

[0767] 32 first insulating film (substrate insulating film)

[0768] 33 semiconductor portion (first semiconductor layer)

[0769] 33a Upper surface

[0770] 33b Lower surface part

[0771] 33c1, 3c2, 3c3, 3c4 side parts

[0772] 33X Natural Oxide Film

[0773] 33Y Oxide

[0774] 34 Second insulating film (surrounding insulating film)

[0775] 35a, 35b, 35c1, 35c2 grooved parts

[0776] 36 Gate insulation film

[0777] 37 Gate electrode

[0778] 37a Head (Part 1)

[0779] 37b1, 37b2 Legs (Part 2)

[0780] 38a, 38b contact electrodes (first contact electrodes)

[0781] 38A1, 38b1 Head (first part)

[0782] 38A2, 38b2 Legs (Part 2)

[0783] 39a, 39b n-type semiconductor region

[0784] 40a, 40b n-type semiconductor region (extension region)

[0785] 41a, 41b, 41c side wall spacers

[0786] 42 Buffer insulation film

[0787] 43a, 43b n-type semiconductor region

[0788] 44a, 44b main electrode area

[0789] 45 channel forming part

[0790] 46 third insulating film (cover insulating film)

[0791] 47, 47J Insulation layer (including insulation layer)

[0792] 48a, 48b, 48c grooved parts

[0793] 49a, 49b, 49c contact electrodes (second contact electrodes)

[0794] 50a, 50b, 50c wiring

[0795] 102Semiconductor Chip

[0796] 102A pixel array unit

[0797] 102B Peripheral part

[0798] 103 pixels

[0799] 104 Vertical drive circuit

[0800] 105 columns signal processing circuit

[0801] 106 Horizontal drive circuit

[0802] 107 Output Circuit

[0803] 108 Control Circuit

[0804] 110 pixel drive lines

[0805] 111 vertical signal line

[0806] 113 Logic Circuits

[0807] 114 Pads

[0808] 115 Pixel Circuit

[0809] 124 Photoelectric conversion unit

[0810] 130 semiconductor layer (second semiconductor layer)

[0811] 131 Insulation layer

[0812] 141 planarization layer

[0813] 142 Color filter layer

[0814] 143 Lens Layer

[0815] 200 Electronic equipment

[0816] 201 Solid-state imaging device

[0817] 202 Optical lens

[0818] 203 Shutter device

[0819] 204 drive circuit

[0820] 205 Signal Processing Circuit

[0821] 206 Incident light.

Claims

1. A semiconductor device comprising: a semiconductor portion having an island shape, having an upper surface portion and a side surface portion; a field effect transistor having a gate electrode disposed on the semiconductor portion, with a gate insulating film interposed between the gate electrode and the semiconductor portion; an insulating layer, covering the field effect transistor; as well as a contact electrode disposed on the insulating layer so as to overlap the semiconductor portion outside the gate electrode in a plan view, wherein the contact electrode is connected to the upper surface portion and the side surface portion of the semiconductor portion.

2. The semiconductor device according to claim 1, wherein The gate electrode is disposed on the upper surface portion and the side surface portion along a first direction of the semiconductor portion, and The contact electrode is positioned closer to the gate electrode than an end portion of the semiconductor portion in a second direction intersecting the first direction.

3. The semiconductor device according to claim 2, wherein: The contact electrode is connected to at least one of the two side surface portions of the semiconductor portion located on opposite sides in the first direction.

4. The semiconductor device according to claim 1, wherein The semiconductor portion further includes a lower surface portion opposite to the upper surface portion, and The contact electrode is also connected to the lower surface portion.

5. The semiconductor device according to claim 2, wherein: The field effect transistor further includes a sidewall spacer disposed on a sidewall of the gate electrode, and The contact electrode has a width narrower than a width including the gate electrode and the sidewall spacers on both sides of the gate electrode in the first direction of the semiconductor portion.

6. The semiconductor device according to claim 1 , further comprising a through contact electrode penetrating the insulating layer and disposed on an outer side of the semiconductor portion adjacent to the contact electrode in the first direction, in, The contact electrode is connected to the side surface portion on the side of the semiconductor portion opposite to the through contact electrode side.

7. The semiconductor device according to claim 1, wherein The field effect transistor further includes a pair of main electrode regions provided on the semiconductor portion on both sides of the gate electrode in a gate length direction, and The contact electrode is electrically connected to one of the pair of main electrode regions.

8. The semiconductor device according to claim 1 , further comprising a photoelectric conversion unit and a pixel circuit that converts the signal charge photoelectrically converted by the photoelectric conversion unit into a pixel signal, in, At least one of a plurality of pixel transistors included in the pixel circuit is configured by the field effect transistor. 9 . The semiconductor device according to claim 8 , further comprising a semiconductor layer which is arranged to overlap with the semiconductor portion in a plan view and is provided with the photoelectric conversion unit.

10. A semiconductor device comprising a semiconductor portion having an island shape, the semiconductor portion having an upper surface portion and a side surface portion; a field effect transistor having a gate electrode disposed on the semiconductor portion, with a gate insulating film interposed between the gate electrode and the semiconductor portion; an insulating layer, covering the field effect transistor; as well as a contact electrode disposed on the insulating layer so as to overlap the semiconductor portion outside the gate electrode in a plan view, wherein the contact electrode is connected to the upper surface portion and the side surface portion of the semiconductor portion and is formed in the same layer as the gate electrode.

11. The semiconductor device according to claim 10, wherein The semiconductor portion is composed of a single crystal, and The contact electrode is made of a polycrystalline semiconductor material.

12. The semiconductor device according to claim 10, wherein: A plurality of insulators are interspersed between the semiconductor portion and the contact electrode.

13. The semiconductor device according to claim 10, wherein: The gate insulating film is selectively provided on the upper surface portion and the side surface portion between the gate electrode side of the contact electrode and the semiconductor portion.

14. The semiconductor device according to claim 10, wherein: In a plan view, a portion of the gate electrode overlapping the semiconductor portion and a portion of the contact electrode overlapping the semiconductor portion have the same thickness.

15. The semiconductor device according to claim 10, wherein The gate electrode is disposed on the upper surface portion and the side surface portion along a first direction of the semiconductor portion, and The contact electrode is positioned closer to the gate electrode than an end portion of the semiconductor portion in a second direction intersecting the first direction.

16. The semiconductor device according to claim 15, wherein: The contact electrode is connected to at least one of the two side surface portions located on opposite sides of the semiconductor portion in the first direction.

17. The semiconductor device according to claim 10, wherein: The semiconductor portion further includes a lower surface portion opposite to the upper surface portion, and The contact electrode is also connected to the lower surface portion.

18. The semiconductor device according to claim 10, wherein The contact electrode is a first contact electrode, The semiconductor device further includes a second contact electrode connected to the first contact electrode while overlapping the first contact electrode in a plan view.

19. The semiconductor device according to claim 10, wherein: A wiring provided on a side of the insulating layer opposite to the semiconductor layer side is connected to the contact electrode.

20. An electronic device, comprising: Semiconductor devices; an optical lens that forms an image of image light from a subject on an imaging surface of the semiconductor device; as well as a signal processing circuit that performs signal processing on a signal output from the semiconductor device, the semiconductor device comprising: a semiconductor portion having an island shape, having an upper surface portion and a side surface portion; a field effect transistor having a gate electrode provided on the upper surface portion and the side surface portion of the semiconductor portion, with a gate insulating film interposed between the gate electrode and the side surface portion; an insulating layer covering the field effect transistor; and a contact electrode disposed on the insulating layer so as to overlap the semiconductor portion outside the gate electrode in a plan view, wherein the contact electrode is connected to the upper surface portion and the side surface portion of the semiconductor portion.

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