Semiconductor device

Abstract

A semiconductor device (1) is provided with: a rectangular semiconductor chip (2) having a long side extending in a first direction and a short side extending in a second direction; a semiconductor chip (2) is provided with: a first vertical MOS transistor (10) provided with a first gate pad (119) and a plurality of first source pads (111); and a second vertical MOS transistor (20) provided with a second gate pad (129) and a plurality of second source pads (121). A plurality of first column arrangement regions (71) in which the source pads are linearly arranged in the first direction and a plurality of second column arrangement regions (72) in which the source pads are linearly arranged in the second direction are formed on the upper surface of the semiconductor chip (2); the semiconductor device (1) is further provided with a plurality of ball-shaped bump electrodes (3) connected to the first gate pad (119), the plurality of first source pads (111), the second gate pad (129), and the plurality of second source pads (121), respectively.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Conventionally, there is known a semiconductor device (for example, refer to Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-005732 Summary of the invention

[0006] Problems to be solved by the invention

[0007] In recent years, there has been an increasing number of cases where a semiconductor chip is mounted on a mounting substrate and an underfill material is filled between the semiconductor chip and the mounting substrate.

[0008] Therefore, an object of the present disclosure is to provide a semiconductor device including a semiconductor chip, which is suitable for filling an underfill material between the semiconductor chip and the mounting substrate after the semiconductor device is mounted on the mounting substrate.

[0009] Means used to solve problems

[0010] A semiconductor device according to a technical solution of the present disclosure is a chip-size package type semiconductor device that can be mounted face-down; the semiconductor device comprises a rectangular semiconductor chip whose long sides extend in a first direction and whose short sides extend in a second direction in a planar view of the semiconductor device; the semiconductor chip comprises: a semiconductor layer having a semiconductor substrate; and a first vertical MOS transistor and a second vertical MOS transistor, the first vertical MOS transistor being formed in a first region of the semiconductor layer, and the second vertical MOS transistor being formed in a second region of the semiconductor layer, the first region and the second region being one side and the other side that divide the semiconductor chip into two equal parts in terms of area in the planar view; the semi-conductor layer has a semiconductor substrate; and a semiconductor layer having a semiconductor substrate; and a semiconductor layer having a semiconductor substrate; and a semiconductor layer having a semiconductor substrate; and the ... The conductive substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; the boundary line between the first region and the second region is a line segment extending in the second direction; the first vertical MOS transistor has a first gate pad and a plurality of first source pads on the upper surface of the semiconductor chip in the first region; the second vertical MOS transistor has a second gate pad and a plurality of second source pads on the upper surface of the semiconductor chip in the second region; in the above-mentioned planar observation, the first gate pad, the plurality of first source pads, the second gate pad and the plurality of second source pads are circular with a diameter less than 378 μm; The upper surface of the chip, in the above-mentioned plane observation, is configured with a plurality of first column configuration areas and a plurality of second column configuration areas, in the above-mentioned plurality of first column configuration areas, more than 4 and less than 2nx source pads among the above-mentioned plurality of first source pads and the above-mentioned plurality of second source pads are configured in a straight line with their respective centers arranged in the above-mentioned first direction, and in the above-mentioned plurality of second column configuration areas, more than 2 and less than ny source pads among the above-mentioned plurality of first source pads or the above-mentioned plurality of second source pads are configured in a straight line with their respective centers arranged in the above-mentioned second direction; in the above-mentioned plane observation, the width of each of the above-mentioned plurality of first column configuration areas is equal to the width of the above-mentioned four and less than 2nx source pads configured in the first column configuration area. The maximum diameter among the diameters of the above 2nx or less source pads, the width of each of the above multiple second column-shaped configuration areas is equal to the maximum diameter among the diameters of the above 2 or more and ny or less source pads configured in the second column-shaped configuration area; in the above plane observation, let the length of the above long side be Lx in μm, let the length of the above short side be Ly in μm, let the maximum diameter among the diameters of the above multiple first source pads and the above multiple second source pads be rs in μm, then nx is the largest integer greater than 2 for which the relationship nx<1 / 3×(Lx / rs-3) holds; ny is the largest integer greater than 2 for which the relationship ny<2 / 3×(Ly / rs-1) holds;In the above-mentioned planar observation, the closest distance between the plurality of first source pads and the plurality of second source pads, and the closest distance between the plurality of second row-shaped configuration areas are rs / 2 or more and are in μm, and the diameter of the first gate pad and the diameter of the second gate pad are rs and are in μm; in the above-mentioned planar observation, the first gate pad is arranged farther from the boundary line than the second row-shaped configuration area closest to the boundary line in the first area among the plurality of second row-shaped configuration areas; in the above-mentioned planar observation, the second gate pad is arranged farther from the boundary line than the second row-shaped configuration area closest to the boundary line in the second area among the plurality of second row-shaped configuration areas; the above-mentioned semiconductor device further comprises a plurality of ball-shaped bump electrodes that are connected in a one-to-one contact manner at positions directly above the first gate pad, the plurality of first source pads, the second gate pad, and the plurality of second source pads. ;

[0011] Effects of the Invention

[0012] According to a semiconductor device of one aspect of the present disclosure, there is provided a semiconductor device suitable for filling an underfill material between a semiconductor chip and a mounting substrate after the semiconductor device is mounted on a mounting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view showing an example of the structure of a semiconductor device according to an embodiment.

[0014] Figure 2 This is a cross-sectional view schematically showing an example of a state in which the semiconductor device according to the embodiment is mounted on a mounting substrate according to the embodiment.

[0015] Figure 3 It is a plan view showing an example of the structure of a semiconductor device according to an embodiment.

[0016] Figure 4 It is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment.

[0017] Figure 5 It is a plan view of a typical example of a semiconductor chip according to the embodiment.

[0018] Figure 6 Schematic diagram showing the relationship between the diameter of the pad according to the embodiment and the height of the ball-type bump electrode after the heat treatment according to the embodiment.

[0019] Fig. 7A This is a plan view showing an example of the positional relationship between the first gate pad and the plurality of first source pads, and an example of the positional relationship between the second gate pad and the plurality of second source pads according to the embodiment.

[0020] Figure 7B This is a plan view showing an example of the positional relationship between the first gate pad and the plurality of first source pads, and an example of the positional relationship between the second gate pad and the plurality of second source pads according to the embodiment.

[0021] Figure 8 It is a plan view showing the longest distance between adjacent source pads in the second row arrangement region according to the embodiment.

[0022] Fig.9A FIG. 1 is a cross-sectional view showing an example of a cross section of a ball-type bump electrode after heat treatment according to the embodiment.

[0023] Fig. 9B FIG. 1 is a cross-sectional view showing an example of a cross section of a ball-type bump electrode after heat treatment according to the embodiment.

[0024] Fig.10 This is a table showing the relationship between the diameter of the pad, the height of the ball-type bump electrode after the heat treatment, and the diameter of the ball-type bump electrode before the heat treatment according to the embodiment.

[0025] Fig.11A 1 is a line graph showing the relationship between the diameter of the source pad and the number of source pads that can be arranged in the second row arrangement region according to the embodiment.

[0026] Fig. 11B It is a line graph showing the relationship between the diameter of the source pad and the occupancy rate of the total area of ​​the source pad with respect to the area of ​​the upper surface of the semiconductor chip according to the embodiment.

[0027] Fig.12 It is a plan view showing another example of the structure of the semiconductor device according to the embodiment.

[0028] Fig.13 It is a plan view showing another example of the structure of the semiconductor device according to the embodiment.

[0029] Fig.14 It is a plan view showing another example of the structure of the semiconductor device according to the embodiment. DETAILED DESCRIPTION

[0030] (Process of obtaining a technical solution of the present disclosure)

[0031] Conventionally, there is known a semiconductor chip composed of a dual-structure vertical MOS transistor having a common drain, which is used for overcharge protection and / or overdischarge protection of a lithium-ion battery.

[0032] A relatively large current flows through such a semiconductor chip. Therefore, it is desired to reduce the resistance of the current path of the current flowing through the semiconductor chip and to improve the heat dissipation of the semiconductor chip.

[0033] On the other hand, as described above, in recent years, there has been an increasing number of cases in which an underfill material is filled between a semiconductor chip and a mounting substrate after the semiconductor chip is mounted on the mounting substrate.

[0034] In order to appropriately fill the gap between the semiconductor chip and the mounting substrate with an underfill material, it is effective to provide ball-shaped bump electrodes on the mounting surface of the semiconductor chip.

[0035] However, if the spacing between the ball-shaped bump electrodes is enlarged in order to improve the permeability of the bottom filling material, the resistance of the current path of the current flowing through the semiconductor chip increases, and the heat dissipation of the semiconductor chip decreases. On the contrary, if the spacing between the ball-shaped bump electrodes is narrowed in order to reduce the resistance of the current path of the current flowing through the semiconductor chip or / and improve the heat dissipation of the semiconductor chip, the permeability of the bottom filling material decreases.

[0036] Therefore, the inventors have conducted special experiments and research on a semiconductor device that can improve the penetration of the bottom filling material after a semiconductor chip composed of a dual-structure vertical MOS transistor with a common drain is mounted on a mounting substrate, and suppress the high resistance of the current path of the current flowing through the semiconductor chip and the decrease in the heat dissipation of the semiconductor chip.

[0037] As a result, the inventors conceived of the semiconductor device of the present disclosure described below.

[0038] A semiconductor device according to a technical solution of the present disclosure is a chip-size package type semiconductor device that can be mounted face-down; the semiconductor device comprises a rectangular semiconductor chip whose long sides extend in a first direction and whose short sides extend in a second direction in a planar view of the semiconductor device; the semiconductor chip comprises: a semiconductor layer having a semiconductor substrate; and a first vertical MOS transistor and a second vertical MOS transistor, the first vertical MOS transistor being formed in a first region of the semiconductor layer, and the second vertical MOS transistor being formed in a second region of the semiconductor layer, the first region and the second region being one side and the other side that divide the semiconductor chip into two equal parts in terms of area in the planar view; the semi-conductor layer has a semiconductor substrate; and a semiconductor layer having a semiconductor substrate; and a semiconductor layer having a semiconductor substrate; and a semiconductor layer having a semiconductor substrate; and the ... The conductive substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; the boundary line between the first region and the second region is a line segment extending in the second direction; the first vertical MOS transistor has a first gate pad and a plurality of first source pads on the upper surface of the semiconductor chip in the first region; the second vertical MOS transistor has a second gate pad and a plurality of second source pads on the upper surface of the semiconductor chip in the second region; in the above-mentioned planar observation, the first gate pad, the plurality of first source pads, the second gate pad and the plurality of second source pads are circular with a diameter less than 378 μm; The upper surface of the chip, in the above-mentioned plane observation, is configured with a plurality of first column configuration areas and a plurality of second column configuration areas, in the above-mentioned plurality of first column configuration areas, more than 4 and less than 2nx source pads among the above-mentioned plurality of first source pads and the above-mentioned plurality of second source pads are configured in a straight line with their respective centers arranged in the above-mentioned first direction, and in the above-mentioned plurality of second column configuration areas, more than 2 and less than ny source pads among the above-mentioned plurality of first source pads or the above-mentioned plurality of second source pads are configured in a straight line with their respective centers arranged in the above-mentioned second direction; in the above-mentioned plane observation, the width of each of the above-mentioned plurality of first column configuration areas is equal to the width of the above-mentioned four and less than 2nx source pads configured in the first column configuration area. The maximum diameter among the diameters of the above 2nx or less source pads, the width of each of the above multiple second column-shaped configuration areas is equal to the maximum diameter among the diameters of the above 2 or more and ny or less source pads configured in the second column-shaped configuration area; in the above plane observation, let the length of the above long side be Lx in μm, let the length of the above short side be Ly in μm, let the maximum diameter among the diameters of the above multiple first source pads and the above multiple second source pads be rs in μm, then nx is the largest integer greater than 2 for which the relationship nx<1 / 3×(Lx / rs-3) holds; ny is the largest integer greater than 2 for which the relationship ny<2 / 3×(Ly / rs-1) holds;In the above-mentioned planar observation, the closest distance between the plurality of first source pads and the plurality of second source pads, and the closest distance between the plurality of second row-shaped configuration areas are rs / 2 or more and are in μm, and the diameter of the first gate pad and the diameter of the second gate pad are rs and are in μm; in the above-mentioned planar observation, the first gate pad is arranged farther from the boundary line than the second row-shaped configuration area closest to the boundary line in the first area among the plurality of second row-shaped configuration areas; in the above-mentioned planar observation, the second gate pad is arranged farther from the boundary line than the second row-shaped configuration area closest to the boundary line in the second area among the plurality of second row-shaped configuration areas; the above-mentioned semiconductor device further comprises a plurality of ball-shaped bump electrodes that are connected in a one-to-one contact manner at positions directly above the first gate pad, the plurality of first source pads, the second gate pad, and the plurality of second source pads. ;

[0039] According to the semiconductor device of the above structure, when the semiconductor device is mounted face down on the mounting substrate, a straight gap extending in the second direction is ensured between the semiconductor chip and the mounting substrate. Thus, the bottom filling material can flow into between the semiconductor chip and the mounting substrate through the straight gap.

[0040] Furthermore, generally speaking, when a semiconductor device having a rectangular semiconductor chip is mounted face down on a mounting substrate by reflow, it is known that due to the heat during reflow, the semiconductor chip may bend in a direction away from the mounting substrate toward the center along the long side direction of the semiconductor chip, i.e., the first direction.

[0041] In contrast, according to the semiconductor device of the above structure, the straight gap ensured extends in the second direction perpendicular to the first direction. Therefore, even if the semiconductor chip is bent along the first direction in a direction in which the center portion is away from the mounting substrate when the semiconductor device is mounted on the mounting substrate, the bottom filling material can flow between the semiconductor chip and the mounting substrate through the straight gap extending in the second direction perpendicular to the first direction.

[0042] Therefore, according to the semiconductor device having the above structure, when the semiconductor device is mounted on a mounting substrate, the penetration of the underfill material can be improved regardless of whether the semiconductor chip is bent.

[0043] Furthermore, according to the semiconductor device having the above structure, it is possible to ensure a relatively large number of ball-shaped bump electrodes provided directly above the plurality of first source pads and the plurality of second source pads.

[0044] Therefore, according to the semiconductor device having the above structure, after the semiconductor device is mounted on a mounting substrate, it is possible to suppress the increase in resistance of the current path of the current flowing through the semiconductor chip and to suppress the decrease in the heat dissipation of the semiconductor chip.

[0045] Thus, according to the semiconductor device with the above structure, the penetration of the underfill material after the semiconductor device is mounted on the mounting substrate can be improved, and the resistance of the current path flowing through the semiconductor chip can be suppressed from increasing, thereby suppressing the reduction of the heat dissipation of the semiconductor chip.

[0046] Therefore, according to the semiconductor device having the above structure, it is possible to provide a semiconductor device suitable for filling an underfill material between the semiconductor chip and the mounting substrate after the semiconductor device is mounted on the mounting substrate.

[0047] Furthermore, in the planar view, the closest distance between the plurality of first row-shaped arrangement regions may be greater than or equal to rs / 2, with the unit being μm.

[0048] Thus, even when the semiconductor device is mounted face down on the mounting substrate, a straight gap extending in the first direction is ensured between the semiconductor chip and the mounting substrate.

[0049] Therefore, after the semiconductor device is mounted on the mounting substrate, the penetration of the underfill material can be further improved.

[0050] Furthermore, in the planar view, the diameters of the plurality of first source pads and the plurality of second source pads may be rs, with the unit being μm.

[0051] Thus, even when the semiconductor device is mounted face down on the mounting substrate, it is possible to suppress the increase in resistance of the current path of the current flowing through the semiconductor chip, thereby suppressing a decrease in the heat dissipation of the semiconductor chip.

[0052] In addition, it may be that, in the above-mentioned planar observation, in each of the above-mentioned multiple first-column configuration areas, the diameter of the above-mentioned 4 or more and 2nx or less source pads configured in the first-column configuration area decreases monotonically in the direction from the source pad farthest from the boundary line toward the source pad closest to the boundary line in the above-mentioned first area, and decreases monotonically in the direction from the source pad farthest from the boundary line toward the source pad closest to the boundary line in the above-mentioned second area.

[0053] Generally speaking, when a spherical bump electrode is arranged on a circular pad and heat treatment is performed to join the spherical bump electrode to the circular pad, the smaller the diameter of the circular pad is, the higher the height of the spherical bump electrode from the surface of the semiconductor chip after the heat treatment is.

[0054] Therefore, according to the semiconductor device of the above structure, when the semiconductor device is mounted on a mounting substrate, in a case where the semiconductor chip is bent along the first direction toward the direction in which the central portion is away from the mounting substrate, if a direction orthogonal to the first direction and the second direction is set as a third direction, then in each of the first column-shaped configuration areas, the position of the highest point in the third direction of the spherical bump electrode directly above each source pad can be made relatively consistent.

[0055] In addition, it may be that, in the above-mentioned planar observation, in each of the above-mentioned multiple first column-shaped configuration areas, the closest distance of the above-mentioned 4 or more and 2nx or less source pads configured in the first column-shaped configuration area increases monotonically in the direction from the source pad farthest from the above-mentioned boundary line toward the closest source pad in the above-mentioned first area, and increases monotonically in the direction from the source pad farthest from the above-mentioned boundary line toward the closest source pad in the above-mentioned second area.

[0056] As described above, generally speaking, in a state where a spherical bump electrode is arranged on a circular pad, if a heat treatment is performed in order to bond the spherical bump electrode to the circular pad, the smaller the diameter of the circular pad, the higher the height of the spherical bump electrode from the surface of the semiconductor chip after the heat treatment. In addition, in a case where the distance between the centers of the circular pads is equal, the smaller the diameter of the circular pad, the larger the closest distance of the circular pad. That is, in this case, it can be said that the higher the closest distance of the pad increases, the higher the height of the spherical bump electrode from the surface of the semiconductor chip.

[0057] Therefore, according to the semiconductor device of the above structure, when the semiconductor device is mounted on a mounting substrate, in a case where the semiconductor chip is bent along the first direction toward the direction in which the center portion is away from the mounting substrate, if a direction orthogonal to the first direction and the second direction is set as a third direction, then in each of the first column-shaped configuration areas, the position of the highest point in the third direction of the spherical bump electrode directly above each source pad can be made relatively consistent.

[0058] In addition, it may be that, in the above-mentioned planar observation, in each of the second column-shaped configuration areas among the above-mentioned multiple second column-shaped configuration areas that are most closely opposed to each other with the above-mentioned boundary line, the diameter of the above-mentioned more than 2 and less than ny source pads is equal to the smallest diameter among the diameters of the above-mentioned multiple first source pads and the above-mentioned multiple second source pads.

[0059] As described above, generally speaking, when a spherical bump electrode is arranged on a circular pad, if heat treatment is performed in order to join the spherical bump electrode to the circular pad, the smaller the diameter of the circular pad is, the higher the height of the spherical bump electrode from the surface of the semiconductor chip after the heat treatment will be.

[0060] Therefore, according to the semiconductor device of the above structure, when the semiconductor device is mounted on a mounting substrate, in a case where the semiconductor chip is bent along the first direction toward the direction in which the center portion is away from the mounting substrate, if a direction orthogonal to the first direction and the second direction is set as a third direction, then in each of the first column-shaped configuration areas, the position of the highest point in the third direction of the spherical bump electrode directly above each source pad can be made relatively consistent.

[0061] In addition, it may be that, in the above-mentioned planar observation, in each of the above-mentioned multiple first-column configuration areas, the height of the spherical bump electrode among the above-mentioned multiple spherical bump electrodes located directly above each of the above-mentioned 4 or more and 2nx or less source pads configured in the first-column configuration area from the upper surface of the above-mentioned semiconductor chip monotonically increases in the direction from the spherical bump electrode farthest from the above-mentioned boundary line toward the spherical bump electrode closest to the above-mentioned first area, and monotonically increases in the direction from the spherical bump electrode farthest from the above-mentioned boundary line toward the spherical bump electrode closest to the above-mentioned second area.

[0062] Therefore, when the semiconductor device is mounted on a mounting substrate, in a case where the semiconductor chip is bent along the first direction toward the center portion away from the mounting substrate, if a direction orthogonal to the first direction and the second direction is defined as a third direction, then in each of the first column-shaped configuration areas, the position of the highest point in the third direction of the spherical bump electrode directly above each source pad can be made relatively consistent.

[0063] In addition, it may be that, in the above-mentioned planar observation, in each of the above-mentioned multiple first-column configuration areas, the surface area of ​​the spherical bump electrode among the above-mentioned multiple spherical bump electrodes located directly above each of the above-mentioned 4 or more and 2nx or less source pads configured in the first-column configuration area monotonically increases in the direction from the spherical bump electrode farthest from the above-mentioned boundary line toward the spherical bump electrode closest to the above-mentioned first area, and monotonically increases in the direction from the spherical bump electrode farthest from the above-mentioned boundary line toward the spherical bump electrode closest to the above-mentioned second area.

[0064] As described above, generally speaking, when a spherical bump electrode is arranged on a circular pad, if a heat treatment is performed to bond the spherical bump electrode to the circular pad, the smaller the diameter of the circular pad, the higher the height of the spherical bump electrode from the surface of the semiconductor chip after the heat treatment. In addition, generally speaking, the higher the height of the spherical bump electrode from the surface of the semiconductor chip, the more its surface area increases. That is, it can be said that the larger the surface area of ​​the spherical bump electrode, the higher its height from the surface of the semiconductor chip.

[0065] Therefore, according to the semiconductor device of the above structure, when the semiconductor device is mounted on a mounting substrate, in a case where the semiconductor chip is bent along the first direction toward the direction in which the center portion is away from the mounting substrate, if a direction orthogonal to the first direction and the second direction is set as a third direction, then in each of the first column-shaped configuration areas, the position of the highest point in the third direction of the spherical bump electrode directly above each source pad can be made relatively consistent.

[0066] Furthermore, in each of the second column-shaped arrangement regions that are most closely opposed to each other with the boundary line interposed therebetween among the plurality of second column-shaped arrangement regions in the planar view, the number of the two or more and ny or less source pads may be ny.

[0067] In the semiconductor device of the above structure, among the current paths of the current flowing through the semiconductor chip, the current path of the current flowing through the semiconductor chip via the source pad in the second column-shaped configuration area which is closest to each other with a boundary line sandwiched among multiple second column-shaped configuration areas is the shortest within the semiconductor chip.

[0068] Therefore, by setting the number of source pads in the second column-shaped configuration areas that are most closely opposed to the boundary line in a plurality of second column-shaped configuration areas to the maximum number ny between 2 and ny as in the above-mentioned structure, after the semiconductor device is mounted on the mounting substrate, the high resistance of the current path of the current flowing through the semiconductor chip can be suppressed.

[0069] In addition, it may be that, in the above-mentioned planar observation, the distance between the above-mentioned first gate pad and the first source pad closest to the above-mentioned first gate pad among the above-mentioned multiple first source pads is greater than rs, and is larger than the closest distance of the above-mentioned multiple first source pads; the distance between the above-mentioned second gate pad and the second source pad closest to the above-mentioned second gate pad among the above-mentioned multiple second source pads is greater than rs, and is larger than the closest distance of the above-mentioned multiple second source pads.

[0070] This can suppress short circuits between the first gate pad and any one of the plurality of first source pads and short circuits between the second gate pad and any one of the plurality of second source pads.

[0071] In addition, it may be that, in the above-mentioned planar observation, the longest distance among the distances between mutually adjacent source pads among the above-mentioned more than 2 and less than ny source pads in each of the above-mentioned multiple second column-shaped configuration areas, that is, the adjacent longest distance, in the above-mentioned first area, decreases monotonically in the direction from the second column-shaped configuration area farthest from the above-mentioned boundary line among the above-mentioned multiple second column-shaped configuration areas toward the second column-shaped configuration area closest to the above-mentioned first area, and in the above-mentioned second area, decreases monotonically in the direction from the second column-shaped configuration area farthest from the above-mentioned boundary line among the above-mentioned multiple second column-shaped configuration areas toward the second column-shaped configuration area closest to the above-mentioned second area; each of the above-mentioned multiple first column-shaped configuration areas The number of source pads among the above-mentioned 4 or more and 2nx or less, with respect to (1) more than two first-column-arrangement areas among the above-mentioned multiple first-column-arrangement areas whose distance to the long side of one of the above-mentioned long sides is shorter than the distance to the long side of the other side, decreases monotonically in the direction from the first-column-arrangement area closest to the above-mentioned one long side toward the first-column-arrangement area farthest away, and with respect to (2) more than two first-column-arrangement areas whose distance to the long side of the above-mentioned other side is shorter than the distance to the long side of the above-mentioned one side, decreases monotonically in the direction from the first-column-arrangement area closest to the above-mentioned other long side toward the first-column-arrangement area farthest away.

[0072] In addition, it may be that, in the above-mentioned planar observation, the position in the above-mentioned second direction of each of the above-mentioned 4 or more and 2nx or less source pads in the 1st column-shaped configuration area on one side of the above-mentioned multiple first column-shaped configuration areas adjacent to each other is inconsistent with the position in the above-mentioned second direction of any of the above-mentioned 4 or more and 2nx or less source pads in the 1st column-shaped configuration area on the other side of the above-mentioned multiple first column-shaped configuration areas adjacent to each other.

[0073] Alternatively, rs may be 196 to 226, or 250 to 280.

[0074] In addition, it may be that, in the above-mentioned planar observation, in each of the above-mentioned multiple first-column configuration areas, among the above-mentioned 4 or more and 2nx or less source pads configured in the first-column configuration area, the diameter of the source pad farthest from the above-mentioned boundary line in the above-mentioned first area and the diameter of the source pad farthest from the above-mentioned boundary line in the above-mentioned second area are 250 μm or more and 280 μm or less, and the diameter of the source pad closest to the above-mentioned boundary line in the above-mentioned first area and the diameter of the source pad closest to the above-mentioned boundary line in the above-mentioned second area are 196 μm or more and 226 μm or less.

[0075] In addition, it is possible that the rs is greater than 150; the height of the plurality of spherical bump electrodes from the upper surface of the semiconductor chip is 70 μm or more and 130 μm or less; the cross-sectional area under the plane parallel to the upper surface of the semiconductor chip of the plurality of spherical bump electrodes monotonically decreases as the distance from the upper surface of the semiconductor chip increases from a closer distance to a farther distance.

[0076] Hereinafter, a specific example of a semiconductor device according to one aspect of the present disclosure will be described with reference to the accompanying drawings. The embodiments described herein all represent specific examples of the present disclosure. Therefore, the numerical values, shapes, constituent elements, arrangements and connection forms of the constituent elements, and steps (processes) and the order of steps described in the following embodiments are given as examples and are not intended to limit the present disclosure. In addition, the drawings are schematic views and are not necessarily strictly drawn. In each drawing, the same reference numerals are given to substantially the same structures, and repeated descriptions are omitted or simplified.

[0077] In the present disclosure, the distance between a first element and a second element means the shortest distance between an arbitrary point on the outer periphery of the first element and an arbitrary point on the outer periphery of the second element.

[0078] In addition, in the present disclosure, the closest distance between a plurality of elements means the shortest distance among the distances between each pair of the two elements among all the plurality of elements.

[0079] In addition, in the present disclosure, changing monotonically means a function that is a monotonically increasing function in a broad sense or a monotonically decreasing function in a broad sense. That is, a monotonically increasing function in a broad sense means a function f(x) such that f(x1) ≤ f(x2) when x1 < x2, and a monotonically decreasing function in a broad sense means a function f(x) such that f(x1) ≥ f(x2) when x1 < x2.

[0080] (Embodiment)

[0081] <Structure of Semiconductor Device>

[0082] Hereinafter, the structure of the semiconductor device according to the embodiment will be described. The semiconductor device according to the embodiment is a semiconductor device including a semiconductor chip having a dual structure in which two vertical MOS (Metal Oxide Semiconductor) transistors sharing a drain are formed, and a plurality of spherical bump electrodes. The two vertical MOS transistors are, for example, so-called trench MOS transistors. Here, it is assumed that the two vertical MOS transistors are so-called trench MOS transistors and will be described.

[0083] Figure 1 is a perspective view showing an example of the structure of the semiconductor device 1 according to the embodiment. As Figure 1As shown, the semiconductor device 1 includes a semiconductor chip 2 and a plurality of ball-shaped bump electrodes 3 arranged on the upper surface of the semiconductor chip 2 .

[0084] More specifically, in the semiconductor device 1, on the upper surface of the semiconductor chip 2, there are a plurality of spherical bump electrodes 3 that are connected, i.e., joined, in a one-to-one contact manner, at positions directly above each of the first gate pad 119 described later, the plurality of first source pads 111 described later, the second gate pad 129 described later, and the plurality of second source pads 121 described later.

[0085] The plurality of ball-shaped bump electrodes 3 are formed by, for example, heat-treating solder ball materials.

[0086] Figure 2 1 is a cross-sectional view schematically showing an example of a state in which the semiconductor device 1 is mounted on a mounting substrate 500. Figure 2 As shown, the semiconductor device 1 is mounted face down on the mounting substrate 500 .

[0087] like Figure 2 As shown, since the semiconductor device 1 has a plurality of ball-shaped bump electrodes 3 on the upper surface of the semiconductor chip 2, a gap is ensured between the semiconductor chip 2 and the mounting substrate 500 when the semiconductor device 1 is mounted on the mounting substrate 500. Therefore, when the semiconductor device 1 is mounted on the mounting substrate 500, the bottom filling material can penetrate between the semiconductor chip 2 and the mounting substrate 500.

[0088] Figure 3 is a plan view showing an example of the structure of the semiconductor device 1. However, Figure 3 This is a diagram in which the illustration of a plurality of ball-shaped bump electrodes 3 is omitted. Figure 3 It is also a plan view of the semiconductor chip 2 .

[0089] like Figure 3 As shown, in the plan view of the semiconductor device 1, that is, in the plan view of the semiconductor chip 2, the semiconductor chip 2 has its long side in the first direction ( Figure 3 The short side extends in the second direction ( Figure 3 A rectangle extending in the Y-axis direction).

[0090] Figure 4 It is a cross-sectional view showing an example of the structure of the semiconductor device 1 . Figure 4 express Figure 3 The cross section at I-I.

[0091] like Figure 3 , Figure 4As shown, the semiconductor chip 2 includes a metal layer 30, a semiconductor layer 40, an oxide film 34, a protective film 35, a first vertical MOS transistor 10 formed in the semiconductor layer 40 in the first area A1, and a second vertical MOS transistor 20 formed in the semiconductor layer 40 in the second area A2. The first area A1 and the second area A2 are one side and the other side that divide the semiconductor chip 2 into two equal parts in terms of area when the semiconductor chip 2 is observed in a planar manner.

[0092] Here, in the plan view of the semiconductor device 1, the boundary line 90 between the first region A1 and the second region A2 is in the second direction ( Figure 3 A line segment extending in the Y-axis direction in .

[0093] The boundary line 90 can be understood as an imaginary line along the center position of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. In addition, although it has a limited width, it can also be understood as the interval itself. Even in the case of this interval, it can be recognized as a line in the appearance at a low magnification or with the naked eye.

[0094] Here, in the first region A1, the first vertical MOS transistor 10 includes a first source electrode 11 and a Figure 3 , Figure 4 The first gate electrode 19 not shown in the figure (described later) Figure 5 In the second region A2, the second vertical MOS transistor 20 includes a second source electrode 21 and a Figure 3 , Figure 4 The second gate electrode 29 not shown in the figure (described later) Figure 5 (see figure in the figure).

[0095] In addition, here, on the upper surface of the semiconductor chip 2 in the first area A1, the first vertical MOS transistor 10 has a first gate pad 119 and a plurality of first source pads 111, and on the upper surface of the semiconductor chip 2 in the second area A2, the second vertical MOS transistor 20 has a second gate pad 129 and a plurality of second source pads 121.

[0096] Here, in plan view of semiconductor device 1 , first gate pad 119 , first source pads 111 , second gate pad 129 , and second source pads 121 are circular in shape with a diameter smaller than 378 μm.

[0097] In the present disclosure, the semiconductor chip 2 is described assuming that it includes the metal layer 30 , but the semiconductor chip 2 is not necessarily limited to the structure including the metal layer 30 .

[0098] The semiconductor layer 40 is formed by laminating a semiconductor substrate 32 and a low-concentration impurity layer 33 .

[0099] The semiconductor substrate 32 is arranged on the lower surface side of the semiconductor layer 40 , and is made of silicon containing impurities of the first conductivity type.

[0100] The low-concentration impurity layer 33 is disposed on the upper surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and contains first-conductivity-type impurities at a concentration lower than the first-conductivity-type impurities of the semiconductor substrate 32. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32 by epitaxial growth, for example.

[0101] The oxide film 34 is disposed on the upper surface of the semiconductor layer 40 and is formed in contact with the low-concentration impurity layer 33 .

[0102] The protection film 35 is a protection film that covers the upper surface of the first vertical MOS transistor 10 and the upper surface of the second vertical MOS transistor 20 , and has a plurality of openings.

[0103] Here, the protective film 35 covering the upper surface of the first vertical MOS transistor 10 and the upper surface of the second vertical MOS transistor 20 refers to a state in which the protective film 35 is formed on substantially the entire surface of the semiconductor chip 2 except for the opening portion in a planar observation of the semiconductor layer 40. Here, substantially the entire surface of the semiconductor chip 2 refers to the entire surface of the semiconductor chip 2 except for the peripheral region slightly remaining at the four sides of the semiconductor chip 2 after slicing in the region of the wafer ensured as a slicing margin when the semiconductor chip 2 is sliced ​​from the wafer. Therefore, in this peripheral region, the oxide film 34 is exceptionally exposed on the upper surface of the semiconductor chip 2.

[0104] In addition, the opening of the protective film 35 referred to in the present disclosure refers to a shape in which the entire length of the periphery of the opening is closed by the protective film 35 in a planar view of the semiconductor device 1. Therefore, in a planar view of the semiconductor device 1, a shape in which a part of the periphery of the opening overlaps with the peripheral area of ​​the oxide film 34 exceptionally exposed on the upper surface of the semiconductor chip 2 does not correspond to the opening of the protective film 35 referred to in the present disclosure.

[0105] The metal layer 30 is formed in contact with the lower surface of the semiconductor substrate 32, and can be made of silver, copper, nickel or their alloys, or a metal material with good conductivity that can function as an electrode. In addition, the metal layer 30 may also contain trace amounts of elements other than metals mixed as impurities during the manufacturing process of the metal material.

[0106] The first body region 18 including impurities of a second conductivity type different from the first conductivity type is formed in the low concentration impurity layer 33 of the first region A1. In the first body region 18, the first gate conductor 15, the first gate insulating film 16, and the first source region 14 including impurities of the first conductivity type are formed.

[0107] The first source electrode 11 is composed of a portion 12 and a portion 13 , and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13 .

[0108] The first gate conductor 15 is connected via Figure 3 , Figure 4 The first gate wiring 61 (not shown) Figure 5 Figure ) and Figure 3 , Figure 4 The first gate electrode 19 (not shown) Figure 5 (Figure 2) Electrical connections.

[0109] The portion 12 is a layer that contacts and connects to the spherical bump electrode 3, i.e., is bonded to the spherical bump electrode 3, and can be made of one or more metal materials including nickel, titanium, tungsten, and palladium as a non-limiting example. The upper surface of the portion 12 can be plated with gold or the like.

[0110] The upper surface of the portion 12 has a plurality of exposed portions exposed on the upper surface of the semiconductor chip 2 through the plurality of openings of the protective film 35. These plurality of exposed portions correspond to the plurality of first source pads 111. That is, the plurality of first source pads 111 are the plurality of exposed portions of the portion 12, respectively.

[0111] The portion 13 is a layer connecting the portion 12 to the first source region 14 and the first body region 18 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver as a non-limiting example.

[0112] In addition, Figure 3 , Figure 4 The first gate electrode 19 (not shown) Figure 5 The upper surface of the semiconductor chip 2 (shown in the figure) has an exposed portion exposed on the upper surface of the semiconductor chip 2 through the opening of the protective film 35. The exposed portion corresponds to the first gate pad 119. That is, the first gate pad 119 is Figure 3 , Figure 4 The first gate electrode 19 (not shown) Figure 5 The exposed portion of the

[0113] The second body region 28 including impurities of a second conductivity type different from the first conductivity type is formed in the low concentration impurity layer 33 of the second region A2. In the second body region 28, a second source region 24 including impurities of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed.

[0114] The second source electrode 21 is composed of a portion 22 and a portion 23 , and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23 .

[0115] The second gate conductor 25 is connected via Figure 3 , Figure 4 The second gate wiring 62 (not shown) Figure 5 Figure ) and Figure 3 , Figure 4 The second gate electrode 29 (not shown) Figure 5 (Figure 2) Electrical connections.

[0116] The portion 22 is a layer that contacts and connects to the spherical bump electrode 3, i.e., is bonded to the spherical bump electrode 3, and can be made of one or more metal materials including nickel, titanium, tungsten, and palladium as a non-limiting example. The upper surface of the portion 22 can be plated with gold or the like.

[0117] The upper surface of the portion 22 has a plurality of exposed portions exposed on the upper surface of the semiconductor chip 2 through the plurality of openings of the protective film 35. These plurality of exposed portions correspond to the plurality of second source pads 121. That is, the plurality of second source pads 121 are the plurality of exposed portions of the portion 22, respectively.

[0118] The portion 23 is a layer connecting the portion 22 to the second source region 24 and the second body region 28 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver as a non-limiting example.

[0119] In addition, Figure 3 , Figure 4 The second gate electrode 29 (not shown) Figure 5 The upper surface of the semiconductor chip 2 is provided with an exposed portion exposed on the upper surface of the semiconductor chip 2 through the opening of the protective film 35. The exposed portion corresponds to the second gate pad 129. That is, the second gate pad 129 is Figure 3 , Figure 4 The second gate electrode 29 (not shown) Figure 5 The exposed portion of the

[0120] With the above-described structures of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, a portion of the low-concentration impurity layer 33 and the semiconductor substrate 32 function as a common drain region obtained by commonizing the first drain region of the first vertical MOS transistor 10 and the second drain region of the second vertical MOS transistor 20. That is, the semiconductor substrate 32 functions as a common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20.

[0121] In the semiconductor chip 2, for example, the first conductivity type may be set to N type, the second conductivity type may be set to P type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 may be N type semiconductors, and the first body region 18 and the second body region 28 may be P type semiconductors.

[0122] In addition, in the semiconductor chip 2, for example, the first conductivity type can be set to P type, the second conductivity type can be set to N type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 are P type semiconductors, and the first body region 18 and the second body region 28 are N type semiconductors.

[0123] In the present disclosure, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are described assuming that they are so-called N-channel transistors in which the first conductivity type is N-type and the second conductivity type is P-type.

[0124] In addition, in the present disclosure, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are described assuming that they are the same. Further, in the present disclosure, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are described assuming that they are in a line symmetric relationship with the boundary line 90 as the symmetry axis in the plan view of the semiconductor device 1.

[0125] like Figure 3 As shown, on the upper surface of the semiconductor chip 2, in the plan view of the semiconductor device 1, a plurality of first columnar configuration areas 71 (corresponding to Figure 3 In the first column configuration area 71A to the first column configuration area 71E), four or more 2nx (the definition of nx will be described later, in the first column configuration area 71A to the first column configuration area 71E) of the plurality of first source pads 111 and the plurality of second source pads 121 are arranged. Figure 3 In the example shown, nx is 4) or less, the centers of the source pads are arranged in a straight line in the first direction; and a plurality of second columnar configuration areas 72 (corresponding to Figure 3 In the second column configuration area 72A to the second column configuration area 72H), two or more ny (the definition of ny will be described later) of the plurality of first source pads 111 or the plurality of second source pads 121 are arranged in Figure 3 In the example shown, the centers of the source pads (ny = 4) or less are arranged in a straight line in the second direction.

[0126] Here, in the planar observation of the semiconductor device 1, the width of each of the multiple first column-shaped configuration areas 71 is equal to the maximum diameter among the diameters of the source pads configured in the first column-shaped configuration area 71, and the width of each of the multiple second column-shaped configuration areas 72 is equal to the maximum diameter among the diameters of the source pads configured in the second column-shaped configuration area 72.

[0127] In addition, here, in the planar observation of the semiconductor device 1, if the length of the long side of the semiconductor chip 2 is Lx [μm], the length of the short side is Ly [μm], and the maximum diameter among the diameters of the plurality of first source pads 111 and the plurality of second source pads 121 is rs [μm], then nx is the largest integer greater than 2 for which the relationship nx<1 / 3×(Lx / rs-3) holds, and ny is the largest integer greater than 2 for which the relationship ny<2 / 3×(Ly / rs-1) holds.

[0128] In addition, here, in the planar observation of the semiconductor device 1, the closest distance between the multiple first source pads 111 and the multiple second source pads 121, and the closest distance between the multiple second column-shaped configuration areas 72 are greater than rs / 2 [μm], and the diameter of the first gate pad 119 and the diameter of the second gate pad 129 are rs [μm].

[0129] In addition, here, in the planar observation of the semiconductor device 1, the first gate pad 119 is configured in the first area A1 farther away from the boundary line 90 than the second column-shaped configuration area 72 closest to the boundary line 90, and the second gate pad 129 is configured in the second area A2 farther away from the boundary line 90 than the second column-shaped configuration area 72 closest to the boundary line 90.

[0130] <Typical example of semiconductor chip>

[0131] Hereinafter, a typical example of the semiconductor chip 2 will be described.

[0132] Figure 5 FIG. 2 is a plan view of a typical example of a semiconductor chip 2. Figure 5 , the first source electrode 11, the first gate electrode 19, the first gate wiring 61, the second source electrode 21, the second gate electrode 29 and the second gate wiring 62 are illustrated as if they can be visually seen from the outside of the semiconductor chip 2, but in fact, these components cannot be directly visually seen from the outside of the semiconductor chip 2.

[0133] like Figure 5As shown, typically, the diameters of all pads of the semiconductor chip 2 may be the same 200 [μm] in a plan view of the semiconductor device 1. Here, the pads are the first gate pad 119, the plurality of first source pads 111, the second gate pad 129, and the plurality of second source pads 121.

[0134] Typically, when the semiconductor device 1 is viewed in a plan view, the long side of the semiconductor chip 2 is 3400 [μm] and the short side is 1960 [μm].

[0135] In addition, typically, the number of the plurality of first row-arrangement regions 71 of the semiconductor chip 2 may be five, and the number of the plurality of second row-arrangement regions 72 may be eight.

[0136] Typically, all source pads of semiconductor chip 2 are arranged in one of first row arrangement regions 71 and in one of second row arrangement regions 72. Here, source pads refer to first source pads 111 and second source pads 121.

[0137] Typically, the number of source pads arranged in each first row arrangement region 71 of semiconductor chip 2 is 4 to 8, and the number of source pads arranged in each second row arrangement region 72 is 2 to 5.

[0138] Typically, in plan view of the semiconductor device 1 , the closest distance between the plurality of first row-shaped arrangement regions 71 of the semiconductor chip 2 and the closest distance between the plurality of second row-shaped arrangement regions 72 may be 150 [μm].

[0139] <Inspection>

[0140] Below, refer to Figure 2 to Figure 4 The structure of the semiconductor chip 2 having the above-described configuration will be examined.

[0141] During the heat treatment process for bonding the ball-shaped bump electrode 3 to the pad and / or when mounting on the mounting substrate, the ball-shaped bump electrode 3 may overflow from the outer periphery of the pad by a maximum overflow amount of 1 / 4 of the pad diameter in a planar view of the semiconductor device 1. Therefore, in order to prevent the ball-shaped bump electrodes 3 located directly above the adjacent pads from contacting each other even if the ball-shaped bump electrodes 3 are heat treated, the arrangement position of the pad needs to be determined in consideration of the overflow amount.

[0142] In order to make the description less complicated than necessary, the following description is given assuming that the diameters of all the source pads are equal, that is, the maximum diameter is rs [μm].

[0143] In two adjacent source pads, in order to prevent the spherical bump electrodes 3 from contacting each other even if there is an overflow of rs / 4 [μm] from the spherical bump electrodes 3 located directly above each other, the distance between the adjacent source pads is only required to be greater than (rs / 4)×2=rs / 2 [μm].

[0144] If the ball-shaped bump electrodes 3 located right above the mutually adjacent pads do not contact each other, the penetration of the underfill material will not be hindered.

[0145] In particular, since the distance between the adjacent second row-shaped configuration areas 72 is rs / 2 [μm], a straight gap extending in the second direction is ensured between the semiconductor chip 2 and the mounting substrate 500. Thus, the underfill material can flow into between the semiconductor chip 2 and the mounting substrate 500 through these straight gaps.

[0146] In order to prevent the spherical bump electrode 3 from flowing to the outside of the semiconductor chip 2 along the second direction, the distance between the long side of the semiconductor chip 2 and the spherical bump electrode 3 is preferably greater than rs / 2 [μm]. Furthermore, as described above, in the heat treatment process for bonding the spherical bump electrode 3 to the pad and / or when mounting on the mounting substrate, the spherical bump electrode 3 may overflow from the outer periphery of the pad by a maximum overflow amount of 1 / 4 of the diameter of the pad in the planar observation of the semiconductor device 1, so the distance between the long side of the semiconductor chip 2 and the source pad located nearby is preferably greater than rs / 2+rs / 4=rs×3 / 4 [μm].

[0147] From this, it can be seen that the maximum number ny of source pads that can be arranged in second row arrangement region 72 may be the largest integer that satisfies the equation Ly-ny×rs≥(rs / 2)×(ny-1)+rs×(3 / 4)×2.

[0148] That is, it can be seen that ny may be the largest integer for which the relationship ny<2 / 3×(Ly / rs-1) holds.

[0149] It is known that when a semiconductor device 1 having a rectangular semiconductor chip 2 is mounted face down on a mounting substrate 500 by reflow, the semiconductor chip 2 may bend along the long side direction of the semiconductor chip 2, i.e., the first direction, toward the center portion away from the mounting substrate 500 due to the heat during reflow.

[0150] Therefore, in order to prevent the ball-shaped bump electrode 3 from flowing to the outside of the semiconductor chip 2 along the first direction, the distance between the short side of the semiconductor chip 2 and the ball-shaped bump electrode 3 is preferably rs×3 / 4 [μm] or more.

[0151] Furthermore, in order to prevent the short circuit between the first vertical MOS transistor 10 and the second vertical MOS transistor 20 in the center of the semiconductor chip 2 , the distance between the boundary line 90 and the ball-shaped bump electrode 3 is preferably rs×3 / 4 [μm] or more.

[0152] Furthermore, as described above, in the heat treatment process for joining the spherical bump electrode 3 to the pad and / or when installing it on the mounting substrate, the spherical bump electrode 3 may overflow from the outer periphery of the pad by a maximum of 1 / 4 of the diameter of the pad when observing the semiconductor device 1 in a planar manner, so the distance between the short side of the semiconductor chip 2 and the source pad located nearby is preferably greater than rs×3 / 4+rs / 4=rs[μm].

[0153] Similarly, the distance between boundary line 90 and the source pad located near the boundary line 90 is preferably not less than rs×3 / 4+rs / 4=rs [μm].

[0154] Based on this, it can be seen that in the first column configuration area 71, when only observing the range of the first vertical MOS transistor 10, if the maximum number of source pads that can be configured is set to nx, then nx can be the largest integer for which the equation Lx / 2-nx×rs≥(rs / 2)×(nx-1)+rs×2 holds true.

[0155] Since the maximum number of source pads that can be arranged in first row arrangement region 71 is twice nx, it can be seen that twice the largest integer nx that satisfies the relationship nx<1 / 3×(Lx / rs−3) may be sufficient.

[0156] In the planar observation of the semiconductor device 1, the area sandwiched by the two second column-shaped configuration areas 72 that are most closely opposed to each other with the boundary line 90 is the opposing area where the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are opposed to each other, and is the area with the highest current density in the current path of the current flowing through the semiconductor chip 2.

[0157] Therefore, it is preferable that elements that may hinder the flow of current are arranged as little as possible in the opposing region.

[0158] Therefore, in a planar observation of the semiconductor device 1, the first gate pad 119 is preferably configured in the first area A1 farther away from the boundary line 90 than the second column-shaped configuration area 72 closest to the boundary line 90, and the second gate pad 129 is preferably configured in the second area A2 farther away from the boundary line 90 than the second column-shaped configuration area 72 closest to the boundary line 90.

[0159] According to the semiconductor device 1 of the above structure, when the semiconductor device 1 is mounted face down on the mounting substrate 500, straight gaps extending in the second direction are ensured between the semiconductor chip 2 and the mounting substrate 500. Thus, the underfill material can flow into between the semiconductor chip 2 and the mounting substrate 500 through these straight gaps.

[0160] In addition, it is generally known that when a semiconductor device 1 having a semiconductor chip 2 having a rectangular shape in a plan view of the semiconductor device 1 is mounted face-down on a mounting substrate 500 by reflow, the semiconductor chip 2 is deformed along the first direction (the long side direction of the semiconductor chip 2) due to the heat during reflow. Figure 3 A situation in which the central portion is bent in a direction away from the mounting substrate 500 (in the X-axis direction).

[0161] On the other hand, according to the semiconductor device 1 of the above structure, the straight gap ensured is in the second direction ( Figure 3 Therefore, when the semiconductor device 1 is mounted on the mounting substrate 500, even if the semiconductor chip 2 is bent along the first direction in a direction in which the center portion is away from the mounting substrate 500, the bottom filling material can flow into between the semiconductor chip 2 and the mounting substrate 500 through the straight gap extending in the second direction orthogonal to the first direction.

[0162] Therefore, according to the semiconductor device 1 having the above-described structure, when the semiconductor device 1 is mounted on the mounting substrate 500 , the penetration of the underfill material can be improved regardless of whether the semiconductor chip 2 is bent.

[0163] Furthermore, according to the semiconductor device 1 having the above structure, it is possible to ensure a relatively large number or as many as possible of the ball-shaped bump electrodes 3 provided directly above the first source pads 111 and the second source pads 121 .

[0164] Therefore, according to the semiconductor device 1 having the above structure, after the semiconductor device 1 is mounted on the mounting substrate 500 , the resistance of the current path of the current flowing through the semiconductor chip 2 can be suppressed from increasing, and the heat dissipation of the semiconductor chip 2 can be suppressed from decreasing.

[0165] Thus, according to the semiconductor device 1 having the above structure, the penetration of the underfill material after the semiconductor device 1 is mounted on the mounting substrate 500 can be improved, and the resistance of the current path flowing through the semiconductor chip 2 can be suppressed from increasing, thereby suppressing the reduction in the heat dissipation of the semiconductor chip 2.

[0166] Thus, according to the semiconductor device 1 having the above-described structure, a semiconductor device suitable for filling the underfill material between the semiconductor chip 2 and the mounting substrate 500 after the semiconductor device 1 is mounted on the mounting substrate 500 is provided.

[0167] Furthermore, in a plan view of the semiconductor device 1 , the closest distance between the plurality of first row-arranged regions 71 may be rs / 2 [μm].

[0168] Thus, in a state where the semiconductor device 1 is mounted face down on the mounting substrate 500 , a straight gap extending in the first direction is ensured between the semiconductor chip 2 and the mounting substrate 500 .

[0169] Furthermore, in a plan view of semiconductor device 1 , the diameters of first source pads 111 and second source pads 121 may be rs [μm].

[0170] Thus, even when the semiconductor device 1 is mounted face down on the mounting substrate 500 , it is possible to suppress the resistance of the current path of the current flowing through the semiconductor chip 2 from increasing, thereby suppressing the reduction in the heat dissipation of the semiconductor chip 2 .

[0171] Figure 6 It means that the first direction ( Figure 6 The X-axis direction in the middle) and the second direction ( Figure 6 The direction perpendicular to the Y-axis direction in the figure is set as the third direction ( Figure 6 In the Z-axis direction), the pad ( Figure 6 Schematic diagram of the relationship between the diameter of the first gate pad 119, multiple first source pads 111, the second gate pad 129 and multiple second source pads 121) and the height of the spherical bump electrode 3 to the surface of the semiconductor chip 2 in the third direction after heat treatment.

[0172] Generally, solder balls of the same size are used to form the spherical bump electrodes 3. Therefore, when the spherical bump electrodes 3 are brought into contact with the upper surface of the pad by heat treatment, the smaller the diameter of the pad, the higher the height of the spherical bump electrodes 3 from the surface of the semiconductor chip 2.

[0173] Therefore, if Figure 6 As shown, when the semiconductor chip 2 is bent along the first direction toward the center portion away from the mounting substrate 500, the position of the highest point in the third direction of the spherical bump electrode 3 after heat treatment can be made more consistent by making the diameter of the solder pad smaller as the distance from the boundary line 90 increases.

[0174] That is, in each of the multiple first column-shaped configuration areas 71, the diameter of the source pad configured in the first column-shaped configuration area 71 may be monotonically reduced in the direction from the source pad farthest from the boundary line 90 toward the source pad closest to the boundary line in the first area A1, and monotonically reduced in the direction from the source pad farthest from the boundary line 90 toward the source pad closest to the boundary line in the second area A2.

[0175] Thus, in each of the first row-arranged regions 71 , the positions of the highest points of the ball-shaped bump electrodes 3 located directly above the source pads in the third direction can be relatively aligned.

[0176] When the distances between the centers of the source pads are equal, the smaller the diameter of the source pad is, the larger the closest distance of the source pad is. That is, in this case, the larger the closest distance of the source pad is, the smaller the diameter of the source pad is.

[0177] Therefore, in each of the multiple first column-shaped configuration areas 71, the closest distance of the source pads configured in the first column-shaped configuration area 71 can be monotonically increasing in the direction from the source pad farthest from the boundary line 90 toward the closest source pad in the first area A1, and monotonically increasing in the direction from the source pad farthest from the boundary line 90 toward the closest source pad in the second area A2.

[0178] Thus, in each of the first row-arranged regions 71 , the positions of the highest points of the ball-shaped bump electrodes 3 located directly above the source pads in the third direction can be relatively aligned.

[0179] Alternatively, in each of second row-shaped arrangement regions 72 that are most closely opposed to each other with boundary line 90 interposed therebetween, the diameter of the source pad may be equal to the smallest diameter among the diameters of the plurality of first source pads 111 and the plurality of second source pads 121 .

[0180] Thus, in each of the first row-arranged regions 71 , the positions of the highest points of the ball-shaped bump electrodes 3 located directly above the source pads in the third direction can be relatively aligned.

[0181] In addition, in each of the multiple first column-shaped configuration areas 71, the height of the spherical bump electrode 3 located directly above each source pad configured in the first column-shaped configuration area 71 from the upper surface of the semiconductor chip 2 can be monotonically increased in the direction from the spherical bump electrode 3 farthest from the boundary line 90 toward the spherical bump electrode 3 closest to the boundary line in the first area A1, and monotonically increased in the direction from the spherical bump electrode 3 farthest from the boundary line 90 toward the spherical bump electrode 3 closest to the boundary line in the second area A2.

[0182] Thus, in each of the first row-arranged regions 71 , the positions of the highest points of the ball-shaped bump electrodes 3 located directly above the source pads in the third direction can be relatively aligned.

[0183] Generally speaking, the higher the height of the spherical bump electrode 3 from the surface of the semiconductor chip 2 is, the larger the surface area of ​​the spherical bump electrode 3 is. That is, the higher the height of the spherical bump electrode 3 from the surface of the semiconductor chip 2 is, the larger the surface area of ​​the spherical bump electrode 3 is.

[0184] Therefore, in each of the multiple first column-shaped configuration areas 71, the surface area of ​​the spherical bump electrode 3 located directly above each source pad configured in the first column-shaped configuration area 71 can be monotonically increasing in the direction from the spherical bump electrode 3 farthest from the boundary line 90 toward the spherical bump electrode 3 closest to the boundary line in the first area A1, and monotonically increasing in the direction from the spherical bump electrode 3 farthest from the boundary line 90 toward the spherical bump electrode 3 closest to the boundary line in the second area A2.

[0185] Thus, in each of the first row-arranged regions 71 , the positions of the highest points of the ball-shaped bump electrodes 3 located directly above the source pads in the third direction can be relatively aligned.

[0186] In semiconductor device 1 , the current flowing through semiconductor chip 2 via the source pads arranged in second row arrangement region 72 which is most closely opposed across boundary line 90 has the shortest flow distance within semiconductor chip 2 among the currents flowing through semiconductor chip 2 .

[0187] Therefore, the number of source pads may be ny in each of the second columnar configuration regions 72 that are most closely opposed to each other with the boundary line 90 sandwiched therebetween. That is, the number of source pads in each of the second columnar configuration regions 72 that are most closely opposed to each other with the boundary line 90 sandwiched therebetween may be set to the maximum number ny between 2 or more and ny or less.

[0188] Thus, after the semiconductor device 1 is mounted on the mounting substrate 500 , it is possible to suppress the increase in resistance of the current path of the current flowing through the semiconductor chip 2 .

[0189] Fig. 7A , Figure 7B It is a plan view showing an example of the positional relationship between the first gate pad 119 and the plurality of first source pads 111 and an example of the positional relationship between the second gate pad 129 and the plurality of second source pads 121 .

[0190] like Fig. 7A , Figure 7BAs shown, the distance between the first gate pad 119 and the first source pad 111 closest to the first gate pad 119 may be greater than rs and greater than the closest distance between the multiple first source pads 111, and the distance between the second gate pad 129 and the second source pad 121 closest to the second gate pad 129 may be greater than rs and greater than the closest distance between the multiple second source pads 121.

[0191] This can suppress short circuits between the first gate pad and any one of the plurality of first source pads and short circuits between the second gate pad and any one of the plurality of second source pads.

[0192] Figure 8 It is a plan view showing the longest distance among the distances between mutually adjacent source pads in second row arrangement region 72 , that is, the adjacent longest distance.

[0193] like Figure 8 As shown, it can be that, with respect to the longest adjacent distances in the plurality of second columnar configuration regions 72, in the first region A1, the distances are monotonically reduced in the direction from the second columnar configuration region 72 farthest from the boundary line 90 toward the second columnar configuration region 72 closest to the boundary line 90, and in the second region A2, the distances are monotonically reduced in the direction from the second columnar configuration region 72 farthest from the boundary line 90 toward the second columnar configuration region 72 closest to the boundary line 90, and with respect to the number of source pads in each of the plurality of first columnar configuration regions 71, (1) with respect to the number of source pads to the semiconductor chip 2) with respect to two or more first column-shaped configuration areas 71 whose distance to the long side of one side is shorter than the distance to the long side of the other side, the distance decreases monotonically in the direction from the first column-shaped configuration area 71 closest to the long side of one side toward the first column-shaped configuration area 71 farthest away; (2) with respect to two or more first column-shaped configuration areas 71 whose distance to the long side of the other side is shorter than the distance to the long side of one side, the distance decreases monotonically in the direction from the first column-shaped configuration area 71 closest to the long side of the other side toward the first column-shaped configuration area 71 farthest away.

[0194] Furthermore, if Figure 8 As shown, in each of the plurality of first row-shaped arrangement regions 71 , the number of source pads arranged in the first row-shaped arrangement region 71 may decrease two by two as the distance from the long side of the closest semiconductor chip 2 increases row by row.

[0195] Thus, by arranging the first gate pad 119 and the second gate pad 129 on Figure 8 The positions shown can suppress short circuits between the first gate pad 119 and any of the plurality of first source pads 111 and short circuits between the second gate pad 129 and any of the plurality of second source pads 121 .

[0196] Fig.9A , Fig. 9BThis is a cross-sectional view showing an example of a cross section of the ball-type bump electrode 3 after the heat treatment, when the ball-type bump electrode 3 is brought into contact with and connected to the upper surface of the pad by the heat treatment.

[0197] Fig.9A This is a cross-sectional view of a spherical bump electrode 3 in a plane parallel to the upper surface of the semiconductor chip 2 , in which the cross-sectional area decreases monotonically from closer to the upper surface of the semiconductor chip 2 to farther away.

[0198] Here, Fig.9A The spherical bump electrode 3 of the shape shown is also called a dome-shaped bump electrode.

[0199] Fig. 9B This is a cross-sectional view showing a case where the cross-sectional area of ​​the spherical bump electrode 3 in a plane parallel to the upper surface of the semiconductor chip 2 first increases monotonically and then decreases monotonically as it moves from closer to the upper surface of the semiconductor chip 2 to farther away.

[0200] Here, Fig. 9B The spherical bump electrode 3 of the shape shown is also called a non-dome-shaped bump electrode. In the present disclosure, both the dome-shaped bump electrode and the non-dome-shaped bump electrode are the spherical bump electrode 3.

[0201] In order to avoid difficulty in manufacturing the semiconductor device 1 , the spherical bump electrode 3 may be preferably a dome-shaped bump electrode.

[0202] In particular, it is known that, in the case where a water-soluble film is formed on the upper surface of the semiconductor chip 2 in a process after the spherical bump electrode 3 is brought into contact with the upper surface of the pad and connected by heat treatment, when the spherical bump electrode 3 is a non-dome-shaped bump electrode, the formation of the water-soluble film becomes difficult.

[0203] In addition, from the perspective of ensuring the permeability of the bottom filling material between the semiconductor chip 2 and the mounting substrate 500 when the semiconductor device 1 is mounted on the mounting substrate 500, the height of the spherical bump electrode 3 from the upper surface of the semiconductor chip 2 after heat treatment is preferably greater than 70 [μm] and less than 130 [μm].

[0204] It is known that, if the radius of the solder pad when the spherical bump electrode 3 is brought into contact with the upper surface of the solder pad and connected by heat treatment is denoted as r [μm], and the radius of the solder ball material before the heat treatment is denoted as R [μm], then the height H [μm] of the spherical bump electrode 3 from the upper surface of the semiconductor chip 2 after the heat treatment is expressed by the following (Formula 1).

[0205] [Formula 1]

[0206]

[0207] Fig.10 This is a table showing the values ​​[μm] of the diameter (=2R) of the solder ball material before heat treatment required in order to make the height (=H) of the spherical bump electrode 3 after heat treatment 70 [μm], 100 [μm] and 130 [μm] when the diameter of the solder pad (=2r) is 150 [μm], 200 [μm], 250 [μm] and 300 [μm] respectively, as calculated by (Formula 1).

[0208] like Fig.10 As shown, when the pad diameter is 150 [μm], the diameter of the solder ball material before heat treatment is 164 [μm] in order to make the height of the ball-shaped bump electrode 3 after heat treatment 130 [μm]. That is, in this case, the ball-shaped bump electrode 3 after heat treatment becomes a non-dome-shaped bump electrode.

[0209] Therefore, in the range where the spherical bump electrode 3 after heat treatment is a dome-shaped bump electrode, in order to make the height of the spherical bump electrode 3 after heat treatment from the upper surface of the semiconductor chip 2 the desired height of 70 [μm] to 130 [μm], the diameter of the pad needs to be larger than 150 [μm].

[0210] Therefore, it is possible that rs is greater than 150, the height of the multiple spherical bump electrodes 3 from the upper surface of the semiconductor chip 2 is greater than 70 [μm] and less than 130 [μm], and the cross-sectional area of ​​the multiple spherical bump electrodes 3 under the plane parallel to the upper surface of the semiconductor chip 2 decreases monotonically from closer to the upper surface of the semiconductor chip 2 to farther away.

[0211] Furthermore, it is known that when the semiconductor chip 2 bends in a direction in which the center portion moves away from the mounting substrate 500 along the first direction which is the longitudinal direction of the semiconductor chip 2 , the warpage may reach 30 [μm].

[0212] Therefore, in such a case, it is preferred that when the height of the spherical bump electrode 3 arranged directly above the pad located near the short side of the semiconductor chip 2 is set to 100 [μm], the diameter of the pad is pre-adjusted so that the height of the ball arranged directly above the pad located near the boundary line 90 becomes 130 [μm].

[0213] Therefore, in such a case, Fig.10 As shown by the arrows, it is preferable that the diameter of the pad located near the short side of the semiconductor chip 2 is set to about 250 [μm], and the diameter of the pad located near the boundary line 90 is adjusted to about 200 [μm].

[0214] Furthermore, it is preferable to perform adjustment according to the warpage amount of the semiconductor chip 2 so that the diameter of the pad gradually changes to an appropriate value in the first direction.

[0215] Fig.11A It is a line graph showing the relationship between the diameter rs1 [μm] of the source pad and the number ny1 [number] of source pads that can be arranged in the second column configuration area 72 when the length Lx of the long side of the semiconductor chip 2 is 3400 [μm], the length Ly of the short side is 1960 [μm], and the diameters of all source pads are consistent with rs1 [μm].

[0216] like Fig.11A As shown, the number of source pads that can be arranged in one second row arrangement region 72 changes in stages according to the diameter of the source pads.

[0217] like Fig.11A As shown, if the diameter of the source pad becomes 378 [μm] or more, only one source pad can be arranged in one second row arrangement region 72. That is, the source pads can no longer be arranged in a row in the second direction. Therefore, the diameter of the source pad is preferably less than 378 [μm].

[0218] Furthermore, as described above, the diameter of the source pad needs to be larger than 150 [μm].

[0219] Fig. 11B It is a line graph showing the relationship between the diameter rs1 [μm] of the source pad and the occupancy rate [%] of the total area of ​​the source pads of the semiconductor chip 2 relative to the area of ​​the upper surface of the semiconductor chip 2 when the length Lx of the long side of the semiconductor chip 2 is 3400 [μm], the length Ly of the short side is 1960 [μm], and the diameters of all the source pads are consistent with rs1 [μm].

[0220] In order to suppress the increase in resistance of the current path of the current flowing through semiconductor chip 2 and suppress the reduction in heat dissipation of semiconductor chip 2, the larger the occupancy rate of the total area of ​​the source pads of semiconductor chip 2 relative to the surface area of ​​the upper surface of semiconductor chip 2, the better.

[0221] Therefore, the diameter of the source pad is Fig. 11B As shown, it is preferable that the total area of ​​the source pads of the semiconductor chip 2 has a maximum occupancy rate of 226 [μm] or 280 [μm] relative to the surface area of ​​the upper surface of the semiconductor chip 2 .

[0222] On the other hand, when the semiconductor chip 2 is actually manufactured, the diameter of the source pad may vary by ±15 [μm] due to manufacturing variations. Therefore, considering the manufacturing variations, the diameter of the source pad is preferably 196 [μm] to 226 [μm] or 250 [μm] to 280 [μm], so that even if manufacturing variations occur, the diameter does not exceed 226 [μm] or 280 [μm].

[0223] Furthermore, it is also possible that, considering the possibility of the semiconductor chip 2 bending along the first direction toward the center away from the mounting substrate 500, in each of the multiple first column-shaped configuration areas 71, among the source pads configured in the first column-shaped configuration area 71, the diameter of the source pad farthest from the boundary line 90 in the first area A1 and the diameter of the source pad farthest from the boundary line 90 in the second area A2 are not less than 250 [μm] and not more than 280 [μm], and the diameter of the source pad closest to the boundary line 90 in the first area A1 and the diameter of the source pad closest to the boundary line 90 in the second area A2 are not less than 196 [μm] and not more than 226 [μm].

[0224] Fig.12 is a plan view showing another example of the structure of the semiconductor device 1. However, Fig.12 This is a diagram in which the illustration of a plurality of ball-shaped bump electrodes 3 is omitted. Fig.12 It is also a plan view of the semiconductor chip 2 .

[0225] like Fig.12 As shown, in a plan view of the semiconductor device 1 , the first gate pad 119 and the second gate pad 129 may not be arranged in the second row arrangement region 72 .

[0226] Furthermore, in the plan view of semiconductor device 1 , as long as the closest distance between the source pads is greater than or equal to rs / 2, the closest distance between first row arrangement regions 71 may be less than rs / 2.

[0227] In addition, in the plan view of the semiconductor device 1, the source pads in one of the first row-shaped arrangement regions 71 adjacent to each other among the plurality of first row-shaped arrangement regions 71 are respectively directed in the second direction ( Fig.12 The position in the Y-axis direction) may also be inconsistent with the position in the second direction of any source pad in the first column-shaped configuration area 71 on the other side of the mutually adjacent first column-shaped configuration area 71.

[0228] In addition, in the plan view of the semiconductor device 1, there may be a source pad that is not arranged in the first row arrangement region 71. Fig.12As shown, in the plan view of the semiconductor device 1, for example, as in the case of the black-painted source pads, there may be two source pads less than four, each with its center in the first direction ( Fig.12 Source pads arranged in a straight line in the X-axis direction (in the X-axis direction).

[0229] Fig.13 is a plan view showing another example of the structure of the semiconductor device 1. However, Fig.13 This is a diagram in which the illustration of a plurality of ball-shaped bump electrodes 3 is omitted. Fig.13 It is also a plan view of the semiconductor chip 2 .

[0230] like Fig.13 As shown, in the planar observation of the semiconductor device 1, as long as the closest distance between the source pads is greater than rs / 2, the first column-shaped configuration areas 71 on one side of the plurality of first column-shaped configuration areas 71 adjacent to each other may overlap with the first column-shaped configuration areas 71 on the other side.

[0231] Furthermore, in the plan view of the semiconductor device 1, the closest distances between adjacent source pads in the same second row arrangement region 72 may be different. Fig.13 As shown, in a plan view of semiconductor device 1 , for example, the closest distance between the black-painted source pads may be longer than the closest distance between other mutually adjacent source pads in second column arrangement region 72 including these black-painted source pads.

[0232] Fig.14 is a plan view showing another example of the structure of the semiconductor device 1. However, Fig.14 This is a diagram in which the illustration of a plurality of ball-shaped bump electrodes 3 is omitted. Fig.14 It is also a plan view of the semiconductor chip 2 .

[0233] like Fig.14 As shown, in the plan view of the semiconductor device 1 , the closest distance of the second row-shaped arrangement regions 72 can be equal to rs / 2.

[0234] (Replenish)

[0235] The semiconductor device of one technical solution of the present disclosure is described above based on the implementation method, but the present disclosure is not limited to the implementation method. As long as it does not deviate from the main purpose of the present disclosure, various modified forms that a person skilled in the art can think of by implementing the implementation method, or forms constructed by combining constituent elements of different modified examples can also be included in the scope of one or more technical solutions of the present disclosure.

[0236] Industrial Applicability

[0237] The present disclosure can be widely used in semiconductor devices and the like.

[0238] Description of Reference Numerals

[0239] 1 Semiconductor devices

[0240] 2 Semiconductor Chips

[0241] 3 Ball-shaped bump electrodes

[0242] 101st vertical MOS transistor

[0243] 11 1st source electrode

[0244] Parts 12, 13, 22, 23

[0245] 141st source region

[0246] 15 1st gate conductor

[0247] 16 1st gate insulating film

[0248] 181st body area

[0249] 19 1st gate electrode

[0250] 202nd vertical MOS transistor

[0251] 21 second source electrode

[0252] 24 Second source region

[0253] 25 2nd gate conductor

[0254] 26 second gate insulating film

[0255] 28 Second body area

[0256] 29 second gate electrode

[0257] 30 Metal Layer

[0258] 32 Semiconductor substrate

[0259] 33 Low concentration impurity layer

[0260] 34 Oxide film

[0261] 35 Protective film

[0262] 40 Semiconductor layer

[0263] 611st gate wiring

[0264] 62 2nd gate wiring

[0265] 71, 71A, 71B, 71C, 71D, 71E 1st row arrangement area

[0266] 72, 72A, 72B, 72C, 72D, 72E, 72F, 72G, 72H, second row configuration area

[0267] 90 Boundary Line

[0268] 111 1st source pad

[0269] 119 1st gate pad

[0270] 121 2nd source pad

[0271] 129 2nd gate pad

[0272] 500 mounting base plate

[0273] A1 Area 1

[0274] A2 Area 2

Claims

1. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, characterized in that: The semiconductor device comprises a rectangular semiconductor chip whose long sides extend in a first direction and whose short sides extend in a second direction in a plan view of the semiconductor device; The semiconductor chip has: a semiconductor layer having a semiconductor substrate; and a first vertical MOS transistor and a second vertical MOS transistor, wherein the first vertical MOS transistor is formed in the semiconductor layer in a first region, and the second vertical MOS transistor is formed in the semiconductor layer in a second region, wherein the first region and the second region are one side and the other side that divide the semiconductor chip into two equal parts in terms of area when viewed in the plane; The semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; The boundary line between the first region and the second region is a line segment extending in the second direction; The first vertical MOS transistor includes a first gate pad and a plurality of first source pads on the upper surface of the semiconductor chip in the first region; The second vertical MOS transistor includes a second gate pad and a plurality of second source pads on the upper surface of the semiconductor chip in the second region; In the above-mentioned planar observation, the above-mentioned first gate pad, the above-mentioned plurality of first source pads, the above-mentioned second gate pad, and the above-mentioned plurality of second source pads are circular with a diameter less than 378 μm; On the upper surface of the semiconductor chip, in the plane observation, a plurality of first columnar arrangement regions and a plurality of second columnar arrangement regions are arranged, in the plurality of first columnar arrangement regions, 4 or more and 2nx of the plurality of first source pads and the plurality of second source pads are arranged in a straight line with their respective centers in the first direction, and in the plurality of second columnar arrangement regions, 2 or more and ny of the plurality of first source pads or the plurality of second source pads are arranged in a straight line with their respective centers in the second direction; In the above-mentioned planar observation, the width of each of the plurality of first columnar arrangement regions is equal to the largest diameter among the diameters of the 4 or more and 2nx or less source pads arranged in the first columnar arrangement region, and the width of each of the plurality of second columnar arrangement regions is equal to the largest diameter among the diameters of the 2 or more and ny or less source pads arranged in the second columnar arrangement region; In the above-mentioned plane observation, let the length of the above-mentioned long side be Lx in μm, let the length of the above-mentioned short side be Ly in μm, let the largest diameter among the diameters of the above-mentioned plurality of first source pads and the above-mentioned plurality of second source pads be rs in μm, then nx is the largest integer greater than 2 for which the relationship nx<1 / 3×(Lx / rs-3) holds; ny is the largest integer greater than 2 for which the relationship ny<2 / 3×(Ly / rs-1) holds; In the above-mentioned planar observation, the closest distance between the plurality of first source pads and the plurality of second source pads, and the closest distance between the plurality of second columnar arrangement regions are greater than rs / 2 and are expressed in μm, and the diameter of the first gate pad and the diameter of the second gate pad are rs and are expressed in μm; In the above-mentioned planar observation, the above-mentioned first gate pad is arranged farther from the above-mentioned boundary line than the second row-shaped arrangement area|region which is closest to the above-mentioned boundary line in the above-mentioned first area among the above-mentioned plurality of second row-shaped arrangement areas; In the above-mentioned planar observation, the above-mentioned second gate pad is arranged farther from the above-mentioned boundary line than the second row-shaped arrangement area|region which is closest to the above-mentioned boundary line in the above-mentioned second area|region among the above-mentioned plurality of second row-shaped arrangement areas; The semiconductor device further includes a plurality of ball-shaped bump electrodes that are connected in a one-to-one contact manner directly above the first gate pad, the plurality of first source pads, the second gate pad, and the plurality of second source pads.

2. The semiconductor device according to claim 1, wherein In the planar observation, the closest distance between the plurality of first row-shaped arrangement regions is greater than or equal to rs / 2, and the unit is μm.

3. The semiconductor device according to claim 1 or 2, wherein: In the above-mentioned planar observation, the diameters of the plurality of first source pads and the plurality of second source pads are rs, and the unit is μm.

4. The semiconductor device according to claim 1, wherein: In the above-mentioned planar observation, in each of the above-mentioned multiple first-column configuration areas, the diameter of the above-mentioned 4 or more and 2nx or less source pads configured in the first-column configuration area decreases monotonically in the direction from the source pad farthest from the above-mentioned boundary line toward the source pad closest to the above-mentioned first area, and decreases monotonically in the direction from the source pad farthest from the above-mentioned boundary line toward the source pad closest to the above-mentioned second area.

5. The semiconductor device according to claim 4, wherein: In the above-mentioned planar observation, in each of the above-mentioned multiple first-column configuration areas, the closest distance of the above-mentioned 4 or more and 2nx or less source pads configured in the first-column configuration area increases monotonically in the direction from the source pad farthest from the above-mentioned boundary line toward the closest source pad in the above-mentioned first area, and increases monotonically in the direction from the source pad farthest from the above-mentioned boundary line toward the closest source pad in the above-mentioned second area.

6. The semiconductor device according to claim 1, wherein: In the above-mentioned planar observation, in each of the second column-shaped configuration areas among the above-mentioned multiple second column-shaped configuration areas that are most closely opposite to each other with the above-mentioned boundary line sandwiched therebetween, the diameter of the above-mentioned more than 2 and less than ny source pads is equal to the smallest diameter among the diameters of the above-mentioned multiple first source pads and the above-mentioned multiple second source pads.

7. The semiconductor device according to claim 1, wherein In the above-mentioned planar observation, in each of the above-mentioned multiple first-column configuration areas, the height of the spherical bump electrode among the above-mentioned multiple spherical bump electrodes located directly above each of the above-mentioned 4 or more and 2nx or less source pads configured in the first-column configuration area from the upper surface of the above-mentioned semiconductor chip monotonically increases in the direction from the spherical bump electrode farthest from the above-mentioned boundary line toward the spherical bump electrode closest to the above-mentioned first area, and monotonically increases in the direction from the spherical bump electrode farthest from the above-mentioned boundary line toward the spherical bump electrode closest to the above-mentioned second area.

8. The semiconductor device according to claim 1, wherein In the above-mentioned planar observation, in each of the above-mentioned multiple first-column configuration areas, the surface area of ​​the spherical bump electrode among the above-mentioned multiple spherical bump electrodes located directly above each of the above-mentioned 4 or more and 2nx or less source pads configured in the first-column configuration area monotonically increases in the direction from the spherical bump electrode farthest from the above-mentioned boundary line toward the spherical bump electrode closest to the above-mentioned first area, and monotonically increases in the direction from the spherical bump electrode farthest from the above-mentioned boundary line toward the spherical bump electrode closest to the above-mentioned second area.

9. The semiconductor device according to claim 3, wherein: In the planar view, in each of the second row-shaped arrangement regions that are most closely opposed to each other with the boundary line interposed therebetween among the plurality of second row-shaped arrangement regions, the number of the two or more and the ny or less source pads is ny.

10. The semiconductor device according to claim 9, wherein: In the above plane observation, The distance between the first gate pad and the first source pad closest to the first gate pad among the plurality of first source pads is greater than rs and is greater than the closest distance among the plurality of first source pads. The distance between the second gate pad and a second source pad closest to the second gate pad among the plurality of second source pads is greater than rs and is greater than the closest distance among the plurality of second source pads.

11. The semiconductor device according to claim 10, wherein: In the above plane observation, The longest distance among the distances between mutually adjacent source pads among the above-mentioned more than 2 and less than ny source pads in each of the above-mentioned multiple second column-shaped arrangement areas, i.e., the adjacent longest distance, in the above-mentioned first area, decreases monotonically in the direction from the second column-shaped arrangement area farthest from the above-mentioned boundary line toward the second column-shaped arrangement area closest to the above-mentioned multiple second column-shaped arrangement areas, and in the above-mentioned second area, decreases monotonically in the direction from the second column-shaped arrangement area farthest from the above-mentioned boundary line toward the second column-shaped arrangement area closest to the above-mentioned multiple second column-shaped arrangement areas; The number of the above-mentioned more than 4 and less than 2nx source pads in each of the above-mentioned multiple first-column-shaped configuration areas, with respect to (1) more than two first-column-shaped configuration areas whose distance to the long side of one of the above-mentioned long sides is shorter than the distance to the long side of the other side among the above-mentioned multiple first-column-shaped configuration areas, decreases monotonically in the direction from the first-column-shaped configuration area closest to the above-mentioned one long side toward the first-column-shaped configuration area farthest away, and with respect to (2) more than two first-column-shaped configuration areas whose distance to the long side of the above-mentioned other side is shorter than the distance to the long side of the above-mentioned one side, decreases monotonically in the direction from the first-column-shaped configuration area closest to the above-mentioned other long side toward the first-column-shaped configuration area farthest away.

12. The semiconductor device according to claim 1, wherein In the above plane observation, The positions in the second direction of each of the above-mentioned 4 or more and 2nx or less source pads in the 1st column-shaped configuration area on one side of the above-mentioned multiple 1st column-shaped configuration areas adjacent to each other are inconsistent with the positions in the second direction of any of the above-mentioned 4 or more and 2nx or less source pads in the 1st column-shaped configuration area on the other side of the above-mentioned multiple 1st column-shaped configuration areas adjacent to each other.

13. The semiconductor device according to claim 3, wherein: rs is 196 to 226, or 250 to 280.

14. The semiconductor device according to claim 4, wherein: In the above-mentioned planar observation, in each of the above-mentioned multiple first-column configuration areas, among the above-mentioned 4 or more and 2nx or less source pads configured in the first-column configuration area, the diameter of the source pad farthest from the above-mentioned boundary line in the above-mentioned first area and the diameter of the source pad farthest from the above-mentioned boundary line in the above-mentioned second area are not less than 250 μm and not more than 280 μm, and the diameter of the source pad closest to the above-mentioned boundary line in the above-mentioned first area and the diameter of the source pad closest to the above-mentioned boundary line in the above-mentioned second area are not less than 196 μm and not more than 226 μm.

15. The semiconductor device according to claim 1, wherein rs is greater than 150; The height of the plurality of ball-shaped bump electrodes from the upper surface of the semiconductor chip is not less than 70 μm and not more than 130 μm; The cross-sectional areas of the plurality of ball-shaped bump electrodes, which are located on a plane parallel to the upper surface of the semiconductor chip, decrease monotonically as they move from closer to the upper surface of the semiconductor chip to farther away.

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