Test element for bonded structures

Abstract

The invention discloses a bonding structure for testing a semiconductor device and a method for testing the semiconductor device. The bonding structure may include a test element and one or more semiconductor elements. The test element may include test circuitry. The test element may be bonded to the semiconductor device or embedded within the semiconductor device. The test element may be configured to test the semiconductor device. The test element may be configured to test a first semiconductor device to which it is bonded and other semiconductor devices bonded to the first semiconductor device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 344,772, filed on May 23, 2022, entitled “TESTING ELEMENTS FOR BONDED STRUCTURES,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The field relates to self-test devices for bonding structures, and more particularly to self-test elements including self-test circuitry. Background Art

[0004] The complexity of semiconductor devices, particularly system-on-chip (SoC) devices, has increased while the size and dimensions have decreased. As SoC devices and semiconductor devices become more complex, the importance of testing the functionality of these devices has increased. However, it can be challenging to provide test circuitry that adequately tests the important active circuits of a chip without causing an increase in the footprint of the chip. Therefore, a need for improved self-testing devices and processes remains. Summary of the invention

[0005] In one aspect, a bonding structure is described. The bonding structure may include: a first semiconductor element including a first active circuit device; and a test element including a test circuit device, the test element being directly bonded to the first semiconductor element along a bonding interface without an adhesive; wherein the test circuit device is configured to test functionality of at least a portion of the first active circuit device of the first semiconductor element.

[0006] In some embodiments, the test element further comprises a memory configured to store the results of the test. In some embodiments, the test element is smaller than the first semiconductor element. In some embodiments, the first non-conductive bonding layer of the first semiconductor element is directly bonded to the second non-conductive bonding layer of the test element without the intervening adhesive; and wherein the first contact feature of the first semiconductor element is directly bonded to the second contact feature of the test element without the intervening adhesive. In some embodiments, the test element further comprises a plurality of signal contact pads. In some embodiments, a majority of the plurality of signal contact pads are configured to test at least a portion of a first active circuit device of the first semiconductor element.

[0007] In another aspect, a bonded structure is described. The bonded structure may include: a first semiconductor element including a test circuit device; a second semiconductor element directly bonded to the first semiconductor element along a bonding interface without an adhesive, the second semiconductor element including a first active circuit device; and wherein the test circuit device is configured to test functionality of at least part of the first active circuit device of the second semiconductor element.

[0008] In some embodiments, the test circuit device is further configured to store the result of at least a portion of the functionality of the first active circuit device. In some embodiments, the first non-conductive bonding layer of the first semiconductor element is directly bonded to the second non-conductive layer of the second semiconductor element without the intervening adhesive; and wherein the first contact feature of the first semiconductor element is directly bonded to the second contact feature of the second semiconductor element without the intervening adhesive. In some embodiments, the bonded structure further includes a third semiconductor element, the third semiconductor element includes a second active circuit device, the third semiconductor element is directly bonded to the second semiconductor element, and the test circuit device is configured to test at least a portion of the functionality of the second active circuit device. In some embodiments, the bonded structure further includes a fourth semiconductor element, the fourth semiconductor element includes a third active circuit device, the fourth semiconductor element is directly bonded to the third semiconductor element.

[0009] In some embodiments, the first semiconductor element further includes a fourth active circuit device. In some embodiments, the test circuit device of the first semiconductor element is configured to test at least part of the functionality of the first active circuit device, the second active circuit device, the third active circuit device, and / or the fourth active circuit device. In some embodiments, the combined structure further includes a third semiconductor element, the third semiconductor element including the second active circuit device, the third semiconductor element being directly bonded to the first semiconductor element; and wherein the test circuit device is configured to test at least part of the functionality of the second active circuit device. In some embodiments, the first semiconductor element includes a test chip. In some embodiments, the test chip is configured to test only the active circuit devices of one or more other semiconductor elements, and no other active circuit devices. In some embodiments, the combined structure further includes a third semiconductor element, the third semiconductor element including the second active circuit device and a second bonding layer, the second bonding layer being bonded to the second semiconductor element without an adhesive; and wherein the test circuit device is configured to test at least part of the functionality of the third active circuit device.

[0010] In some embodiments, the bonded structure further comprises a fourth semiconductor element comprising a third active circuit device and a third bonding layer, the third bonding layer being bonded to the second semiconductor element without an adhesive; and wherein the test circuit device is configured to test functionality of at least a portion of the third active circuit device. In some embodiments, the test circuit device is configured to send one or more signals to the first active circuit device. In some embodiments, the one or more signals detect one or more portions of the first active circuit device. In some embodiments, the first active circuit device transmits a return signal, and the return signal is transmitted from the first active circuit device to the test circuit device; and the test circuit device is configured to analyze the return signal and send an indication signal to the first device.

[0011] In another aspect, a bonded structure is described. The bonded structure may include: a wafer (which may be referred to as a base wafer) including a first active circuit device and a self-test core; and a first semiconductor element including a second active circuit device, the semiconductor element being directly bonded to the base wafer without an adhesive, wherein the self-test core includes a test circuit device configured to test at least a portion of the functionality of at least one of the first active circuit device and the second active circuit device.

[0012] In some embodiments, the first non-conductive bonding layer of the base wafer is directly bonded to the second non-conductive layer of the first semiconductor element without an intervening adhesive; and wherein the first contact feature of the base wafer is directly bonded to the second contact feature of the first semiconductor element without an intervening adhesive. In some embodiments, the bonded structure further comprises a third semiconductor element comprising a third active circuit device, a third non-conductive bonding layer, and a third contact feature in communication with the third active circuit device; wherein the third non-conductive bonding layer is directly bonded to the first non-conductive bonding layer of the base wafer without an intervening adhesive; and the third contact feature is directly bonded to the first contact feature of the base wafer without an adhesive. In some embodiments, the first semiconductor element comprises a fourth non-conductive bonding layer and a fourth contact feature in communication with the second active circuit device.

[0013] In some embodiments, the bonding structure also includes a second semiconductor element, which includes a third active circuit device, a third non-conductive bonding layer, and a third contact feature that communicates with the third active circuit device; and wherein the third non-conductive bonding layer of the second semiconductor element and the fourth non-conductive bonding layer of the first semiconductor element are directly bonded without the intervention of an adhesive; and the third contact feature of the second semiconductor element is directly bonded to the fourth contact feature of the first semiconductor element without the intervention of an adhesive.

[0014] In some embodiments, the second semiconductor element further comprises a fifth non-conductive bonding layer and a fifth contact feature in communication with the third active circuit device. In some embodiments, the bonded structure further comprises a third semiconductor element comprising a fourth active circuit device, a sixth non-conductive bonding layer, and a sixth contact feature in communication with the third active circuit device; wherein the sixth non-conductive bonding layer of the third semiconductor element and the fifth non-conductive bonding layer of the second semiconductor element are directly bonded without intervening adhesive; and the sixth contact feature of the third semiconductor element is directly bonded to the fifth contact feature of the second semiconductor element without intervening adhesive. In some embodiments, the test circuit device is configured to test at least a portion of the functionality of at least one of the first active circuit device, the second active circuit device, the third active circuit device, and the fourth active circuit device.

[0015] In another aspect, a method for forming a bonded structure is described, the method comprising: providing a first semiconductor element comprising a test circuit device; bonding the first semiconductor element to a second semiconductor element without an adhesive; wherein the second semiconductor element comprises a first active circuit device, and the test circuit device is configured to test functionality of the first active circuit device.

[0016] In some embodiments, the method further comprises: bonding a third semiconductor element comprising a second active circuit device to the first semiconductor element without an adhesive. In some embodiments, the method further comprises: bonding a third semiconductor element comprising a second active circuit device to the second semiconductor element. In some embodiments, the method further comprises: bonding a fourth semiconductor element comprising a third active circuit device to the second semiconductor element. In some embodiments, the first semiconductor element comprises a test chip.

[0017] In some embodiments, the method further comprises: bonding at least one semiconductor component including active circuitry to a second semiconductor component; and wherein the test circuitry is configured to test at least a portion of functionality of the at least one semiconductor component.

[0018] In another embodiment, a bonding structure may include: a first semiconductor element including a first active circuit device; a first non-conductive bonding layer of the first semiconductor element, at least partially defining a direct bonding surface of the bonding structure; and one or more traces connected to the first active circuit device and extending at least partially into the first non-conductive bonding layer, wherein the one or more traces are configured to provide electrical communication between the first active circuit device and a test element, and the one or more traces terminate at or below the direct bonding surface.

[0019] In some embodiments, the bonding structure may include a first contact feature at least partially embedded within the first non-conductive bonding layer and connected to one or more traces, the first contact feature being configured to directly bond to a corresponding second contact feature of the test element. In some embodiments, the bonding structure may include a plurality of contact features at least partially embedded in the first non-conductive bonding layer, wherein the first non-conductive layer and the plurality of contact features cooperate to at least partially define a bonding surface for direct hybrid bonding. In some embodiments, one or more traces terminate at or below the bonding surface of the bonding structure, and the one or more traces are not connected to contact pads at the bonding surface of the bonding structure.

[0020] For the purpose of summarizing the present disclosure and its advantages over the prior art, certain objects and advantages of the present disclosure are described herein. Not all such objects or advantages may be achieved in any particular embodiment. Thus, for example, those skilled in the art will recognize that the present invention may be implemented or performed in a manner that achieves or optimizes one advantage or a group of advantages taught herein without necessarily achieving other objects or advantages taught or suggested herein.

[0021] All these embodiments are intended to be within the scope of the invention disclosed herein. These and other embodiments will become apparent to those skilled in the art by the following detailed description of the preferred embodiments with reference to the attached drawings, and the present invention is not limited to any particular preferred embodiment(s) disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A is a schematic side cross-sectional view of a self-test chip directly bonded to a semiconductor element according to one embodiment.

[0023] Figure 1B is a schematic side cross-sectional view of a self-test chip directly bonded to a semiconductor device according to another embodiment.

[0024] Figure 1C is a schematic top view showing a self-test chip bonded to a semiconductor element.

[0025] Figure 2A is a schematic top view showing a self-test chip bonded to a semiconductor element in a wafer form.

[0026] Figure 2B is a schematic top view showing a semiconductor element having a conventional built-in self-test circuit integrated with a chip in the form of a wafer.

[0027] Figure 3A is a schematic side cross-sectional view of a self-test core embedded in a chip bonded to a semiconductor element.

[0028] Figure 3B is a schematic side cross-sectional view of a self-test core embedded in a chip bonded to a plurality of semiconductor elements laterally spaced apart from one another on the chip.

[0029] Figure 3C is a schematic side cross-sectional view of a test core embedded in a chip bonded to a plurality of stacked semiconductor elements.

[0030] Figure 4 is a schematic illustration of a direct bond test core configuration compared to a built-in self-test configuration formed in a semiconductor device die according to various embodiments.

[0031] FIG. 5A to FIG. 5B A process for forming a direct hybrid bonded structure without an intervening adhesive is schematically illustrated according to some embodiments. DETAILED DESCRIPTION

[0032] Overview

[0033] The present disclosure may be understood by referring to the following detailed description. It should be noted that, for the purpose of clarity of illustration, some elements in the various drawings may not be drawn to scale, may be represented schematically or conceptually, or may not completely correspond to some physical configurations of the embodiments.

[0034] Embodiments relate to test elements for semiconductor devices, such as systems on chip (SoC). The test element or self-test core (ST core) disclosed herein can reduce the area of ​​the semiconductor device used to perform the self-test function. This may be attributed to the self-test core being bonded to a suitable bonding surface of the semiconductor device, rather than being patterned on the area to be tested of the chip. As explained herein, the ST core can be provided in a separate chip or chiplet that is directly bonded to a base element, which can include a chip (or wafer) to be tested or a host device bonded to a (multiple) chip to be tested.

[0035] Conventionally, self-test devices (e.g., self-test circuits) are widely used to evaluate and self-test semiconductor devices using as few probe contacts as possible. As semiconductor devices (e.g., chips or integrated circuit devices) become more and more complex, self-test architectures become increasingly important because they allow higher yields to be achieved in more complex devices. In particular, SoC devices that are difficult to test with external measurement devices benefit from built-in self-test structures and circuits.

[0036] One method for performing functional testing is the built-in self-test method (BIST). Conventional BIST methods dedicate portions of the chip area to self-test circuitry. More complex semiconductor devices also utilize more complex self-test circuitry. However, complex self-test circuitry takes up more space on the chip, limiting the ability to miniaturize complex semiconductor devices.

[0037] In some devices, self-test circuits are added within the saw lanes. However, self-test circuits have become larger and more complex, which has hindered efforts to miniaturize devices. Therefore, there is a need for self-test circuits with high functionality (e.g., self-test circuit devices that test most of the functionality of a semiconductor device) without occupying a large area of ​​the semiconductor device (e.g., within the die).

[0038] Various embodiments disclosed herein can utilize a self-test core including a test circuit device. In some embodiments, the self-test core can include a chip and can be bonded to the surface of a semiconductor element. The self-test core can be configured to test some or all functionality of a semiconductor device. In some embodiments, the self-test core can be bonded to a first semiconductor element, which is bonded to other semiconductor elements. In some embodiments, the self-test core can be configured to test some or all functionality of other bonded semiconductor elements.

[0039] In some embodiments, the self-test core can be embedded in the basic element. In some embodiments, the embedded self-test core can be configured to test some or all functionality of the basic element. In some embodiments, the basic element can be combined with other semiconductor devices. In some embodiments, the self-test core can be configured to test some or all functionality of some or all semiconductor elements combined to the basic element. In some embodiments, the basic element is a chip, a wafer or an interposer.

[0040] Another advantage of using a self-test core or self-test chip according to the disclosed embodiments is the availability of using a low-cost process node to pattern the test circuit device (e.g., a 40-nm process node), while a higher resolution process node (e.g., a 2nm process node) can be used to pattern the active circuit device of the semiconductor element. This change in patterning can result in a reduction in the cost associated with the test circuit device, so that the test element (e.g., a test chiplet) can be patterned with a lower cost technology, and the semiconductor tube core with a more advanced active circuit device can be patterned with a higher resolution and more expensive technology. Using direct bonding to bond the test element to the semiconductor tube core allows decoupling of the test element (e.g., a test chiplet) and the semiconductor element (e.g., an active tube core), so that the element can be manufactured using different processing nodes and technologies. Using direct bonding can also achieve this cost-effective node strategy, for example by enabling fine pitch contacts, which provide a large number of input / output ("I / O") pins for the test chip circuit device. Fine pitch contacts can allow high-density testing that can be achieved through direct bonding.

[0041] The test element or self-test core (eg, chip or chiplet) may be directly bonded (eg, using a hybrid direct bonding technique such as that used by Adeia of San Jose, California). The self-test core is a semiconductor component (such as a semiconductor chip) that can benefit from self-testing. After the self-test core is bonded to the component (such as a semiconductor chip or an integrated device die), the self-test core can test some or all functionality of the component.

[0042] Example embodiment of a test element for a bonding structure

[0043] Figure 1A 1 is a schematic side cross-sectional view of a test chip 102 (e.g., a test core or a self-test core) bonded to a semiconductor element 104. In some embodiments, the test chip 102 may include a core substrate 106, a test circuit device 108 patterned in a portion of the substrate 106, and a chip bonding layer (e.g., a bonding layer 110). The test chip 102 may test active circuit devices of one or more other semiconductor elements and may not itself have any other active circuit devices. In various embodiments, at least 80% or at least 90% of all circuit devices in the test chip 102 include the test circuit device 108. In some embodiments, all circuit devices provided in the test chip 102 include the test circuit device 108. The test circuit device 108 may include one or both of a logic circuit device and / or a memory circuit device.

[0044] The bonding layer 110 may include a dielectric layer 111 and a plurality of conductive contacts 113 at least partially embedded in the dielectric layer 111. Figure 1A The chip bonding layer 110 is schematically illustrated as a single layer, but it should be understood that the layer 110 may include multiple layers or sub-layers. In various embodiments, the bonding layer 110 may include one or more back-end-of-line (BEOL) layers provided on the core substrate 106. In some embodiments, the semiconductor element 104 may include a device and / or substrate bonding surface (e.g., a bonding layer that may be a dielectric layer 114), the device including an active circuit device 109 patterned in a portion of the substrate 112 (in Figure 1A 104) may be patterned)), the substrate bonding surface having a plurality of conductive contacts 115 at least partially embedded in a dielectric layer 114. In some embodiments, the substrate 112 of the semiconductor device 104 may include a system-on-chip (SoC) device. In some embodiments, the semiconductor element 104 may include a central processing unit, a memory device, a microcontroller, a microprocessor, an application-specific integrated circuit, a graphics processing unit, or any combination thereof. The substrate 112 of the semiconductor device 104 may include a semiconductor device portion that includes a semiconductor material such as silicon. For example, the substrate 112 may include single crystal silicon or polycrystalline silicon. In some embodiments, the semiconductor element 104 may include a through-hole 138. The through-hole 138 may include a metal structure that extends at least partially through and / or completely through the semiconductor element 104. In some embodiments, the through-hole 138 may include a conductive material such as copper or any other suitable conductive material. In some embodiments, the active circuit device 109 may be connected to the surface of the substrate 112 via an input or output structure. In some embodiments, the input and / or output structure may be, for example, a through-hole 138. The input and / or output structure may be in electrical communication with the active circuit device 109. In some embodiments, the semiconductor element 104 may include a routing circuit device that communicates with and / or is connected to the active circuit device 109. In some embodiments, the input and / or output structure may include a routing circuit device. In some embodiments, the electrical contact 115 may be electrically connected to and / or communicate with one and / or both of the active circuit device 109 and / or the routing circuit device.

[0045] although Figure 1AThe substrate bonding layer 114 is schematically illustrated as a single layer, but it should be understood that the layer 114 may include multiple layers or sub-layers (including, for example, the above-mentioned (multiple) BEOL layers). In some embodiments, the test chip 102 can be directly hybrid bonded to the semiconductor element 104. In some embodiments, the chip bonding layer 110 is directly bonded to the substrate bonding surface 114. In the hybrid bonding configuration, the non-conductive dielectric layers 114 and 110 can be directly bonded without an adhesive, and the opposing contacts 113 and 115 can also be directly bonded without an adhesive. In some embodiments, the dielectric layers 111 and 114 may include an inorganic dielectric material compatible with integrated circuit manufacturing. For example, the dielectric layers 111 and 114 may be a dielectric material (such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon and / or any other suitable dielectric material). In some embodiments, the conductive contacts 113 and 115 may include any suitable metal (such as copper).

[0046] In some embodiments, the test chip 102 can test some and / or all functionality of the active circuit devices 109 of the semiconductor element 104. In some embodiments, the active circuit devices 109 can include one and / or both of logic circuit devices and / or memory circuit devices. For example, in operation, the test circuit device 108 can send one or more signals to the active circuit device 109 (e.g., one or more transistors) through the conductive contact pads 113 and 115 of the direct bonding of the test chip 102 and the semiconductor element 104. Additionally or alternatively, in order to test the semiconductor element 104, the test chip 102 can communicate with the active circuit device 109 in the semiconductor element 104 through the lateral traces and / or vertical interconnects in the chip. The lateral traces can route one or more signals laterally through the lateral traces from the active circuit device 109 to the contact pads 113 and 115. In some embodiments, the non-conductive layer can be one or more back-end processing (BEOL) layers. In some embodiments, the non-conductive layer or dielectric layer 114 can be formed on the traces. The transmitted (multiple) signals may detect portions of the active circuit device (e.g., one or more transistors to be detected or tested), and the active circuit device under test may emit a return signal, which is transmitted from the semiconductor element 104 to the test circuit device 108 of the test chip 102 through the contact pads 113 and 115 of the bonding layer. The return signal may be processed by the test circuit device, which may be programmed to determine whether the tested active circuit device of the semiconductor element 104 is functional and / or non-functional. The return signal may also be saved by the internal memory of the test chip 102. The test chip 102 may send an indication signal to the semiconductor element 104 and / or an external device (e.g., a package or a system board), which indicates the status of the active circuit device under test (e.g., whether the tested (multiple) circuits are functional and / or non-functional). The test chip 102 may store the return signal, which may be retrieved by a test engineer or an external test system.

[0047] In some embodiments, the functionality of the semiconductor element 104 may indicate the suitability of the semiconductor element 104 for a given purpose and / or the quality of the semiconductor element 104. In some embodiments, the quality of the semiconductor element 104 corresponds to whether the semiconductor element 104 operates according to design. In some embodiments, after testing the active circuit device 109, the test chip 102 may remain bonded to the semiconductor element 104 and placed into the electronic device. In other embodiments, the test chip 102 may be peeled from the semiconductor element 104 before the semiconductor element 104 is packaged and / or placed into the electronic device. For example, the test chip 102 may be polished off the semiconductor element 104 or otherwise removed from the semiconductor element 104. In embodiments where the test chip 102 is removed from the semiconductor element 104, one or more traces connected to the active circuit device 109 may extend from the active circuit device 109 at least partially into the non-conductive layer 114. The one or more traces may terminate at a location at or below the bonding surface of the element 104. In some embodiments, traces may extend from active circuit device 109 to one or more test contact features or pads (e.g., pads 115) bonded to test chip 102 prior to stripping. After stripping, one or more test contact features or pads may be exposed at the hybrid bonding surface and may not be directly bonded to another component. Other pads 115 of component 104 may be directly bonded to corresponding pads of other components (such as other active dies).

[0048] Figure 1B is a schematic side cross-sectional view of a test chip 102 (eg, a test core or a self-test core) bonded to a semiconductor element 104. In some embodiments, the test chip 102 may include a test circuitry 108 patterned in a portion of a substrate 106 and a chip bonding layer (eg, bonding layer 110).

[0049] The bonding layer 110 may include a dielectric layer 111 and a plurality of conductive contacts 113 at least partially embedded in the dielectric layer 111. Figure 1B The chip bonding layer 110 is schematically illustrated as a single layer, but it should be understood that the layer 110 may include multiple layers or sub-layers. In some embodiments, the semiconductor element 104 may include a device including an active circuit device 109 (e.g., a circuit device including at least one integrated circuit having at least one transistor) patterned in a portion of the substrate 112, and a substrate bonding surface (e.g., a bonding layer that may be a dielectric layer 114), the substrate bonding surface having a plurality of conductive contacts 115 at least partially embedded in the dielectric layer 114. Although Figure 1BThe substrate bonding layer 114 is schematically illustrated as a single layer, but it should be understood that the layer 114 may include multiple layers or sub-layers. In some embodiments, the semiconductor element 104 may include a central processing unit, a memory device, a microcontroller, a microprocessor, an application specific integrated circuit, a graphics processing unit, or any combination thereof. The substrate 112 of the semiconductor device 104 may include silicon. For example, the substrate 112 may include single crystal silicon or polycrystalline silicon.

[0050] although Figure 1A The substrate bonding layer 114 is schematically illustrated as a single layer, but it should be understood that the layer 114 may include multiple layers or sub-layers. In some embodiments, the test chip 102 may be directly hybrid bonded to the semiconductor element 104. In some embodiments, the chip bonding layer 110 may be directly bonded to the substrate bonding surface 114. In the hybrid bonding configuration, the non-conductive dielectric layers 114 and 111 may be directly bonded without an adhesive, and the opposing contacts 113 and 115 may also be directly bonded without an adhesive. In some embodiments, the dielectric layers 111 and 114 may include an inorganic dielectric material compatible with integrated circuit manufacturing. For example, the dielectric layers 111 and 114 may be a dielectric material (such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon and / or any other suitable dielectric material). In some embodiments, the conductive contacts 113 and 115 may include any suitable metal (such as copper).

[0051] In some embodiments, the second semiconductor element 116 can be bonded to the substrate bonding surface 114 at a first location via a second device bonding layer 118. The second semiconductor element 116 can include a second semiconductor device 120 and a second element bonding surface (e.g., a bonding layer that can be a dielectric layer 118), the second semiconductor device 120 including an active circuit device 123 (e.g., a circuit device including at least one integrated circuit having one or more transistors and / or SoC) patterned in and / or on a portion of the element 116, and the second element bonding surface having a plurality of conductive contacts 119 at least partially embedded in the dielectric layer 118. Although Figure 1B The second bonding layer 118 is schematically illustrated as a single layer, but it should be understood that the layer 118 may include multiple layers or sub-layers. In some embodiments, the second semiconductor element 116 may be directly hybrid bonded to the semiconductor element 104. In some embodiments, the second element bonding layer 118 may be directly bonded to the substrate bonding surface 114. In a hybrid bonding configuration, the non-conductive dielectric layers 114 and 118 may be directly bonded without an adhesive, and the opposing contacts 119 and 115 may be directly bonded without an adhesive.

[0052] In some embodiments, the third semiconductor element 122 may be bonded to the substrate bonding surface 114 at a second location via a third device bonding layer 124. The third semiconductor element 122 may include a third semiconductor device 126. The third semiconductor element 122 and the second semiconductor element 116 may be mounted to a common semiconductor element 104. As shown, the third semiconductor element 122 and the second semiconductor element 116 may be laterally spaced apart on the semiconductor 104. In some embodiments, the third semiconductor element 122 may include a device and a bonding surface (e.g., a bonding layer that may be a dielectric layer 124), the device including an active circuit device 125 (e.g., a circuit device including at least one integrated circuit having one or more transistors and / or SoC, which may include one or both of a logic circuit device and / or a memory circuit device) patterned in a portion of the element 122, the bonding surface having a plurality of conductive contacts 121 at least partially embedded in the dielectric layer 124. Although Figure 1B The third device bonding layer 124 is schematically illustrated as a single layer, but it should be understood that the layer 124 may include multiple layers or sub-layers. In some embodiments, the third semiconductor element 122 may be directly hybrid bonded to the semiconductor element 104. In some embodiments, the third element bonding layer 124 may be directly bonded to the substrate bonding surface 114. In a hybrid bonding configuration, the non-conductive dielectric layers 114 and 124 may be directly bonded without an adhesive, and the opposing contacts 121 and 115 may be directly bonded without an adhesive.

[0053] In some embodiments, semiconductor elements 104, 116, and / or 122 may include vias 138. Vias 138 may include metal structures that extend at least partially through and / or completely through the semiconductor device. In some embodiments, vias 138 may include conductive materials (such as copper or any other suitable conductive material). In some embodiments, semiconductor element 104 may include routing circuitry that communicates with and / or is connected to active circuitry 109. In some embodiments, input and / or output structures may include routing circuitry. In some embodiments, electrical contacts 115 may be electrically connected to and / or communicate with one and / or both of active circuitry 109 and / or routing circuitry.

[0054] In some embodiments, the test chip 102 may test at least part and / or all functionality of the semiconductor element 104, part and / or all functionality of the second semiconductor element 116, and / or part and / or all functionality of the third semiconductor element 122. In some embodiments, in order to test part and / or all functionality of the second semiconductor element 116 and / or the third semiconductor element 122, the test chip 102 need not be directly bonded to the second semiconductor element 116 and / or the third semiconductor element 122. In some embodiments, the functionality of the semiconductor elements 104, 116, and / or 122 may indicate the suitability of each semiconductor element for a given purpose and / or the quality of each semiconductor element. In some embodiments, the quality of the semiconductor elements 104, 116, and / or 122 may correspond to whether the semiconductor elements 104, 116, and / or 122 function according to design.

[0055] In some embodiments, other semiconductor elements may be bonded to semiconductor element 104. Test chip 102 may test some or all functionality of these additional bonded semiconductor elements in a manner similar to that described above. In some embodiments, test chip 102 may test some or all functionality of any number of semiconductor devices (e.g., 1, 2, 3, 4, 5, 6, 7, or more semiconductor devices). In some embodiments, test chip 102 may test multiple semiconductor devices sequentially and / or simultaneously.

[0056] In some embodiments, the test chip 102 may include a plurality of contact pads. In some embodiments, the contact pads may include signal pads (e.g., pads for sending signals), power pads (e.g., pads configured to connect to a power source and send power), and / or ground pads (e.g., pads designed to ground an electronic device). In some embodiments, the signal pads may conduct the test signal from the test chip 102 to a portion of the semiconductor element 104 and / or a portion or all of the functionality of the second semiconductor element 116 and / or a portion or all of the functionality of the third semiconductor element 122.

[0057] In some embodiments, the test chip 102 may include a plurality of signal pads. In some embodiments, the plurality of signal pads may be at the bonding interface 130. In some embodiments, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 99% of the signal pads, or any value therebetween, may test a portion of the semiconductor element 104 and / or a portion or all of the functionality of the second semiconductor element 116 and / or a portion or all of the functionality of the third semiconductor element 122. In some embodiments, 90% of the signal pads may test a portion or all of the functionality of the semiconductor element 112. In some embodiments, 50% of the signal pads may test a portion or all of the functionality of the semiconductor element 112.

[0058] Figure 1C yes Figure 1A to Figure 1B A schematic top view of a test chip 102 (e.g., a test core or self-test core) in wafer form bonded to a semiconductor element 104 is depicted. The test core 128a may include a test pad 132 and is positioned on a surface of the semiconductor element 104. The test core 128a and the test circuit device 108 may be in electrical communication with the test pad 132. The test pad 132 may be in electrical communication with the semiconductor element 104 and the integrated circuit device 109. The test pad 132 may be placed in a dicing street 136 and then may be removed by a dicing process.

[0059] The test core 128b may include a test pad 134, and it is positioned at the back side of the test core 128b. The test pad 134 may be in electrical communication with the test circuit device 108. The test pad 134 may be in electrical communication with the semiconductor element 104 and the integrated circuit device 109. The test pads 132 and 134 may allow the active circuit device 109 to be tested by an external probe. In some embodiments, the test pads 132 and 134 may send a signal from the test circuit device 108 to an external device (e.g., a package or a system board or an external operator), which indicates the state of the active circuit device being tested (e.g., whether the tested (multiple) circuits are functional and / or non-functional).

[0060] like Figure 2A and Figure 2B As shown, the use of the incorporated self-test chip 206 can improve device yield. Figure 2A A top view of an uncut wafer 200 with semiconductor devices 202 and bonded self-test cores or chips 206 is shown. Figure 2A In the embodiment, each semiconductor device 202 can be bonded to a bonded self-test core 206. By bonding a bonded self-test core 206 to each semiconductor device 208, the total number of semiconductor devices 202 that can be manufactured from the uncut wafer 200 is greater than if the test circuitry is patterned in a portion of the semiconductor device 202. In one example, such as Figure 2A As shown, the number of semiconductor devices 204 fabricated from the wafer 200 is forty-two (42).

[0061] Figure 2B The diagram illustrates a relatively small number of semiconductor devices that can be fabricated on a wafer 200 having built-in self-test circuitry according to conventional self-test methods. Figure 2B In the embodiment, the uncut wafer 200 and Figure 2A However, with Figure 2A Different, in Figure 2BIn the embodiment, the self-test circuit device 208 is built into each semiconductor device 204. The built-in test circuit device 208, which can expand the footprint of the semiconductor device 204, can result in a significant reduction in the number of semiconductor devices 204 that can be produced from the uncut wafer 200. Because the built-in self-test circuit device 208 is patterned into the semiconductor device 204, the footprint of the semiconductor device 204 (e.g., the overall size of the device) increases. Increasing the device size can reduce the number of semiconductor devices 204 that can be manufactured from the wafer 200. However, in Figure 2A 2, the self-test circuitry is externalized on the direct-bonded chip 206. Removing the test circuitry from the device footprint 202 may allow for a smaller device footprint, resulting in more devices per wafer 200. As mentioned above, the fine pitch context enabled by the direct hybrid bonding technique may allow for a large number of test I / O pads to test complex active circuits on the semiconductor device 204.

[0062] like Figure 2A As shown, the self-test chip may be suitable for testing uncut or cut wafers (e.g., device dies). In some embodiments, depending on cost, node, yield, and overall economics, the self-test chip may be suitable for a die-to-wafer format. In a die-to-wafer format, a plurality of cut self-test chips or dies may be bonded to a wafer containing a semiconductor device. In a wafer-to-wafer format, a wafer of test chips may be directly bonded to a wafer of a semiconductor device and then singulated together.

[0063] Figure 3A is a schematic side cross-sectional view of a self-test core 302 patterned in a base chip 304. In some embodiments, the self-test core 302 may include a test circuit device 303. In some embodiments, the self-test core 302 may be patterned in the base chip 304. The base chip 304 may include a substrate bonding surface (e.g., a bonding layer that may be a dielectric layer 306) and a device, the substrate bonding surface having a plurality of conductive contacts 307 at least partially embedded in the dielectric layer 306, the device including an active circuit device 305 (e.g., a circuit device including at least one integrated circuit) patterned in a portion of the base chip 304. The active circuit device 305 may include one or both of a memory circuit device and / or a logic circuit device. Although Figure 3AThe base chip bonding layer 306 is schematically illustrated as a single layer, but it should be understood that the layer 306 may include multiple layers or sub-layers. In some embodiments, the second semiconductor device 313 may include a second device front side bonding layer 308 and an active circuit device 310 (e.g., a circuit device including at least one integrated circuit) patterned in a portion of the second semiconductor device 313. The second device front side bonding layer 308 may be a dielectric layer 308 having a plurality of conductive contacts 311 at least partially embedded in the dielectric layer 308. The active circuit device 310 may include one or both of a logic circuit device and / or a memory circuit device. Although Figure 3A The second device front side bonding layer 308 is schematically illustrated as a single layer, but it should be understood that the layer 308 may include multiple layers or sub-layers. In some embodiments, the base chip bonding layer 306 may be directly bonded to the second device front side bonding layer 308. In a hybrid bonding configuration, the non-conductive dielectric layers 306 and 308 may be directly bonded without an adhesive, and the opposing contacts 311 and 307 may be directly bonded without an adhesive.

[0064] In some embodiments, the self-test core 302 can test some or all functionality of the active circuit devices 310 of the base chip 304 and / or the second semiconductor device. The test path 300 illustrates that the self-test core 302 can be in electrical communication with the base chip 304 and the second semiconductor element 313. For example, to test the base chip 304, the self-test core 302 can communicate with the active circuit devices 305 in the base chip 304 through lateral traces in the chip. Similarly, the test circuit device 303 can send one or more signals to the active circuit devices 310 (e.g., one or more transistors) of the second semiconductor element 313 through the directly bonded conductive contact pads 307 and 311 of the base chip 304 and the second semiconductor element 313. The transmitted signal(s) may detect portions of the active circuit device 310 of the second semiconductor element 313 (e.g., one or more transistors to be detected or tested), and the active circuit device 310 under test may emit a return signal that is transmitted from the second semiconductor element 313 to the test circuit device 303 of the self-test core 302 through the contact pads 307 and 311 of the bonding layers 306 and 308. The return signal may be processed by the test circuit device 303, which may be programmed to determine whether the active circuit device 310 under test of the second semiconductor element 313 is functional and / or non-functional. The return signal may also be saved by the internal memory of the self-test core 302. The self-test core 302 may send an indication signal to the base chip 304, the second semiconductor device 312, and / or an external device (e.g., a package or a system board), the indication signal indicating the state of the active circuit device under test (e.g., whether the circuit(s) under test are functional and / or non-functional). For example, a test engineer or test machine can access the return signal stored in the self-test core by probing the contacts of the self-test core 302. In some embodiments, the self-test core 302 can test some or all functionality of any number of semiconductor devices (e.g., 1, 2, 3, 4, 5, 6, 7 or more semiconductor devices). In some embodiments, the self-test core 302 can test multiple semiconductor devices sequentially and / or simultaneously.

[0065] Figure 3B 3 is a schematic side cross-sectional view of a self-test core 302 patterned in a base chip 304. In some embodiments, the self-test core 302 may include a test circuit device 303. Figure 3ASimilarly, the second semiconductor device 313 may have an active circuit device 310 that may be bonded to the base chip 304 in a first location. In some embodiments, the third semiconductor device 317 may include a third device front side bonding layer 314 and an active circuit device 316 (e.g., a circuit device including at least one integrated circuit) patterned in a portion of the third semiconductor device 317. The third device front side bonding layer 314 may be a dielectric layer having a plurality of conductive contacts 315 at least partially embedded therein. The third semiconductor device 317 may be bonded to a second location on the base chip 304. In some embodiments, the active circuit device 316 may include one or both of a logic circuit device and / or a memory circuit device. In some embodiments, the base chip bonding layer 306 is directly bonded to the third device front side bonding layer 314. In a hybrid bonding configuration, the non-conductive dielectric layers 306 and 314 may be directly bonded without an adhesive, and the opposing contacts 315 and 307 may also be directly bonded without an adhesive.

[0066] although Figure 3B The third device front side bonding layer 314 is schematically illustrated as a single layer, but it should be understood that the layer 314 may include multiple layers or sub-layers. In some embodiments, the self-test core 302 may be formed with Figure 3A A similar manner as described tests some or all functionality of the base chip 304, the second semiconductor device 313, and / or the third semiconductor device 317. The test path 300 illustrates that the self-test core 302 can be in electrical communication with the base chip 304, the second semiconductor device 313, and the third semiconductor device 317. Figure 3B It is illustrated that the base chip 304 can be bonded to two other semiconductor components 313 and 317, but it should be understood that the base chip 304 can also be bonded to more than two semiconductor components. Similarly, it should be understood that although only three test paths 300 are illustrated, the self-test core 302 can test some or all functionality of any semiconductor component bonded to the base wafer 304. As a non-limiting example, dozens or hundreds of semiconductor devices can be bonded to the base wafer 304 and tested by the self-test core 302 embedded in the base wafer 304.

[0067] Figure 3C304, which may be bonded to other semiconductor components. In some embodiments, the self-test core 302 may include a test circuit device 303. In some embodiments, the self-test core 302 may be patterned in the base chip 304. The base chip 304 may include a device including an active circuit device 305 (e.g., a circuit device including at least one integrated circuit patterned in a portion of the base chip 304) and a substrate bonding surface (e.g., a bonding layer that may be a dielectric layer 306), the substrate bonding surface having a plurality of conductive contacts 307 at least partially embedded in the dielectric layer 306. In some embodiments, the active circuit device 305 may be one or both of a logic circuit device and / or a memory circuit device. In some embodiments, the second semiconductor device 313 may include an active circuit device 310 (e.g., a circuit device including at least one integrated circuit (which may be one or both of a logic circuit device and / or a memory circuit device)) patterned in a portion of the second semiconductor device 313, a second device front side bonding layer 308 and a second device back side layer 312 (which may be dielectric layers 308 and 312), and a plurality of conductive contacts 311 at least partially embedded in the dielectric layers 308 and 312. In some embodiments, the second semiconductor device 310 may include one or more through-holes 324 that electrically connect the second device front side bonding layer 308 to the second device back side bonding layer 312. Although Figure 3C The second device backside bonding layer 312 and the second frontside device bonding layer 308 are schematically illustrated as single layers, but it should be understood that the layers 308 and 312 may include multiple layers or sub-layers. In some embodiments, the base chip bonding layer 306 may be directly bonded to the second device frontside bonding layer 308. In a hybrid bonding configuration, the non-conductive dielectric layers 306 and 308 may be directly bonded without an adhesive, and the opposing contacts 311 and 307 may also be directly bonded without an adhesive. Although FIG. 3A to FIG. 3C The base chip 304 is schematically illustrated, but it should be understood that the base chip 304 may be a chip, a wafer, an interposer, and / or a semiconductor element.

[0068] In some embodiments, the third semiconductor device 317 may include an active circuit device 316 (e.g., a circuit device including at least one integrated circuit) patterned in a portion of the third semiconductor device 317, a third device back side bonding layer 318, and a third device front side bonding layer 314 (which may be dielectric layers 314 and 318), and a plurality of conductive contacts 315 at least partially embedded in the dielectric layers 314 and 318 (which may be directly bonded to the second device back side bonding layer 312). In some embodiments, the active circuit device 316 may be one or both of a logic circuit device and / or a memory circuit device. In a hybrid bonding configuration, the non-conductive dielectric layers 312 and 314 may be directly bonded without an adhesive, and the opposing contacts 311 and 315 may be directly bonded without an adhesive. In some embodiments, one or more vias 324 may electrically connect the third device front side bonding layer 314 to the third device back side bonding layer 318. Although Figure 3C The third device backside bonding layer 318 and the third device frontside bonding layer 314 are schematically illustrated as single layers, but it is understood that the layers 314 and 318 may include multiple layers or sub-layers.

[0069] In some embodiments, the fourth semiconductor device 322 may include an active circuit device 321 (e.g., a circuit device including at least one integrated circuit) patterned in a portion of the fourth semiconductor device 322, a fourth device back side bonding layer 326 and a fourth device front side bonding layer 320 (which may be dielectric layers 320 and 326), and a plurality of conductive contacts 323 at least partially embedded in the dielectric layers 320 and 326 (which may be directly bonded to the third device back side bonding layer 318). In some embodiments, the active circuit device 321 may be one or both of a logic circuit device and / or a memory circuit device. In a hybrid bonding configuration, the non-conductive dielectric layers 320 and 318 may be directly bonded without an adhesive, and the opposing contacts 315 and 323 may be directly bonded without an adhesive. In some embodiments, one or more vias 324 may electrically connect the fourth device front side bonding layer 320 to the fourth device back side bonding layer 326. Although Figure 3C The fourth device backside bonding layer 326 and the fourth frontside device bonding layer 320 are schematically illustrated as single layers, but it should be understood that the layers 320 and 326 may include multiple layers or sub-layers. In some embodiments, the self-test core 302 may be formed with Figures 1A to 2B The described manner tests some and / or all functionality of the base chip 304, the second semiconductor device 310, the third semiconductor device 316, and / or the fourth semiconductor device 322. The test path 300 illustrates that the self-test core 302 can be in electrical communication with the base chip 304, the second semiconductor device 310, the third semiconductor device 316, and / or the fourth semiconductor device 322. Although Figure 3B The combined structure 328 of four components is shown: the base chip 304, the second semiconductor component 313, the third semiconductor component 316, and the fourth semiconductor component 322, but it should be understood that according to some embodiments, the combined structure 328 may include tens and / or hundreds of components. Figure 3C Only four test paths 300 are illustrated, but self-test core 302 can test some or all functionality of any semiconductor element in bonded structure 328. As a non-limiting example, dozens and / or hundreds of semiconductor devices can be bonded to base wafer 304 and tested by self-test core 302.

[0070] Figure 4 is a schematic illustration of a test core configuration compared to a built-in self-test configuration according to various embodiments. Figure 4 , the left column 406 illustrates different embodiments of chips and chip stacks using a self-test core 402 (also referred to herein as a "self-test chip") according to various embodiments disclosed herein, which can be directly bonded to a semiconductor chip having active circuit devices, which can be one or both of logic circuit devices and / or memory circuit devices to be tested. The right column 408 illustrates a conventional version of a similar chipset using built-in self-test circuits 404 patterned in the semiconductor chip. The self-test core can be manufactured in a node that is more cost-effective than traditional built-in self-test. As shown in FIG. Figure 4 As illustrated, although the resolution of the self-test core's node 20nm may be lower than the resolution of the equivalent built-in self-test 7nm, the cost of the 20nm node may be much lower than the built-in self-test (e.g., 10% lower, 20% lower, 30% lower, etc.). The cost of the 20nm node may be lower because the lower resolution 20nm node is cheaper to produce than the high resolution 7nm node, and because it can be directly bonded to the semiconductor components, the 20nm node does not require any footprint of the semiconductor components. In addition, the self-test core or chip can scan, test and / or verify a larger area than a traditional built-in self-test because the self-test core or chip can scan and / or test many chips or even an entire system. In addition, some operations of the built-in self-test can utilize similar "base" code, which can allow for the consolidation of test areas and / or a reduction in the overall silicon area dedicated to test nodes. For example, Figure 4It is illustrated that in a conventional built-in self-test system, each die has a portion of the wafer footprint dedicated to built-in self-test 404. However, self-test chip 402 can allow the use of a (potentially larger) chip to test multiple chips. Because one self-test chip 402 can test multiple chips, self-test chip 402 can be more efficient and / or reduce overall cost. In addition, because self-test chip 402 is not within the footprint of the device, self-test chip 402 can cover more algorithms and greater testing capabilities than built-in self-test circuit 404, which can further reduce the complexity of other chips or devices due to the off-board of possible test logic.

[0071] In some embodiments, the bonding layer may include a non-conductive layer (e.g., a dielectric material) in which the conductive contact is at least partially embedded. In some embodiments, the dielectric layer may include an inorganic dielectric material compatible with integrated circuit manufacturing. In some embodiments, the dielectric layer may be a dielectric material (such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, and / or any other suitable dielectric material). The conductive contact may include any suitable metal (such as copper).

[0072] In some embodiments, the semiconductor device may include an integrated circuit device having active circuit devices (e.g., circuit devices having one or more transistors). In some embodiments, the semiconductor device may include a system on chip (SoC) device. In some embodiments, the semiconductor device may include a central processing unit, a memory device, a microcontroller, a microprocessor, an application specific integrated circuit, a graphics processing unit, or any combination thereof.

[0073] In some embodiments, the semiconductor device may include a semiconductor substrate. In some devices, the semiconductor substrate may include silicon. In some devices, the semiconductor substrate may include monocrystalline silicon or polycrystalline silicon. In some embodiments, the semiconductor device may include a through hole. In some embodiments, the through hole may include a metal structure that at least partially extends through (e.g., completely through) the semiconductor device. In some embodiments, the through hole may include a conductive material. In some embodiments, the through hole may include copper or any other suitable conductive material.

[0074] In some embodiments, the self-test core can be a self-test chip. In some embodiments, the self-test core can include a test chip. In some embodiments, the self-test chip can include a test circuit device. In some embodiments, the test circuit device can include an integrated circuit. In some embodiments, the test circuit device can be integrated into a basic device. In some embodiments, the self-test core can be configured to test some or all functionality of a semiconductor device. In some embodiments, the self-test core can be configured to test some or all functionality of any number of semiconductor devices (e.g., 1, 2, 3, 4, 5, 6, 7 or more semiconductor devices). In some embodiments, the self-test core can be configured to test multiple devices sequentially and / or simultaneously.

[0075] In some embodiments, the self-test core can be bonded to the semiconductor element without adhesive. In some embodiments, the self-test core bonded to the semiconductor element can be in electrical communication with one or more integrated circuits within the semiconductor element. In some embodiments, the self-test core can be capable of verifying or testing the functionality of the semiconductor element and / or one or more integrated circuits therein.

[0076] In some embodiments, the self-test core may include a chip having an integrated circuit device. In some embodiments, the self-test core may include a chip or an electrical component or a part of a device having a routing circuit device. In some embodiments, the routing circuit device may include an electrical input or an electrical output. In some embodiments, the routing circuit device may be connected to the integrated circuit device or may be electrically or otherwise communicated with the integrated circuit device. In some embodiments, the self-test core may include an electrical contact or contact pad. In some embodiments, the electrical contact or contact pad may be electrically communicated with one or both of the test circuit device or the integrated circuit device.

[0077] In some embodiments, the self-test core can test some or all functionality of the semiconductor device. In some embodiments, the self-test core is configured to provide an output signal. In some embodiments, the output signal is related to the functionality of the semiconductor device. In some embodiments, the functionality of the semiconductor device indicates the suitability of the device for a given purpose of the device quality. In some embodiments, the device quality corresponds to whether the device operates according to design.

[0078] In some embodiments, the semiconductor element includes an integrated circuit within a substrate. In some embodiments, the integrated circuit is connected to the surface of the substrate via an input or output structure. In some embodiments, the input or output structure is a through hole. In some embodiments, the input or output structure is in electrical communication with the integrated circuit. In some embodiments, the semiconductor element includes a routing circuit device that communicates with or is connected to the integrated circuit device. In some embodiments, the input or output structure may include a routing circuit device. In some embodiments, the semiconductor device may include an electrical contact (e.g., a contact pad). In some embodiments, the electrical contact pad or contact may be electrically connected to or communicate with one or both of the integrated circuit device or the routing circuit device.

[0079] Examples of direct binding methods and direct binding structures

[0080] Various embodiments disclosed herein relate to direct bonding structures, in which two or more elements can be directly bonded to each other without the need for an intervening adhesive. Figure 5A and 5B Schematically illustrates a process for forming a direct hybrid bonded structure without an intervening adhesive, according to some embodiments. Figure 5A and Figure 5B In the embodiment, the combined structure 500 includes two elements 502 and 504, which can be directly bonded to each other at the bonding interface 518 without the need for an intervening adhesive. Two or more microelectronic elements 502 and 504 (such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, separate active devices such as power switches, etc.) can be stacked on each other or bonded to each other to form the combined structure 500. The conductive feature 506a of the first element 502 (such as a contact pad, an exposed end of a via (such as a TSV) or a through-substrate electrode) can be electrically connected to the corresponding conductive feature 506b of the second element 504. Any suitable number of elements can be stacked in the combined structure 500. For example, a third element (not shown) can be stacked on the second element 504, a fourth element (not shown) can be stacked on the third element, and so on. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 502. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the laterally stacked additional element may be two times smaller than the second element.

[0081] In some embodiments, elements 502 and 504 are directly bonded to each other without adhesive. In various embodiments, a non-conductive field region including a non-conductive or dielectric material can serve as a first bonding layer 508a of a first element 502, which can be directly bonded to a corresponding non-conductive field region without adhesive, and the non-conductive field region includes a non-conductive or dielectric material serving as a second bonding layer 508b of a second element 504. Non-conductive bonding layers 508a and 508b can be disposed on respective front sides 514a and 514b of device portions 510a and 510b (such as semiconductor (e.g., silicon) portions of elements 502, 503). Active devices and / or circuit devices can be patterned and / or otherwise disposed in or on device portions 510a and 510b. Active devices and / or circuit devices may be disposed at or near the front sides 514a and 514b of device portions 510a and 510b, and / or disposed at or near the relative back sides 516a and 516b of device portions 510a and 510b. A bonding layer may be provided on the front side and / or back side of the element. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer 508a of the first element 502. In some embodiments, the non-conductive bonding layer 508a of the first element 502 may be directly bonded to the corresponding non-conductive bonding layer 508b of the second element 504 using a dielectric to dielectric bonding technique. For example, a non-conductive or dielectric to dielectric bond may be formed without an adhesive using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes. It should be appreciated that in various embodiments, bonding layers 508a and / or 508b may include a non-conductive material such as a dielectric material such as silicon oxide or an undoped semiconductor material such as undoped silicon. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or may include carbon such as silicon carbide, silicon carbonitride, low-K dielectric materials, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon or materials including a diamond surface. Such carbon-containing ceramic materials may be considered inorganic despite including carbon. In some embodiments, the dielectric material does not include a polymer material such as an epoxy, resin, or molding material.

[0082] In some embodiments, device portions 510a and 510b may have significantly different coefficients of thermal expansion (CTE), thereby defining a heterostructure. The CTE difference between device portions 510a and 510b, particularly between the bulk semiconductor (typically the single crystal portion of device portions 510a, 510b), may be greater than 5ppm or greater than 10ppm. For example, the CTE difference between device portions 510a and 510b may be in the range of 5ppm to 100ppm, 5ppm to 40ppm, 10ppm to 100ppm, or 10ppm to 40ppm. In some embodiments, one of device portions 510a and 510b may include an optoelectronic single crystal material (including a perovskite material) for optical piezoelectric or thermoelectric applications, and the other of device portions 510a, 510b includes a more conventional substrate material. For example, one of the device portions 510a, 510b includes lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), while the other of the device portions 510a, 510b includes silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the device portions 510a and 510b includes a III-V single semiconductor material (such as gallium arsenide (GaAs) or gallium nitride (GaN)), and the other of the device portions 510a and 510b may include a non-III-V semiconductor material (such as silicon (Si)), or may include other materials with similar CTE (such as quartz, fused silica glass, sapphire, or glass).

[0083] In various embodiments, a direct hybrid bond may be formed without an intervening adhesive. For example, the non-conductive bonding surfaces 512a and 512b may be polished to a high degree of smoothness. The non-conductive bonding surfaces 512a and 512b may be polished using, for example, chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 512a and 512b may be less than For example, the roughness of the bonding surfaces 512a and 512b may be about to to or to . The bonding surfaces 512a and 512b may be cleaned and exposed to plasma and / or etchant to activate the surfaces 512a and 512b. In some embodiments, the surfaces 512a and 512b may be terminated with a substance after activation or during activation (e.g., during a plasma and / or etching process). Without being limited by theory, in some embodiments, an activation process may be performed to destroy chemical bonds at the bonding surfaces 512a and 512b, and a termination process may provide additional chemicals at the bonding surfaces 512a and 512b, thereby increasing the binding energy during direct bonding. In some embodiments, activation and termination are provided in the same step, such as a plasma for activating and terminating the surfaces 512a and 512b. In other embodiments, the bonding surfaces 512a and 512b may be terminated in a separate process to provide additional substances for direct bonding. In various embodiments, the termination substance may include nitrogen. For example, in some embodiments, (multiple) bonding surfaces 512a, 512b may be exposed to a nitrogen-containing plasma. Further, in some embodiments, the bonding surfaces 512a and 512b may be exposed to fluorine. For example, one or more fluorine peaks may be present at or near the bonding interface 518 between the first element 502 and the second element 504. Thus, in the direct bonding structure 500, the bonding interface 518 between the two non-conductive materials (e.g., bonding layers 508a and 508b) may include a very smooth interface having a higher nitrogen content and / or fluorine peaks at the bonding interface 518. Additional examples of activation and / or termination processes may be found in U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes. After the activation process, the roughness of the polished bonding surfaces 512a and 512b may be slightly rougher (e.g., about to to or possibly even rougher).

[0084] In various embodiments, the conductive feature 506a of the first element 502 can also be directly bonded to the corresponding conductive feature 506b of the second element 504. For example, a direct hybrid bonding technique can be used to provide a conductor-to-conductor direct bond along a bonding interface 518, which includes a covalently directly bonded non-conductive to non-conductive (e.g., dielectric to dielectric) surface prepared as described above. In various embodiments, conductor-to-conductor (e.g., conductive feature 506a to conductive feature 506b) direct bonding and dielectric to dielectric hybrid bonding can be formed using direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,552,988, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes. In the direct hybrid bonding embodiments described herein, the conductive features are provided in the non-conductive bonding layer, and both the conductive features and the non-conductive features are prepared (such as by the planarization, activation and / or termination treatment described above) for direct bonding. Therefore, the bonding surface prepared for direct bonding includes both conductive features and non-conductive features.

[0085] For example, non-conductive (e.g., dielectric) bonding surfaces 512a, 512b (e.g., inorganic dielectric surfaces) can be prepared and directly bonded to each other without intervening adhesives as explained above. Conductive contact features (e.g., conductive features 506a and 506b, which can be at least partially surrounded by non-conductive dielectric field regions within bonding layers 508a, 508b) can also be directly bonded to each other without intervening adhesives. In various embodiments, conductive features 506a, 506b can include discrete pads or traces at least partially embedded in the non-conductive field regions. In some embodiments, the conductive contact features can include exposed contact surfaces of substrate through-holes (e.g., through-silicon vias (TSVs)). In some embodiments, the respective conductive features 506a and 506b can be recessed below the dielectric field region or the outer (e.g., upper) surface (non-conductive bonding surfaces 512a and 512b) of the non-conductive bonding layers 508a and 508b, for example, by less than 30nm, less than 20nm, less than 15nm, or less than 10nm, for example, within a range of 2nm to 20nm or within a range of 4nm to 10nm. In various embodiments, the size of the recesses in the opposing elements can be such that the total gap between the opposing contact pads is less than 15nm or less than 10nm prior to direct bonding. In some embodiments, the non-conductive bonding layers 508a and 508b can be directly bonded to each other at room temperature without the need for an adhesive, and then the bonded structure 500 can be annealed. Upon annealing, the conductive features 506a and 506b can expand and contact each other to form a metal-to-metal direct bond. Advantageously, direct bonding interconnects or Technology can enable high density of conductive features 506a and 506b to be connected across direct bonding interface 518 (e.g., small pitch or fine pitch of conventional array). In some embodiments, the spacing of conductive features 506a and 506b (such as conductive traces embedded in the bonding surface of one of the bonding elements) can be less than 100 microns or less than 10 microns or even less than 2 microns. For some applications, the ratio of the spacing of conductive features 506a and 506b to one of the dimensions (e.g., diameter) of the bonding pad is less than 20, or less than 10, or less than 5, or less than 3, and sometimes desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonding elements in the bonding element can be in the range of 0.3 to 20 microns (e.g., in the range of 0.3 to 3 microns). In various embodiments, conductive features 506a and 506b and / or traces can include copper or copper alloys, although other metals may be suitable. For example, conductive features disclosed herein, such as conductive features 506a and 506b, may include fine grain metal (eg, fine grain copper).

[0086] Therefore, in the direct bonding process, the first element 502 can be directly bonded to the second element 504 without the need for intervening adhesive. In some arrangements, the first element 502 may include a singularized element, such as a singularized integrated device die. In other arrangements, the first element 502 may include a carrier or substrate (e.g., a wafer), which includes multiple (e.g., tens, hundreds, or multiple) device regions, which form multiple integrated device dies when singularized. Similarly, the second element 504 may include a singularized element, such as a singularized integrated device die. In other arrangements, the second element 504 may include a carrier or substrate (e.g., a wafer). The embodiments disclosed herein may be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes accordingly. In the wafer-to-wafer (W2W) process, two or more wafers may be directly bonded to each other (e.g., directly mixed and bonded), and singularized using a suitable singularization process. After singulation, side edges of the singulated structure (eg, side edges of two bonded elements) may be substantially flush and may include markings indicating a common singulation process of the bonded structure (eg, saw marks if a saw singulation process was used).

[0087] As explained herein, the first element 502 and the second element 504 can be directly combined with each other without adhesive, which is different from the deposition process, and produces a different interface structure compared to deposition. In one application, the width of the first element 502 in the combined structure is similar to the width of the second element 504. In some other embodiments, the width of the first element 502 in the combined structure 500 is different from the width of the second element 504. Similarly, the width or area of ​​the larger element in the combined structure can be at least 10% larger than the width or area of ​​the smaller element. The first element 502 and the second element 504 can include non-deposition elements accordingly. Further, different from the deposited layer, the direct combined structure 500 can include a defective area along the combined interface 518, and there is a nanometer-level gap (nano gap) in the defective area. Due to the activation (such as exposure to plasma) of the combined surface 512a and 512b, the nano gap can be formed. As explained above, the combined interface 518 can include the concentration of materials from activation and / or the last chemical treatment process. For example, in the embodiment activated by nitrogen plasma, a nitrogen peak can be formed at the combined interface 518. The nitrogen peak can be detected using secondary ion mass spectrometry (SIMS) technology. In various embodiments, for example, nitrogen termination treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) can replace the OH groups on the hydrolyzed (OH-terminated) surface with NH2 molecules to produce a nitrogen-terminated surface. In an embodiment activated using oxygen plasma, an oxygen peak can be formed at the bonding interface 518. In some embodiments, the bonding interface 518 may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As explained herein, direct bonding may include covalent bonds that are stronger than van der Waals bonds. Bonding layers 508a and 508b may also include polished surfaces that are flattened to a high degree of smoothness.

[0088] In various embodiments, the metal-to-metal bond between the conductive features 506a and 506b can be bonded so that the metal grains grow into each other across the bonding interface 518. In some embodiments, the metal is or includes copper, which can have grains oriented along the 511 crystal plane to improve copper diffusion across the bonding interface 518. In some embodiments, the conductive features 506a and 506b can include a nanotwinned copper grain structure, which can assist in merging the conductive features during annealing. The bonding interface 518 can extend substantially completely to at least a portion of the bonding conductive features 506a and 506b, so that there is substantially no gap between the non-conductive bonding layers 508a and 508b at or near the bonding conductive features 506a and 506b. In some embodiments, a barrier layer can be provided below the conductive features 506a and 506b (which can include copper, for example) and / or a barrier layer can be provided laterally surrounding the conductive features 506a and 506b. However, in other embodiments, there may be no barrier layer beneath conductive features 506a and 506b as described, for example, in US Pat. No. 11,195,748, which is incorporated herein by reference in its entirety and for all purposes.

[0089] Advantageously, very fine pitches and / or small pad sizes between adjacent conductive features 506a and 506b may be achieved using the hybrid bonding techniques described herein. For example, in various embodiments, the pitch p (i.e., the distance from edge to edge or from center to center) between adjacent conductive features 506a (or 506b) may be Figure 1A The major lateral dimension (e.g., pad diameter) may be in the range of 0.5 microns to 50 microns, in the range of 0.75 microns to 25 microns, in the range of 1 micron to 25 microns, in the range of 1 micron to 10 microns, or in the range of 1 micron to 5 microns. Further, the major lateral dimension (e.g., pad diameter) may also be small, such as in the range of 0.25 microns to 30 microns, in the range of 0.25 microns to 5 microns, or in the range of 0.5 microns to 5 microns.

[0090] As described above, the non-conductive bonding layers 508a, 508b can be directly bonded to each other without an adhesive, and then the bonded structure 500 can be annealed. During annealing, the conductive features 506a, 506b can expand and contact each other to form a direct metal-to-metal bond. In some embodiments, the materials of the conductive features 506a, 506b can interdiffuse during the annealing process.

[0091] the term

[0092] Unless the context clearly requires otherwise, throughout the description and claims, the words "comprise", "comprising", "include", "including", etc. should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to". The word "coupled" as generally used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Similarly, the word "connected" as generally used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Additionally, when used in this application, the words "herein", "above", "below" and words of similar meaning should refer to the entire application, rather than any particular part of the application. In addition, as used herein, when a first element is described as being "on" or "above" a second element, the first element can be directly on or above the second element, so that the first element and the second element are in direct contact, or the first element can be indirectly on or above the second element, so that one or more elements are between the first element and the second element. Where the context permits, the words used in the singular or plural in the above specific embodiments may also include the plural or singular, respectively. The word "or" refers to a list of two or more items and covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0093] Furthermore, unless specifically stated otherwise or otherwise understood to be used within the context, conditional language used herein (such as "can," "could," "might," "may," "eg," "for example," "such as," etc.) is generally intended to convey that certain embodiments include and other embodiments do not include certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that features, elements, and / or states are in any way required for one or more embodiments.

[0094] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein may be implemented in a variety of other forms; in addition, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, when a block is presented in a given arrangement, an alternative embodiment may utilize different components and / or circuit topologies to perform similar functionality, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and actions of the various embodiments described above may be combined to provide further embodiments. The attached claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the present disclosure.

[0095] Several illustrative examples of test elements and related systems and methods for combining structures have been disclosed. Although the present disclosure is described according to certain illustrative examples and uses, other examples and other uses (including examples and uses that do not provide all the features and advantages stated herein) are also within the scope of the present disclosure. In various examples, the arrangement or execution of parts, elements, features, actions or steps may be different from those described, and parts, elements, features, actions or steps may be combined, merged, added or omitted. All possible combinations and sub-combinations of elements and parts described herein are intended to be included in the present disclosure. No single feature or set of features is necessary or indispensable.

[0096] Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations, either individually or in any suitable subcombination. Furthermore, while features may be described above as functioning in certain combinations, one or more features from a claimed combination may in some cases be excised from the combination, and the combination may be claimed as a subcombination or a variation of a subcombination.

[0097] Further, although illustrative examples have been described, any examples with equivalent elements, modifications, omissions, and / or combinations are also within the scope of the present disclosure. In addition, although certain aspects, advantages, and novel features are described herein, not all such advantages may be achieved according to any particular example. For example, some examples within the scope of the present disclosure achieve one advantage or a group of advantages taught herein without necessarily achieving other advantages taught or suggested herein. Further, some examples may achieve advantages different from those taught or suggested herein.

[0098] Some examples have been described in conjunction with the accompanying drawings. These drawings may or may not be drawn and / or shown to scale, but such ratios should not be restrictive, because other than the sizes and ratios shown, other sizes and ratios are expected and within the scope of the disclosed invention. Distances, angles, etc. are merely illustrative and do not necessarily have an exact relationship with the actual size and layout of the illustrated device. Components may be added, removed, and / or rearranged. Further, the disclosure of any specific features, aspects, methods, characteristics, features, qualities, attributes, elements, etc. associated with various examples herein may be used for all other examples stated herein. Additionally, any method described herein may be practiced using any device suitable for performing the enumerated steps.

[0099] To summarize the present disclosure, certain aspects, advantages and features of the present invention are described herein. According to any specific example of the present invention disclosed herein, all or any such advantages may not be achieved. Any aspect of the present disclosure is not necessary or indispensable. In many examples, the configuration mode of the device, system and method may be different from that illustrated in the drawings or the description herein. For example, various functionalities provided by the illustrated modules may be combined, rearranged, added or deleted. In some implementations, additional or different processors or modules may perform some or all of the functionalities described with reference to the examples described and illustrated in the drawings. Many implementation variations are possible. Any feature, structure, step or process disclosed in this specification may be included in any example.

Claims

1. A combined structure comprising: A first semiconductor element including a first active circuit device; as well as a test element including a test circuit device, the test element being directly bonded to the first semiconductor element along a bonding interface without adhesive; Wherein the test circuit arrangement is configured to test functionality of at least part of the first active circuit arrangement of the first semiconductor element. 2 . The bonding structure according to claim 1 , wherein the test element further comprises a memory configured to store a result of the test. The bonding structure according to claim 1 , wherein the test element is smaller than the first semiconductor element.

4. The bonding structure according to claim 1, wherein the first non-conductive bonding layer of the first semiconductor element is directly bonded to the second non-conductive bonding layer of the test element without intervening adhesive; And wherein the first contact feature of the first semiconductor element is directly bonded to the second contact feature of the test element without intervening adhesive. 5 . The bonding structure according to claim 1 , wherein the test element further comprises a plurality of signal contact pads. 6 . The bonding structure of claim 5 , wherein a majority of the plurality of signal contact pads are configured to test at least a portion of the first active circuit device of the first semiconductor element.

7. A combined structure comprising: A first semiconductor component including a test circuit device; a second semiconductor element directly bonded to the first semiconductor element along a bonding interface without an adhesive, the second semiconductor element including a first active circuit device; and Wherein the test circuit arrangement is configured to test functionality of at least part of the first active circuit arrangement of the second semiconductor element. 8 . The combined structure of claim 7 , wherein the test circuit device is further configured to store a result of the at least partial functionality of the first active circuit device.

9. The bonding structure according to claim 7, wherein the first non-conductive bonding layer of the first semiconductor element is directly bonded to the second non-conductive layer of the second semiconductor element without intervening adhesive; And wherein the first contact feature of the first semiconductor element is directly bonded to the second contact feature of the second semiconductor element without an intervening adhesive.

10. The bonded structure of claim 7, further comprising a third semiconductor element, the third semiconductor element comprising a second active circuit device, the third semiconductor element being directly bonded to the second semiconductor element, the test circuit device being configured to test at least part of the functionality of the second active circuit device. 11 . The bonded structure according to claim 10 , further comprising a fourth semiconductor element, the fourth semiconductor element comprising a third active circuit device, the fourth semiconductor element being directly bonded to the third semiconductor element.

12. The combined structure of claim 11, wherein the first semiconductor element further comprises a fourth active circuit device.

13. The combined structure of claim 12, wherein the test circuit device of the first semiconductor element is configured to test at least part of the functionality of the first active circuit device, the second active circuit device, the third active circuit device and / or the fourth active circuit device.

14. The bonded structure according to claim 7, further comprising a third semiconductor element, the third semiconductor element comprising a second active circuit device, the third semiconductor element being directly bonded to the first semiconductor element; and Wherein the test circuit arrangement is configured to test at least part of the functionality of the second active circuit arrangement.

15. The combined structure according to claim 7, wherein the first semiconductor element comprises a test chip. 16 . The combined structure of claim 15 , wherein the test chip is configured to test only the active circuit devices of one or more other semiconductor elements and no other active circuit devices.

17. The bonded structure of claim 16, further comprising a third semiconductor element, the third semiconductor element comprising a second active circuit device and a second bonding layer, the second bonding layer being bonded to the second semiconductor element without an adhesive; and The test circuit arrangement is configured to test at least part of the functionality of the third active circuit arrangement.

18. The bonded structure of claim 17, further comprising a fourth semiconductor element, the fourth semiconductor element comprising a third active circuit device and a third bonding layer, the third bonding layer being bonded to the second semiconductor element without an adhesive; and Wherein the test circuit arrangement is configured to test at least part of the functionality of the third active circuit arrangement.

19. The combined structure of claim 18, wherein the test circuit device is configured to send one or more signals to the first active circuit device.

20. The combined structure of claim 19, wherein the one or more signals probe one or more portions of the first active circuit device.

21. The combined structure according to claim 20, wherein the first active circuit device transmits a return signal, and the return signal is transmitted from the first active circuit device to the test circuit device; and The test circuitry is configured to analyze the return signal and send an indication signal to the first device.

22. A combined structure comprising: A wafer including a first active circuit device and a self-test core; as well as a first semiconductor element including a second active circuit device, the semiconductor element being directly bonded to the wafer without an adhesive, Wherein the self-test core comprises a test circuit device configured to test at least a portion of functionality of at least one of the first active circuit device and the second active circuit device.

23. The bonding structure of claim 22, wherein the first non-conductive bonding layer of the wafer is directly bonded to the second non-conductive layer of the first semiconductor element without intervening adhesive; and The first contact features of the wafer are directly bonded to the second contact features of the first semiconductor element without intervening adhesive.

24. The bonded structure of claim 23, further comprising a third semiconductor element comprising a third active circuit device, a third non-conductive bonding layer, and a third contact feature in communication with the third active circuit device; wherein the third non-conductive bonding layer is directly bonded to the first non-conductive bonding layer of the wafer without an intervening adhesive; and The third contact feature is directly bonded to the first contact feature of the wafer without adhesive.

25. The bonded structure of claim 23, wherein the first semiconductor element comprises a fourth non-conductive bonding layer and a fourth contact feature in communication with the second active circuit device.

26. The bonded structure of claim 25, further comprising a second semiconductor element comprising a third active circuit device, a third non-conductive bonding layer, and a third contact feature in communication with the third active circuit device; and wherein the third non-conductive bonding layer of the second semiconductor element and the fourth non-conductive bonding layer of the first semiconductor element are directly bonded without intervening adhesive; and The third contact feature of the second semiconductor element is directly bonded to the fourth contact feature of the first semiconductor element without an intervening adhesive.

27. The bonded structure of claim 26, wherein the second semiconductor element further comprises a fifth non-conductive bonding layer and a fifth contact feature in communication with the third active circuit device.

28. The bonded structure of claim 27, further comprising a third semiconductor element comprising a fourth active circuit device, a sixth non-conductive bonding layer, and a sixth contact feature in communication with the third active circuit device; wherein the sixth non-conductive bonding layer of the third semiconductor element and the fifth non-conductive bonding layer of the second semiconductor element are directly bonded without intervening adhesive; and The sixth contact feature of the third semiconductor element is directly bonded to the fifth contact feature of the second semiconductor element without an intervening adhesive.

29. The combined structure of claim 28, wherein the test circuit device is configured to test at least a portion of functionality of at least one of the first active circuit device, the second active circuit device, the third active circuit device, and the fourth active circuit device.

30. A method of forming a bonded structure, the method comprising: providing a first semiconductor component including a test circuit arrangement; bonding the first semiconductor element to a second semiconductor element without an adhesive; The second semiconductor element comprises a first active circuit device, and the test circuit device is configured to test the functionality of the first active circuit device.

31. The method according to claim 30, further comprising: A third semiconductor element including a second active circuit device is bonded to the first semiconductor element without an adhesive.

32. The method according to claim 31, further comprising: A third semiconductor element including a second active circuit device is coupled to the second semiconductor element.

33. The method according to claim 32, further comprising: A fourth semiconductor element including a third active circuit device is coupled to the second semiconductor element.

34. The method of claim 33, wherein the first semiconductor element comprises a test chip.

35. The method of claim 34, further comprising: bonding at least one semiconductor element including an active circuit device to the second semiconductor element; and Wherein the test circuit arrangement is configured to test at least a part of the functionality of the at least one semiconductor component.

36. A combined structure comprising: A first semiconductor element including a first active circuit device; a first non-conductive bonding layer of the first semiconductor element at least partially defining a direct bonding surface of the bonding structure; as well as One or more traces connected to the first active circuit device and extending at least partially into the first non-conductive bonding layer, wherein the one or more traces are configured to provide electrical communication between the first active circuit device and a test element, the one or more traces terminating at or below the direct bonding surface.

37. The bonding structure according to claim 36 further includes a first contact feature, which is at least partially embedded in the first non-conductive bonding layer and connected to the one or more traces, and the first contact feature is configured to directly bond to a corresponding second contact feature of the test element.

38. The integrated circuit device of claim 36, further comprising a plurality of contact features at least partially embedded in the first non-conductive bonding layer, wherein the first non-conductive layer and the plurality of contact features cooperate to at least partially define a bonding surface for direct hybrid bonding.

39. The integrated circuit device of claim 36, wherein the one or more traces are not connected to contact pads at the bonding surface of the bonding structure.

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