Crystal grain, semiconductor packaging structure, enabling pin configuration method and memory

Abstract

The embodiment of the invention discloses a crystal grain, a semiconductor packaging structure, an enabling pin configuration method and a memory, relates to the technical field of storage, and solves the problems of high production cost and low production efficiency caused by the fact that a central flash memory chip in the prior art comprises a fixed number of chip enabling pins. According to the specific scheme, a crystal grain is provided, a peripheral circuit in the crystal grain is configured as follows: firstly, a control command is received, indication information is generated according to the control command, the control command is used for indicating the crystal grain to determine the address of the crystal grain, the indication information is used for indicating M crystal grains to share the same enabling pin, and M is a positive integer larger than or equal to 1. Then, the address of the crystal grain is determined according to the indication information, the address of the crystal grain is sent, and the address is used for addressing an enable signal provided by the enable pin.

Description

A crystal chip, semiconductor packaging structure, enabling pin configuration method and memory Technical Field

[0001] The embodiments of the present disclosure relate to the field of storage technology, and more particularly to a die, a semiconductor packaging structure, an enable pin configuration method, and a memory. Background Art

[0002] A NAND (Non-AND) storage device includes a main control chip and multiple flash memory chips coupled to the main control chip's chip enable pin (CE pin). As applications continue to increase the capacity of NAND storage devices, various packaging methods for flash memory chips have emerged to increase the capacity of NAND storage devices. These packaging methods can reduce the number of chip enable pins on a flash memory chip. Thus, with a fixed number of chip enable pins on the main control chip, the main control chip can be coupled with more flash memory chips, thereby increasing the capacity of the NAND storage device.

[0003] However, since the number of chip enable pins included in the flash memory chip packaged in any of the above-mentioned types of packaging methods is fixed and cannot be adjusted according to the capacity requirements of the NAND storage device and the number of chip enable pins of the main control chip, it is necessary to produce flash memory chips in multiple packaging methods and test them for customers to choose, resulting in high production costs and low production efficiency.

[0004] Summary of the Invention

[0005] The embodiments of the present disclosure provide a die, a semiconductor packaging structure, an enable pin configuration method, and a memory, which solve the problem in the prior art that flash memory chips include a fixed number of chip enable pins, resulting in high production costs and low production efficiency.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a die is provided, which includes a peripheral circuit, and the peripheral circuit is configured to: receive a control command, generate indication information according to the control command, determine the address of the die according to the indication information, and send the address of the die; wherein the control command is used to instruct the die to determine the address of the die; the indication information is used to indicate that M die share the same enable pin, M is a positive integer greater than or equal to 1; the address is used to address the enable signal provided by the enable pin.

[0008] The grain provided by the embodiment of the present disclosure receives control commands and generates indication information through a peripheral circuit, and determines the address of the grain according to the indication information, thereby realizing a configuration in which logically M grains share one enable pin. In this way, when the grain is applied to a flash memory chip, the number of enable pins of the flash memory chip can be flexibly configured according to the application's requirements for the capacity of the NAND storage device and the number of enable pins of the main control chip, thereby reducing the packaging method of the flash memory chip during production, thereby reducing the occupied packaging reliability certification resources and test program development resources, reducing production costs, and improving production efficiency. For example, since there are fewer packaging methods for flash memory chips, it can help customers reduce import certification tests, reduce material control costs, and help customers reduce testing costs and improve production efficiency. In addition, during use, customers can meet different production needs by configuring the number of enable pins of the flash memory chip, which can improve customer satisfaction.

[0009] In some embodiments, the peripheral circuit includes a control circuit, and a trigger, a first decoding circuit, and a second decoding circuit coupled in sequence. The control circuit is configured to receive a control command and generate and send indication information based on the control command. The trigger is configured to receive the indication information and send the indication information to the first decoding circuit. The first decoding circuit is configured to determine a first coded value of a die based on the indication information. The second decoding circuit is configured to decode the first coded value to obtain an address of the die.

[0010] The grain provided by the embodiment of the present disclosure receives and generates indication information through a control circuit, determines a first coding value of the grain based on the indication information through a first decoding circuit, and then decodes the first decoding value through a second decoding circuit to determine the address of the grain, thereby realizing the logical configuration between M grains and one enable pin.

[0011] In some embodiments, the peripheral circuit further includes a register coupled to the first decoding circuit. The first decoding circuit is further configured to set a first value in the register to a second value, the first value being used to indicate that the encoding value of the die is the second encoding value, and the second value being used to indicate that the encoding value of the die is the first encoding value.

[0012] The die provided by the embodiment of the present disclosure sets the register to different values ​​through the first decoding circuit, so that when the die is applied to a flash memory chip, repeated address encoding of multiple die in the flash memory chip can be avoided.

[0013] In some embodiments, the value of M includes: 1, 2, 4, 8, 16 or 32.

[0014] In another aspect, a semiconductor package structure is provided, comprising N dies as described above. M of the N dies are configured to receive control commands, the control commands instructing the M dies to determine respective addresses, which are used to address enable signals provided by enable pins, where M is a positive integer greater than or equal to 1, N is a positive integer greater than or equal to 2, and M is less than or equal to N. The M dies are also configured to send respective addresses.

[0015] In some embodiments, when M is greater than or equal to 2, the code values ​​of the M dies are different.

[0016] In some embodiments, the M dies include a target die, wherein the target die is configured to receive a chip select signal, the chip select signal being used to select the target die to receive an enable signal, and the chip select signal including an address of the target die.

[0017] On the other hand, a method for configuring the enable pin of a grain is provided, wherein the grain includes a peripheral circuit, and the method includes: the peripheral circuit receives a control command, generates indication information according to the control command, determines the address of the grain according to the indication information, and sends the address of the grain; wherein the control command is used to instruct the grain to determine the address of the grain, the indication information is used to indicate that M grains share the same enable pin, and M is a positive integer greater than or equal to 1; the address is used to address the enable signal provided by the enable pin.

[0018] In some embodiments, the peripheral circuit includes a control circuit, and a trigger, a first decoding circuit, and a second decoding circuit coupled in sequence. The method further includes: the control circuit receiving a control command and generating and sending indication information based on the control command; the trigger receiving the indication information and sending the indication information to the first decoding circuit; the first decoding circuit determining a first coded value of the die based on the indication information; and the second decoding circuit decoding the first coded value to obtain an address of the die.

[0019] In some embodiments, the peripheral circuit also includes a register, which is coupled to the first decoding circuit. The method also includes: the first decoding circuit sets the first value in the register to a second value, the first value is used to indicate that the coding value of the grain is the second coding value, and the second value is used to indicate that the coding value of the grain is the first coding value.

[0020] In some embodiments, the value of M includes: 1, 2, 4, 8, 16 or 32.

[0021] On the other hand, a method for configuring an enable pin of a semiconductor package structure is provided, wherein the semiconductor package structure includes N dies, and any one of the N dies includes a peripheral circuit, where N is a positive integer greater than or equal to 2. The method includes: the peripheral circuit receives a control command, generates indication information according to the control command, determines the address of the dies according to the indication information, and sends the address of the dies; wherein the control command is used to instruct the dies to determine the address of the dies; the indication information is used to indicate that M dies share the same enable pin, where M is a positive integer greater than or equal to 1; and the peripheral circuit address is used to address the enable signal provided by the enable pin.

[0022] In some embodiments, the peripheral circuit includes a control circuit, and a trigger, a first decoding circuit, and a second decoding circuit coupled in sequence. The method further includes: the control circuit receiving a control command and generating and sending indication information based on the control command; the trigger receiving the indication information and sending the indication information to the first decoding circuit; the first decoding circuit determining a first coded value of the die based on the indication information; and the second decoding circuit decoding the first coded value to obtain an address of the die.

[0023] In some embodiments, the peripheral circuit also includes a register, which is coupled to the first decoding circuit. The method also includes: the first decoding circuit sets the first value in the register to a second value, the first value is used to indicate that the coding value of the grain is the second coding value, and the second value is used to indicate that the coding value of the grain is the first coding value.

[0024] In some embodiments, the value of M includes: 1, 2, 4, 8, 16 or 32.

[0025] In some embodiments, when M is greater than or equal to 2, the code values ​​of the M dies are different.

[0026] In some embodiments, the M dies include a target die, and the method further includes: a peripheral circuit in the target die receives a chip select signal, the chip select signal is used to select the target die to receive an enable signal, and the chip select signal includes an address of the target die.

[0027] On the other hand, a memory is provided, which includes the semiconductor packaging structure provided by the aforementioned aspects.

[0028] On the other hand, a storage system is provided, which includes a controller and at least one memory coupled to the controller, wherein the controller is used to control the memory to read data, and the memory is the memory provided above.

[0029] On the other hand, an electronic device is provided, which includes the storage system provided above.

[0030] It can be understood that the beneficial effects that can be achieved by the semiconductor packaging structure, the enable pin configuration method of the chip, the enable pin configuration method of the semiconductor packaging structure, the memory, the storage system and the electronic device provided by the above-mentioned embodiments of the present disclosure can refer to the beneficial effects of the chip above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0032] FIG1 is a schematic structural diagram of an electronic device according to some embodiments;

[0033] FIG2 is a schematic diagram of the structure of a NAND memory according to some embodiments;

[0034] FIG3 is a schematic structural diagram of a memory unit according to some embodiments;

[0035] FIG4 is a schematic structural diagram of a NAND storage device according to some embodiments;

[0036] FIG5 is a schematic structural diagram of a flash memory chip according to some embodiments;

[0037] FIG6 is a schematic structural diagram of a die according to some embodiments;

[0038] FIG7 is a schematic structural diagram of a peripheral circuit according to some embodiments;

[0039] FIG8 is a schematic diagram of a semiconductor package structure according to some embodiments;

[0040] FIG9 is a schematic diagram of another semiconductor package structure according to some embodiments;

[0041] FIG10 is a schematic diagram of yet another semiconductor package structure according to some embodiments;

[0042] FIG11 is a flow chart of a method for configuring enable pins of a die according to some embodiments;

[0043] FIG12 is a flow chart of another method for configuring enable pins of a die according to some embodiments;

[0044] FIG13 is a flow chart of a method for configuring enable pins of a semiconductor package structure according to some embodiments. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0052] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0053] An embodiment of the present disclosure provides an electronic device, for example, the electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, or a digital multimedia player. For example, as shown in FIG1 , a structural diagram of an electronic device provided by an embodiment of the present disclosure is shown, and the electronic device includes a host 110 and a storage system 120. The host 110 is coupled to the storage system 120 to write data to the storage system 120 or read data stored in the host 110. The host 110 can also be referred to as a master device, and the storage system 120 can also be referred to as a slave device. In the electronic device, the slave device can be accessed by different master devices. For example, taking the electronic device as a mobile phone as an example, the central processing unit (CPU), digital signal processing (DSP), etc. of the mobile phone can all access the storage system 120 as the host 110.

[0054] Specifically, the host 110 is configured to process data from the NAND memory 122. For example, the host 110 may include a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor. Data is transmitted between the host 110 and the controller 121 using at least one of a variety of interface protocols.

[0055] For example, the interface protocol includes at least one of a universal serial bus (USB) protocol, a Microsoft Management Console (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-E (Peripheral Component Interconnect Express) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an integrated drive electronic (IDE) protocol, or a FireWire protocol.

[0056] The storage system 120 includes a controller 121 and multiple memories, which may include multiple NAND memories (or NAND flash chips or flash chips) 122 and / or multiple dynamic random access memories (DRAMs). The present embodiment of the application uses the example of a storage system 120 including multiple NAND memories 122 as an example for illustrative description. The controller 121 is used to balance the data write load on each NAND memory 122, coordinate and maintain collaboration between different NAND memories 122, thereby reducing the average read, write, and erase wear of all NAND memories 122, reducing the occurrence of bad blocks, and extending the service life of the NAND memories 122.

[0057] Specifically, the controller 121 can process input / output (I / O) requests received from the host 110 and ensure the integrity and effective storage of the data to be stored based on the I / O requests. For example, the controller 121 can cache the data received from the host 110 and perform redundant arrays of independent disks (RAID) (or disk array) calculations based on the received data to obtain RAID check data and cache the RAID check data. The RAID check data is used to recover data damaged during encoding or storage. The controller 121 can also send the data received from the host 110 and the calculated RAID check data to the NAND memory 122 for storage.

[0058] In some embodiments, the controller 121 can be configured to control operations in the NAND memory 122, such as read, write, erase, or encode operations. The controller 121 can also be configured to manage various functions of data stored or to be stored in the NAND memory 122, including but not limited to bad block management, garbage collection, logical to physical address conversion, or wear leveling. In some embodiments, the controller 121 is also configured to use error correction code (ECC) to recover data read from the NAND memory 122 or data written to the NAND memory 122. Of course, the controller 121 can also perform any other suitable functions on the NAND memory 122, for example, formatting the NAND memory 122, which is not specifically limited in the embodiments of the present application.

[0059] In some embodiments, the controller 121 may control the operation of the NAND memory 122 by generating control signals to control striping, calculation, or storage of data in the NAND memory 122. Alternatively, the controller 121 may receive signals for the operation of the NAND memory 122 from the host 110 to control striping, calculation, or storage of data in the NAND memory 122.

[0060] In some embodiments, the controller 121 may include different modules in a single device, such as an integrated circuit chip, for example, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), or a separate device with dedicated functions. In some embodiments, the components of the controller 121 may be in an integrated device, or distributed in different locations but communicate with each other via a network.

[0061] FIG2 is a schematic diagram of the structure of a NAND memory 122 according to an embodiment of the present disclosure. To increase storage capacity, the NAND memory 122 typically includes multiple die (DIEs) 1221, such as D0 and D1. Each DIE 1221 has multiple planes (PLs), such as PL0, PL1, PL2, and PL3.

[0062] Each PL may include one or more memory blocks, and each memory block may be further divided into multiple strings (STRs). Each STR includes memory cells for storing an upper page (UP) data portion, a middle page (MP) data portion, and a lower page (LP) data portion. The memory cells are coupled to a plurality of word lines (WL) arranged vertically, and to a plurality of bit lines (BL) arranged horizontally. Structurally, each STR may include multiple gate conductive layers extending laterally. A memory block includes multiple gate conductive layers stacked vertically at multiple levels, and each gate conductive layer is coupled to memory cells in multiple pages in the STRs distributed laterally in the memory block.

[0063] In one possible embodiment, each memory cell in the NAND memory 122 may be a charge trapping transistor. The structure of a charge trapping transistor is similar to that of a metal-oxide-semiconductor field-effect transistor (MOSFET), except that a charge trapping layer is inserted into the gate oxide dielectric layer of the MOSFET to store charge. In some embodiments, the memory cell may also be a floating gate transistor. A floating gate transistor inserts an additional floating gate (FG) (referred to as a floating gate) into the gate oxide dielectric layer of the MOSFET to store charge. The floating gate transistor has two gates (a conventional control gate (CG) and a floating gate). The difference between a floating gate transistor and a charge trapping transistor lies in the different materials used to store charge. For example, a floating gate transistor uses a floating gate to store charge. The floating gate is a conductor, and charge can move freely in the floating gate. A charge trapping transistor uses a charge trapping layer to store charge. The charge trapping layer is an insulator, such as silicon nitride, and charge is not easily moved in the charge trapping layer.

[0064] FIG3 is a schematic diagram of the structure of a memory cell in a NAND memory 122. The memory cell of the NAND memory includes a source (S), a drain (D), and a gate (G), as well as a floating gate and a control gate. When the threshold voltage of the memory cell is greater than a threshold (also referred to as a reference threshold voltage), it is identified as data "0," and when the threshold voltage of the memory cell is less than a threshold, it is identified as data "1." An insulating layer is provided between the floating gate and the substrate. When power is off, the insulating layer isolates the floating gate from the outside world, preventing the floating gate from losing charge and thus preventing data loss during power outages.

[0065] In the initial state, the floating gate does not store any charge, so the initial value of the stored data in the memory cell is "1". According to the Fowler-Nordheim tunneling effect, the data stored in the memory cell can be changed by changing the amount of charge stored in the floating gate. For example, by applying a programming voltage to the control gate, the charge passes through the insulating layer to charge the floating gate, which is called a programming operation. Accordingly, the data stored in the memory cell changes from "1" to "0". The charge in the floating gate is discharged through the insulating layer to achieve data erasure. This process is called an erase operation. Accordingly, the data stored in the memory cell changes from "0" to "1".

[0066] Since the NAND memory 122 has a large capacity and a fast rewriting speed, it is widely used in various electronic devices or storage devices.

[0067] For example, FIG4 is a schematic diagram of the structure of a NAND storage device 400 provided in an embodiment of the present disclosure. The NAND storage device 400 is a specific storage system 120, and includes a main control chip 410 (equivalent to the controller 121 described above) and multiple flash memory chips 420 (equivalent to the NAND memory 122 described above). The multiple chip enable pins on the main control chip 410 are respectively coupled to the chip enable pins on the multiple flash memory chips 420. The multiple flash memory chips 420 are used to store data, and the main control chip 410 is used to balance the data write load on each flash memory chip 420, coordinate and maintain the collaboration between different flash memory chips 420, thereby reducing the read, write and erase losses of all flash memory chips 420, reducing the occurrence of bad blocks, and extending the service life of the flash memory chips 420.

[0068] As the demand for the capacity of the NAND storage device 400 by applications continues to increase, in order to increase the capacity of the NAND storage device 400, a variety of packaging methods have emerged for packaging the flash memory chip 420. These various packaging methods can reduce the number of chip enable pins of the flash memory chip 420, so that when the number of chip enable pins of the main control chip 410 is constant, the main control chip 410 can be coupled with more flash memory chips 420 to increase the capacity of the NAND storage device 400.

[0069] Specifically, take the flash memory chip 420 as a ball grid array (BGA) 132, 8-die package (octal die package, ODP) as an example. As shown in (a) of Figure 5, the flash memory chip 420 can be packaged in a manner that one chip enable pin is coupled to one die. In this case, the address of each die can be lun0. The flash memory chip 420 is coupled to the main control chip 410 through eight chip enable pins. The main control chip 410 can enable the corresponding die through different chip enable pins. Alternatively, as shown in (b) of Figure 5, the flash memory chip 420 can be packaged in a manner that one chip enable pin is coupled to two die. In this case, the addresses of each two die can be lun0 and lun1 respectively for distinction. The flash memory chip 420 is coupled to the main control chip 410 through four chip enable pins. The main control chip 410 can enable the corresponding die through different chip enable pins and die addresses. Alternatively, as shown in (c) in Figure 5, the flash memory chip 420 can be packaged in a manner of coupling one chip enable pin with four grains. In this case, the addresses of each of the four grains can be lun0, lun1, lun2 and lun3 respectively for distinction. The flash memory chip 420 is coupled to the main control chip 410 through two chip enable pins, and the main control chip 410 can enable the corresponding grains through different chip enable pins and grain addresses.

[0070] It can be understood that compared with the flash memory chip 420 shown in (a) in Figure 5, the flash memory chip 420 shown in (b) and (c) in Figure 5 includes the same number of grains, but includes fewer chip enable pins. Therefore, when the number of chip enable pins of the main control chip 410 is certain, the flash memory chip 420 shown in (b) and (c) in Figure 5 can be used, so that the main control chip 410 can be coupled with more flash memory chips 420 to increase the capacity of the NAND storage device 400 and meet the needs of the application.

[0071] However, since the number of chip enable pins included in the flash memory chip 420 is fixed in the various packaging methods shown in Figure 5, the customer cannot adjust the number of chip enable pins on the flash memory chip 420 according to the application's requirements for the capacity of the NAND storage device 400 and the number of chip enable pins of the main control chip 410. Therefore, it is necessary to produce flash memory chips 420 in multiple packaging methods at the same time and test them for customer selection.

[0072] Generally, certification of a flash memory chip 420 with a single packaging method takes 2 to 3 months. Flash memory chips 420 with multiple packaging methods will require a large amount of packaging reliability certification resources and test program development resources, and will also increase the cost of subsequent maintenance, resulting in higher production costs. At the same time, due to the limited resources mentioned above, the certification time of flash memory chips 420 with different packaging methods will be in a certain order. Flash memory chips 420 awaiting certification will not be able to be produced, resulting in low production efficiency. Moreover, different customers have different requirements for the packaging methods of flash memory chips 420. If flash memory chips 420 with a single packaging method are prioritized for testing, it will not be possible to meet the needs of all customers, resulting in low customer satisfaction. In addition, flash memory chips 420 with different packaging methods are different types of products for customers. During use, customers need to add new material codes to distinguish between different types of flash memory chips 420, which increases the customer's material control costs. For each flash memory chip 420 with a different packaging method, customers need to undergo import certification testing, which will result in low production efficiency and increase the customer's testing costs.

[0073] In order to solve the problem that in the above-mentioned various types of packaging methods, the flash memory chip 420 includes a fixed number of chip enable pins, resulting in high production costs and low production efficiency, the embodiment of the present disclosure provides a grain that can be applied to the above-mentioned flash memory chip 420, which can reduce the production cost of the flash memory chip 420 and improve production efficiency.

[0074] 6 is a schematic diagram of the structure of a die 600 provided in an embodiment of the present disclosure, and the die 600 can be applied to the NAND memory device 400 described above. The die 600 includes a peripheral circuit 610 and a memory array 620 coupled to the peripheral circuit 610 .

[0075] In which, the peripheral circuit 610 is configured to receive a control command and generate indication information according to the control command, the control command is used to instruct the grain 600 to determine the address of the grain 600, and the indication information is used to indicate that M grains share the same enable pin (also called a chip enable pin), where M is a positive integer greater than or equal to 1.

[0076] Optionally, the die 600 may be any one of the M die, which is not limited in the embodiment of the present disclosure.

[0077] Optionally, when the die 600 is applied to the flash memory chip 420 , the control command may be generated by the main control chip 410 , and the peripheral circuit 610 may receive and generate the indication information according to the control command.

[0078] Optionally, when the die 600 is applied to the flash memory chip 420 , the M die sharing the same enable pin includes: the M die are coupled to the same enable pin of the main control chip 410 to share the same enable pin on the main control chip 410 .

[0079] Optionally, the value of M includes: 1, 2, 4, 8, 16 or 32. The embodiment of the present disclosure does not limit the specific value of M.

[0080] For example, when the value of M is 1, the indication information is used to instruct one die to use an enable pin of the main control chip 410 . When the value of M is 2, the indication information is used to instruct two die to share the same enable pin of the main control chip 410 .

[0081] In addition, the peripheral circuit 610 is also configured to determine the address of the grain 600 according to the indication information, and send the address of the grain 300 to the main control chip 410. The address is used for addressing the enable signal provided by the above-mentioned enable pin, so that the main control chip 410 can enable the grain 600 through the address of the grain 600.

[0082] Specifically, when the value of M is 1, it can be understood that the indication information is used to indicate that one die is coupled to one enable pin, and the one die is die 600. In this case, the peripheral circuit 610 can determine the address of the die 600 based on the indication information. For example, the peripheral circuit 610 can determine that the address of the die 600 is lun1 based on the indication information.

[0083] When the value of M is greater than 1, it can be understood that the indication information is used to indicate that M grains are coupled to 1 enable pin, and the M grains include grain 600. At this time, the process in which the peripheral circuit 610 determines the address of grain 600 according to the indication information can include multiple implementation methods. The embodiment of the present disclosure does not limit how the peripheral circuit 610 specifically determines the address of grain 600 according to the indication information.

[0084] Exemplarily, when the value of M is greater than 1, the control command received by the above-mentioned peripheral circuit 610 may also include the address coding information of the grain 600, so that the indication information generated by the peripheral circuit 610 also includes the address coding information of the grain 600. The peripheral circuit 610 can determine the address of the grain 600 based on the address coding information, thereby avoiding the address of the grain 600 from being repeated with the addresses of other grains among the M grains.

[0085] For example, when the value of M is 2, the control command received by the peripheral circuit 610 may also include the address coding information 1 of the grain 600, so that the indication information generated by the peripheral circuit 610 according to the control command also includes the address coding information 1 of the grain 600. The peripheral circuit 610 can determine that the address of the grain 600 is lun1 based on the address coding information in the indication information.

[0086] Optionally, the address encoding value of the die 600 may include 1 bit, or may include more bits. The embodiment of the present application does not limit the number of bits used to encode the address of the die 600.

[0087] For example, the address of die 600 may be encoded as 1.

[0088] It is understood that when the die 600 provided in the embodiment of the present disclosure is applied to the flash memory chip 420, first, the enable pins on the flash memory chip 420 coupled to the M die 600 can be short-circuited together by routing traces on a printed circuit board (PCB), and then coupled to a single enable pin on the main control chip 410, thereby physically achieving a configuration in which the M die share a single enable pin. Subsequently, the peripheral circuit 610 in the die 600 can receive control commands and generate indication information, and determine the address of the die 600 based on the indication information, thereby achieving a logical configuration between the M die and the single enable pin, thereby enabling the flash memory chip 420 to be configured into different packaging forms.

[0089] The die 600 provided in the embodiment of the present disclosure receives control commands and generates indication information through the peripheral circuit 610, and determines the address of the die 600 based on the indication information, thereby realizing a configuration in which M die logically share one enable pin. In this way, when the die 600 is applied to the flash memory chip 420, the number of enable pins of the flash memory chip 420 can be flexibly configured according to the application's requirements for the capacity of the NAND storage device 400 and the number of enable pins of the main control chip 410. This can reduce the packaging method of the flash memory chip 420 during production, thereby reducing the resources occupied for packaging reliability certification and test program development, reducing production costs, and improving production efficiency. For example, since there are fewer packaging methods for flash memory chips, it can help customers reduce import certification tests, reduce material control costs, and help customers reduce testing costs and improve production efficiency. In addition, during use, customers can meet different production needs by configuring the number of enable pins of the flash memory chip 420, which can improve customer satisfaction.

[0090] In one possible embodiment, as shown in FIG7 , the peripheral circuit 610 includes a control circuit 611 and a logic circuit 612, such as a register transfer level (RTL) logic circuit. The logic circuit 612 includes a trigger 6121, a first decoding circuit 6122, and a second decoding circuit 6123, which are coupled in sequence. It should be understood that in some examples, other peripheral circuits not shown in FIG7 may also be included, and the present disclosure is not limited thereto.

[0091] The control circuit 611 is configured to receive a control command and, based on the control command, generate and send the aforementioned indication information to a trigger 6121. The trigger 6121 is configured to receive the indication information and send the indication information to a first decoding circuit 6122. The first decoding circuit 6122 is configured to determine a first coded value of the die 600 based on the indication information. This first coded value may also be referred to as a multi-die stack (MDS) value. The second decoding circuit 6123 is configured to decode the first coded value to obtain the address of the die 600.

[0092] Optionally, the first coding value of the die 600 determined by the first decoding circuit 6122 according to the indication information may include a 4-bit coding value, an 8-bit coding value, or a coding value in other ways, which is not limited in the embodiment of the present disclosure.

[0093] For example, consider the case where die 600 is applied to the aforementioned flash memory chip 420, where the flash memory chip 420 includes eight die and the first encoding value includes a 4-bit encoding value. As shown in Table 1 below, when the indication information indicates that a die shares the same enable pin, the correspondence between the die and the enable pin in the flash memory chip 420 can be considered one-to-one. The first decoding circuit 6122 can determine, based on the indication information, that the first encoding value of die 600 is 4'b1111.

[0094] For another example, as shown in Table 1 below, when the indication information is used to indicate that two dies share the same enable pin, the correspondence between the dies and the enable pins in the flash memory chip 420 can be called a one-to-two relationship, and the first decoding circuit 6122 can determine the first coding value of the dies 600 as either 4'b1101 or 4'b1100 based on the indication information.

[0095] For another example, as shown in Table 1 below, when the indication information is used to indicate that four grains share the same enable pin, the correspondence between the grains and the enable pins in the flash memory chip 420 can be called one-to-four, and the first decoding circuit 6122 can determine the first coding value of the grain 600 to be any one of 4'b1011, 4'b1010, 4'b1001 or 4'b1000 based on the indication information.

[0096] For another example, as shown in Table 1 below, when the indication information is used to indicate that eight grains share the same enable pin, the correspondence between the grains and the enable pins in the flash memory chip 420 can be called one-to-eight, and the first decoding circuit 6122 can determine, based on the indication information, that the first coding value of the grain 600 is any one of 4'b0111, 4'b0110, 4'b0101, 4'b0100, 4'b0011, 4'b0010, 4'b0001, or 4'b1000.

[0097] Table 1

[0098]

[0099] Optionally, when the second decoding circuit 6123 decodes the first coding value to determine the address of the die 600, the address of the die 600 may include a 1-bit coding value, a 4-bit coding value, or a coding value in other ways, which is not limited in the embodiment of the present disclosure.

[0100] For example, taking the address of the die 600 as including a 1-bit code value, when the first code value is 4′b1111, the second decoding circuit 6123 may decode the first code value 4′b1111 to determine that the address of the die 600 is lun1.

[0101] The die 600 provided in the embodiment of the present disclosure receives and generates indication information through the control circuit 611, determines the first encoding value of the die 600 based on the indication information through the first decoding circuit 6122, and then decodes the first decoding value to determine the address of the die 600 by the second decoding circuit 6123, thereby realizing the logical configuration between M die and one enable pin. In this way, when the flash memory chip 420 uses the die 600, the number of enable pins of the flash memory chip 420 can be flexibly configured according to the application's requirements for the capacity of the NAND storage device 400 and the number of enable pins of the main control chip 410. This can reduce the packaging methods that need to be verified and tested for the flash memory chip 420 during production, thereby reducing production costs and improving production efficiency. For example, since there are fewer packaging methods for flash memory chips, it can help customers reduce import certification testing, reduce material control costs, and help customers reduce testing costs and improve production efficiency. In addition, during use, customers can meet different production needs by configuring the number of enable pins of the flash memory chip 420, which can improve customer satisfaction.

[0102] In a possible embodiment, as shown in FIG. 7 , the peripheral circuit 610 further includes a register 6124 , which is coupled to the first decoding circuit 6122 .

[0103] The first decoding circuit 6122 is further configured to set the first value in the register 6124 to a second value, where the first value is used to indicate that the encoding value of the die 600 is the second encoding value, and the second value is used to indicate that the encoding value of the die 600 is the first encoding value.

[0104] The first coding value is the coding value of the die 600 determined by the first decoding circuit 6122 according to the indication information, and the second coding value is a preset coding value of the die 600 .

[0105] Optionally, the first value may be 0 and the second value may be 1; or, the first value may be 1 and the second value may be 0. The embodiment of the present disclosure does not limit the specific values ​​of the first value and the second value.

[0106] For example, in the case where die 600 is applied to the aforementioned flash memory chip 420 and the indication information is used to indicate that two dies share the same enable pin, and the two dies include a first die and a second die, after the first decoding circuit 6122 in the first die determines that the first code value of the first die is 4b'1000 based on the indication information, the first decoding circuit 6122 may set the first value 0 in the register 6124 to the second value 1. Thus, the control circuit 611 in the second die may determine that the first decoding circuit 6122 in the first die has determined the first code value based on the second value 1 in the register 6124 in the first die, and determine that the first code value is 4b'1000. Furthermore, the control circuit 611 in the second die may control the first decoding circuit 6122 to determine that the first code value of the second die is 4b'1001. It can be understood that by setting register 6124 to different values ​​to indicate whether the first die has completed encoding, repeated encoding of the first die and the second die can be avoided, so as to prevent the first decoded values ​​of the first die and the second die from being decoded to the same address.

[0107] The chip 600 provided in the embodiment of the present disclosure sets the register 6124 to different values ​​through the first decoding circuit 6122 , so that when the chip 600 is applied to the flash memory chip 420 , repeated address encoding of multiple chips in the flash memory chip 420 can be avoided.

[0108] As shown in (a) of Figure 8, an embodiment of the present disclosure also provides a semiconductor packaging structure 800, which includes a packaging substrate 810, N grains 820 arranged on the packaging substrate 810, and a plurality of packaging pins arranged on the packaging substrate 810, the plurality of packaging pins including N enable pins 830, the N grains 820 are respectively coupled to one enable pin of the N enable pins 830, and the structure of the N grains 820 is the structure of the grain shown in Figure 6 or Figure 7.

[0109] The M grains among the N grains 820 are used to receive control commands sent by the main control chip 410. The control commands are used to instruct the M grains to determine their respective addresses. The address of each grain is used to address the enable signal provided by the enable pin. M is a positive integer greater than or equal to 1, N is a positive integer greater than or equal to 2, and M is less than or equal to N.

[0110] Optionally, the value of N may include any one of 2, 4 or 8, and the embodiment of the present disclosure does not limit the specific value of N.

[0111] For example, when the value of N is 2, the semiconductor package structure 800 is a double die package (DDP) having two stacked dies. When the value of N is 4, the semiconductor package structure 800 is a quaternary die package (QDP) having four stacked dies. When the value of N is 8, the semiconductor package structure 800 is an octal die package having eight stacked dies.

[0112] Optionally, the value of M may include 1, 2, 4, 8, 16 or 32, and the embodiment of the present disclosure does not limit the specific value of M.

[0113] Optionally, when the number of enable pins on the main control chip 410 is greater, the value of M is smaller; and when the number of enable pins on the main control chip 410 is smaller, the value of M is larger.

[0114] For example, let's assume that N dies 820 include 8 dies, and N enable pins 830 include 8 enable pins CE0 to CE8. When the number of enable pins on the main control chip 410 is 8, the value of M can be 1, as shown in (a) of FIG9 , where each die is coupled to one enable pin. When the number of enable pins on the main control chip 410 is 4, the value of M can be 2, as shown in (b) of FIG9 . In this case, the enable pins corresponding to every two of the 8 dies can be short-circuited together by routing on the printed circuit board, so that every two dies can share one enable pin on the main control chip 410. When the number of enable pins on the main control chip 410 is 2, the value of M can be 4, as shown in (c) of FIG9 . In this case, the enable pins corresponding to every four of the 8 dies can be short-circuited together by routing on the printed circuit board, so that every four dies can share one enable pin on the main control chip. It is understandable that, according to the number of enable pins on the main control chip 410 , the correspondence between the N dies 820 and the enable pins on the main control chip 410 can be flexibly configured by routing on the printed circuit board.

[0115] For another example, taking the N grains 820 including 2 grains and the value of M as 1, it can be understood that at this time, the two grains are respectively coupled to an enable pin on the main control chip 410, and the two grains can respectively receive the control command sent by the main control chip 410. The control command is used to instruct one grain to determine its respective address, so that the two grains can determine their respective addresses according to the control command.

[0116] Optionally, when M is greater than or equal to 2, the encoding values ​​of the M dies are different, so that the dies sharing the same enable pin can be distinguished by the different encoding values. Specifically, the different encoding values ​​of the M dies may include: the M dies having different first encoding values; further, the second decoding circuit 6123 in each die may decode the first decoding value to obtain a corresponding address; or, the encoding values ​​of the addresses of the M dies are different.

[0117] For example, referring to Table 1, assuming that N dies 820 include 8 dies, when the value of M is 2, every two dies in the 8 dies can receive control commands sent by the master control chip 410 and determine their respective first code values ​​based on the control commands. The first code values ​​of each 2 dies can be 4'b1101 and 4'b1100, respectively. Furthermore, the second decoding circuit 6123 in each dies can decode the corresponding first code value to obtain the corresponding address. When the value of M is 4, every four dies in the 8 dies can receive control commands sent by the master control chip 410 and determine their respective first code values ​​based on the control commands. The first code values ​​of each four dies can be 4'b1011, 4'b1010, 4'b1001, and 4'b1000, respectively. Furthermore, the second decoding circuit 6123 in each dies can decode the corresponding first decoding value to obtain the corresponding address.

[0118] For another example, taking N dies 820 including 8 dies as an example, in conjunction with (b) of FIG9 , when the value of M is 2, every two dies in the 8 dies can receive control commands sent by the main control chip 410 and determine their respective addresses based on the control commands. The addresses of every two dies can be lun0 and lun1, respectively. In conjunction with (c) of FIG9 , when the value of M is 4, every four dies in the 8 dies can receive control commands sent by the main control chip 410 and determine their respective addresses based on the control commands. The addresses of every four dies can be lun0, lun1, lun2, and lun3, respectively.

[0119] The M dies are further configured to send their respective addresses to the main control chip 410. Optionally, when the semiconductor package structure 800 is applied to the flash memory chip 420, the M dies sending their respective addresses includes: the M dies sending their respective addresses to the main control chip 410, so that the main control chip 410 can enable the corresponding dies through the enable pin shared by the M dies and the addresses of the M dies.

[0120] For example, as shown in FIG10(a), in a semiconductor package structure 800, N dies 820 include dies 0 to 7, N enable pins 830 include CE0 to CE7, the initial MDSs of the eight dies are all 4b'1111, and the eight dies are each coupled to an enable pin of the semiconductor package structure 800. As shown in FIG10(b), when the value of M is 4, the enable pins of every four of the eight dies can be shorted together on the printed circuit board, thereby physically achieving a configuration in which the four dies share one enable pin. The master control chip 410 can send control commands to die 0-3 and die 4-7 via a shared enable pin. Die 0-3 or die 4-7 can receive and, based on the control commands, determine the MDSs (first decoding values) of the four die: 4b'1011, 4b'1010, 4b'1001, and 4b'1000, respectively. Furthermore, the second decoding circuit 6123 in each of the four die can determine the address of each die based on the corresponding MDS and send it to the master control chip 410, thereby logically implementing a configuration in which the four die share a single enable pin. Furthermore, the master control chip 410 can enable any of die 0-3 using CE0 and the address of die 0-3, and can enable any of die 4-7 using CE4 and the address of die 4-7.

[0121] It can be understood that when the semiconductor packaging structure 800 provided in the embodiment of the present disclosure is applied to the above-mentioned flash memory chip 420, the M grains sharing the same enable pin among the N grains 820 receive control commands, determine their respective addresses according to the control commands, and send their respective addresses to the main control chip 410. The main control chip 410 can enable the corresponding grain through any grain address among the M grains.

[0122] Optionally, the N dies 820 may be coupled to the package substrate 810 by wire bonding, vertical wire bonding, through silicon via (TSV), or other methods. The disclosed embodiments do not limit how the N dies 820 are coupled to the package substrate 810.

[0123] Optionally, when the N die 820 are coupled with the packaging substrate 810, the N die 820 can adopt the same coupling method with the packaging substrate 810, or can adopt multiple coupling methods with the packaging substrate 810. The method of coupling with the packaging substrate 810 using multiple coupling methods can also be called a mixed bonding method. The embodiment of the present application does not limit the specific number of coupling methods used when coupling the N die 820 with the packaging substrate 810.

[0124] Wire bonding involves coupling any two of the N dies 820 or coupling a die to the package substrate 810 via a thin metal wire. Through-silicon via (TSV) technology involves penetrating the N dies 820 to achieve coupling between the N dies 820 and between the N dies 820 and the package substrate 810.

[0125] For example, as shown in FIG8(a), any two of the N dies 820 can be bonded via wires 840, thereby coupling the N dies 820 to the package substrate 810. Alternatively, as shown in FIG8(b), the N dies 820 can be coupled to the package substrate 810 via vertical wires 850. Alternatively, as shown in FIG8(c), any two of the N dies 820 can be coupled via through-silicon vias 860, thereby coupling the N dies 820 to the package substrate 810.

[0126] Optionally, the semiconductor package structure 800 may be packaged using BGA packaging technology, or may be packaged using thin small outline package (TSOP) technology. The embodiment of the present disclosure does not limit the specific packaging technology used by the semiconductor package structure 800.

[0127] Optionally, the specific value of M is negatively correlated with the number of the plurality of package pins on the semiconductor package structure 800. Specifically, when the number of the plurality of package pins is greater, the specific value of M is smaller, and when the number of the plurality of package pins is smaller, the specific value of M is larger.

[0128] For example, when the semiconductor package structure 800 is a BGA132 / BGA154 ODP package, the value of M may include 1, 2, or 4. In this case, the number of enable pins of the semiconductor package structure 800 for receiving the enable signal includes 8, 4, or 2. When the semiconductor package structure 800 is a BGA272 ODP package, the semiconductor package structure 800 includes more package pins compared to when the semiconductor package structure 800 is a BGA132 / BGA154 ODP package. In this case, the value of M may include 1 or 2. In this case, the number of enable pins of the semiconductor package structure 800 for receiving the enable signal includes 8 and 4.

[0129] Based on this, as exemplarily shown in Tables 2 and 3 below, the embodiment of the present disclosure also provides packaging modes that can be supported by the semiconductor packaging structure 800, as well as possible values ​​of the number of enable pins for receiving enable signals in each packaging mode.

[0130] Table 2

[0131]

[0132] Table 3

[0133]

[0134]

[0135] It should be noted that the descriptions related to the die 600 in the above embodiments can be correspondingly referred to in the embodiments of the semiconductor package structure 800 , and the embodiments of the present disclosure will not be repeated here.

[0136] In the semiconductor package structure 800 provided by the embodiment of the present disclosure, M grains sharing the same enable pin receive and determine their respective addresses according to the control command, and then send their respective addresses, so as to achieve the configuration of logically M grains sharing one enable pin. In this way, when the semiconductor package structure 800 is applied to the flash memory chip 420, the number of enable pins of the flash memory chip 420 can be flexibly configured according to the application's requirements for the capacity of the NAND storage device 400 and the number of enable pins of the main control chip 410, thereby reducing the packaging method of the flash memory chip 420 during production, thereby reducing the occupied packaging reliability certification resources and test program development resources, reducing production costs, and improving production efficiency. For example, since there are fewer packaging methods for flash memory chips, it can help customers reduce import certification tests, reduce material control costs, and help customers reduce testing costs and improve production efficiency. In addition, during use, customers can meet different production needs by configuring the number of enable pins of the flash memory chip 420, which can improve customer satisfaction.

[0137] In a possible embodiment, the M dies include a target die, which is used to receive a chip select signal, which is used to select the target die to receive an enable signal, and the chip select signal includes an address of the target die.

[0138] Optionally, the target grain may be any one of the M grains, and the embodiment of the present disclosure does not limit which one of the M grains the target grain is.

[0139] Optionally, when the semiconductor package structure 800 is applied to the above-mentioned flash memory chip 420 , the target die receives the chip select signal, including: receiving the chip select signal sent by the main control chip 410 .

[0140] For example, with reference to FIG10(b), assuming that the value of M is 4, the four dies include target die 0, and the address of die 0 is lun0, target die 0 can receive a chip select signal sent by the master control chip 410. The chip select signal can include the address lun0 of die 0, so that the chip select signal can select die 0, so that die 0 can receive the enable signal sent by the master control chip 410 via the enable pin CE0.

[0141] In the semiconductor package structure 800 provided by the embodiment of the present disclosure, a target die among M dies receives a chip select signal including the target die address, so the target die can be selected through the chip select signal, and the target die can receive an enable signal.

[0142] As shown in FIG. 11 , an embodiment of the present disclosure further provides a method for configuring enable pins of a die, which can be applied to the above-mentioned die 600 . The method includes steps S1101 to S1102 .

[0143] S1101: The peripheral circuit 610 receives a control command and generates instruction information according to the control command, wherein the control command is used to instruct the die 600 to determine the address of the die 600, and the instruction information is used to instruct M dies to share the same enable pin, where M is a positive integer greater than or equal to 1.

[0144] Optionally, the die 600 may be any one of the M die, which is not limited in the embodiment of the present disclosure.

[0145] Optionally, the value of M includes: 1, 2, 4, 8, 16 or 32. The embodiment of the present disclosure does not limit the specific value of M.

[0146] In a possible embodiment, the peripheral circuit 610 includes a control circuit 611. The peripheral circuit 610 receives a control command and generates indication information according to the control command, including: the control circuit 611 receives a control command and generates and sends indication information according to the control command.

[0147] S1102 : The peripheral circuit 610 determines the address of the die 600 according to the indication information, and sends the address of the die 600 , which is used for addressing of the enable signal provided by the enable pin.

[0148] Optionally, the address coding value of the die 600 may include 1 bit, or may include more bits. The embodiment of the present application does not limit the number of bits used to encode the specific address coding value of the die 600.

[0149] In one possible embodiment, the peripheral circuit 610 further includes a logic circuit 612, which includes a trigger 6121, a first decoding circuit 6122, and a second decoding circuit 6123 coupled in sequence. Determining the address of the die 600 based on the indication information includes: the trigger 6121 receiving the indication information and sending the indication information to the first decoding circuit 6122. The first decoding circuit 6122 determines a first code value of the die 600 based on the indication information. The second decoding circuit 6123 decodes the first code value to obtain the address of the die 600.

[0150] Optionally, the first decoding circuit 6122 determines, based on the indication information, that the first coding value of the die 600 includes a 4-bit coding value, an 8-bit coding value, or a coding value in other ways, which is not limited in the embodiment of the present disclosure.

[0151] Optionally, when the second decoding circuit 6123 decodes the first coding value to determine the address of the die 600, the address of the die 600 may include a 1-bit coding value, a 4-bit coding value, or a coding value in other ways, which is not limited in the embodiment of the present disclosure.

[0152] The method for configuring the enable pins of a die provided in the embodiments of the present disclosure receives a control command and generates indication information through the peripheral circuit 610, and determines the address of the die 600 based on the indication information, thereby achieving a configuration in which M die logically share a single enable pin. Thus, when the die 600 is applied to the flash memory chip 420, the number of enable pins of the flash memory chip 420 can be flexibly configured based on the application's requirements for the capacity of the NAND storage device 400 and the number of enable pins of the main control chip 410. This can reduce the number of packaging methods for the flash memory chip 420 during production, thereby reducing the resources required for packaging reliability certification and test program development, reducing production costs, and improving production efficiency.

[0153] In a possible embodiment, the peripheral circuit 610 further includes a register 6124 , which is coupled to the first decoding circuit 6122 . Furthermore, as shown in FIG. 12 , after the above step S1102 , the method may further include step S1103 .

[0154] S1103 , the first decoding circuit 6122 sets the first value in the register 6124 to the second value, where the first value is used to indicate that the encoding value of the die 600 is the second encoding value, and the second value is used to indicate that the encoding value of the die 600 is the first encoding value.

[0155] The first code value is the code value of the die 600 determined by the first decoding circuit 6122 according to the indication information, and the second code value is the code value of the die 600 before the first decoding circuit 6122 determines the first code value according to the indication information.

[0156] Optionally, the first value may be 0 and the second value may be 1; or, the first value may be 1 and the second value may be 0. The embodiment of the present disclosure does not limit the specific values ​​of the first value and the second value.

[0157] It should be noted that the relevant descriptions about the die 600 in the above embodiments can be referred to in the embodiments of the method for configuring the enable pins of the die, and will not be repeated herein in the embodiments of the present disclosure.

[0158] The embodiment of the present disclosure provides a method for configuring the enable pins of the die, which sets the register 6124 to different values ​​through the first decoding circuit 6122, so that when the die 600 is applied to the flash memory chip 420, the address duplication encoding of multiple die in the flash memory chip 420 can be avoided.

[0159] As shown in Figure 13, an embodiment of the present disclosure also provides an enable pin configuration method for a semiconductor packaging structure, which can be applied to the above-mentioned semiconductor packaging structure 800 including N grains 820, any one of the N grains 820 includes a peripheral circuit 610, and the method includes steps S1301 to S1302.

[0160] S1301: The peripheral circuit 610 receives a control command and generates instruction information according to the control command, wherein the control command is used to instruct the die 600 to determine the address of the die 600, and the instruction information is used to instruct M dies to share the same enable pin, where M is a positive integer greater than or equal to 1.

[0161] Optionally, the value of N may include any one of 2, 4 or 8, and the embodiment of the present disclosure does not limit the specific value of N.

[0162] Optionally, the value of M may include 1, 2, 4, 8, 16 or 32. The embodiment of the present disclosure does not limit the specific value of M.

[0163] Optionally, when M is greater than or equal to 2, the coding values ​​of the M dies are different, so that the dies that share the same enable pin can be distinguished by different coding values.

[0164] In a possible embodiment, the peripheral circuit 610 includes a control circuit 611. The peripheral circuit 610 receives a control command and generates indication information according to the control command, including: the control circuit 611 receives a control command and generates and sends indication information according to the control command.

[0165] S1302 : The peripheral circuit 610 determines the address of the die 600 according to the indication information, and sends the address of the die 600 , which is used for addressing of the enable signal provided by the enable pin.

[0166] Optionally, the address coding value of the die 600 may include 1 bit, or may include more bits. The embodiment of the present application does not limit the number of bits used to encode the specific address coding value of the die 600.

[0167] In one possible embodiment, the peripheral circuit 610 further includes a trigger 6121, a first decoding circuit 6122, and a second decoding circuit 6123 coupled in sequence. Determining the address of the die 600 based on the indication information includes: the trigger 6121 receiving the indication information and sending the indication information to the first decoding circuit 6122. The first decoding circuit 6122 determines a first code value of the die 600 based on the indication information. The second decoding circuit 6123 decodes the first code value to obtain the address of the die 600.

[0168] Optionally, the first decoding circuit 6122 determines, based on the indication information, that the first coding value of the die 600 includes a 4-bit coding value, an 8-bit coding value, or a coding value in other ways, which is not limited in the embodiment of the present disclosure.

[0169] Optionally, when the second decoding circuit 6123 decodes the first coding value to determine the address of the die 600, the address of the die 600 may include a 1-bit coding value, a 4-bit coding value, or a coding value in other ways, which is not limited in the embodiment of the present disclosure.

[0170] The enable pin configuration method for a semiconductor package structure provided by the embodiments of the present disclosure receives a control command and generates indication information through the peripheral circuit 610, determines and sends the address of the die 600 based on the indication information, thereby achieving a configuration in which M die logically share a single enable pin. Thus, when the die 600 is applied to a flash memory chip 420, the number of enable pins of the flash memory chip 420 can be flexibly configured based on the application's requirements for the capacity of the NAND storage device 400 and the number of enable pins of the main control chip 410. This reduces the number of packaging methods for the flash memory chip 420 during production, thereby reducing the resources required for package reliability certification and test program development, reducing production costs, and improving production efficiency.

[0171] In a possible embodiment, the peripheral circuit 610 further includes a register 6124, and the register 6124 is coupled to the first decoding circuit 6122. Furthermore, as shown in FIG13 , after the above step S1302, the method may further include step S1303.

[0172] S1303 , the first decoding circuit 6122 sets the first value in the register 6124 to the second value, where the first value is used to indicate that the encoding value of the die 600 is the second encoding value, and the second value is used to indicate that the encoding value of the die 600 is the first encoding value.

[0173] The first code value is the code value of the die 600 determined by the first decoding circuit 6122 according to the indication information, and the second code value is the code value of the die 600 before the first decoding circuit 6122 determines the first code value according to the indication information.

[0174] Optionally, the first value may be 0 and the second value may be 1; or, the first value may be 1 and the second value may be 0. The embodiment of the present disclosure does not limit the specific values ​​of the first value and the second value.

[0175] The enable pin configuration method of the semiconductor package structure provided by the embodiment of the present disclosure sets the register 6124 to different values ​​through the first decoding circuit 6122, so that when the grain 600 is applied to the flash memory chip 420, the address duplication encoding of multiple grains in the flash memory chip 420 can be avoided.

[0176] In a possible embodiment, the M dies in the semiconductor package structure 800 include a target die. Furthermore, as shown in FIG13 , after the above step S1303 , the method further includes step S1304 .

[0177] S1304 , the peripheral circuit 610 in the target die receives a chip select signal, where the chip select signal is used to select the target die to receive an enable signal, and the chip select signal includes the address of the target die.

[0178] Optionally, the target grain may be any one of the M grains, and the embodiment of the present disclosure does not limit which one of the M grains the target grain is.

[0179] It should be noted that the relevant descriptions about the semiconductor package structure 800 in the above embodiments can be referred to in the embodiments of the enable pin configuration method of the semiconductor package structure, and the embodiments of the present disclosure will not be repeated here.

[0180] According to the enable pin configuration method of the semiconductor packaging structure provided by the embodiment of the present disclosure, a target die among M die receives a chip select signal including the address of the target die, so that the target die can be selected by the chip select signal and the target die can receive the enable signal.

[0181] The present disclosure also provides a memory including a semiconductor package structure 800 as shown in Figures 5 to 7. For example, the memory may be the NAND memory 122 shown in Figure 1 or Figure 2 in the above examples.

[0182] The present disclosure also provides a storage system including a controller and at least one memory coupled to the controller, wherein the controller is configured to control the memory to read data, and the memory has a structure as shown in FIG11 . For example, the storage system may be the storage system 120 shown in FIG1 or FIG2 in the aforementioned example.

[0183] For another example, the storage system may be the NAND storage device 400 shown in FIG. 4 , the controller may be the main control chip 410 , and the at least one memory may be the flash memory chip 420 .

[0184] The present disclosure also provides an electronic device including a storage system and a processor coupled to the storage system. For example, the electronic device may be the electronic device shown in FIG1 in the aforementioned example.

[0185] It should be noted that the descriptions of the die 600 and the semiconductor package structure 800 in the above embodiments can be correspondingly referred to in the embodiments of the memory, storage system and electronic device, and will not be repeated herein in the embodiments of the present disclosure.

[0186] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present disclosure shall be covered by the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure shall be based on the scope of protection of the claims.

Claims

1. A crystal grain, characterized in that: The die includes peripheral circuitry configured to: receiving a control command and generating instruction information according to the control command, wherein the control command is used to instruct the die to determine the address of the die, and the instruction information is used to instruct M die to share the same enable pin, where M is a positive integer greater than or equal to 1; The address of the die is determined according to the indication information, and the address of the die is sent, where the address is used for addressing the enable signal provided by the enable pin.

2. The crystal grain according to claim 1, characterized in that The peripheral circuit includes: a control circuit, and a trigger, a first decoding circuit and a second decoding circuit coupled in sequence; The control circuit is configured to receive the control command, and generate and send the indication information according to the control command; The trigger is configured to receive the indication information and send the indication information to the first decoding circuit; The first decoding circuit is configured to determine a first coding value of the die according to the indication information; The second decoding circuit is configured to decode the first coding value to obtain the address of the die.

3. The crystal grain according to claim 2, characterized in that The peripheral circuit further includes a register, and the register is coupled to the first decoding circuit; The first decoding circuit is further configured to set the first value in the register to a second value, wherein the first value is used to indicate that the coding value of the grain is the second coding value, and the second value is used to indicate that the coding value of the grain is the first coding value.

4. The crystal grain according to claim 3, characterized in that The value of M includes: 1, 2, 4, 8, 16 or 32.

5. A semiconductor packaging structure, characterized in that: The semiconductor package structure comprises N dies according to any one of claims 1 to 4; M of the N die are configured to receive a control command, wherein the control command is configured to instruct the M die to determine respective addresses, wherein the addresses are configured to address an enable signal provided by the enable pin, where M is a positive integer greater than or equal to 1, N is a positive integer greater than or equal to 2, and M is less than or equal to N; The M grains are also used to send their respective addresses.

6. The semiconductor package structure according to claim 5, wherein: When M is greater than or equal to 2, the code values ​​of the M grains are different.

7. The semiconductor package structure according to claim 5 or 6, wherein: The M grains include the target grain; wherein, The target die is used to receive a chip select signal, where the chip select signal is used to select the target die to receive the enable signal. The chip select signal includes the address of the target die.

8. A method for configuring the enable pins of a die, characterized in that: The die includes peripheral circuits, and the method includes: The peripheral circuit receives a control command and generates instruction information according to the control command, wherein the control command is used to instruct the die to determine the address of the die, and the instruction information is used to instruct M die to share the same enable pin, where M is a positive integer greater than or equal to 1; The peripheral circuit determines the address of the die according to the indication information and sends the address of the die, where the address is used for addressing the enable signal provided by the enable pin.

9. The method according to claim 8, characterized in that The peripheral circuit includes: a control circuit, and a trigger, a first decoding circuit, and a second decoding circuit coupled in sequence. The method further includes: The control circuit receives the control command, and generates and sends the instruction information according to the control command; The trigger receives the indication information and sends the indication information to the first decoding circuit; The first decoding circuit determines a first coding value of the die according to the indication information; The second decoding circuit decodes the first coding value to obtain the address of the die.

10. The method according to claim 9, characterized in that The peripheral circuit further includes a register coupled to the first decoding circuit. The method further includes: The first decoding circuit sets the first value in the register to a second value, wherein the first value is used to indicate that the encoding value of the grain is the second encoding value, and the second value is used to indicate that the encoding value of the grain is the first encoding value.

11. The method according to claim 10, characterized in that The value of M includes: 1, 2, 4, 8, 16 or 32.

12. A method for configuring enable pins of a semiconductor package structure, characterized in that: The semiconductor package structure includes N dies, any one of the N dies includes a peripheral circuit, N is a positive integer greater than or equal to 2, and the method includes: The peripheral circuit receives a control command and generates instruction information according to the control command, wherein the control command is used to instruct the die to determine the address of the die, and the instruction information is used to instruct M die to share the same enable pin, where M is a positive integer greater than or equal to 1; The peripheral circuit determines the address of the die according to the indication information and sends the address of the die, where the address is used for addressing the enable signal provided by the enable pin.

13. The method according to claim 12, characterized in that The peripheral circuit includes a control circuit, and a trigger, a first decoding circuit, and a second decoding circuit coupled in sequence. The method further includes: The control circuit receives the control command, and generates and sends the instruction information according to the control command; The trigger receives the indication information and sends the indication information to the first decoding circuit; The first decoding circuit determines a first coding value of the die according to the indication information; The second decoding circuit decodes the first coding value to obtain the address of the die.

14. The method according to claim 13, characterized in that The peripheral circuit further includes a register coupled to the first decoding circuit. The method further includes: The first decoding circuit sets the first value in the register to a second value, wherein the first value is used to indicate that the encoding value of the grain is the second encoding value, and the second value is used to indicate that the encoding value of the grain is the first encoding value.

15. The method according to claim 14, characterized in that The value of M includes: 1, 2, 4, 8, 16 or 32.

16. The method according to claim 15, characterized in that When M is greater than or equal to 2, the code values ​​of the M grains are different.

17. The method according to claim 15 or 16, characterized in that The M grains include a target grain, and the method further includes: The peripheral circuit in the target die receives a chip select signal, where the chip select signal is used to select the target die to receive the enable signal, and the chip select signal includes an address of the target die.

18. A memory, characterized in that: The memory includes the semiconductor package structure according to any one of claims 5 to 7.

19. A storage system, characterized in that: The storage system includes a controller and at least one memory coupled to the controller, wherein the controller is configured to control the memory to read data, and the memory is the memory according to claim 18.

20. An electronic device, characterized in that: The electronic device comprises the storage system according to claim 19.

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