N-polar III-nitride device structure with p-type layer

Abstract

An N-polarity III-N high electron mobility transistor device may include a III-N channel layer on an N-side of a III-N back barrier, where a compositional difference between the channel layer and the back barrier is such that a 2DEG channel is induced in the III-N channel layer adjacent to an interface between the III-N channel layer and the back barrier. The device may further include a p-type III-N layer on the III-N channel layer and a thick III-N cap layer on the p-type III-N layer. The III-N cap layer may cause an increase in charge density of the 2DEG channel directly below the cap layer, and the p-type III-N layer may be used to prevent parasitic 2DEG formation in the III-N cap layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor material structures and devices, and in particular to devices formed from N-polar Group III-nitride layers. Background Art

[0002] III-N nitride semiconductor devices, such as III-N high electron mobility transistors (HEMTs), are typically formed from a III-N material structure grown on a substrate in a III-polar orientation (i.e., in the [0 0 0 1] direction). An example III-polar III-N HEMT device 100 is shown in FIG. 1 . In device 100 , III-N layers 111 , 112 , and 113 are formed on a suitable substrate 110 , such as silicon (Si), silicon carbide (SiC), sapphire, or GaN, in a III-polar orientation (i.e., in the [0 0 0 1] direction, as shown). III-N layer 111 is a buffer layer and may be formed of AlN, AlGaN, GaN, or a combination thereof. III-N layer 112 is a channel layer, such as GaN. III-N layer 113 is a barrier layer, such as AlGaN. The compositions of the III-N layers 112 and 113 are selected such that a two-dimensional electron gas (2DEG) channel 120 is induced in the III-N channel layer 112 that extends from the source 121 to the drain 122. A gate insulator 132 is formed on the III-N barrier layer 113, and a gate 123 is formed on the gate insulator 132. A voltage applied to the gate 123 relative to the source 121 modulates the charge in the 2DEG 120 directly beneath the gate 123, thereby modulating the current flowing between the source 121 and the drain 122 during device operation.

[0003] A nitrogen-polar (N-polar) III-N HEMT device 200 (i.e., a device in which III-N layers 211, 213, and 212 are oriented in the [0 0 0 -1] direction on substrate 210) is shown in FIG2. In device 200, a III-N channel layer 212 (i.e., a layer containing a 2DEG channel 220) is formed on a III-N barrier layer 213 (thus, in an N-polar III-N HEMT, the barrier layer is often referred to as a "back barrier"). A gate insulator 232 may be used to reduce gate leakage, which may otherwise be more persistent in an N-polar device than in a III-polar device because the III-N barrier layer (e.g., layer 213) is not between the gate 223 and the channel in an N-polar device. In many cases, an N-polar III-N device such as device 200 may have lower contact resistance (e.g., at source contact 221 and drain contact 222, respectively) than a III-polar III-N device such as device 100. However, other challenges in N-polar III-N technology still continue to exist. Summary of the invention

[0004] In a first aspect, a semiconductor device includes a III-N back barrier, the III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer. The device also includes a III-N channel layer on an N-face of the first III-N layer, a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer, a p-type III-N layer on an N-face of the III-N channel layer, and a III-N cap layer on an N-face of the p-type III-N layer. The III-N channel layer and the III-N cap layer each have a band gap that is smaller than a band gap of the first III-N layer.

[0005] In a second aspect, a semiconductor device includes a III-N back barrier, the III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer. The device also includes a III-N channel layer on an N-face of the first III-N layer, a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer, a p-type III-N layer on an N-face of the III-N channel layer, and a III-N cap layer on an N-face of the p-type III-N layer. Adjacent to the interface between the III-N channel layer and the first III-N layer, a conduction band energy of the first III-N layer is greater than a conduction band energy of the III-N channel layer.

[0006] In a third aspect, a semiconductor device includes a III-N back barrier, the III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer. The device also includes a III-N channel layer on an N-face of the first III-N layer, wherein the first III-N layer has a larger bandgap than the III-N channel layer. The device further includes a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer, a p-type III-N layer on the N-face of the III-N channel layer, and an n-type III-N layer between the III-N channel layer and the p-type III-N layer.

[0007] In a fourth aspect, a semiconductor device includes a III-N back barrier, the III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer. The device also includes a III-N channel layer on the N-face of the first III-N layer, the III-N channel layer including a gate region and a plurality of proximity regions on the opposite side of the gate region. The device further includes a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer, a III-N barrier layer on the N-face of the III-N channel layer, a III-N cap layer on the N-face of the III-N barrier layer, and a p-type III-N layer. The III-N channel layer and the III-N cap layer each have a band gap smaller than the band gaps of both the first III-N layer and the III-N barrier layer, and both the III-N barrier layer and the III-N cap layer are on the proximity region of the III-N channel layer, but not on the gate region of the III-N channel layer.

[0008] Any of the devices described herein may include one or more of the following features, each individually or in combination with one another. The band gap of the p-type III-N layer may be smaller than the band gap of the first III-N layer. The thickness of the III-N channel layer may be greater than the thickness of the p-type III-N layer. The thickness of the III-N cap layer may be greater than the thickness of the III-N channel layer. The device may further include a III-N barrier layer between the III-N channel layer and the p-type III-N layer, wherein the band gaps of the III-N channel layer and the p-type III-N layer are each smaller than the band gap of the III-N barrier layer. The device may further include an n-type III-N layer between the III-N channel layer and the p-type III-N layer. The n-type III-N layer may be doped with a concentration of at least 10 16 cm -3The p-type III-N layer may be a first p-type III-N layer, and the semiconductor device may further include a second p-type III-N layer and a III-N barrier layer, and wherein the III-N barrier layer is between the first p-type layer and the second p-type layer. The band gaps of the III-N channel layer, the n-type III-N layer, the first p-type III-N layer and the second p-type III-N layer, and the III-N cap layer may each be smaller than the band gap of the III-N barrier layer. The III-N channel layer may include a gate region and a plurality of proximity regions on opposite sides of the gate region, the semiconductor device may further include a source contact, a drain contact, and a gate contact, and the gate contact may be on the gate region of the III-N channel layer. The III-N cap layer may be on the proximity region of the III-N channel layer, but not on the gate region of the III-N channel layer. The device may further include a plurality of contacts on the N-face of the III-N channel layer, the plurality of contacts including a source contact, a gate contact, and a drain contact. The III-N channel layer may include a gate region and a plurality of proximity regions on opposite sides of the gate region, wherein the III-N capping layer is on the proximity regions of the III-N channel layer but not on the gate region of the III-N channel layer, and the gate contact is on the gate region of the III-N channel layer. The device may further include a gate insulator between the gate contact and the III-N channel layer. The thickness of the p-type III-N layer may be less than 8 nm, and the concentration of acceptors in the p-type III-N layer may be greater than 10 18 cm -3 The acceptor concentration in the p-type III-N layer may be less than the donor concentration in the n-type III-N layer. The donor concentration in the n-type III-N layer may be at least 10 16 cm -3 The device may further include a gate contact on a gate region of the III-N channel layer, wherein the p-type III-N layer is between the gate contact and the III-N channel layer. The p-type III-N layer may directly contact the III-N channel layer, the III-N barrier layer, and the III-N cap layer.

[0009] In another aspect, a method of forming a semiconductor device includes forming a III-N back barrier on a substrate, the III-N back barrier having a III-group face proximal to the substrate and an N-face opposite to the III-group face, wherein the III-N back barrier includes one or more III-N layers, and the one or more III-N layers of the III-N back barrier include a first III-N layer. The method also includes forming a III-N channel layer on the N-face of the first III-N layer, forming a p-type III-N layer on the N-face of the III-N channel layer, and forming a III-N cap layer on the N-face of the p-type III-N layer. The III-N channel layer and the III-N cap layer may each have a band gap that is smaller than a band gap of the first III-N layer. In addition, the semiconductor device may include a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer.

[0010] Any of the methods described herein may each individually or in combination with one another include one or more of the following features. The method may include forming a recess through the entire thickness of the III-N cap layer in a gate region of the semiconductor device, and depositing a gate contact on the gate region of the semiconductor device. The recess may extend through the entire thickness of the p-type III-N layer. The method may further include forming a III-N barrier layer between the III-N channel layer and the p-type III-N layer. The method may further include forming a gate insulator between the III-N barrier layer and the gate contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is a cross-sectional view of a Group III polarity III-N transistor device.

[0012] FIG. 2 is a cross-sectional view of an N-polar III-N transistor device.

[0013] Figure 3-5 are cross-sectional views of various implementations of N-polar III-N transistor devices.

[0014] Figure 6 yes Figure 5 Cross-sectional view of a portion of an N-polarity III-N transistor device.

[0015] Figure 7 is a cross-sectional view of another embodiment of an N-polar III-N transistor device.

[0016] Figure 8 Graphical Formation Figure 7 A method for a transistor device.

[0017] Figure 9-12 is a cross-sectional view of another embodiment of an N-polar III-N transistor device.

[0018] Figures 13A-13F Graphical Formation Fig.12 A method for a transistor device.

[0019] Figure 14-15 is a cross-sectional view of another embodiment of an N-polar III-N transistor device.

[0020] Like numbers in the drawings represent like elements. DETAILED DESCRIPTION

[0021] N-polarity III-nitride semiconductor devices suitable for a wide variety of applications, including RF electronics and power conversion, are described herein. The devices each include a p-type III-N layer configured to address various issues in device performance that might otherwise occur. As used herein, the term III-nitride or III-N material, layer, device, etc. refers to a device composed of a p-type III-N layer and a p-type III-N layer according to the stoichiometric formula Sc v B w Al x In y Ga z N a (D) b A material or device composed of a compound semiconductor material of the invention, wherein v+w+x+y+z is approximately 1, 0≤v≤1, 0≤w≤1, 0≤x≤1, 0≤y≤1, 0≤z≤1, a+b is approximately 1, 0.9≤a≤1, 0≤b≤0.1, and (D) is any Group V element except nitrogen. In a III-N transistor device, the channel through which current is conducted may be contained within one or more III-N layers of the device.

[0022] Figure 3 3 is a cross-sectional view of an example N-polar III-N semiconductor device 300. Device 300 includes a substrate 310 and a plurality of III-N layers 311, 313, and 312 formed on substrate 310 in an N-polar orientation (i.e., in the [0 0 0 -1] direction, as shown). Substrate 310 may be any substrate suitable for epitaxially growing III-N layers thereon, such as silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), or sapphire (Al2O3). III-N layer 311 is a buffer layer and may be formed of AlN, AlGaN, GaN, or a combination thereof. III-N layer 313 formed on the N-face of III-N buffer layer 311 serves as a back barrier. III-N layer 312 formed on the N-face of III-N back barrier 313 serves as a channel layer.

[0023] The compositions of the III-N back barrier 313 and the III-N channel layer 312 are selected such that a two-dimensional electron gas (2DEG) channel 320 is induced in the III-N channel layer 312 adjacent to the interface between the III-N channel layer 312 and the III-N back barrier 313. To induce the 2DEG channel 320, the compositions of the III-N layers 312 and 313 may be selected such that adjacent to the interface between the layers 312 and 313, the conduction band energy in the III-N back barrier 313 is greater than the conduction band energy in the III-N channel layer 312. That is, at the interface between the III-N layers 312 and 313, the conduction band energy may be discontinuous, wherein the conduction band energy on the back barrier side of the interface is greater than the conduction band energy on the channel layer side of the interface. Such conduction band energy discontinuity may typically be achieved by selecting a material for the III-N channel layer 312 that has a smaller band gap than the band gap of the III-N back barrier 313. For example, the III-N channel layer 312 may be formed of GaN, and the III-N back barrier may be formed of Al x Ga 1-x N is formed, wherein the aluminum fraction composition x may be in the range of 0.2≤x≤0.4.

[0024] The III-N back barrier 313 may be formed as a single III-N layer or as a plurality of III-N layers. Figure 3 Embodiment 300 of the device Figure 4 , the III-N back barrier 313 may include a first III-N layer 441 and a second III-N layer 442. In the case where the III-N back barrier 313 is formed as a single layer, the entire III-N back barrier 313 is implemented as the first III-N layer. In the case where the III-N back barrier 313 is formed as a plurality of III-N layers, the first III-N layer 441 may be adjacent to the III-N channel layer 312 and may directly contact the III-N channel layer 312, such that the 2DEG channel 320 is adjacent to the interface between the III-N channel layer 312 and the first III-N layer 441 of the III-N back barrier 313. In this case, the first III-N layer 441 may have a band gap greater than the band gap of the III-N channel layer 312. In some embodiments, the first III-N layer 441 is formed of AlN.

[0025] The device 300 further includes a III-N barrier layer 314 on the N-face of the III-N channel layer 312. The III-N barrier layer 314 may be formed of a material having a larger band gap than the band gap of the III-N channel layer 312. For example, when the III-N channel layer 312 is formed of GaN, the III-N barrier layer 314 may be formed of Al. y Ga1-y N is formed, where the aluminum fraction composition y can be in the range of 0.1≤y≤0.6. The III-N barrier layer 314 can be used to reduce gate leakage in the device and increase the device breakdown voltage. However, the III-N barrier layer 314 can also cause a reduction in the charge density of the 2DEG channel 320 due to the polarization of the layer. In order to minimize this reduction in charge density, the III-N barrier layer 314 can be made thin, for example, less than 10nm, less than 8nm, less than 5nm, or less than 3nm thick.

[0026] The device 300 also includes a source contact 321 and a drain contact 322, respectively, and a gate contact 323 between the source contact and the drain contact. A gate insulator 332 is optionally included between the gate contact 323 and the underlying III-N material to reduce gate leakage during device operation. A voltage applied to the gate contact 323 relative to the source contact 321 modulates the charge in the 2DEG 320 in the gate region of the device, thereby modulating the current flowing between the source contact 321 and the drain contact 322 during device operation. The source contact 321 and the drain contact 322 are each electrically connected to the 2DEG channel 320. As used herein, two or more contacts or other objects (such as conductive layers or components) are referred to as "electrically connected" if they are connected by a material having sufficient conductivity to ensure that the potential at each of the contacts or other objects is intended to be the same, i.e., substantially the same, at all times under any bias conditions. As used herein, the "gate region" of a device or the "gate region" of one or more layers of a device refers to the region containing the portion of the 2DEG channel modulated by the gate contact, which is typically directly below the gate contact. As used herein, the "contact region" of a device or the "contact region" of one or more layers of a device is the region directly below the source contact and the drain contact. As used herein, the "proximity region" of a device or the "proximity region" of one or more layers of a device is the region between the gate region and the contact region. The proximity region between the source contact and the gate region is typically referred to as the source proximity region, and the proximity region between the drain contact and the gate region is typically referred to as the gate proximity region.

[0027] Figure 5 5 is a cross-sectional view of another example N-polarity III-N semiconductor device 500. The device 500 includes a substrate 510, a III-N buffer layer 511, a III-N back barrier 513, a III-N channel layer 512, and a III-N barrier layer 514. The substrate 510 and the III-N layers 511, 513, 512, and 514 may be respectively Figure 3310, 311, 313, 312, and 314 of the device 300 are similar or identical. Similar to other devices described herein, the composition of the III-N back barrier 513 and the III-N channel layer 512 is selected so that a 2DEG channel 520 is induced in the III-N channel layer 512 adjacent to the interface between the III-N channel layer 512 and the III-N back barrier 513. The source contact 521 and the drain contact 522 are respectively formed on the regrown III-N n-type region 516, which has sufficient conductivity to electrically connect the source contact and the drain contact to the 2DEG channel 520. However, the source contact 521 and the drain contact 522 may respectively alternatively directly contact the 2DEG channel 520, as in the device 300.

[0028] Device 500 is similar to Figure 3 The device 300 of FIG. 5 is a device of the type shown in FIG. 5 , but further includes a thick III-N capping layer 515 on the proximity regions of the III-N layers 511, 513, 512, and 514. The III-N capping layer 515 may be formed by first depositing the material of the III-N capping layer as a single layer, and then etching through the entire thickness of the III-N capping layer over the gate region and contact regions of the device 500, thereby leaving the material of the III-N capping layer only on the proximity regions. A gate insulator 532 is conformally deposited in a recess formed in the III-N capping layer 515 over the gate region of the device. The gate insulator 532 may optionally extend over the upper surface of the III-N capping layer 515, as shown. A gate contact 523 is formed on the gate insulator 532 over the gate region of the device in the recess formed through the III-N capping layer 515.

[0029] The III-N capping layer 515 may have a band gap smaller than the band gap of the III-N back barrier 513 or smaller than the band gap of the first III-N layer of the III-N back barrier 513. For example, when the III-N back barrier 513 (or the first III-N layer of the III-N back barrier 513) is composed of Al x Ga 1-x When the III-N barrier layer 514 is formed of Al(0.2≤x≤0.4), the III-N cap layer 515 may be formed of GaN. The III-N cap layer 515 may also have a band gap smaller than the band gap of the III-N barrier layer 514. For example, when the III-N barrier layer 514 is formed of Al y Ga 1-y When N(0.1≤y≤0.6) is formed, the III-N capping layer 515 may be formed of GaN. The III-N capping layer 515 may be undoped or unintentionally doped. The concentration of all dopants in the III-N capping layer may be less than 10 17 cm -3 , less than 1016 cm -3 or less than 10 15 cm -3 .

[0030] The III-N channel layer 512 can be thin, and can, for example, have a thickness of less than 25 nm, less than 20 nm, less than 18 nm, less than 15 nm, or less than 13 nm. The III-N capping layer 515 can have a thickness greater than the thickness of the III-N channel layer 512. For example, the thickness of the III-N capping layer 515 can be greater than 25 nm, greater than 30 nm, greater than 35 nm, or greater than 40 nm.

[0031] The III-N capping layer 515 can cause an increase in the charge density of the 2DEG channel 520 directly beneath the capping layer (e.g., in the device proximity region), and can also mitigate the effects of DC-RF dispersion in the device by moving surface states associated with the upper surface of the III-N material away from the 2DEG channel 520. Therefore, the thickness of the III-N capping layer 515 can be greater than the thickness of the III-N channel layer 512, and can be, for example, greater than 10 nm, greater than 20 nm, greater than 30 nm, or greater than 40 nm. In some embodiments, the reduction in 2DEG charge density caused by including the III-N barrier layer 514 is at least partially offset by including the III-N capping layer 515 in the device proximity region. This can reduce parasitic source and drain resistances in the device 500, thereby improving device performance. However, as Figure 6 As shown in FIG. 5A , which is an enlarged view of a portion of the device 500 , due to the compositional differences between the III-N barrier layer 514 and the III-N capping layer 515 (described above), typically when the thickness of the III-N capping layer 515 is greater than about 12 nm (the exact thickness of the induced parasitic 2DEG depends at least in part on the compositions of the III-N barrier layer 514 and the III-N capping layer 515), a secondary parasitic 2DEG 530 may also be formed in the III-N capping layer 515. The parasitic 2DEG 530 may reduce the lateral barrier between the gate contact 523 and the drain contact 522, respectively, thereby increasing gate leakage in the device during operation.

[0032] Figure 7 is a cross-sectional view of another N-polarity III-N device 700 similar to Figure 5 The device 500 of the present invention further includes a p-type III-N layer 717 between the III-N cap layer 515 and the III-N barrier layer 514 in the device proximity region (but not in the gate region). The p-type III-N layer 717 can be used to prevent parasitic 2DEG (e.g., Figure 6The 2DEG 530 shown in FIG. 5 is formed in the III-N cap layer 515. While this can reduce gate leakage in the device during operation, it can also cause a slight decrease in the 2DEG charge density in the device close region, thereby increasing parasitic source and drain resistance. This decrease in 2DEG charge density can be minimized by making the thickness of the p-type III-N layer 717 very small and the p-type doping level very high. For example, the thickness of the p-type III-N layer can be less than 10 nm, less than 8 nm, less than 6 nm, or less than 5 nm, and the concentration of acceptors can be greater than 5×10 17 cm -3 , greater than 10 18 cm -3 , greater than 4×10 18 cm -3 or greater than 8×10 18 cm -3 .

[0033] Figure 7 The device 700 may be configured according to Figure 8 800 is formed. First, a III-N buffer layer (e.g., layer 511) is formed (e.g., epitaxially grown) on a substrate (e.g., substrate 510), wherein an N-face of the III-N buffer layer is opposite to the substrate and a group III face is adjacent to the substrate (step 801). Next, a III-N back barrier (e.g., layer 513) is formed on the N-face of the III-N buffer layer (step 802). Next, a III-N channel layer (e.g., layer 512) is formed on the N-face of the III-N back barrier (step 803). When the III-N back barrier is formed of a plurality of III-N layers and includes a first III-N layer (e.g., Figure 4When a III-N channel layer is formed on the N-face of the first III-N layer (e.g., layer 441 in ), a III-N channel layer may be formed on the N-face of the first III-N layer. A III-N barrier layer (e.g., layer 514) is then formed on the N-face of the III-N channel layer (step 804). Next, a p-type III-N layer (e.g., layer 717) is formed on the N-face of the III-N barrier layer (step 805), after which a III-N cap layer (e.g., layer 515) is formed on the N-face of the p-type III-N layer (step 806). Next, etching is performed to remove the III-N cap layer 515, the p-type III-N layer 717, and the III-N barrier layer in the contact area of ​​the device (step 807), and selective area epitaxial growth is performed to form a III-N n-type region 516 in the device contact area (step 808). Next, a recess extending through the entire thickness of the III-N cap layer 515 and the p-type III-N layer 717 is formed by etching in the gate area of ​​the device (step 809). In order to precisely control the depth of the recess, an etch having selectivity between the III-N cap layer 515, the p-type III-N layer 717, and the III-N barrier layer 514 may be used. That is, the etching process for forming the recess may be performed at a thickness lower than that of the material of the III-N barrier layer 514 (e.g., Al y Ga 1-y N) at a higher rate than the III-N cap layer 515 (e.g., unintentionally doped GaN or n-type GaN) and the p-type III-N layer 717 (e.g., p-type GaN), thereby allowing the etching to stop precisely at or near the upper surface (i.e., the [0 0 0-1] surface) of the III-N barrier layer 514. Finally, source and drain contacts (e.g., contacts 521 and 522, respectively) are deposited on the III-N n-type region 516, a gate insulator 532 is optionally deposited on the III-N material layer, and a gate contact 523 is deposited on the gate region of the device (step 810).

[0034] Fig. 9 is a cross-sectional view of another N-polarity III-N device 900 similar to Figure 7Device 700 of the present invention also includes a p-type III-N layer 717 below the gate contact 523 in the gate region of the device. Device 900 can be formed via the following modifications to method 800. When forming a recess in the gate region of the device (step 809 of method 800), the recess is formed through the III-N cap layer 515 but not through the p-type III-N layer 717. In order to precisely control the depth of the recess, an etch having selectivity between the III-N cap layer 515 and the p-type III-N layer 717 can be used. That is, the etching process used to form the recess can selectively etch the material of the III-N cap layer 515 (e.g., unintentionally doped GaN or n-type GaN) at a higher rate than the material of the p-type III-N layer 717 (e.g., p-type GaN), thereby allowing the etching to stop precisely at or near the upper surface (i.e., the [0 0 0 -1] surface) of the p-type III-N layer 717. All other steps for forming device 900 are the same as those of method 800.

[0035] Fig.10 is a cross-sectional view of another N-polar III-N device 1000 similar to Fig. 9 Device 900 of the present invention is described above, except that the III-N barrier layer 514 is omitted, and the p-type III-N layer 717 is formed directly on the III-N channel layer 512 (and on the N-face of the III-N channel layer 512). Device 1000 can be formed via the following modifications to method 800. Step 804 is omitted, and in step 805, the p-type III-N layer is instead formed on the N-face of the III-N channel layer. Additionally, when a recess is formed in the gate region of the device (step 809 of method 800), the recess is formed through the III-N cap layer and not through the p-type III-N layer. All other steps for forming device 1000 are the same as those of method 800.

[0036] Fig.11 is a cross-sectional view of another N-polarity III-N device 1100 similar to Fig.10 The device 1000 of claim 1000, except that the device 1100 further includes an n-type III-N layer 1118 between the III-N channel layer 512 and the p-type III-N layer 717, thereby forming a pn junction in the gate region. Including the n-type III-N layer 1118 may cause an increase in 2DEG charge density and may at least partially offset the decrease in 2DEG charge density caused by including the p-type III-N layer 717. In addition, as Fig.11, the gate insulator 532 may be omitted so that the gate contact 523 directly contacts the p-type III-N layer 717. Therefore, the voltage applied to the gate contact 523 relative to the source contact 521 to modulate the 2DEG charge density in the gate region is directly applied to the p-type III-N layer 717, thereby modulating the voltage across the pn junction formed by the p-type III-N layer 717 and the n-type III-N layer 1118.

[0037] When selecting the doping density and thickness of the p-type III-N layer 717 and the n-type III-N layer 1118, it may be preferred to select a small thickness for each of these layers in order to maintain a large coupling between the gate contact 523 and the 2DEG channel 520 in the gate region of the device 1100. In addition, it may be preferred that the donor density in the n-type III-N layer 1118 is large in order to increase the 2DEG charge density, but the planar donor density in the n-type III-N layer 1118 is less than the planar acceptor density in the p-type III-N layer 717 to ensure that the n-type III-N layer 1118 is fully depleted. If the n-type III-N layer 1118 is not fully depleted, there may be a path for source-drain leakage current to pass through the n-type III-N layer 1118 during device operation. In addition, it may be preferred that the doping density in the p-type III-N layer is large so that the planar acceptor density in the p-type III-N layer 717 is large enough to suppress the formation of a parasitic 2DEG channel in the III-N cap layer 515. As used herein, the "area density" of a dopant (e.g., donor or acceptor) or charge carrier (e.g., electron or hole) in a material layer refers to the density of the dopant or charge carrier in the layer per unit cross-sectional area as viewed from a direction perpendicular to the surface (or interface) of the layer. In the case where the dopant or charge carrier density is uniform throughout the layer, the areal density of the dopant or charge carrier is simply the product of the dopant / carrier density and the thickness of the layer. In the case where the dopant or charge carrier density varies over the thickness of the layer, the areal density is equal to the integral of the dopant / carrier density over the entire thickness of the layer.

[0038] In view of the above, the thickness of the p-type III-N layer 717 may be less than 20 nm, less than 15 nm, less than 12 nm, or less than 10 nm, and the concentration of the acceptors may be greater than 5×10 17 cm -3 , greater than 10 18 cm -3 , greater than 4×10 18 cm -3 , greater than 8×10 18 cm -3 or greater than 10 19 cm -3The thickness of the n-type III-N layer 1118 may be less than 20 nm, less than 15 nm, less than 12 nm, less than 10 nm, or less than 5 nm, and the concentration of the donor may be greater than 5×10 17 cm -3 , greater than 10 18 cm -3 , greater than 4×10 18 cm -3 , greater than 8×10 18 cm -3 , greater than 10 19 cm -3 , greater than 2×10 19 cm -3 or greater than 3×10 19 cm -3 The areal donor density in the n-type III-N layer 1118 may be less than the areal acceptor density in the p-type III-N layer 717, e.g., less than 90%, less than 80%, less than 60%, less than 40%, less than 20%, or less than 10% of the areal acceptor density in the p-type III-N layer 717. The areal donor density in the n-type III-N layer 1118 may be in a range of 10% to 99% of the areal acceptor density in the p-type III-N layer 717.

[0039] Fig.12 yes Fig.11 1 . A cross-sectional view of another configuration 1100′ of the device shown in FIG. 1 . In configuration 1100′, both the III-N cap layer 515 and the p-type III-N layer 717 are removed in the contact regions, but the n-type III-N layer 1118 is not removed in the contact regions, and the source contact 521 and the drain contact 522 are directly on and contact the n-type III-N layer 1118, respectively. Because the p-type III-N layer 717 is removed in the contact regions, the n-type III-N layer 1118 is not depleted in these regions, thereby allowing low resistance ohmic contacts to be formed for the source contact 521 and the drain contact 522, respectively, and allowing the source contact and the drain contact to be electrically connected to the 2DEG channel 520.

[0040] exist Figures 13A-13F 1 . First, various N-polarity III-N layers (510, 511, 513, 512, 1118, 717, and 515) of the device 1100' are sequentially formed on the substrate 510, and a mask layer 1333 (which may be formed of silicon dioxide (SiO2) or another dielectric or polymer material) is formed on the III-N cap layer 515. Fig.13A Next, the aperture 1342 is etched through the mask layer 1333 ( Fig. 13B). The mask layer 1333 is then used as a hard mask to form a recess 1343 in the III-N cap layer 515 in the gate region of the device ( Fig. 13C ). Gate contact 523 is then deposited within the recess in III-N cap layer 515, within the aperture in mask layer 1333, and on a portion of the upper surface of mask layer 1333 ( Fig.13D ). The portion of the gate contact 523 on the upper surface of the mask layer 1333 is then used as an etching mask to remove the mask layer 1333, the III-N cap layer 515, and the p-type III-N layer 717 in the contact area of ​​the device ( Fig.13E ). Next, metal deposition is performed to deposit source contact 521 and drain contact 522, respectively, and some of source and drain metal 1223 is also deposited on gate contact 523 ( Fig.13F ). Note that using method 1300, using a line-of-sight deposition technique such as metal evaporation for source contact 521 and drain contact 522, respectively, can allow these contacts to be self-aligned relative to gate contact 523. The thickness of source contact 521 and drain contact 522 can be less than the combined thickness of layers 717, 515, and 1333, respectively, to prevent shorting of the source contact and drain contact to gate contact 523. Finally, the remaining portion of mask layer 1333 is removed, resulting in Fig.12 Device 1100'.

[0041] Fig.14 is a cross-sectional view of another N-polarity III-N device 1400 similar to Fig.12 The device 1100' is shown in FIG. 1100' except that the device 1400 further includes a second p-type III-N layer 1417 and a III-N barrier layer 1414 between the p-type III-N layers 717 and 1417. The III-N barrier layer 1414 may have a Figure 5-7 and Fig. 9 14. The III-N barrier layer 1414 may be similar or identical in composition and thickness to the III-N barrier layer 514 in FIG. The III-N barrier layer 1414 may act as an etch stop layer during fabrication of the device 1400, allowing for better process control when etching the III-N material in the device contact region prior to depositing the source contact 521 and the drain contact 522, respectively.

[0042] Fig.15 is a cross-sectional view of another N-polarity III-N device 1500 similar to Figure 5Device 500 of the type shown in FIG. 1 , except that device 1500 does not include a gate insulator between gate contact 523 and the underlying III-N material (e.g., III-N barrier layer 514 and III-N cap layer 515). Instead, after forming a recess through III-N cap layer 515 and III-N barrier layer 514 and forming insulator layer 1532 on the III-N material, material of insulator layer 1532 (which serves as a gate insulator in device 500) is removed over a gate region of device 1500, and a p-type III-N layer 1517 (e.g., p-type GaN) is regrown in the gate region on an upper surface of III-N barrier layer 514 and along sidewalls of III-N cap layer 515. As shown, gate contact 523 is formed directly on and contacts p-type III-N layer 1517. The regrown p-type III-N layer 1517 may have a thickness of less than 20 nm, less than 15 nm, less than 12 nm, in a range of 2 nm to 20 nm, in a range of 2 nm to 15 nm, or in a range of 2 nm to 12 nm. The acceptor concentration in the p-type III-N layer 1517 may be the same as previously described for Figure 7 The acceptor concentration in the p-type layer 717 of the device 700 is the same as described above. Fig.15 , but p-type III-N layer 1517 may optionally be formed on the upper surface of III-N cap layer 515 (between layers 515 and 1532 or in place of layer 1532 ), and / or p-type III-N layer 1517 may optionally be formed on III-N n-type region 516 .

[0043] Various devices and material structures thereof, as well as methods of forming the devices, have been described above. However, it should be understood that they have been presented by way of example only and not limitation. Embodiments have been particularly shown and described, but it will be understood that various changes in form and detail may be made. Therefore, other embodiments are within the scope of the following claims.

Claims

1. A semiconductor device, include: A III-N back barrier comprising one or more III-N layers, the one or more III-N layers of the III-N back barrier comprising a first III-N layer; a III-N channel layer on an N-face of the first III-N layer; a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer; A p-type III-N layer on the N-face of the III-N channel layer; and III-N capping layer, which is on the N surface of the p-type III-N layer; The III-N channel layer and the III-N capping layer each have a band gap that is smaller than a band gap of the first III-N layer.

2. The semiconductor device according to claim 1, in, The p-type III-N layer has a band gap smaller than the band gap of the first III-N layer.

3. The semiconductor device according to claim 1, in, The thickness of the III-N channel layer is greater than the thickness of the p-type III-N layer.

4. The semiconductor device according to claim 1, in, The thickness of the III-N capping layer is greater than the thickness of the III-N channel layer.

5. The semiconductor device according to claim 1, further comprising a III-N barrier layer between the III-N channel layer and the p-type III-N layer, in, The band gaps of the III-N channel layer and the p-type III-N layer are each smaller than a band gap of the III-N barrier layer. 6 . The semiconductor device of claim 1 , further comprising an n-type III-N layer between the III-N channel layer and the p-type III-N layer.

7. The semiconductor device according to claim 6, in, The n-type III-N layer is doped with a donor at a concentration of at least 1016 cm-3.

8. The semiconductor device according to claim 6, in, The p-type III-N layer is a first p-type III-N layer, and the semiconductor device further includes a second p-type III-N layer and a III-N barrier layer, and wherein the III-N barrier layer is between the first p-type layer and the second p-type layer.

9. The semiconductor device according to claim 8, in, The band gaps of the III-N channel layer, the n-type III-N layer, the first and second p-type III-N layers, and the III-N cap layer are each smaller than a band gap of the III-N barrier layer.

10. The semiconductor device according to claim 1, in: The III-N channel layer includes a gate region and a plurality of access regions on opposite sides of the gate region; the semiconductor device further includes a source contact, a drain contact, and a gate contact; and The gate contact is on the gate region of the III-N channel layer.

11. The semiconductor device according to claim 10, in, The III-N capping layer is on the proximity region of the III-N channel layer but not on the gate region of the III-N channel layer.

12. A semiconductor device, include: A III-N back barrier comprising one or more III-N layers, the one or more III-N layers of the III-N back barrier comprising a first III-N layer; a III-N channel layer on an N-face of the first III-N layer; a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer; A p-type III-N layer on the N-face of the III-N channel layer; and III-N capping layer, which is on the N surface of the p-type III-N layer; wherein, Adjacent to the interface between the III-N channel layer and the first III-N layer, a conduction band energy of the first III-N layer is greater than a conduction band energy of the III-N channel layer. 13 . The semiconductor device of claim 12 , further comprising a plurality of contacts on the N-face of the III-N channel layer, the plurality of contacts comprising a source contact, a gate contact, and a drain contact.

14. The semiconductor device according to claim 13, in, The III-N channel layer includes a gate region and a plurality of proximity regions on opposite sides of the gate region, the III-N capping layer is on the proximity regions of the III-N channel layer but not on the gate region of the III-N channel layer, and the gate contact is on the gate region of the III-N channel layer. 15 . The semiconductor device of claim 14 , further comprising a gate insulator between the gate contact and the III-N channel layer.

16. The semiconductor device according to claim 12, in, The thickness of the p-type III-N layer is less than 8 nm, and the concentration of acceptors in the p-type III-N layer is greater than 1018 cm-3.

17. A semiconductor device, include: A III-N back barrier comprising one or more III-N layers, the one or more III-N layers of the III-N back barrier comprising a first III-N layer; a III-N channel layer on an N-face of the first III-N layer, wherein the first III-N layer has a larger bandgap than the III-N channel layer; a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer; A p-type III-N layer on the N-face of the III-N channel layer; and An n-type III-N layer is between the III-N channel layer and the p-type III-N layer.

18. The semiconductor device according to claim 17, in, The acceptor concentration in the p-type III-N layer is less than the donor concentration in the n-type III-N layer.

19. The semiconductor device according to claim 17, in, The donor concentration in the n-type III-N layer is at least 1016 cm-3.

20. A semiconductor device, include: A III-N back barrier comprising one or more III-N layers, the one or more III-N layers of the III-N back barrier comprising a first III-N layer; a III-N channel layer on an N-face of the first III-N layer, the III-N channel layer comprising a gate region and a plurality of access regions on opposite sides of the gate region; a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer; A III-N barrier layer on the N-face of the III-N channel layer; A III-N capping layer on the N-face of the III-N barrier layer; and p-type III-N layer; wherein, The III-N channel layer and the III-N cap layer each have a band gap that is smaller than a band gap of both the first III-N layer and the III-N barrier layer; and Both the III-N barrier layer and the III-N capping layer are on the proximity region of the III-N channel layer but not on the gate region of the III-N channel layer.

21. The semiconductor device of claim 20, further comprising a gate contact on the gate region of the III-N channel layer, in, The p-type III-N layer is between the gate contact and the III-N channel layer.

22. The semiconductor device according to claim 21, in, The p-type III-N layer directly contacts the III-N channel layer, the III-N barrier layer, and the III-N cap layer.

23. A method of forming a semiconductor device, include: forming a III-N back barrier on a substrate, wherein the III-N back barrier has a group III face close to the substrate and an N face opposite to the group III face, wherein the III-N back barrier comprises one or more III-N layers, and the one or more III-N layers of the III-N back barrier comprise a first III-N layer; forming a III-N channel layer on the N-surface of the first III-N layer; forming a p-type III-N layer on an N-face of the III-N channel layer; and A III-N capping layer is formed on the N surface of the p-type III-N layer; wherein, The III-N channel layer and the III-N cap layer each have a band gap that is smaller than a band gap of the first III-N layer; and The semiconductor device includes a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer. 24 . The method of claim 23 , further comprising forming a recess through the entire thickness of the III-N capping layer in a gate region of the semiconductor device, and depositing a gate contact on the gate region of the semiconductor device.

25. The method according to claim 24, in, The recess extends through the entire thickness of the p-type III-N layer. 26 . The method of claim 24 , further comprising forming a III-N barrier layer between the III-N channel layer and the p-type III-N layer. 27 . The method of claim 26 , further comprising forming a gate insulator between the III-N barrier layer and the gate contact.

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