Power management chip and its pin detection circuit

Abstract

The embodiment of the present disclosure provides a power management chip and a pin detection circuit thereof. The pin detection circuit includes a detection module and an output module. The detection module can compare the difference between the voltage of each power ground pad and the voltage of the analog ground pad with a preset voltage to obtain N power ground comparison signals and N analog ground comparison signals, determine the analog ground detection signal according to the N analog ground comparison signals, and determine the power ground detection signal according to the N power ground comparison signals. When the analog ground detection signal is an analog ground abnormal signal or the power ground detection signal is a power ground abnormal signal, the output module generates a ground pin abnormal indication signal. The pin detection circuit can indicate that the ground pin connection is abnormal, thereby improving the functional safety mechanism of the chip.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a power management chip and a pin detection circuit thereof. Background Art

[0002] The power chip circuit usually includes a control and drive circuit and a power stage circuit. The signal in the control and drive circuit is weak and easily affected by the strong signal in the power stage circuit. Therefore, it is necessary to distinguish the ground lines of the control and drive circuit and the power stage circuit. The control and drive circuit is connected to the analog ground, and the power stage circuit is connected to the power ground. The power management chip is a multi-channel power chip that can provide multi-channel power. It has an analog ground pin and multiple power ground pins. Each channel power supply corresponds to a power ground pin.

[0003] After the power management chip is powered on, there are two common abnormal connections of the ground pin. One is that the ground pad is not connected to the board-level ground of the board-level circuit due to the broken internal package wire or the cracked connection between the flip chip and the frame. The other is that the ground pad is not connected to the board-level ground due to external cold soldering. With the development of integrated circuits, the demand for functional safety of power management chips has increased, so a technical solution that can indicate abnormal ground pin connection is urgently needed to improve the functional safety mechanism of the chip. Summary of the invention

[0004] The present disclosure provides a power management chip and a pin detection circuit thereof, which can indicate abnormal ground pin connection, thereby improving the functional safety mechanism of the chip.

[0005] In a first aspect, the present disclosure provides a pin detection circuit for a power management chip, wherein the power management chip includes an analog ground pad, an analog ground pin, N power ground pads and N power ground pins, the analog ground pad is grounded through the analog ground pin, each power ground pad is grounded through a power ground pin, and N is an integer greater than 1.

[0006] The pin detection circuit includes: a detection module and an output module, the first input end of the detection module is connected to the analog ground pad, the N second input ends of the detection module are connected to the N power ground pads in a one-to-one correspondence, and the output end of the detection module is connected to the input end of the output module.

[0007] The detection module is configured to compare the difference between the voltage of each power ground pad and the voltage of the analog ground pad with a preset voltage to obtain N power ground comparison signals and N analog ground comparison signals, determine the analog ground detection signal based on the N analog ground comparison signals, and determine the power ground detection signal based on the N power ground comparison signals.

[0008] The output module is configured to generate a ground pin abnormal connection indication signal when the analog ground detection signal is an analog ground abnormal signal or the power ground detection signal is a power ground abnormal signal.

[0009] In some embodiments of the present disclosure, the detection module includes an analog ground detection unit and a power ground detection unit, the first input end of the analog ground detection unit and the second input end of the power ground detection unit are connected to the analog ground pad, the N second input ends of the analog ground detection unit are connected to the N power ground pads one-to-one, the N first input ends of the power ground detection unit are connected to the N power ground pads one-to-one, the output end of the analog ground detection unit is connected to the first input end of the output module, and the output end of the power ground detection unit is connected to the second input end of the output module.

[0010] The analog ground detection unit is configured to compare the voltage of each power ground pad with the sum of the preset voltage and the voltage of the analog ground pad to obtain N analog ground comparison signals, and determine the analog ground detection signal according to whether there is a high level signal in the N analog ground comparison signals.

[0011] The power ground detection unit is configured to compare the voltage of the analog ground pad with the sum of the preset voltage and the voltage of each power ground pad to obtain N power ground comparison signals, and determine the power ground detection signal according to whether there is a high level signal in the N power ground comparison signals.

[0012] In some embodiments of the present disclosure, the analog ground detection unit includes a first OR gate and N analog ground comparators, the non-phase input terminal of the i-th analog ground comparator is connected to the analog ground pad, the inverting input terminal of the i-th analog ground comparator is connected to the i-th power ground pad, the output terminal of the i-th analog ground comparator is connected to the i-th input terminal of the first OR gate, and the output terminal of the first OR gate is connected to the first input terminal of the output module, wherein 1≤i≤N and i is an integer.

[0013] The i-th analog ground comparator is configured to output a high level signal when the voltage of the analog ground pad is greater than the sum of the voltage of the i-th power ground pad and a preset voltage, and to output a low level signal when the voltage of the analog ground pad is less than the sum of the voltage of the i-th power ground pad and the preset voltage.

[0014] The first OR gate is configured to generate an analog ground abnormal signal when a high level signal exists in the N analog ground comparison signals, and to generate an analog ground normal signal when a high level signal does not exist in the N analog ground comparison signals.

[0015] In some embodiments of the present disclosure, the power ground detection unit includes a second OR gate and N power ground comparators, the positive input terminal of the i-th power ground comparator is connected to the i-th power ground pad, the inverting input terminal of the i-th power ground comparator is connected to the analog ground pad, the output terminal of the i-th power ground comparator is connected to the i-th input terminal of the second OR gate, and the output terminal of the second OR gate is connected to the second input terminal of the output module, wherein 1≤i≤N and i is an integer.

[0016] The i-th power ground comparator is configured to output a high level signal when the voltage of the i-th power ground pad is greater than the sum of the voltage of the analog ground pad and the preset voltage, and to output a low level signal when the voltage of the i-th power ground pad is less than the sum of the voltage of the analog ground pad and the preset voltage.

[0017] The second OR gate is configured to generate a power abnormality signal when there is a high level signal among the N power comparison signals; and to generate a power normal signal when there is no high level signal among the N power comparison signals.

[0018] In some embodiments of the present disclosure, the comparator includes a current source, a resistor, a first current mirror structure, a second current mirror structure and a first transistor, the input end of the first current mirror structure is connected to an external power supply, the first output end of the first current mirror structure is connected to the first ground pad through the current source, the second output end of the first current mirror structure is connected to the first ground pad through the second current mirror structure, the third output end of the first current mirror structure is connected to the second ground pad through the second current mirror structure and the resistor in sequence, the fourth output end of the first current mirror structure is connected to the first ground pad through the first transistor, the third output end of the first current mirror structure is connected to the control end of the first transistor, and the fourth output end of the first current mirror structure is connected to the output end of the comparator.

[0019] When the comparator is an analog ground comparator, the first ground pad is an analog ground pad and the second ground pad is a power ground pad; when the comparator is a power ground comparator, the first ground pad is a power ground pad and the second ground pad is an analog ground pad.

[0020] In some embodiments of the present disclosure, the first current mirror structure includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor, and a width-to-length ratio of the third transistor is equal to a width-to-length ratio of the fourth transistor.

[0021] The first end of the second transistor, the first end of the third transistor, the first end of the fourth transistor and the first end of the fifth transistor are connected to an external power supply, and the control end of the second transistor is connected to the second end of the second transistor, the control end of the third transistor, the control end of the fourth transistor and the control end of the fifth transistor.

[0022] The second end of the second transistor is connected to the first output end of the first current mirror structure, the second end of the third transistor is connected to the second output end of the first current mirror structure, the second end of the fourth transistor is connected to the third output end of the first current mirror structure, and the second end of the fifth transistor is connected to the fourth output end of the first current mirror structure.

[0023] In some embodiments of the present disclosure, the second current mirror structure includes a sixth transistor and a seventh transistor, and a width-to-length ratio of the sixth transistor is equal to a width-to-length ratio of the seventh transistor.

[0024] The second end of the sixth transistor is connected to the control end of the sixth transistor, the control end of the seventh transistor and the second end of the third transistor, the first end of the sixth transistor is connected to the first ground pad, the second end of the seventh transistor is connected to the second end of the fourth transistor, and the first end of the seventh transistor is connected to the second ground pad through a resistor.

[0025] In some embodiments of the present disclosure, the comparator also includes a capacitor, a first Schmitt trigger and a second Schmitt trigger. The third output terminal of the first current mirror structure is connected to the control terminal of the first transistor through the first Schmitt trigger. The fourth output terminal of the first current mirror structure is connected to the output terminal of the comparator through the second Schmitt trigger. The fourth output terminal of the first current mirror structure is also connected to the first ground pad through the capacitor.

[0026] In some embodiments of the present disclosure, the output module includes a third OR gate, a first input end of the third OR gate is connected to the output end of the analog ground detection unit, and a second input end of the third OR gate is connected to the output end of the power ground detection unit.

[0027] In a second aspect, the present disclosure provides a power management chip, including an analog ground pad, an analog ground pin, N power ground pads, N power ground pins, and any pin detection circuit provided in the first aspect.

[0028] The technical solution disclosed in the present invention provides a pin detection circuit of a power management chip, including a detection module and an output module. The detection module can compare the difference between the voltage of each power ground pad and the voltage of the analog ground pad with a preset voltage to obtain N power ground comparison signals and N analog ground comparison signals, determine the analog ground detection signal according to the N analog ground comparison signals, and determine the power ground detection signal according to the N power ground comparison signals. When the analog ground detection signal is an analog ground abnormal signal or the power ground detection signal is a power ground abnormal signal, the output module generates a ground pin abnormal indication signal, which can indicate that the ground pin connection is abnormal, thereby improving the functional safety mechanism of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure, wherein:

[0030] Figure 1 A schematic diagram of abnormal connection of a ground pin provided in an embodiment of the present disclosure;

[0031] Figure 2 A schematic diagram of the structure of a power management chip provided in an embodiment of the present disclosure;

[0032] Figure 3 A schematic diagram of the structure of another power management chip provided in an embodiment of the present disclosure;

[0033] Figure 4 A schematic diagram of the structure of a pin detection circuit provided by an embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of the structure of another pin detection circuit provided in an embodiment of the present disclosure;

[0035] Figure 6 A circuit diagram of a pin detection circuit provided by an embodiment of the present disclosure;

[0036] Figure 7 A circuit diagram of another pin detection circuit provided by an embodiment of the present disclosure;

[0037] Figure 8 A circuit diagram of a comparator provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0040] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0041] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0042] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0043] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two). Similarly, "plurality groups" and "at least two groups" mean more than two groups (including two).

[0044] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0045] The power chip circuit usually includes a control and drive circuit and a power stage circuit. The signal in the control and drive circuit is weak, and the current in the power stage circuit is large. The large current will produce a large voltage drop in the control and drive circuit, causing the signal in the control and drive circuit to be seriously distorted, which may cause at least part of the function of the control and drive circuit to fail. Therefore, it is necessary to connect the control and drive circuit to the analog ground and the power stage circuit to the power ground to distinguish the ground of the control and drive circuit from that of the power stage circuit, so as to prevent the control and drive circuit from being affected by the large current in the power stage circuit.

[0046] A single-channel power supply chip generally has two ground pins, one ground pin is an analog ground pin, and the other ground pin is a power ground pin. The power management chip integrates a multi-channel power supply and has at least three ground pins, one of which is an analog ground and the other multiple ground pins are power ground pins. All ground pins of the power management chip will be connected to the board-level ground line in the board-level circuit.

[0047] Figure 1 The schematic diagram of abnormal ground pin connection provided in the embodiment of the present disclosure, after the power management chip is powered on, the abnormal ground pin connection includes the following two situations: one is that the internal package wire is broken or the connection between the flip chip and the frame is cracked, so that the connection between the ground pad Pad_g and the ground pin Pin_g is disconnected, resulting in the ground pad Pad_g not being connected to the board-level GND, such as Figure 1 As shown in part (a) of the figure, the other is external cold soldering, which disconnects the ground pin Pin_g from the board-level GND, resulting in the ground pad Pad_g not being connected to the board-level GND, as shown in Figure 1 As shown in part (b) of .

[0048] With the development of integrated circuits, the demand for functional safety of power management chips has increased. For example, the functional safety requirement includes the ability to indicate whether the ground pin connection is normal after the power management chip is powered on. Therefore, a technical solution that can indicate abnormal ground pin connection is urgently needed to improve the functional safety mechanism of the chip.

[0049] Figure 2 A schematic diagram of the structure of a power management chip provided by an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the power management chip includes an analog ground pad Pad_A, an analog ground pin Pin_A, N power ground pads Pad_P and N power ground pins Pin_P, the analog ground pad Pad_A is connected to the board-level ground through the analog ground pin Pin_A, each power ground pad Pad_P is connected to the board-level ground through a power ground pin Pin_P, and N is an integer greater than 1.

[0050] For example, Figure 2As shown, N=3, then the power management chip includes 3 power ground pads Pad_P and 3 power ground pins Pin_P, wherein the 3 power ground pads Pad_P are respectively the first power ground pad Pad_P1, the second power ground pad Pad_P2 and the third power ground pad Pad_P3, and the 3 power ground pins Pin_P are respectively the first power ground pin Pin_P1, the second power ground pin Pin_P2 and the third power ground pin Pin_P3. The first power ground pad Pad_P1 is connected to the board-level GND through the first power ground pin Pin_P1, the second power ground pad Pad_P2 is connected to the board-level GND through the second power ground pin Pin_P2, and the third power ground pad Pad_P3 is connected to the board-level GND through the third power ground pin Pin_P3.

[0051] In other implementations, N may be 2, and the power management chip includes a first power ground pad Pad_P1, a second power ground pad Pad_P2, a first power ground pin Pin_P1, and a second power ground pin Pin_P2. Figure 3 As shown, Figure 3 A schematic diagram of the structure of another power management chip provided by an embodiment of the present disclosure. Alternatively, N may also be any integer greater than 3, which is not specifically limited in the present disclosure.

[0052] The power management chip also includes a pin detection circuit ( Figure 2 and Figure 3 (not shown in the figure), the pin detection circuit includes N second input terminals, the first input terminal of the pin detection circuit is connected to the analog ground pad Pad_A, and the N second input terminals of the pin detection circuit are connected to the N power ground pads Pad_P in a one-to-one correspondence.

[0053] For example, Figure 2 As shown, the pin detection circuit includes three second input terminals, and the three second input terminals of the pin detection circuit are respectively connected to the first power ground pad Pad_P1, the second power ground pad Pad_P2 and the third power ground pad Pad_P3.

[0054] The power management chip provided in the embodiment of the present disclosure includes a pin detection circuit, which has the same functional modules and beneficial effects as the pin detection circuit. The pin detection circuit of the present disclosure is described in detail with several specific embodiments below.

[0055] Figure 4 A schematic diagram of a pin detection circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 4As shown, the pin detection circuit 100 includes a detection module 110 and an output module 120, wherein the first input end of the detection module 110 is connected to the analog ground pad Pad_A, the N second input ends of the detection module 110 are connected one-to-one with the N power ground pads Pad_P, and the output end of the detection module 110 is connected to the input end of the output module 120.

[0056] The detection module 110 is configured to compare the difference between the voltage V_P of each power ground pad Pad_P and the voltage V_A of the analog ground pad Pad_A with a preset voltage Vpre to obtain N power ground comparison signals S_P and N analog ground comparison signals S_A, determine the analog ground detection signal Det_A according to the N analog ground comparison signals S_A, and determine the power ground detection signal Det_P according to the N power ground comparison signals S_P.

[0057] The output module 120 is configured to generate a ground pin abnormal connection indication signal when the analog ground detection signal Det_A is an analog ground abnormal signal or the power ground detection signal Det_P is a power ground abnormal signal.

[0058] For example, Figure 4 As shown, the detection module 110 may include three second input terminals, and the three second input terminals of the detection module 110 are respectively connected to the first power ground pad Pad_P1, the second power ground pad Pad_P2, and the third power ground pad Pad_P3.

[0059] In other embodiments, the detection module 110 may include two second input terminals, and the two second input terminals of the detection module 110 are respectively connected to the first power ground pad Pad_P1 and the second power ground pad Pad_P2. Figure 5 As shown, Figure 5 A schematic diagram of the structure of another pin detection circuit provided in an embodiment of the present disclosure.

[0060] Alternatively, the detection module 110 may further include more than three second input terminals, and the present disclosure does not impose any specific limitation on this, but only limits the number of the second input terminals of the detection module 110 to be equal to the number of the power ground pads Pad_P.

[0061] Figure 6 A circuit diagram of a pin detection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 6As shown, the detection module 110 includes an analog ground detection unit 111 and a power ground detection unit 112, wherein the first input end of the analog ground detection unit 111 and the second input end of the power ground detection unit 112 are connected to the analog ground pad Pad_A, the N second input ends of the analog ground detection unit 111 are connected to the N power ground pads Pad_P in a one-to-one correspondence, the N first input ends of the power ground detection unit 112 are connected to the N power ground pads Pad_P in a one-to-one correspondence, the output end of the analog ground detection unit 111 is connected to the first input end of the output module 120, and the output end of the power ground detection unit 112 is connected to the second input end of the output module 120.

[0062] For example, Figure 6 As shown, the analog ground detection unit 111 may include three second input terminals, and the three second input terminals of the analog ground detection unit 111 are respectively connected to the first power ground pad Pad_P1, the second power ground pad Pad_P2 and the third power ground pad Pad_P3, and the power ground detection unit 112 includes three first input terminals, and the three first input terminals of the power ground detection unit 112 are respectively connected to the first power ground pad Pad_P1, the second power ground pad Pad_P2 and the third power ground pad Pad_P3.

[0063] In other embodiments, the analog ground detection unit 111 may include two second input terminals, the two second input terminals of the analog ground detection unit 111 are respectively connected to the first power ground pad Pad_P1 and the second power ground pad Pad_P2, and the power ground detection unit 112 includes two first input terminals, the two first input terminals of the power ground detection unit 112 are respectively connected to the first power ground pad Pad_P1 and the second power ground pad Pad_P2, such as Figure 7 , Figure 7 A circuit diagram of another pin detection circuit provided in an embodiment of the present disclosure.

[0064] Alternatively, the analog ground detection unit 111 may also include more than three second input terminals, and the power ground detection unit 112 may include more than three first input terminals. The present disclosure does not make any specific restrictions on this, but only limits the number of second input terminals of the analog ground detection unit 111, the number of first input terminals of the power ground detection unit 112 to be equal to the number of power ground pads Pad_P.

[0065] The analog ground detection unit 111 can compare the sum V_P+Vpre of the voltage V_P of each power ground pad Pad_P and the preset voltage Vpre with the voltage V_A of the analog ground pad Pad_A to obtain N analog ground comparison signals S_A, wherein the analog ground comparison signal S_A includes a high level signal and a low level signal.

[0066] For example, Figure 6As shown, the analog ground detection unit 111 can compare the sum of the voltage V_P1 of the first power ground pad Pad_P1 and the preset voltage Vpre, i.e., V_P1 + Vpre, with the voltage V_A of the analog ground pad Pad_A to obtain the first analog ground comparison signal S_A1, compare the sum of the voltage V_P2 of the second power ground pad Pad_P2 and the preset voltage Vpre, i.e., V_P2 + Vpre, with the voltage V_A of the analog ground pad Pad_A to obtain the second analog ground comparison signal S_A2, and compare the sum of the voltage V_P3 of the third power ground pad Pad_P3 and the preset voltage Vpre, i.e., V_P3 + Vpre, with the voltage V_A of the analog ground pad Pad_A to obtain the third analog ground comparison signal S_A3.

[0067] When the analog ground pad Pad_A is not connected to the board-level GND, the analog ground pad Pad_A is in a floating state, and the voltage V_A of the analog ground pad Pad_A is greater than the preset voltage Vpre, i.e., V_A > Vpre. If a certain power ground pad Pad_P is connected to the board-level GND, the voltage V_P of this power ground pad Pad_P is 0V. After the power management chip is powered on, the voltage V_A of the analog ground pad Pad_A is greater than the sum of the voltage V_P of this power ground pad Pad_P and the preset voltage Vpre, i.e., V_A > V_P + Vpre. At this time, the obtained analog ground comparison signal S_A is a high-level signal.

[0068] If a certain power ground pad Pad_P is not connected to the board-level GND, this power ground pad Pad_P is in a floating state, and the voltage V_P of this power ground pad Pad_P is greater than the preset voltage Vpre, i.e., V_P > Vpre. After the power management chip is powered on, the voltage V_A of the analog ground pad Pad_A may be greater than the sum of the voltage V_P of this power ground pad Pad_P and the preset voltage Vpre, i.e., V_A > V_P + Vpre, or may be less than the sum of the voltage V_P of this power ground pad Pad_P and the preset voltage Vpre, i.e., V_A < V_P + Vpre. At this time, the obtained analog ground comparison signal S_A may be a high-level signal or a low-level signal.

[0069] When the analog ground pad Pad_A is connected to the board-level GND, the voltage V_A of the analog ground pad Pad_A is 0V. If a certain power ground pad Pad_P is connected to the board-level GND, the voltage V_P of this power ground pad Pad_P is 0V. After the power management chip is powered on, the voltage V_A of the analog ground pad Pad_A is less than the sum of the voltage V_P of this power ground pad Pad_P and the preset voltage Vpre, i.e., V_A < V_P + Vpre. At this time, the obtained analog ground comparison signal S_A is a low-level signal.

[0070] If a power ground pad Pad_P is not connected to the board-level GND, the power ground pad Pad_P is in a floating state, and the voltage V_P of the power ground pad Pad_P is greater than a preset voltage Vpre, that is, V_P > Vpre. After the power management chip is powered on, the voltage V_A of the analog ground pad Pad_A is less than the sum V_P + Vpre of the voltage V_P of the power ground pad Pad_P and the preset voltage Vpre, that is, V_A < V_P + Vpre. At this time, the obtained analog ground comparison signal S_A is a low-level signal.

[0071] Accordingly, the analog ground detection unit 111 can determine the analog ground detection signal Det_A according to whether there is a high-level signal in the N analog ground comparison signals S_A. Among them, the analog ground detection signal Det_A includes an analog ground normal signal and an analog ground abnormal signal. For example, the analog ground normal signal is a low-level signal, and the analog ground abnormal signal is a high-level signal.

[0072] Specifically, when there is a high-level signal in the N analog ground comparison signals S_A, the analog ground detection signal Det_A determined by the analog ground detection unit 111 is an analog ground abnormal signal. When there is no high-level signal in the N analog ground comparison signals S_A, the analog ground detection signal Det_A determined by the analog ground detection unit 111 is an analog ground normal signal.

[0073] For example, as Figure 6 shown, when the first analog ground comparison signal S_A1 is a high-level signal, the analog ground detection signal Det_A is an analog ground abnormal signal. When the second analog ground comparison signal S_A2 is a high-level signal, the analog ground detection signal Det_A is an analog ground abnormal signal. When the third analog ground comparison signal S_A3 is a high-level signal, the analog ground detection signal Det_A is an analog ground abnormal signal. When the first analog ground comparison signal S_A1, the second analog ground comparison signal S_A2, and the third analog ground comparison signal S_A3 are all low-level signals, the analog ground detection signal Det_A is an analog ground normal signal.

[0074] The power ground detection unit 112 can compare the sum V_A + Vpre of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre with the voltages V_P of the respective power ground pads Pad_P to obtain N power comparison signals S_P. Among them, the power comparison signals S_P include high-level signals and low-level signals.

[0075] Exemplarily, as Figure 6As shown, the power ground detection unit 112 can compare the sum V_A + Vpre of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre with the voltage V_P1 of the first power ground pad Pad_P1, the voltage V_P2 of the second power ground pad Pad_P2, and the voltage V_P3 of the third power ground pad Pad_P3 respectively, to obtain the first power ground comparison signal S_P1, the second power ground comparison signal S_P2, and the third power ground comparison signal S_P3.

[0076] When a certain power ground pad Pad_P is not connected to the board-level GND, the power ground pad Pad_P is in a floating state, and the voltage V_P of the power ground pad Pad_P is greater than the preset voltage Vpre, that is, V_P > Vpre. If the analog ground pad Pad_A is connected to the board-level GND, the voltage V_A of the analog ground pad Pad_A is 0V. After the power management chip is powered on, the voltage V_P of the power ground pad Pad_P is greater than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, that is, V_P > V_A + Vpre. At this time, the obtained power ground comparison signal S_P is a high-level signal.

[0077] If the analog ground pad Pad_A is not connected to the board-level GND, the analog ground pad Pad_A is in a floating state, and the voltage V_A of the analog ground pad Pad_A is greater than the preset voltage Vpre, that is, V_A > Vpre. After the power management chip is powered on, the voltage V_P of the power ground pad Pad_P may be greater than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, that is, V_P > Pad_A + Vpre, or may be less than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, that is, V_P < Pad_A + Vpre. At this time, the obtained power ground comparison signal S_P may be a high-level signal or a low-level signal.

[0078] When a certain power ground pad Pad_P is connected to the board-level GND, the voltage V_P of the power ground pad Pad_P is 0V. If the analog ground pad Pad_A is connected to the board-level GND, the voltage V_A of the analog ground pad Pad_A is 0V. After the power management chip is powered on, the voltage V_P of the power ground pad Pad_P is less than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, that is, V_P < V_A + Vpre. At this time, the obtained power ground comparison signal S_P is a low-level signal.

[0079] If the analog ground pad Pad_A is not connected to the board-level GND, the analog ground pad Pad_A is in a floating state, and the voltage V_A of the analog ground pad Pad_A is greater than the preset voltage Vpre, that is, V_A > Vpre. After the power management chip is powered on, the voltage V_P of the power ground pad Pad_P is less than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, that is, V_P < Pad_A + Vpre. At this time, the obtained power ground comparison signal S_P is a low-level signal.

[0080] Accordingly, the power ground detection unit 112 can determine the power ground detection signal Det_P according to whether there is a high-level signal in the N power ground comparison signals S_P. Among them, the power ground detection signal Det_P includes a power ground normal signal and a power ground abnormal signal. For example, the power ground normal signal is a low-level signal, and the power ground abnormal signal is a high-level signal.

[0081] Specifically, when there is a high-level signal in the N power ground comparison signals S_P, the power ground detection signal Det_P determined by the power ground detection unit 112 is a power ground abnormal signal. When there is no high-level signal in the N power ground comparison signals S_P, the power ground detection signal Det_P determined by the power ground detection unit 112 is a power ground normal signal.

[0082] For example, as Figure 6 shown, when the first power ground comparison signal S_P1 is a high-level signal, the power ground detection signal Det_P is a power ground abnormal signal. When the second power ground comparison signal S_P2 is a high-level signal, the power ground detection signal Det_P is a power ground abnormal signal. When the third power ground comparison signal S_P3 is a high-level signal, the power ground detection signal Det_P is a power ground abnormal signal. When the first power ground comparison signal S_P1, the second power ground comparison signal S_P2, and the third power ground comparison signal S_P3 are all low-level signals, the power ground detection signal Det_P is a power ground normal signal.

[0083] Exemplarily, continue to refer to Figure 6 and Figure 7 , the output module 120 includes a third OR gate OR3. The first input terminal of the third OR gate OR3 is connected to the output terminal of the analog ground detection unit 111, and the second input terminal of the third OR gate OR3 is connected to the output terminal of the power ground detection unit 112.

[0084] The analog ground normal signal is a low level signal, and the analog ground abnormal signal is a high level signal. When the third OR gate OR3 receives the analog ground abnormal signal, the third OR gate OR3 outputs a high level signal, that is, generates a ground pin abnormal connection indication signal. The power ground normal signal is a low level signal, and the power ground abnormal signal is a high level signal. When the third OR gate OR3 receives the power ground abnormal signal, the third OR gate OR3 generates a ground pin abnormal connection indication signal. When the third OR gate OR3 receives the analog ground normal signal and the power ground normal signal, the third OR gate OR3 outputs a low level signal, that is, generates a ground pin normal connection indication signal.

[0085] In this way, the output module 120 generates a ground pin abnormal connection indication signal when the analog ground detection signal Det_A is an analog ground abnormal signal or the power ground detection signal Det_P is a power ground abnormal signal, and generates a ground pin normal connection indication signal when the analog ground detection signal Det_A is an analog ground normal signal and the power ground detection signal Det_P is a power ground normal signal.

[0086] That is to say, the output module 120 can generate a ground pin connection indication signal based on the analog ground detection signal Det_A and the power ground detection signal Det_P, wherein the ground pin connection indication signal includes a ground pin abnormal connection indication signal and a ground pin normal connection indication signal, for example, the ground pin abnormal connection indication signal is a high level signal, and the ground pin normal connection indication signal is a low level signal.

[0087] In the disclosed embodiment, the pin detection circuit includes a detection module and an output module. The detection module can compare the difference between the voltage of each power ground pad and the voltage of the analog ground pad with a preset voltage to obtain N power ground comparison signals and N analog ground comparison signals, determine the analog ground detection signal according to the N analog ground comparison signals, and determine the power ground detection signal according to the N power ground comparison signals. When the analog ground detection signal is an analog ground abnormal signal or the power ground detection signal is a power ground abnormal signal, the output module generates a ground pin abnormal indication signal, which can indicate that the ground pin connection is abnormal, thereby improving the functional safety mechanism of the chip.

[0088] In some embodiments, see Figure 6 and Figure 7 The analog ground detection unit 111 includes a first OR gate OR1 and N analog ground comparators CMP_A, wherein the non-inverting input terminal of the i-th analog ground comparator CMP_Ai is connected to the analog ground pad Pad_A, the inverting input terminal of the i-th analog ground comparator CMP_Ai is connected to the i-th power ground pad Pad_Pi, the output terminal of the i-th analog ground comparator CMP_Ai is connected to the i-th input terminal of the first OR gate OR1, and the output terminal of the first OR gate OR1 is connected to the first input terminal of the output module 120, wherein 1≤i≤N and i is an integer.

[0089] The i-th analog ground comparator CMP_Pi is configured to output a high-level signal when the voltage V_A of the analog ground pad Pad_A is greater than the sum of the voltage V_Pi of the i-th power ground pad Pad_Pi and a preset voltage Vpre, and output a low-level signal when the voltage V_A of the analog ground pad Pad_A is less than the sum of the voltage V_Pi of the i-th power ground pad Pad_Pi and the preset voltage Vpre.

[0090] The first OR gate OR1 is configured to generate an analog ground abnormal signal when there is a high-level signal among the N analog ground comparison signals S_A, and generate an analog ground normal signal when there is no high-level signal among the N analog ground comparison signals S_A.

[0091] Exemplarily, as Figure 6 shown, the analog ground detection unit 111 includes 3 analog ground comparators CMP_A, namely the first analog ground comparator CMP_A1, the second analog ground comparator CMP_A2, and the third analog ground comparator CMP_A3.

[0092] Among them, the non-inverting input terminals of the first analog ground comparator CMP_A1, the second analog ground comparator CMP_A2, and the third analog ground comparator CMP_A3 are connected to the analog ground pad Pad_A, the inverting input terminal of the first analog ground comparator CMP_A1 is connected to the first power ground pad Pad_P1, the inverting input terminal of the second analog ground comparator CMP_A2 is connected to the second power ground pad Pad_P2, and the inverting input terminal of the third analog ground comparator CMP_A3 is connected to the third power ground pad Pad_P3.

[0093] When the voltage V_A of the analog ground pad Pad_A is greater than the sum of the voltage V_P1 of the first power ground pad Pad_P1 and the preset voltage Vpre, that is, V_A > V_P1 + Vpre, the first analog ground comparison signal S_A1 output by the first analog ground comparator CMP_A1 is a high-level signal. When the voltage V_A of the analog ground pad Pad_A is less than the sum of the voltage V_P1 of the first power ground pad Pad_P1 and the preset voltage Vpre, that is, V_A < V_P1 + Vpre, the first analog ground comparison signal S_A1 output by the first analog ground comparator CMP_A1 is a low-level signal.

[0094] When the voltage V_A of the analog ground pad Pad_A is greater than the sum of the voltage V_P2 of the second power ground pad Pad_P2 and the preset voltage Vpre, i.e., V_A > V_P2 + Vpre, the second analog ground comparison signal S_A2 output by the second analog ground comparator CMP_A2 is a high-level signal. When the voltage V_A of the analog ground pad Pad_A is less than the sum of the voltage V_P2 of the second power ground pad Pad_P2 and the preset voltage Vpre, i.e., V_A < V_P2 + Vpre, the second analog ground comparison signal S_A2 output by the second analog ground comparator CMP_A2 is a low-level signal.

[0095] When the voltage V_A of the analog ground pad Pad_A is greater than the sum of the voltage V_P3 of the third power ground pad Pad_P3 and the preset voltage Vpre, i.e., V_A > V_P3 + Vpre, the third analog ground comparison signal S_A3 output by the third analog ground comparator CMP_A3 is a high-level signal. When the voltage V_A of the analog ground pad Pad_A is less than the sum of the voltage V_P3 of the third power ground pad Pad_P3 and the preset voltage Vpre, i.e., V_A < V_P3 + Vpre, the third analog ground comparison signal S_A3 output by the third analog ground comparator CMP_A3 is a low-level signal.

[0096] The first OR gate OR1 receives the first analog ground comparison signal S_A1, the second analog ground comparison signal S_A2, and the third analog ground comparison signal S_A3, and performs an OR operation on the first analog ground comparison signal S_A1, the second analog ground comparison signal S_A2, and the third analog ground comparison signal S_A3. When there is a high-level signal among the first analog ground comparison signal S_A1, the second analog ground comparison signal S_A2, and the third analog ground comparison signal S_A3, the first OR gate OR1 outputs a high-level signal, that is, an analog ground abnormal signal is generated. When the first analog ground comparison signal S_A1, the second analog ground comparison signal S_A2, and the third analog ground comparison signal S_A3 are all low-level signals, the first OR gate OR1 outputs a high-level signal, that is, an analog ground normal signal is generated.

[0097] In other embodiments, the analog ground detection unit 111 may include two analog ground comparators CMP_A, namely the first analog ground comparator CMP_A1 and the second analog ground comparator CMP_A2. The non-inverting input terminals of the first analog ground comparator CMP_A1 and the second analog ground comparator CMP_A2 are connected to the analog ground pad Pad_A. The inverting input terminal of the first analog ground comparator CMP_A1 is connected to the first power ground pad Pad_P1, and the inverting input terminal of the second analog ground comparator CMP_A2 is connected to the second power ground pad Pad_P2, as Figure 7 shown.

[0098] Alternatively, the analog ground detection unit 111 may include more than three analog ground comparators CMP_A. The present disclosure does not specifically limit the number of the analog ground comparators CMP_A, but only limits the number of the analog ground comparators CMP_A to be equal to the number of the power ground pads Pad_P.

[0099] In some embodiments, see Figure 6 and Figure 7 The power ground detection unit 112 includes a second OR gate OR2 and N power ground comparators CMP_P, wherein the positive input terminal of the i-th power ground comparator CMP_Pi is connected to the i-th power ground pad Pad_Pi, the inverting input terminal of the i-th power ground comparator CMP_Pi is connected to the analog ground pad Pad_A, the output terminal of the i-th power ground comparator CMP_Pi is connected to the i-th input terminal of the second OR gate OR2, and the output terminal of the second OR gate OR2 is connected to the second input terminal of the output module 120.

[0100] The i-th power ground comparator CMP_Pi is configured to output a high level signal when the voltage V_Pi of the i-th power ground pad Pad_Pi is greater than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, and to output a low level signal when the voltage V_Pi of the i-th power ground pad Pad_Pi is less than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre.

[0101] The second OR gate OR2 is configured to generate a power abnormality signal when there is a high level signal among the N power comparison signals S_P, and to generate a power normal signal when there is no high level signal among the N power comparison signals S_P.

[0102] For example, Figure 6 As shown, the power detection unit 112 includes three power comparators CMP_P, namely a first power comparator CMP_P1, a second power comparator CMP_P2 and a third power comparator CMP_P3.

[0103] Among them, the inverting input terminal of the first power ground comparator CMP_P1, the inverting input terminal of the second power ground comparator CMP_P2 and the inverting input terminal of the third power ground comparator CMP_P3 are connected to the analog ground pad Pad_A, the non-inverting input terminal of the first power ground comparator CMP_P1 is connected to the first power ground pad Pad_P1, the non-inverting input terminal of the second power ground comparator CMP_P2 is connected to the second power ground pad Pad_P2, and the non-inverting input terminal of the third power ground comparator CMP_P3 is connected to the third power ground pad Pad_P3.

[0104] When the voltage V_P1 of the first power ground pad Pad_P1 is greater than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, i.e., V_P1 > V_A + Vpre, the first power ground comparison signal S_P1 output by the first power ground comparator CMP_P1 is a high-level signal. When the voltage V_P1 of the first power ground pad Pad_P1 is less than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, i.e., V_P1 < V_A + Vpre, the first power ground comparison signal S_P1 output by the first power ground comparator CMP_P1 is a low-level signal.

[0105] When the voltage V_P2 of the second power ground pad Pad_P2 is greater than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, i.e., V_P2 > V_A + Vpre, the second power ground comparison signal S_P2 output by the second power ground comparator CMP_P2 is a high-level signal. When the voltage V_P2 of the second power ground pad Pad_P2 is less than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, i.e., V_P2 < V_A + Vpre, the second power ground comparison signal S_P2 output by the second power ground comparator CMP_P2 is a low-level signal.

[0106] When the voltage V_P3 of the third power ground pad Pad_P3 is greater than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, i.e., V_P3 > V_A + Vpre, the third power ground comparison signal S_P3 output by the third power ground comparator CMP_P3 is a high-level signal. When the voltage V_P3 of the third power ground pad Pad_P3 is less than the sum of the voltage V_A of the analog ground pad Pad_A and the preset voltage Vpre, i.e., V_P3 < V_A + Vpre, the third power ground comparison signal S_P3 output by the third power ground comparator CMP_P3 is a low-level signal.

[0107] The second OR gate OR2 receives the first power ground comparison signal S_P1, the second power ground comparison signal S_P2, and the third power ground comparison signal S_P3, and performs an OR operation on the first power ground comparison signal S_P1, the second power ground comparison signal S_P2, and the third power ground comparison signal S_P3. When there is a high-level signal among the first power ground comparison signal S_P1, the second power ground comparison signal S_P2, and the third power ground comparison signal S_P3, the second OR gate OR2 outputs a high-level signal, that is, a power ground abnormal signal is generated. When the first power ground comparison signal S_P1, the second power ground comparison signal S_P2, and the third power ground comparison signal S_P3 are all low-level signals, the second OR gate OR2 outputs a low-level signal, that is, a power ground normal signal is generated.

[0108] In other embodiments, the power ground detection unit 112 may include two power ground comparators CMP_P, namely a first power ground comparator CMP_P1 and a second power ground comparator CMP_P2, an inverting input terminal of the first power ground comparator CMP_P1 and an inverting input terminal of the second power ground comparator CMP_P2 are connected to the analog ground pad Pad_A, a positive input terminal of the first power ground comparator CMP_P1 is connected to the first power ground pad Pad_P1, and a positive input terminal of the second power ground comparator CMP_P2 is connected to the second power ground pad Pad_P2, as shown in FIG. Figure 7 shown.

[0109] Alternatively, the power ground detection unit 112 may include more than three power ground comparators CMP_P. The present disclosure does not specifically limit the number of the power ground comparators CMP_P, but only limits the number of the power ground comparators CMP_P to be equal to the number of the power ground pads Pad_P.

[0110] Figure 8 A circuit diagram of a comparator provided in an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, the comparator CMP includes a current source IB, a resistor R, a first current mirror structure 210, a second current mirror structure 220 and a first transistor M1.

[0111] Among them, the input end of the first current mirror structure 210 is connected to the external power supply, the first output end of the first current mirror structure 210 is connected to the first ground pad through the current source IB, the second output end of the first current mirror structure 210 is connected to the first ground pad through the second current mirror structure 220, the third output end of the first current mirror structure 210 is connected to the second ground pad through the second current mirror structure 220 and the resistor R in sequence, and the fourth output end of the first current mirror structure 210 is connected to the first ground pad through the first transistor M1. The third output end of the first current mirror structure 210 is connected to the control end of the first transistor M1, and the fourth output end of the first current mirror structure 210 is connected to the output end of the comparator CMP.

[0112] Continue to see Figure 8 The first current mirror structure 210 includes a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5, wherein a first end of the second transistor M2, a first end of the third transistor M3, a first end of the fourth transistor M4 and a first end of the fifth transistor M5 are connected to an external power supply, and a control end of the second transistor M2 is connected to a second end of the second transistor M2, a control end of the third transistor M3, a control end of the fourth transistor M4 and a control end of the fifth transistor M5.

[0113] The second end of the second transistor M2 is connected to the first output end of the first current mirror structure 210, the second end of the third transistor M3 is connected to the second output end of the first current mirror structure 210, the second end of the fourth transistor M4 is connected to the third output end of the first current mirror structure 210, and the second end of the fifth transistor M5 is connected to the fourth output end of the first current mirror structure 210.

[0114] Exemplarily, the first transistor M1 is an N-type metal oxide semiconductor field effect transistor (NMOS), and the second transistor M2, the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are PMOS.

[0115] The source of the second transistor M2, the source of the third transistor M3, the source of the fourth transistor M4 and the source of the fifth transistor M5 are connected to an external power supply to receive a power supply voltage Vcc provided by the external power supply, and the drain of the second transistor M2 is connected to the first ground pad through the current source IB to receive a bias current Ibia provided by the current source IB.

[0116] The gate of the third transistor M3 is connected to the gate of the second transistor M2 and the drain of the second transistor M2 . The drain of the third transistor M3 is connected to the second current mirror structure 220 . The third transistor M3 can mirror the bias current Ibia into the first output current I1 and output it to the second current mirror structure 220 .

[0117] The gate of the fourth transistor M4 is connected to the gate of the second transistor M2 and the drain of the second transistor M2, and the drain of the fourth transistor M4 is connected to the gate of the first transistor M1. The fourth transistor M4 can mirror the bias current Ibia into a second output current I2 and output it to the gate of the first transistor M1, wherein the width-to-length ratio of the fourth transistor M4 is equal to the width-to-length ratio of the third transistor M3, then I2=I1.

[0118] The gate of the fifth transistor M5 is connected to the gate of the second transistor M2 and the drain of the second transistor M2, the drain of the fifth transistor M5 is connected to the drain of the first transistor M1, the source of the first transistor M1 is connected to the first ground pad, and the fifth transistor M5 can mirror the bias current Ibia into a third output current I3 and output it to the drain of the first transistor M1.

[0119] Continue to see Figure 8The second current mirror structure 220 includes a sixth transistor M6 and a seventh transistor M7, wherein the second end of the sixth transistor M6 is connected to the control end of the sixth transistor M6, the control end of the seventh transistor M7 and the second end of the third transistor M3, the first end of the sixth transistor M6 is connected to the first ground pad, the second end of the seventh transistor M7 is connected to the second end of the fourth transistor M4, and the first end of the seventh transistor M7 is connected to the second ground pad through the resistor R.

[0120] Exemplarily, the sixth transistor M6 and the seventh transistor M7 are NMOS, the drain of the sixth transistor M6 is connected to the gate of the sixth transistor M6, the gate of the seventh transistor M7 and the drain of the third transistor M3, the source of the sixth transistor M6 is connected to the first ground pad, and the source of the seventh transistor M7 is connected to the second ground pad through the resistor R.

[0121] The width-to-length ratio of the sixth transistor M6 is equal to that of the seventh transistor M7 , and the current capabilities of the sixth transistor M6 and the seventh transistor M7 are the same. The source voltage of the seventh transistor M7 is I2*R′, where R′ is the resistance value of the resistor R.

[0122] When the first ground pad is connected to the board-level GND, the first ground pad is normally connected, the voltage of the first ground pad is 0V, that is, the source voltage of the sixth transistor M6 is 0V, the gate-source voltage of the sixth transistor M6 is greater than the gate-source voltage of the seventh transistor M7, and the current capacity of the seventh transistor M7 is less than the current capacity of the sixth transistor M6.

[0123] At this time, the current capacity of the fourth transistor M4 is greater than the current capacity of the seventh transistor M7, and the fourth transistor M4 can pull up the gate voltage of the first transistor M1, so the first transistor M1 is turned on, the drain voltage of the first transistor M1 is pulled down by the first transistor M1, and the comparator CMP outputs a low level signal.

[0124] When the first ground pad is not connected to the board-level GND, the first ground pad is abnormally connected, the first ground pad is in a floating state, the voltage of the first ground pad is greater than I2*R', and I2*R' is defined to be equal to the preset voltage Vpre, that is, the source voltage of the sixth transistor M6 is greater than the preset voltage Vpre, and the gate-source voltage of the sixth transistor M6 is less than the gate-source voltage of the seventh transistor M7, then the current capacity of the seventh transistor M7 is greater than the current capacity of the sixth transistor M6.

[0125] At this time, the current capacity of the fourth transistor M4 is smaller than that of the seventh transistor M7. The seventh transistor M7 can pull down the gate voltage of the first transistor M1, and the first transistor M1 is turned off. The drain voltage of the first transistor M1 is pulled up by the fifth transistor M5, and the comparator CMP outputs a high level signal.

[0126] Based on the above embodiment, when the comparator CMP is an analog ground comparator CMP_A, the first ground pad is the analog ground pad Pad_A, and the second ground pad is the power ground pad Pad_P. If the analog ground pad Pad_A is normally connected, the analog ground comparator CMP_A outputs a low-level signal. If the analog ground pad Pad_A is abnormally connected, the analog ground comparator CMP_A outputs a high-level signal.

[0127] When the comparator CMP is a power ground comparator CMP_P, the first ground pad is the power ground pad Pad_P, and the second ground pad is the analog ground pad Pad_A. If the power ground pad Pad_P is normally connected, the power ground comparator CMP_P outputs a low level signal. If the power ground pad Pad_P is abnormally connected, the power ground comparator CMP_P outputs a high level signal.

[0128] In some embodiments, see Figure 8 The comparator CMP also includes a capacitor C, a first Schmitt trigger SCHMITT1 and a second Schmitt trigger SCHMITT2, wherein the third output end of the first current mirror structure 210 is connected to the control end of the first transistor M1 through the first Schmitt trigger SCHMITT1, the fourth output end of the first current mirror structure 210 is connected to the output end of the comparator CMP through the second Schmitt trigger SCHMITT2, and the fourth output end of the first current mirror structure 210 is also connected to the first ground pad through the capacitor C.

[0129] Exemplarily, the capacitor C is connected between the first ground pad and the input terminal of the second Schmitt trigger SCHMITT2, which can filter out circuit noise to stabilize the input voltage of the second Schmitt trigger SCHMITT2, thereby avoiding the impact of transient mutations introduced by circuit noise on the output signal of the comparator CMP.

[0130] When the drain voltage of the seventh transistor M7 is greater than the first threshold, the first Schmitt trigger SCHMITT1 outputs a high level signal to turn on the first transistor M1. When the drain voltage of the seventh transistor M7 is less than the second threshold, the first Schmitt trigger SCHMITT1 outputs a low level signal to turn off the first transistor M1. The second threshold is less than the first threshold, which can prevent the unstable drain voltage of the seventh transistor M7 from affecting the output signal of the comparator CMP.

[0131] When the drain voltage of the first transistor M1 is less than the third threshold, the second Schmitt trigger SCHMITT2 outputs a low level signal, and the comparator CMP outputs a low level signal. When the drain voltage of the first transistor M1 is greater than the fourth threshold, the second Schmitt trigger SCHMITT2 outputs a high level signal, and the comparator CMP outputs a high level signal. The third threshold is less than the fourth threshold, which can avoid the unstable drain voltage of the first transistor M1 from affecting the output signal of the comparator CMP.

[0132] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural form and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0133] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A pin detection circuit for a power management chip, characterized in that: The power management chip comprises an analog ground pad, an analog ground pin, N power ground pads and N power ground pins, the analog ground pad is grounded through the analog ground pin, each of the power ground pads is grounded through one of the power ground pins, and N is an integer greater than 1; The pin detection circuit comprises: a detection module and an output module; The first input terminal of the detection module is connected to the analog ground pad, the N second input terminals of the detection module are connected to the N power ground pads in a one-to-one correspondence, and the output terminal of the detection module is connected to the input terminal of the output module; The detection module is configured to compare the difference between the voltage of each of the power ground pads and the voltage of the analog ground pad with a preset voltage to obtain N power ground comparison signals and N analog ground comparison signals, determine the analog ground detection signal according to the N analog ground comparison signals, and determine the power ground detection signal according to the N power ground comparison signals; The output module is configured to generate a ground pin abnormal connection indication signal when the analog ground detection signal is an analog ground abnormal signal or the power ground detection signal is a power ground abnormal signal; The detection module includes an analog ground detection unit and a power ground detection unit; The first input end of the analog ground detection unit and the second input end of the power ground detection unit are connected to the analog ground pad, the N second input ends of the analog ground detection unit are connected to the N power ground pads in a one-to-one correspondence, the N first input ends of the power ground detection unit are connected to the N power ground pads in a one-to-one correspondence, the output end of the analog ground detection unit is connected to the first input end of the output module, and the output end of the power ground detection unit is connected to the second input end of the output module; The analog ground detection unit is configured to compare the voltage of each power ground pad with the sum of the preset voltage and the voltage of the analog ground pad to obtain N analog ground comparison signals, and determine the analog ground detection signal according to whether there is a high-level signal in the N analog ground comparison signals; The power ground detection unit is configured to compare the voltage of the analog ground pad, the sum of the preset voltage and the voltage of each power ground pad to obtain N power ground comparison signals, and determine the power ground detection signal according to whether there is a high-level signal in the N power ground comparison signals; The output module comprises a third OR gate; a first input end of the third OR gate is connected to the output end of the analog ground detection unit, and a second input end of the third OR gate is connected to the output end of the power ground detection unit.

2. The pin detection circuit according to claim 1, characterized in that: The analog ground detection unit includes a first OR gate and N analog ground comparators; The non-inverting input terminal of the i-th analog ground comparator is connected to the analog ground pad, the inverting input terminal of the i-th analog ground comparator is connected to the i-th power ground pad, the output terminal of the i-th analog ground comparator is connected to the i-th input terminal of the first OR gate, and the output terminal of the first OR gate is connected to the first input terminal of the output module, wherein 1≤i≤N and i is an integer; The i-th analog ground comparator is configured to output a high level signal when the voltage of the analog ground pad is greater than the sum of the voltage of the i-th power ground pad and the preset voltage, and output a low level signal when the voltage of the analog ground pad is less than the sum of the voltage of the i-th power ground pad and the preset voltage; The first OR gate is configured to generate the analog ground abnormal signal when the high level signal exists in the N analog ground comparison signals; and to generate the analog ground normal signal when the high level signal does not exist in the N analog ground comparison signals.

3. The pin detection circuit according to claim 1, characterized in that: The power detection unit includes a second OR gate and N power comparators; The positive input terminal of the i-th power-to-ground comparator is connected to the i-th power-to-ground pad, the inverting input terminal of the i-th power-to-ground comparator is connected to the analog ground pad, the output terminal of the i-th power-to-ground comparator is connected to the i-th input terminal of the second OR gate, and the output terminal of the second OR gate is connected to the second input terminal of the output module, wherein 1≤i≤N and i is an integer; The i-th power-ground comparator is configured to output a high level signal when the voltage of the i-th power-ground pad is greater than the sum of the voltage of the analog ground pad and the preset voltage, and output a low level signal when the voltage of the i-th power-ground pad is less than the sum of the voltage of the analog ground pad and the preset voltage; The second OR gate is configured to generate the power abnormal signal when the high level signal exists in the N power comparison signals; and to generate the power normal signal when the high level signal does not exist in the N power comparison signals.

4. The pin detection circuit according to claim 2 or 3, characterized in that: The comparator includes a current source, a resistor, a first current mirror structure, a second current mirror structure and a first transistor; The input end of the first current mirror structure is connected to an external power supply, the first output end of the first current mirror structure is connected to a first ground pad through the current source, the second output end of the first current mirror structure is connected to the first ground pad through the second current mirror structure, the third output end of the first current mirror structure is connected to the second ground pad through the second current mirror structure and the resistor in sequence, the fourth output end of the first current mirror structure is connected to the first ground pad through the first transistor, the third output end of the first current mirror structure is connected to the control end of the first transistor, and the fourth output end of the first current mirror structure is connected to the output end of the comparator; When the comparator is an analog ground comparator, the first ground pad is the analog ground pad, and the second ground pad is the power ground pad; when the comparator is a power ground comparator, the first ground pad is the power ground pad, and the second ground pad is the analog ground pad.

5. The pin detection circuit according to claim 4, characterized in that: The first current mirror structure includes a second transistor, a third transistor, a fourth transistor and a fifth transistor, and the width-to-length ratio of the third transistor is equal to the width-to-length ratio of the fourth transistor; The first end of the second transistor, the first end of the third transistor, the first end of the fourth transistor and the first end of the fifth transistor are connected to the external power supply, and the control end of the second transistor is connected to the second end of the second transistor, the control end of the third transistor, the control end of the fourth transistor and the control end of the fifth transistor; The second end of the second transistor is connected to the first output end of the first current mirror structure, the second end of the third transistor is connected to the second output end of the first current mirror structure, the second end of the fourth transistor is connected to the third output end of the first current mirror structure, and the second end of the fifth transistor is connected to the fourth output end of the first current mirror structure.

6. The pin detection circuit according to claim 5, characterized in that: The second current mirror structure includes a sixth transistor and a seventh transistor, and the width-to-length ratio of the sixth transistor is equal to the width-to-length ratio of the seventh transistor; The second end of the sixth transistor is connected to the control end of the sixth transistor, the control end of the seventh transistor and the second end of the third transistor, the first end of the sixth transistor is connected to the first ground pad, the second end of the seventh transistor is connected to the second end of the fourth transistor, and the first end of the seventh transistor is connected to the second ground pad through the resistor.

7. The pin detection circuit according to claim 4, characterized in that: The comparator further includes a capacitor, a first Schmitt trigger and a second Schmitt trigger; The third output end of the first current mirror structure is connected to the control end of the first transistor through the first Schmitt trigger, the fourth output end of the first current mirror structure is connected to the output end of the comparator through the second Schmitt trigger, and the fourth output end of the first current mirror structure is also connected to the first ground pad through the capacitor.

8. A power management chip, characterized in that: It comprises an analog ground pad, an analog ground pin, N power ground pads, N power ground pins and the pin detection circuit according to any one of claims 1 to 7.

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