Ultra-low power consumption Doppler radar chip capable of reducing duty ratio and improving impedance and method thereof

Abstract

According to the ultra-low power consumption Doppler radar chip capable of reducing the duty ratio and improving the impedance and the method thereof, the chip comprises a register, a control circuit, an analog delay circuit, an impedance control switch, a differential amplifier and the like, and the charge leakage amount of a sampling capacitor during the non-working period of a radio frequency circuit is reduced by improving the turn-off impedance of a frequency mixer; and the input impedance of the amplifier is improved to reduce PWM ripples on an intermediate frequency signal, so that the detection performance of a radar chip during intermittent working of a radio frequency circuit under the control of a PWM power-saving pulse is maintained as much as possible, a conventional power-saving mode is changed into an ultra-low power consumption mode, and the working current of a radar module is reduced from several milliamperes to dozens of microamperes. The method can be used for any motion induction radar sensor chip and module with power-saving control, especially a battery-powered access control system and a low-cost bulb lamp in a capacitor voltage reduction mode of high-voltage partial-voltage power supply.

Description

Technical Field

[0001] The present invention relates to the field of radar sensor chips, in particular to an ultra-low power Doppler radar chip and method thereof that reduces duty cycle and increases impedance, and narrows the pulse width of a pulse width modulation signal (PWM power-saving pulse) with a wide pulse width generated by a low-frequency clock source, thereby reducing the duty cycle to reduce the average operating current of the module and the design method of the ultra-low power Doppler radar chip and module. This solution reduces the influence of PWM ripple on detection sensitivity by increasing impedance, is compatible with ultra-low power applications and non-ultra-low power applications, and has high commercial value. Background Art

[0002] Battery-powered products such as access control systems often use infrared pyroelectric sensors to identify whether someone is approaching the access control system, thereby turning on the more power-hungry CMOS camera to start face recognition and fingerprint recognition. Battery-powered automatic lighting facilities such as night lights also require ultra-low power sensors to identify whether there are moving objects approaching the lamps, and to maintain ultra-long standby capabilities, reduce the number of charging times, and realize automatic lighting that turns on the lights when people come and turns off the lights when people leave. However, infrared sensors use Fresnel lenses. If the lens is too small, the sensitivity is not high, and if the lens is too large, it is difficult to install, affecting the appearance. In addition, if the infrared sensor is used for too long, the sensitivity may be affected by the aging and reduced transparency of the organic glass used to make the lens. On hot nights in the south, infrared sensors will also lose their long-distance sensing capabilities because the human body temperature is basically the same as the ambient temperature.

[0003] Microwave radar sensors based on the Doppler effect can be built into access control systems or lamps to be completely invisible, which has unique advantages. However, Doppler radars that work continuously consume a lot of power, and the operating current is generally above 10mA. Even though the cost of radar modules made of radar chips and low-cost microprocessors (MCUs) has been greatly reduced, the power consumption disadvantage still hinders the process of radar sensors replacing infrared sensors. If a pulse working mode is used to allow the RF circuit to work intermittently at a low duty cycle, and only micro-power circuits such as intermediate frequency amplifiers work for a long time, the average operating current of the radar chip can be reduced without changing the algorithm, thereby realizing a micro-power radar module and making it possible for radar sensors to replace infrared sensors.

[0004] In order to generate a power-saving control pulse width modulation signal (PWM), the radar sensor chip needs to have a built-in oscillator and a counter-based PWM signal generator. However, the oscillator based on the inverter plus resistor and the external capacitor method generally needs to consider whether it can start oscillation at low temperature, and it is difficult to reduce the power consumption to less than 10uA. Even if the radar chip integrates a power-saving control pulse generator, an ultra-low power analog-to-digital converter and an internal processor to make a system-level (SOC) radar chip with a trigger function, another independent ultra-low power MCU is required on the module because the radar chip has few pins and it is inconvenient to set different parameters. Different distance parameters and delay parameters are set on the module with different voltage divider resistors. The external MCU samples these setting signals and transmits them to the radar chip through the I2C or UART port. Therefore, the radar module made of the radar sensor chip with a built-in processor will have a high cost due to the redundancy of the microprocessor (MCU). Under the large market conditions of tens of millions of sensors, it will be difficult to obtain a good return on investment due to the cost disadvantage, and it will also slow down the pace of radar sensors replacing infrared sensors. The key issue is that the ultra-low power radar module requires a pulse width modulation (PWM) of about 1us. If a clock of more than 1MHz is used to generate the pulse width modulation (PWM) signal, the clock cannot be powered off and needs to work for a long time. The microprocessor uses this high-frequency clock to generate the PWM control signal of the ultra-low power radar module, which requires hundreds of microamperes of current. It is difficult to reduce power consumption, so an ultra-low power PWM pulse signal generator must be built into the radar chip.

[0005] CN111867025A discloses a low-power microwave sensor and its control circuit. Its working principle is mainly to sample the capacitor after the operational amplifier. The operational amplifier is a push-pull output, with PMOS on the upper side of the output and NMOS on the lower side. When the operational amplifier stops working, the upper and lower MOS tubes are not turned on, thus forming a high impedance. Correspondingly, its patent is low power consumption rather than ultra-low power consumption, that is, the CU needs about 100uA of current to generate a PWM signal with a corresponding pulse width. Summary of the invention

[0006] The purpose of the present invention is to provide an ultra-low power consumption Doppler radar chip and method thereof that reduces duty cycle and increases impedance, by increasing mixer off impedance to reduce charge leakage of sampling capacitor during non-operating period of radio frequency circuit, and increasing amplifier input impedance to reduce PWM ripple on intermediate frequency signal, thereby maintaining the detection performance of radar chip when radio frequency circuit works intermittently under PWM power saving pulse control as much as possible, converting conventional power saving mode into ultra-low power consumption mode, and reducing radar module operating current from several milliamperes to tens of microamperes. This method can be used for any motion sensing radar sensor chip and module with power saving control, especially battery-powered access control system, and low-cost bulb lamp with capacitor step-down mode powered by high voltage voltage division.

[0007] An ultra-low power consumption Doppler radar chip with reduced duty cycle and increased impedance comprises a register and a control circuit. The register is read and written via an I2C serial interface (the I2C serial interface is a 2-wire serial interface originally defined by Philips for consumer products) to set parameters. The control circuit can receive a pulse width modulation signal PWM_OUT output by an external microprocessor and input it into a PWM_IN pin of the radar chip to expand the application mode, and prevent a large current at startup through the PWM_IN pin. The control circuit body comprises an OR gate and an AND gate, which OR an external pulse width modulation signal with a pulse width modulation signal inside the chip, and prohibit the internal pulse width modulation signal by ANDing the control signal of the register with the AND gate. The method of preventing a large current at startup is to connect the PWM_IN pin to a power supply with a resistor on the radar module, and before the low-frequency clock of the chip starts to oscillate and the microprocessor works normally, the power-off control signals described later are set to a high level, so that the radio frequency circuit with a large working current does not work temporarily.

[0008] A coarse pulse width modulation signal generator with a clock oscillator is connected to the control circuit to generate a coarse pulse width modulation signal with a frequency of several hundred Hz and a duty cycle of 1 / M, where M is 8N and N is a positive integer greater than or equal to 1;

[0009] The analog delay circuit is connected to the coarse pulse width modulation signal generator, and different delay times are set by registers to delay the coarse pulse width modulation signal to generate a fine pulse width modulation signal with a low-level pulse width of hundreds of nanoseconds to several microseconds and a period of hundreds of microseconds to several milliseconds, and is connected to the power-off control end of a circuit with a high working frequency and a large working current in the radio frequency circuit but a fast working state after power-on;

[0010] Voltage controlled oscillator, used to generate RF signal and local oscillator signal, and with power-off function;

[0011] The RF power amplifier is connected to the voltage-controlled oscillator and is used to amplify the RF signal. It has a power-off function. The RF signal is sent to the transceiver integrated PCB antenna on the radar module. The antenna transmits the RF signal and receives the echo signal.

[0012] A low-noise RF amplifier is connected to the transceiver integrated PCB antenna on the radar module and has a power-off function to amplify the echo signal;

[0013] The mixer is connected to the low-noise RF amplifier and the voltage-controlled oscillator and has a power-off function. The mixer mixes the echo signal amplified by the low-noise RF amplifier and the local oscillator signal of the voltage-controlled oscillator. The intermediate frequency signal obtained by mixing is the Doppler frequency signal.

[0014] The impedance control switch is connected to the output end of the mixer, and the radar module is provided with a sampling and holding capacitor, one end of the sampling and holding capacitor is connected to the impedance control switch, and the other end of the sampling and holding capacitor is grounded;

[0015] The differential amplifier, as the first-stage intermediate frequency amplifier, is connected to the impedance control switch through the gain resistors Rgp and Rgn and the DC blocking capacitors Cdcp and Cdcn on the radar module to amplify the Doppler frequency signal and perform common-mode suppression to reduce the common-mode interference during intermittent operation and other common-mode interference (such as 50Hz / 60Hz power frequency interference); wherein the output end of the differential amplifier is connected back to the input end of the differential amplifier through the feedback resistors Rfp and Rfn on the radar module, and the gain of the differential amplifier is determined by the ratio of the feedback resistor to the gain resistor; and

[0016] The single operational amplifier, as the second-stage intermediate frequency amplifier, has its inverting input connected to any output of the differential amplifier through the gain resistor Rg and the DC blocking capacitor Cdc on the radar module, further amplifies the Doppler signal and performs appropriate filtering, and connects the output of the differential amplifier to the microprocessor with a built-in analog-to-digital converter on the radar module. After sampling the Doppler signal output by the radar chip through the analog-to-digital converter, the microprocessor distinguishes between noise and effective radar sensing signals; wherein, the output of the single operational amplifier is connected back to the inverting input of the single operational amplifier through the feedback resistor Rf and the feedback capacitor on the radar module, and the non-inverting input of the single operational amplifier is connected to a reference level of 1 / 2 of the power supply voltage inside the chip; the size of the DC blocking capacitor Cdc on the radar module determines the bandwidth of the high-pass filter, and the size of the feedback capacitor on the radar module determines the bandwidth of the low-pass filter;

[0017] Among them, the microprocessor is a low-power microprocessor with a low-frequency clock, a low-power working mode and a sleep mode, and the microprocessor has a timed wake-up function. In the sleep mode, the microprocessor core stops working to reduce power consumption, but the low-frequency clock continues to oscillate and the wake-up timer continues to count; in addition, the pulse width modulation signal PWM_OUT output by the microprocessor can be used to generate a pulse width modulation signal and send it to the PWM_IN input port of the radar chip when the duty cycle is not too low and the power consumption requirement is not harsh, and the microprocessor performs synchronous sampling in an interrupt mode to reduce the influence of the pulse width modulation ripple and improve performance.

[0018] A method for reducing duty cycle and increasing impedance comprises the following steps:

[0019] Step 1, the PWM_IN input port of the control circuit is connected to the power supply with a pull-up resistor, and the RF circuit control signal is pulled up to a high level within a few microseconds of the initial power-on time to turn off the RF circuit to prevent a large current from being turned on; thereafter, the internal clock oscillator of the chip starts to work, and the coarse pulse width modulation signal generator has generated a coarse pulse width modulation signal to control the RF circuit to work intermittently, and the coarse pulse width modulation signal can be transmitted to the analog delay circuit or output to the microprocessor for interrupt sampling or sleep wake-up (INT / WAKE UP);

[0020] Step 2, delaying the coarse pulse width modulation signal of step 1 by using a low-power analog delay circuit set by a chip register to generate an analog delay of hundreds of nanoseconds to several microseconds, and generating a fine pulse width modulation signal with a low-level pulse width of hundreds of nanoseconds to several microseconds and a period of hundreds of microseconds to several milliseconds;

[0021] Step 3, the external standard microprocessor controls the internal enable and delay time of the chip by reading and writing registers through I2C or uses the PWM_EN pin to control the enable of the pulse width modulation signal inside the chip, and sends the pulse width modulation signal with adjustable duty cycle generated inside the chip to the RF circuit power-off control port of the radar sensor chip; wherein, the enable control is implemented by ANDing the PWM_EN control signal with the pulse width modulation signal generated inside the chip through an AND gate to generate a fine-tuning pulse width modulation signal (FINE PWM), when PWM_EN is at a low level, the fine-tuning pulse width modulation signal FIN_PWM becomes a constant low level, and when PWM_EN is at a high level, the fine-tuning pulse width modulation signal FINE_PWM is a pulse width modulation signal with adjustable duty cycle generated inside the chip;

[0022] Step 4: The voltage-controlled oscillator generates a radio frequency signal and a local oscillator signal. The radio frequency signal is amplified by the power amplifier and then transmitted through the transceiver integrated PCB antenna. The voltage-controlled oscillator and the power amplifier both have power-off control ports. Changing the level of the power-off port can allow them to start working or stop working quickly.

[0023] Step 5, the transceiver integrated PCB antenna receives the echo signal, and after amplification by the low-noise RF amplifier, the echo signal and the local oscillator signal are mixed by a mixer to obtain a Doppler frequency signal; wherein, the low-noise RF amplifier and the mixer both have a power-off control port, and changing the level of the power-off port can make them start working quickly or stop working quickly;

[0024] Step 6, the Doppler frequency signal output by the mixer passes through an impedance conversion switch (SW) to the sampling and holding capacitors Csp and Csn and the differential amplifier (the first intermediate frequency amplifier A); wherein the output amplitude of the mixer is determined by the operating current of the mixer and the load resistances Rsp and Rsn on the drain, and the larger the load resistance, the larger the output amplitude; wherein the impedance conversion switch (SW) is closed during the operation of the RF circuit and is disconnected during the non-operation of the RF circuit; during the period when the mixer stops working, its DC voltage will be pulled up to the power supply voltage VDD of the RF circuit because the load resistance is not disconnected; comparatively speaking, if an analog switch (SW) made of PMOS and NMOS is connected in series in the load resistance branch, it can also play a role in increasing the impedance, but this requires that the MOS switch can operate at the RF frequency;

[0025] Step 7, the signal voltage on the sampling and holding capacitor is connected to the input end of the differential amplifier through the DC blocking capacitor, and its gain resistors Rgp and Rgn; a large resistor is used to increase the input impedance of the differential amplifier, and at the same time, the feedback resistors Rfp and Rfn are increased in proportion; the required amplification factor is maintained, that is, the original gain is maintained, and the common-mode suppression capability of the differential amplifier is used to suppress common-mode interference and common-mode noise as much as possible, so that the subsequent amplifier can further amplify;

[0026] Step 8: After the output voltage of the differential amplifier passes through the DC blocking capacitor Cdc, it is sent to the single op amp for further amplification. At the same time, a feedback capacitor of appropriate size can be connected in parallel to the feedback resistor Rf for low-pass filtering to reduce PWM ripple and various noises.

[0027] Step 9: The analog-to-digital converter inside the microprocessor digitizes the analog intermediate frequency signal, performs algorithm processing, and determines whether to output a trigger signal for radar sensing.

[0028] Compared with the previous technology, the beneficial effects of the present invention are:

[0029] 1. This solution uses a low-frequency oscillator and a preliminary PWM signal generator to generate a fine-tuning PWM signal, which realizes the generation of PWM signals with extremely low power consumption; the analog delay method is used to reduce the pulse width of the PWM signal, and extremely low power consumption is used to generate a very small duty cycle (generally less than 3uA), which greatly reduces the average RF current of the radar chip, thereby reducing the circuit cost of powering the radar chip; because it does not rely on the microprocessor (MCU) to provide PWM signals (MCU generally requires more than 100uA of current to provide PWM signals), the low-power microprocessor runs with a low-frequency clock and sleeps after sampling and then wakes up. The average power consumption of the MCU is extremely low, thereby reducing the total power consumption of the radar module, which is suitable for battery-powered scenarios; this solution increases the impedance at both ends of the sampling and holding capacitor to ensure that the sensing distance decreases little after the average operating current of the radar chip is reduced, and the performance of the radar module is kept as low as possible;

[0030] The PWM working pulse width of this solution is very narrow, and the working time of the radar chip RF circuit is very short (0.5us, 1us, 2us, etc.). Generally, the internal resistance of the mixer output is in the range of hundreds of ohms. In such a short time, the voltage on the sampling and holding capacitor can only be reduced to track from the last working voltage to the next working voltage by reducing the capacity of the sampling and holding capacitor. For example, if the internal resistance of the mixer output is 100 ohms, the charging time constant of the external 10nF sampling and holding capacitor is 1us. A larger sampling and holding capacitor will lead to insufficient charging and a smaller signal amplitude, resulting in an increase in the noise contribution of the post-stage amplifier and a reduction in the signal-to-noise ratio of the radar module. However, the RF circuit does not work for more than 2ms. In order to prevent the voltage on the sampling and holding capacitor from changing too much, a large discharge time constant is required, such as about 2ms. Since the capacitance value cannot be increased, it is necessary to disconnect the sampling and holding capacitor from the mixer during the period when the RF circuit is not working, and increase the impedance of the amplifier input to, for example, more than 200k ohms. Another way is to amplify the mixer output first and use a low-resistance output to reduce the charging time constant of the sampling and holding capacitor (for example, reduce the amplifier output resistance to less than 2 ohms so that a sampling and holding capacitor of about 0.47uF can be used). However, this method requires the amplifier to be stable in about 1us, that is, the gain-bandwidth product of the amplifier is high enough and the slew rate is large enough, which is difficult to achieve in a micro-power amplifier below 10uA. Therefore, this solution can reduce the operating current of the amplifier that is always working. This solution does not use the method commonly used by analog-to-digital converters to switch the sampling and holding capacitor to the input and feedback ends of the amplifier, which simplifies the circuit design and adapts to extremely low duty cycles, because the sampling and holding front end of ordinary analog-to-digital converters requires a duty cycle of about 50% of the sampling clock. This solution uses an external sampling capacitor to avoid making a large capacitor inside the chip, reducing the chip area, and thus reducing the chip cost. The input of the mixer to the differential amplifier uses an AC coupling method with an off-chip capacitor to block DC, and the differential amplifier to the post-amplifier also uses an AC coupling method with an off-chip capacitor to block DC, which avoids the trouble of designing an ultra-low offset voltage amplifier, reduces the design difficulty, and reduces the chip area. This solution uses differential amplification, which can use the high common-mode suppression capability of the differential amplifier to suppress the common-mode interference caused by the DC level change of the self-mixing circuit, and also suppresses the common-mode level interference of intermittent operation, while suppressing 50Hz / 60Hz power frequency interference, further reducing noise, thereby improving the performance of the radar module, that is, increasing the sensing distance at the same power consumption.

[0031] 2. Compared with the method of using a high-frequency oscillator inside the chip to make a PWM generator of more than 10 bits, the corresponding circuit of the present invention has lower power consumption; compared with the power-saving method of directly using the PWM signal provided by the MCU to control the RF circuit without processing, this solution has a lower duty cycle than when the MCU directly provides the PWM signal, so the module current can be reduced to a smaller level; the present invention supports the pulse group working mode, which can use photosensitive detection to stop the RF circuit during the day to reduce power consumption, and allow the total current to be further reduced by reducing the detection per second in ultra-low power consumption applications.

[0032] 3. This solution is compatible with conventional power consumption without PWM power saving, ordinary low power consumption with MCU providing PWM power saving pulses, and ultra-low power consumption with chip providing PWM power saving pulses. It also supports synchronous sampling, so the performance is higher than asynchronous sampling, reducing the number of chips for radar chip companies and reducing R&D costs. This solution eliminates the redundancy of external MCUs and processors within the chip, thus lowering module costs. The use of external MCUs allows different customers to choose MCUs with different resources and different algorithms for different applications. The use of external MCUs eliminates the IP costs of radar chip companies to purchase processor cores, avoids the R&D costs of self-developed processors and low-power algorithms, can spread chip costs, speed up product launches, gain competitive advantages, and speed up the replacement of infrared sensors.

[0033] When the PWM duty cycle is 1 / 256 to 255 / 256, the PWM signal of this solution can be provided by the internal clock of the MCU, so the MCU can use the synchronous sampling solution under the PWM interrupt mode; when the PWM duty cycle is 1 / 2 to 1 / 32 or 1 / 250 to 1 / 5000, the PWM signal is provided by the radar chip, but the MCU can still use the I / O pin interrupt or wake-up method for synchronous sampling. The advantage of synchronous sampling is that when the PWM frequency is relatively low, the intermediate frequency amplifier is not required to perform perfect low-pass filtering to reduce the PWM ripple to less than 1mV, and there is no need to use a digital low-pass filter, which can further reduce power consumption, improve performance, and have a longer sensing distance under the same power consumption conditions. Using MCU as an algorithm, complex algorithms can be used in conventional power saving methods, and simple algorithms can be used in ultra-low power consumption, so as to achieve perfect compatibility of the same radar module with different applications, which can support ultra-low power consumption close-range detection powered by batteries, and can also be compatible with home lighting applications with a bulb lamp of about 1mA hanging height of 3 meters and a sensing distance of about 2 meters. Because the module current of about 1mA can be applied to the extremely low-cost radar module power supply method of using a large resistor to divide the voltage from the rectified high-voltage DC power in the RC step-down mode, it can directly replace the infrared sensor. It does not affect the aesthetics of the lamp in the application of bulb lamps at all, and it is convenient for individuals to replace ordinary light bulbs with radar sensor lamps in their own corridors, hallways, toilets, etc., so it has huge commercial value. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the impedance enhancement and radar system working principle of the present invention;

[0035] Figure 2 This is the intermediate frequency signal waveform when the impedance of the sampling and holding circuit is not high enough;

[0036] Figure 3 It is a circuit diagram of low power consumption 1 / 16 coarse pulse width modulation signal (COARSE PWM);

[0037] Figure 4 The circuit diagram of the fine pulse width modulation signal (FINE PWM) using a time delay mode of the present invention;

[0038] Figure 5 A circuit diagram of the present invention for narrowing the low-level pulse width by using simulated delay;

[0039] Figure 6 The waveform diagram of the PWM low-level pulse width narrowing using the analog delay method of the present invention;

[0040] Figure 7 This is a step diagram of the method for reducing duty cycle and increasing impedance according to the present invention. DETAILED DESCRIPTION

[0041] The present invention is described in detail below in conjunction with the accompanying drawings:

[0042] like Figure 1-6 As shown: An ultra-low power consumption Doppler radar chip with reduced duty cycle and increased impedance, including

[0043] Registers and control circuits, the registers are read and written through the I2C serial interface and are used to set parameters; the control circuit can receive the pulse width modulation signal PWM_OUT output by the external microprocessor and input it to the PWM_IN pin to prevent high current at startup; wherein, the main body of the control circuit is an OR gate and an AND gate, which ORs the external pulse width modulation signal with the pulse width modulation signal inside the chip, and prohibits the internal pulse width modulation signal by ANDing the control signal of the register through the AND gate; wherein, the method of preventing high current at startup is to connect the PWM_IN pin to the power supply with a resistor on the radar module, and before the low-frequency clock of the chip starts to oscillate and the microprocessor works normally, the power-off control signals described later are set to a high level, so that the RF circuit with large working current does not work temporarily;

[0044] The present invention uses a low-frequency oscillator and a clock signal divided by 2 for 3 to 5 times to generate a pulse width modulation signal with a higher duty cycle by means of phase OR, and then uses analog delay and inverting AND to reduce the pulse width to reduce the duty cycle of the pulse width modulation signal (PWM power saving control pulse), and increases the off impedance of the mixer output end in the signal chain and the input impedance of the amplifier to reduce the PWM ripple.

[0045] A coarse pulse width modulation signal generator with a clock oscillator is connected to the control circuit to generate a coarse pulse width modulation signal with a frequency of several hundred Hz and a duty cycle of 1 / M, where M is 8N and N is a positive integer greater than 1;

[0046] The analog delay circuit is connected to the coarse pulse width modulation signal generator, and different delay times are set by registers to delay the coarse pulse width modulation signal to generate a fine pulse width modulation signal with a low-level pulse width of hundreds of nanoseconds to several microseconds and a period of hundreds of microseconds to several milliseconds, and is connected to the power-off control end of a circuit with a high working frequency and a large working current in the radio frequency circuit but a fast working state after power-on;

[0047] Specifically, the analog delay circuit uses a current source to charge and discharge the capacitor to delay the coarse pulse width modulation signal, generating an analog delay (N us) of hundreds of nanoseconds to several microseconds, and delays the coarse pulse width modulation signal to generate a fine pulse width modulation signal (FINE PWM) with a low-level pulse width of hundreds of nanoseconds to several microseconds and a period of hundreds of microseconds to several milliseconds, which is connected to the power-off control terminal of the radio frequency circuit; wherein the delay time is achieved by switching the current size of the current source and switching capacitors of different capacitance values, and the delay time can be set by an external pin or an internal register;

[0048] Voltage controlled oscillator, used to generate RF signal and local oscillator signal, and with power-off function;

[0049] The RF power amplifier is connected to the voltage-controlled oscillator and is used to amplify the RF signal. It has a power-off function. The RF signal is sent to the transceiver integrated PCB antenna on the radar module. The antenna transmits the RF signal and receives the echo signal.

[0050] A low-noise RF amplifier is connected to the transceiver integrated PCB antenna on the radar module and has a power-off function to amplify the echo signal;

[0051] The mixer is connected to the low-noise RF amplifier and the voltage-controlled oscillator and has a power-off function. The mixer mixes the echo signal amplified by the low-noise RF amplifier and the local oscillator signal of the voltage-controlled oscillator. The intermediate frequency signal obtained by mixing is the Doppler frequency signal.

[0052] The impedance control switch is connected to the output end of the mixer, and the radar module is provided with a sampling and holding capacitor, one end of the sampling and holding capacitor is connected to the impedance control switch, and the other end of the sampling and holding capacitor is grounded;

[0053] The differential amplifier, as a first-stage intermediate frequency amplifier, is connected to the impedance control switch through the gain resistors Rgp and Rgn and the DC blocking capacitors Cdcp and Cdcn on the radar module to amplify the Doppler frequency signal; wherein the output of the differential amplifier is connected back to the input of the differential amplifier through the feedback resistors Rfp and Rfn on the radar module, and the gain of the differential amplifier is determined by the ratio of the feedback resistor to the gain resistor; and

[0054] The single operational amplifier, as the second-stage intermediate frequency amplifier, has its inverting input connected to any output of the differential amplifier through the gain resistor Rg and the DC blocking capacitor Cdc on the radar module, further amplifies the Doppler signal and performs appropriate filtering, and connects the output of the differential amplifier to a microprocessor with a built-in analog-to-digital converter. After sampling the Doppler signal output by the radar chip through the analog-to-digital converter, the microprocessor distinguishes between noise and effective radar sensing signals; wherein, the output of the single operational amplifier is connected back to the inverting input of the single operational amplifier through the feedback resistor Rf and the feedback capacitor on the radar module, and the inverting input of the single operational amplifier is connected to a reference level of 1 / 2 of the power supply voltage inside the chip; the size of the DC blocking capacitor Cdc on the radar module determines the bandwidth of the high-pass filter, and the size of the feedback capacitor on the radar module determines the bandwidth of the low-pass filter;

[0055] Among them, the microprocessor is a low-power microprocessor with a low-power working mode and a sleep mode with a low-frequency clock, and the microprocessor has a timed wake-up function. In the sleep mode, the microprocessor core stops working to reduce power consumption, but the low-frequency clock continues to oscillate and the wake-up timer continues to count; in addition, the pulse width modulation signal PWM_OUT output by the microprocessor can be used to generate a pulse width modulation signal and send it to the PWM_IN input port of the radar chip when the duty cycle is not too low and the power consumption requirement is not harsh, and the microprocessor performs synchronous sampling in an interrupt mode to reduce the influence of the pulse width modulation ripple and improve performance.

[0056] The microprocessor (MCU) is an external standard microprocessor (MCU), and its analog input port (ADC) is connected to the output of a single op amp; the microprocessor (MCU) controls the enable signal of each module by reading and writing registers through I2C or by high and low levels of pins, and selects to use the internal coarse adjustment PWM of the chip, the internal fine adjustment PWM of the chip, or the PWM signal generated by the external MCU to control the start and power-off of the RF circuit of the radar chip, so that the radar chip can work normally under various duty cycle conditions (DLY_EN is set to a high level to use the internal analog delay, PWM_ENB is set to a low level to use the internal PWM, and EXT_PWM is set to a level; or PWM_ENB is set to a high level without using the internal PWM signal, and the pulse width modulation signal generated by the MCU is transmitted to the EXT_PWM input pin of the radar sensor chip). The intermediate frequency signal output by the radar chip is sent to the analog input port of the MCU after RC low-pass filtering, and the Doppler signal output by the radar chip is sampled by the analog-to-digital converter (ADC) inside the MCU. The MCU performs algorithm processing to distinguish noise from effective radar sensing signals, and performs trigger judgment and light-on delay processing. When the chip generates a PWM signal, an asynchronous sampling method is used. If an MCU is used to generate a PWM signal, the MCU can use the synchronous sampling method of the PWM interrupt method to reduce the impact of PWM ripple and maximize the sensing distance.

[0057] The control circuit is used not only for inputting an external pulse width modulation signal (PWM_OUT) and preventing a large current from being generated when the device is turned on, but also for switching internal control functions.

[0058] A coarse pulse width modulation signal generator with a clock oscillator has a very small operating current (generally in the order of a few microamperes) and can generate a coarse pulse width modulation signal with a frequency of several hundred hertz and a duty cycle of 1 / M, where M is 8N and N is a positive integer greater than or equal to 1;

[0059] The operating current of the analog delay circuit is generally very small (about 1 microampere). Different delay times can be set through registers. The coarse pulse width modulation signal can be delayed to generate a fine pulse width modulation signal with a low level pulse width of hundreds of nanoseconds to several microseconds and a period of hundreds of microseconds to several milliseconds.

[0060] The voltage-controlled oscillator, radio frequency power amplifier, low-noise radio frequency amplifier, and mixer operate at full current when the power-off control signal is at a low level, and stop operating and consume almost no current when the power-off control signal is at a high level.

[0061] The impedance control switch connects the output of the mixer to the sampling and holding capacitor and the input of the differential amplifier during operation, and disconnects the mixer from the sampling and holding capacitor and the differential amplifier during non-operation.

[0062] The chip pins in the differential amplifier can be connected to the input and output terminals of the differential amplifier by externally connecting a DC blocking capacitor Cdcp and a DC blocking capacitor Cdcn, a gain resistor Rgp and a gain resistor Rgn, and a feedback resistor Rfp and a feedback resistor Rfn;

[0063] The differential amplifier is provided with two branches, the first branch is provided with a capacitor Cdcp, a gain resistor Rgp and a feedback resistor Rfp in sequence and is finally connected to the differential amplifier;

[0064] The second branch is provided with a capacitor Cdcn, a gain resistor Rgn and a feedback resistor Rfn in sequence and is finally connected to a differential amplifier;

[0065] One output terminal of the differential amplifier is also connected to a single op amp.

[0066] The sampling and holding capacitor includes a first sampling and holding capacitor Csp and a second sampling and holding capacitor Csn, and the impedance control switch is divided into a first impedance control switch and a second impedance control switch;

[0067] The DC blocking capacitor Cdcp is connected to the first impedance control switch, and a branch is provided between the two to connect the first sampling and holding capacitor Csp;

[0068] The DC blocking capacitor Cdcn is connected to the second impedance controlled switch, and a branch is provided between the two to connect the first sampling and holding capacitor Csn.

[0069] The chip pins in the single operational amplifier can be connected to the DC blocking capacitor Cdc, the gain resistor Rg, the feedback resistor Rf and the input and output ends of the single operational amplifier. The capacitor Cdc, the gain resistor Rg, the feedback resistor Rf and the second amplifier are connected in sequence, and the two ends are connected to the first amplifier and the microprocessor respectively. The in-phase input terminal (positive pole) of the second amplifier is connected to the common mode voltage Vcm (generally 1 / 2 of the power supply voltage), and the inverting input terminal (negative pole) of the second amplifier is connected between the gain resistor Rg and the feedback resistor Rf (generally including the feedback capacitor for low-pass filtering).

[0070] like Figure 7 A method for reducing duty cycle and increasing impedance is shown, comprising the following steps:

[0071] Step 1, the PWM_IN input port of the control circuit is connected to the power supply with a pull-up resistor, and the RF circuit control signal is pulled up to a high level within a few microseconds of the initial power-on time to turn off the RF circuit to prevent a large current from being turned on; thereafter, the internal clock oscillator of the chip starts to work, and the coarse pulse width modulation signal generator has generated a coarse pulse width modulation signal to control the RF circuit to work intermittently, and the coarse pulse width modulation signal can be transmitted to the analog delay circuit or output to the microprocessor for interrupt sampling or sleep wake-up (INT / WAKE UP);

[0072] Step 2, using a chip register to set a low-power analog delay circuit with different delay times to generate an analog delay of hundreds of nanoseconds to several microseconds, and delaying the coarse pulse width modulation signal of step 1 to generate a fine pulse width modulation signal with a low-level pulse width of hundreds of nanoseconds to several microseconds and a period of hundreds of microseconds to several milliseconds;

[0073] Among them, the low-level pulse width in the pulse width modulation signal is equal to the delay time. If digital delay is performed, a high-frequency clock source with a frequency of 1 / N (in megahertz) is required. Because the two clocks are asynchronous, the original PWM signal needs to be synchronized once with a high-frequency clock, and then each synchronization can delay N microseconds. The high-frequency clock source consumes a lot of power, so this patent uses a low-frequency clock source and an analog delay method;

[0074] The method of realizing analog delay circuit is to make a current source with very small current, invert the original PWM signal with an inverter, use the current mirror method to control the charging speed of the PMOS tube to the capacitor, and the NMOS performs normal discharge; thus, the rising edge time of the subsequent circuit becomes slower, and the voltage drop remains basically unchanged; the delayed signal is ANDed with the inverted signal of the original PWM signal, and then inverted, to obtain a narrow low-level pulse, whose pulse width is equal to the delay time. In order to control the delay time and compensate for the error caused by process deviation, MOS tubes can be used to switch different current sources, and MOS can be used to switch different capacitors, so that a variety of delay combinations can be obtained. Among them, the delay time of some combinations is basically the same, and the actual number of combinations is slightly smaller; because the low-level pulse width under different delay time is different, the new PWM signal duty cycle is also different. If the PWM control signal is working during the high level period of the RF circuit, the PMOS can be changed to NMOS, or one more inversion can be performed, or the PMOS and NMOS of the delay circuit can be controlled by current mirrors at the same time, that is, the charging speed and the discharging speed of the capacitor are controlled at the same time, and the rising edge and the falling edge are delayed at the same time; the power consumption of the analog delay circuit is extremely low, and theoretically it is generally only about 1uA. Compared with directly using a high-frequency clock and a digital circuit method to change the current, it achieves the purpose of changing the PWM duty cycle by using an analog delay method. In actual experiments, the power consumption of the present invention is estimated to be around 3uA, and the average RF current is within 10uA. If a high-frequency clock and digital delay are used, the high-frequency clock alone requires a current of more than 20uA. When the MCU is used to generate this PWM signal in actual testing of the present invention, the current requires hundreds of microamperes.

[0075] The specific method is to make a current source with a very small current (IB = about 0.1uA), invert the original PWM signal, use the current mirror method to control the charging speed of the PMOS tube to the capacitor (C = about 0.1pF), and the NMOS performs normal discharge. As a result, the rising edge time of the subsequent circuit becomes slower, and the falling edge time remains basically unchanged. The delayed signal is ANDed with the inverted signal of the original PWM signal, and then inverted (implemented by the NAND gate), and a narrow low-level pulse is obtained, and its pulse width is equal to the delay time. In order to control the delay time and compensate for the error caused by process deviation, MOS tubes can be used to switch different current sources (such as 1*IB, 2*IB, 4*IB), and MOS can be used to switch different capacitors (such as 1C, 2C, 4C, 8C), so that multiple (such as 8x16 = 128) delay combinations can be obtained. Among them, the delay time of some combinations is basically the same, and the actual number of combinations is slightly smaller. Because the low-level pulse width is different under different delay times, the duty cycle of the new PWM signal is also different. If the PWM control signal is working during the high level period of the RF circuit, the PMOS can be changed to NMOS, or an additional inversion can be performed, or the PMOS and NMOS of the delay circuit can be controlled by current mirrors at the same time, that is, the charging speed and the discharging speed of the capacitor can be controlled at the same time, and the rising edge and the falling edge can be delayed at the same time. Because the power consumption of the analog delay circuit is extremely low, only at the order of 1uA, the present invention uses a low-frequency clock source to generate a coarse PWM, and then uses analog delay to generate a fine PWM signal;

[0076] Step 3, the external standard microprocessor controls the internal enable and delay time of the chip by reading and writing registers through I2C or uses the PWM_EN pin to control the enable of the pulse width modulation signal inside the chip, and sends the pulse width modulation signal with adjustable duty cycle generated inside the chip to the RF circuit power-off control port of the radar sensor chip; wherein, the enable control is implemented by ANDing the PWM_EN control signal with the pulse width modulation signal generated inside the chip through an AND gate to generate a fine-tuning pulse width modulation signal (FINE PWM), when PWM_EN is at a low level, the fine-tuning pulse width modulation signal FINE_PWM becomes a constant low level, and when PWM_EN is at a high level, the fine-tuning pulse width modulation signal FINE_PWM is a pulse width modulation signal with adjustable duty cycle generated inside the chip;

[0077] (In the present invention, the RF circuit of the radar chip works during the low level of the pulse signal, and does not work during the high level. If the control level is opposite, an inverter can be added to the input and output);

[0078] The method of narrowing the pulse width of the pulse width modulation signal is to delay the coarse pulse width modulation signal (COARSE_PWM) for an adjustable time, and then AND the delayed coarse pulse width modulation signal with the inverted signal of the original coarse pulse width modulation signal, and then invert it to obtain a new pulse width modulation signal with a narrowed low-level pulse width, and its low-level pulse width is equal to the delay time; the comparative method is to use digital delay, which requires a very high-frequency clock source, and this high-frequency clock oscillator consumes a lot of power (generally about tens of microamperes);

[0079] Among them, the adjustment method of different duty cycles is achieved by setting different analog delay durations, and the setting of different analog durations is achieved by charging the capacitor with different currents. The specific method is to set different charging currents and charged capacitors of different capacities in the register. When the coarse-adjusted pulse width signal is used to charge the capacitor through different driving currents, the voltage of the capacitor is transmitted to the next stage only when it is charged to the flip level of the next-stage digital circuit, thereby achieving different delay durations from the low level to the high level rising edge; similarly, controlling the discharge current of the capacitor can achieve different delay durations from the high level to the low level falling edge.

[0080] Step 4: The voltage-controlled oscillator generates a radio frequency signal and a local oscillator signal. The radio frequency signal is amplified by the power amplifier and then transmitted through the transceiver integrated PCB antenna. The voltage-controlled oscillator and the power amplifier both have power-off control ports. Changing the level of the power-off port can allow them to start working or stop working quickly.

[0081] Step 5, the transceiver integrated PCB antenna receives the echo signal, and after amplification by the low-noise RF amplifier, the echo signal and the local oscillator signal are mixed by a mixer to obtain a Doppler frequency signal; wherein, the low-noise RF amplifier and the mixer both have a power-off control port, and changing the level of the power-off port can make them start working quickly or stop working quickly;

[0082] Step 6, the Doppler frequency signal output by the mixer passes through an impedance conversion switch (SW) to the sampling and holding capacitors Csp and Csn and the differential amplifier; wherein the output amplitude of the mixer is determined by the working current of the mixer and the load resistances Rsp and Rsn on the drain, and the larger the load resistance, the larger the output amplitude; wherein the impedance conversion switch (SW) is closed during the operation of the RF circuit and is disconnected during the non-operation of the RF circuit; if there is no impedance control switch, during the period when the mixer stops working, its DC voltage will be pulled up to the power supply voltage VDD of the RF circuit because the load resistance is not disconnected, thereby generating a large interference with the same PWM frequency on the final intermediate frequency signal, and because the load resistances Rsp and Rsn are relatively small, the charge on the sampling and holding capacitor is discharged too quickly, and the voltage on the sampling and holding capacitor cannot be maintained until the next RF working period, so the final signal amplitude is very small; comparatively speaking, if an analog switch (SW) made of PMOS and NMOS is connected in series in the load resistance branch, it can also play a role in increasing the impedance, but this requires that the MOS switch can work at the RF frequency;

[0083] Among them, due to the limitation of the power supply voltage of the RF circuit, a relatively large load resistance can only be used when the working current is small, but at the same time, it also limits the charging speed of the sampling and holding capacitor, and its charging time is often Rsp*Csp and Rsn*Csn; the impedance conversion switch (SW) is closed during the operation of the RF circuit (voltage-controlled oscillator, RF power amplifier, low-noise RF amplifier, mixer), and is disconnected when the RF circuit is not working. During the closing period of the impedance conversion switch, the sampling and holding capacitor tracks the intermediate frequency signal output by the mixer; during the disconnection period of the impedance conversion switch, the voltage on the sampling and holding capacitor remains basically unchanged due to discharge through the input resistance of the differential amplifier, and only changes slowly; the implementation method of the impedance conversion switch is to use PMOS and NMOS in parallel, invert the control signal, and control the gate voltage of PMOS and NMOS at the same time, so that PMOS and NMOS are turned on at the same time when the RF circuit is working, and PMOS and NMOS are turned off at the same time when the RF circuit is not working; the parallel connection method can reduce the on-resistance and prevent the impedance control switch from failing to turn on the PMOS tube due to the low DC level at both ends of the PMOS tube; the mixer stops working During operation, its DC voltage will be pulled up to the power supply voltage VDD of the RF circuit because the load resistor is not disconnected, thereby generating a large interference with the same PWM frequency on the final intermediate frequency signal, and because the load resistors Rsp and Rsn are relatively small, the charge on the sampling and holding capacitor is discharged too quickly, and the voltage on the sampling and holding capacitor cannot be maintained until the next RF working period, so the final signal amplitude is very small; if a MOS switch is connected in series in the load resistance branch, it can also play a role in increasing the impedance, but this requires the MOS switch to operate at the RF frequency (usually 5.8GHz); the impedance conversion switch (SW) of this solution is connected in series in the intermediate frequency link, and its operating frequency is only a few megahertz, which reduces the design difficulty of the MOS switch.

[0084] The setting of the impedance control switch ensures that the present invention can achieve an excessively small duty cycle. The duty cycle of the present invention theoretically supports 1 / 5000, and the actual duty cycle used is 1 / 1000. If there is no impedance control switch, the duty cycle can generally only be within 1 / 20, that is, the RF current is about 0.6mA.

[0085] In addition, the function of the differential amplifier is to suppress common-mode interference, mainly 50Hz power frequency interference. If the differential amplifier is not used, in addition to the large power frequency interference, the interference caused by PWM modulation is also large.

[0086] Step 7, the signal voltage on the sampling and holding capacitor is connected to the input end of the differential amplifier through the DC blocking capacitor, and its gain resistors Rgp and Rgn are as large as possible to increase the input impedance of the differential amplifier, and at the same time, the feedback resistors Rfp and Rfn are increased in proportion to maintain the required amplification factor, that is, to maintain the original gain, and the common-mode suppression capability of the differential amplifier is used to suppress common-mode interference and common-mode noise as much as possible (common-mode suppression is of great significance to reducing the size of the intermediate frequency ripple during intermittent operation and to reducing 50Hz / 60Hz power frequency interference) for further amplification by the post-stage amplifier;

[0087] like Figure 2 As shown in the figure, if the PWM frequency is low and the RF circuit is not working for a long time, the intermediate frequency output will easily generate large ripples. Because the RF circuit works for a short time under the PWM working mode, the sampling and holding capacitor is not charged enough, so a relatively small sampling and holding capacitor should be selected, so the input impedance of the differential amplifier should be increased as much as possible to keep the voltage of the sampling and holding capacitor unchanged as much as possible during the period when the RF circuit is not working; assuming that the voltage on the sampling and holding capacitor remains unchanged during the period when the RF circuit is not working, the signal after differential amplification will present a step wave similar to the output of analog-to-digital conversion (ADC) and then digital-to-analog conversion (DAC); because the filter circuit on the post-amplifier will perform low-pass filtering, the output waveform will be smoothed into a waveform that is basically the same as the waveform of continuous RF operation, but the amplitude is slightly smaller, so the gain of the amplifier needs to be appropriately increased.

[0088] Specifically, because the RF circuit works for a short time under the PWM working mode, the mixer output has a certain internal resistance. For example, if the mixer output internal resistance is 100 ohms and the capacitor is 100nF, the RC time constant is 10us. When the RF circuit works for less than 10us, the voltage on the sampling capacitor cannot even follow more than 70% of the difference from the previous voltage to the new voltage. For example, with a PWM frequency of 500Hz and a duty cycle of 1 / 1000, the RF circuit works for only 2 microseconds. Because the RF circuit has a high frequency and a short settling time (generally less than 0.1 microseconds, which is greater than 580 cycles for a 5.8GHz signal). If the sampling and holding capacitor is reduced (for example, reduced to 10nF) and the following speed during the sampling period is accelerated, the voltage on the sampling and holding capacitor cannot be kept stable during the non-working period of the RF circuit. For example, the 10nF sampling and holding capacitor is discharged through a 10K ohm resistor (the gain resistor of the differential amplifier), and the time constant is 100us. The 500Hz PWM signal cycle is 2 milliseconds, and the excessive voltage drop of the sampling and holding capacitor causes excessive ripple, so the impedance of the differential amplifier needs to be increased as much as possible (for example, increased to more than 200k ohms). At this time, the feedback resistor can be increased to more than 2M ohms to maintain a gain of more than 10 times for the differential amplifier, fully maintain its common-mode rejection capability, and reduce the impact of the post-amplifier noise on the system. If a differential amplifier is not used and a single-ended amplification method is adopted, a DC-isolated input can also be made at the inverting end of the op amp to eliminate the influence of the DC level. Although the in-phase input has a higher input impedance, the radar chip belongs to high-gain amplification (the intermediate frequency amplification factor is usually more than 1000 times), and the DC level offset caused by the offset voltage (usually a few millivolts) is not easy to handle. The present invention does not limit the use of differential amplifiers or single-ended amplifiers.

[0089] The DC blocking capacitor can eliminate the problem that the differential amplifier cannot use a higher gain due to the difference between the DC level of the mixer and the DC level of the differential amplifier.

[0090] Step 8: After the output voltage of the differential amplifier passes through the DC blocking capacitor Cdc, it is sent to the single op amp for further amplification. At the same time, a feedback capacitor of appropriate size can be connected in parallel to the feedback resistor Rf for low-pass filtering to reduce PWM ripple and various noises.

[0091] Among them, due to the existence of DC blocking capacitors, only AC signals are amplified, the DC offset voltage of the differential amplifier is suppressed, and the DC gain of the single op amp is only 1 times, avoiding signal saturation or signal asymmetry caused by the amplification of the DC offset voltage of the single op amp, thereby avoiding the design of amplifiers with extremely low offset voltage.

[0092] Where the single op amp gain is the feedback resistor divided by the gain resistor ( Figure 1Rf / Rg) determines the series connection of DC blocking capacitor ( Figure 1 The Cdc in the feedback resistor affects the gain and has a high-pass effect, which can be used to suppress interference signals with a period of 10Hz, such as WiFi synchronization pulses. An appropriate capacitor can be connected in parallel to the feedback resistor for low-pass filtering. After the output of the op amp, a resistor can be connected in series and then connected to the ground capacitor for further low-pass filtering, which can reduce PWM ripple and various noises outside the Doppler frequency range (the Doppler chip frequency range of the 5.8GHz radar module is between 5Hz-105Hz).

[0093] Step 9: The analog-to-digital converter inside the microprocessor digitizes the analog intermediate frequency signal, performs algorithm processing, and determines whether to output a trigger signal for radar sensing.

[0094] In step 9, the microprocessor works in ultra-low power mode, and uses a low-frequency clock to make the core work in low power mode; the MCU sets the chip PWM working mode through I2C or pin control to make the radar chip work in PWM mode, and then uses the core to stop running to save power consumption;

[0095] The sampling method is to set the wake-up timer to wake up the core at a frequency of hundreds of Hz. Each time it wakes up, the number of wake-up times is recorded and sampled once, and then the core continues to stop running. If the wake-up count reaches the required number of sampling points, the MCU sets the chip to stop working and sets the core clock to a high-frequency clock to calculate this set of data at the fastest speed, including noise floor update, signal size judgment, whether to output a light-on signal, etc.);

[0096] After the calculation is completed, it is reset to the ultra-low power mode and can sleep for a period of time (if the number of detections per second is relatively small, during this period, the IF amplifier bias current can be set to reduce to maintain the DC level and further reduce power consumption), or the chip's PWM signal can be turned on again to sample through the wake-up method. Because after the RF circuit is turned on, even if the IF circuit is always working, an interference signal will be generated due to the change in the DC level, and a certain amount of time (usually tens of milliseconds) is required; after each wake-up, the count is accumulated and the count value is judged. If the value is too small, no sampling is performed, thus avoiding the collection of interference signals during the IF stability period.

[0097] If the sampling and holding capacitor is relatively low and the input impedance of the intermediate frequency amplifier is not high enough, when the PWM frequency is low, that is, the RF circuit does not work for too long, it is easy to cause the following Figure 2 The PWM ripple is shown. If the MCU sampling is not synchronized with the PWM ripple, the equivalent noise becomes larger. The present invention supports synchronous sampling, so the PWM ripple has no effect on the performance.

[0098] It should be noted that, in the present invention, the control circuit, I2C and register, and MCU microprocessor are all conventional technologies, so the present invention does not elaborate on them.

[0099] The practical application of the present invention is as follows:

[0100] In order to produce 5.8GHz radar chips, a 5.8GHz voltage-controlled oscillator is designed, the power amplifier (PA), low-noise amplifier (LNA) and mixer are optimized for 5.8GHz, and a low-power intermediate frequency amplifier with sufficient gain and low noise is designed, so that the output analog signal is as large as possible and the noise is as small as possible when there is a Doppler signal. The bias control method is used to make the various functional modules of the RF circuit (voltage-controlled oscillator, RF power amplifier, low-noise amplifier and mixer) work in an intermittent manner.

[0101] Choose a 10-pin low-power MCU, use I2C to set the working mode of using analog delay (DLY_ENB is set to low level), set different current sources and delay capacitors to generate different delays. For example, use a 3-bit binary level to control the MOS tube to switch different 100nA, 200nA, 400nA current sources in parallel with the 100nA current source to form 8 different charging currents from 100nA to 800nA. Use a 4-bit binary level to control the MOS to switch different capacitors to form 16 parallel capacitance values ​​of 0.05pF–0.8pF, so 8x16=128 delay combinations can be obtained. Use registers in the control circuit to control different delays. After testing, selecting the appropriate control parameters is equivalent to doing appropriate delay calibration. Therefore, it is not difficult to achieve a variety of delays from 0.4us to 8us.

[0102] Select appropriate external capacitors and set the oscillation frequency to 8kHz. Set the appropriate division ratio so that the coarse PWM frequency is 500Hz with a duty cycle of 1 / 16. Since the PWM period is 2ms, after analog delay, a duty cycle of 1 / 5000–1 / 250 can be achieved, averaging the RF current from 10mA-25mA to 2uA-100uA. If the current of long-term working circuits such as LDO and intermediate frequency op amps is 20uA, and the current of control circuits such as oscillators (2uA) and analog delay circuits is 3uA in total, then the average operating current of the radar chip is 25uA–123uA.

[0103] If a low-power MCU uses a low-frequency clock to generate the core clock and wake-up clock, and the current is 4uA when the core clock stops (STOPEXE), and the current in the low-frequency working mode is 60uA. Use the timer wake-up method to sample, and sample once every 2 wake-ups (each time the sample is taken, the successive comparison analog-to-digital converter (SAR ADC) uses 16 clocks to obtain 1 data, 250Hz sampling rate), if the low-frequency clock is 100kHz, each clock cycle is 10us. Assuming that fast wake-up requires 45 clock cycles, the sampling, wake-up, data acquisition and storage time is about 65 clock cycles, that is, 650us, and wake-up without sampling is about 500us. The actual core working time per second is about 275ms, and the core current is about 20uA.

[0104] Because the ADC consumes additional current, assuming that the ADC current is 1mA at a sampling rate of 500ksps, the current at a sampling rate of 250sps is significantly reduced (but not 0.5uA). Actual tests show that the MCU current in sleep wake-up mode is about 30uA.

[0105] The data is divided into 25 groups, each with 10 points (40ms for each group of data, equivalent to a sine wave cycle of a 25Hz Doppler signal), and the peak-to-peak value is calculated using the method of finding the maximum and minimum values. The MCU uses a high-frequency clock during calculation. If the calculation of each group of data takes 1ms, the current in the MCU high-power mode is 600uA. Since the calculation is performed 25 times per second, the calculation takes 25ms per second, and the average current used for calculation is 15uA. Assuming that 3 out of every 5 peak-to-peak data are greater than the set threshold value, the effective radar signal method is used to determine the trigger, and the detection is performed 5 times per second. Then, the overall module power consumption is 80uA-178uA, which fully meets the ultra-low power consumption scenario of battery power supply.

[0106] If the pulse group working mode is used to reduce the number of monitoring times, the current can be further reduced. For example, the MCU's GPIO is used to reduce the EXT_PWM pin of the radar chip to a low level of 250ms and a high level of 250ms, and the radar chip's RF circuit is controlled to work in a pulse group mode twice per second. The radar chip only works at a duty cycle of 1 / 5000-1 / 250 during the 250ms period. During the other 250ms high level period, the internal PWM signal is blocked by the OR gate, and the RF circuit is powered off and does not work, which can further reduce the average RF current by 1 / 2. Because it takes a certain amount of time to wait for the intermediate frequency signal to stabilize when the RF is turned on, the MCU can turn on the RF first, then sleep and wait for a while, and then start the sampling and calculation of the sleep wake-up mode. Assuming that the MCU algorithm is further simplified, the sampling of 250 points per second is reduced to 60 points, and it is still sampled once every 4ms, and each time there are still 10 points in 1 group of data, but only 6 groups of data are sampled, and the algorithm is simplified to judge that 2 groups of data in 3 groups of data are greater than the threshold value as radar signals, that is, detection is performed twice per second, then the MCU sampling and calculation time are reduced to 1 / 4 of the original. Therefore, the minimum power consumption of the module can be reduced to less than 50uA.

[0107] The present invention is compatible with conventional PWM power saving working modes, and the following two usage modes are given as examples:

[0108] Assuming that the MCU has few pins and does not use I2C, the chip defaults to a 13mA (medium to small) RF current, and generates a 1 / 32 duty cycle PWM by default, averaging the RF current to 406uA. Use a suitable external capacitor to adjust the oscillator frequency to 64kHz, and the PWM frequency of the radar chip is 2kHz. At this time, the oscillation current power consumption is about 15uA. Because the PWM frequency is high and the filtering is sufficient, the MCU performs asynchronous sampling to simplify the program and algorithm. Assuming that the working current of the LDO and amplifier is 25uA, and the working current of the MCU is 600uA, the current of the radar module is 1046uA. In order to prevent the startup current from being large, the external PWM input pin is connected to the power supply with a 10uF capacitor, and the 1k resistor is grounded. The circuit has a time constant of 10ms, which can delay the RF startup time and ensure that the oscillator starts to generate a PWM signal.

[0109] Assuming that the MCU has enough pins, use I2C or pin control to set the current of the RF circuit to 25mA (maximum) when it is always working, turn off the internal PWM signal generator of the chip, and use the MCU's 8-bit PWM generator to generate a PWM signal with a frequency of 1KHz and a duty cycle of 4 / 256, and transmit it to the radar chip, then the RF current averages to 391uA. At the same time, the MCU uses synchronous sampling in the PWM interrupt mode. Assuming that the working current of LDO and amplifier is 25uA, and the working current of MCU is 600uA, the current of the radar module is 1016uA. In order to prevent the startup current from being too large, the first thing to do after the MCU is powered on is to set the GPIO connected to the chip EXT_PWM pin to a high level, and then configure the PWM duty cycle to output the PWM signal, and finally use I2C or other GPIO to bypass or turn off the oscillator and divider inside the chip.

[0110] Tests show that these two radar modules with a current of about 1mA can achieve a sensing distance of more than 3 meters when hung at a height of 3 meters. They can be used in capacitor-type bulbs that draw power using a resistor-type voltage divider, and can directly replace infrared sensors or discrete radar modules.

[0111] In summary, the present invention uses an extremely low-power PWM generation method and cooperates with an external low-power MCU to achieve seamless coverage of 1 / 5000–255 / 256 duty cycles. It can be well compatible with conventional power consumption scenarios and ultra-low power consumption scenarios, and is applied to smart lighting and smart homes, with extremely high commercial value.

[0112] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An ultra-low power consumption Doppler radar chip with reduced duty cycle and increased impedance, characterized in that: include Registers and control circuits read and write registers through an I2C serial interface to set parameters; the control circuit can receive a pulse width modulation signal PWM_OUT output by an external microprocessor, input it to the PWM_IN pin of the radar chip to expand the application mode, and prevent high current at startup through the PWM_IN pin; wherein, the control circuit body is an OR gate and an AND gate, which ORs the external pulse width modulation signal with the pulse width modulation signal inside the chip, and prohibits the internal pulse width modulation signal by ANDing the control signal of the register through the AND gate; wherein, the method of preventing high current at startup is to connect the PWM_IN pin to the power supply with a resistor on the radar module, and before the low-frequency clock of the chip starts to oscillate and the microprocessor works normally, the power-off control signals described later are set to a high level, so that the RF circuit with large working current does not work temporarily; A coarse pulse width modulation signal generator with a clock oscillator is connected to the control circuit to generate a coarse pulse width modulation signal with a frequency of several hundred Hz and a duty cycle of 1 / M, where M is 8N and N is a positive integer greater than or equal to 1; The analog delay circuit is connected to the coarse pulse width modulation signal generator, and different delay times are set by registers to delay the coarse pulse width modulation signal to generate a fine pulse width modulation signal with a low-level pulse width of hundreds of nanoseconds to several microseconds and a period of hundreds of microseconds to several milliseconds, and is connected to the power-off control end of a circuit with a high working frequency and a large working current in the radio frequency circuit but a fast working state after power-on; Voltage controlled oscillator, used to generate RF signal and local oscillator signal, and with power-off function; The RF power amplifier is connected to the voltage-controlled oscillator and is used to amplify the RF signal. It has a power-off function. The RF signal is sent to the transceiver integrated PCB antenna on the radar module. The antenna transmits the RF signal and receives the echo signal. A low-noise RF amplifier is connected to the transceiver integrated PCB antenna on the radar module and has a power-off function to amplify the echo signal; The mixer is connected to the low-noise RF amplifier and the voltage-controlled oscillator and has a power-off function. The echo signal amplified by the low-noise RF amplifier is mixed with the local oscillator signal of the voltage-controlled oscillator. The intermediate frequency signal obtained by mixing is the Doppler frequency signal. The impedance control switch is connected to the output end of the mixer, and the radar module is provided with a sampling and holding capacitor, one end of the sampling and holding capacitor is connected to the impedance control switch, and the other end of the sampling and holding capacitor is grounded; The differential amplifier, as the first-stage intermediate frequency amplifier, is connected to the impedance control switch through the gain resistors Rgp and Rgn and the DC blocking capacitors Cdcp and Cdcn on the radar module to amplify the Doppler frequency signal and perform common-mode suppression to reduce common-mode interference during intermittent operation; wherein the output of the differential amplifier is connected back to the input of the differential amplifier through the feedback resistors Rfp and Rfn on the radar module, and the gain of the differential amplifier is determined by the ratio of the feedback resistor to the gain resistor; and The single operational amplifier, as the second-stage intermediate frequency amplifier, has its inverting input connected to any output of the differential amplifier through the gain resistor Rg and the DC blocking capacitor Cdc on the radar module, further amplifies the Doppler signal and performs appropriate filtering, and connects the output of the differential amplifier to the microprocessor with a built-in analog-to-digital converter on the radar module. After sampling the Doppler signal output by the radar chip through the analog-to-digital converter, the microprocessor distinguishes between noise and effective radar sensing signals; wherein, the output of the single operational amplifier is connected back to the inverting input of the single operational amplifier through the feedback resistor Rf and the feedback capacitor on the radar module, and the non-inverting input of the single operational amplifier is connected to a reference level of 1 / 2 of the power supply voltage inside the chip; the size of the DC blocking capacitor Cdc on the radar module determines the bandwidth of the high-pass filter, and the size of the feedback capacitor on the radar module determines the bandwidth of the low-pass filter; Among them, the microprocessor is a low-power microprocessor with a low-frequency clock, a low-power working mode and a sleep mode, and the microprocessor has a timed wake-up function. In the sleep mode, the microprocessor core stops working to reduce power consumption, but the low-frequency clock continues to oscillate and the wake-up timer continues to count; in addition, the pulse width modulation signal PWM_OUT output by the microprocessor can be used to generate a pulse width modulation signal and send it to the PWM_IN input port of the radar chip when the duty cycle is not too low and the power consumption requirement is not harsh, and the microprocessor performs synchronous sampling in an interrupt mode to reduce the influence of the pulse width modulation ripple and improve performance.

2. The ultra-low power consumption Doppler radar chip with reduced duty cycle and increased impedance according to claim 1, characterized in that: The voltage-controlled oscillator, radio frequency power amplifier, low-noise radio frequency amplifier, and mixer operate at full current when the power-off control signal is at a low level, and stop operating and consume almost no current when the power-off control signal is at a high level.

3. The ultra-low power consumption Doppler radar chip with reduced duty cycle and increased impedance according to claim 1, characterized in that: The impedance control switch connects the output of the mixer to the sampling and holding capacitor and the input of the differential amplifier during operation, and disconnects the mixer from the sampling and holding capacitor and the differential amplifier during non-operation.

4. The ultra-low power consumption Doppler radar chip with reduced duty cycle and increased impedance according to claim 1, characterized in that: The chip pins in the differential amplifier can be connected to the input and output terminals of the differential amplifier by externally connecting a DC blocking capacitor Cdcp and a DC blocking capacitor Cdcn, a gain resistor Rgp and a gain resistor Rgn, and a feedback resistor Rfp and a feedback resistor Rfn; The differential amplifier is provided with two branches, the first branch is provided with a capacitor Cdcp, a gain resistor Rgp and a feedback resistor Rfp in sequence and is finally connected to the differential amplifier; The second branch is provided with a capacitor Cdcn, a gain resistor Rgn and a feedback resistor Rfn in sequence and is finally connected to a differential amplifier; One output terminal of the differential amplifier is also connected to a single op amp.

5. The Doppler radar chip for reducing duty cycle and increasing impedance according to claim 1, characterized in that: The sampling and holding capacitor includes a first sampling and holding capacitor Csp and a second sampling and holding capacitor Csn, and the impedance control switch is divided into a first impedance control switch and a second impedance control switch; The DC blocking capacitor Cdcp is connected to the first impedance control switch, and a branch is provided between the two to connect the first sampling and holding capacitor Csp; The DC blocking capacitor Cdcn is connected to the second impedance controlled switch, and a branch is provided between the two to connect the first sampling and holding capacitor Csn.

6. The Doppler radar chip for reducing duty cycle and increasing impedance according to claim 1, characterized in that: The chip pins in the single operational amplifier can be connected to the DC blocking capacitor Cdc, the gain resistor Rg, the feedback resistor Rf and the input and output ends of the single operational amplifier. The capacitor Cdc, the gain resistor Rg, the feedback resistor Rf and the second amplifier are connected in sequence, and the two ends are connected to the first amplifier and the microprocessor respectively. The non-inverting input end of the second amplifier is connected to the common mode voltage Vcm, and the inverting input end of the second amplifier is connected between the gain resistor Rg and the feedback resistor Rf.

7. The method of reducing duty cycle and increasing impedance according to claim 1, characterized in that: The steps include: Step 1, the PWM_IN input port of the control circuit is connected to the power supply with a pull-up resistor, and the RF circuit control signal is pulled up to a high level within a few microseconds at the beginning of power-on to turn off the RF circuit to prevent high current at startup; thereafter, the internal clock oscillator of the chip starts to work, and the coarse pulse width modulation signal generator generates a coarse pulse width modulation signal to control the RF circuit to work intermittently, and the coarse pulse width modulation signal can be transmitted to the analog delay circuit or output to the microprocessor for interrupt sampling or sleep wake-up (INT / WAKE UP); Step 2, using a chip register to set a low-power analog delay circuit with different delay times to generate an analog delay of hundreds of nanoseconds to several microseconds, and delaying the coarse pulse width modulation signal of step 1 to generate a fine pulse width modulation signal with a low-level pulse width of hundreds of nanoseconds to several microseconds and a period of hundreds of microseconds to several milliseconds; Step 3, the microprocessor controls the internal enable and delay time of the chip by reading and writing registers through I2C or uses the PWM_EN pin to control the enable of the pulse width modulation signal inside the chip, and sends the pulse width modulation signal with adjustable duty cycle generated inside the chip to the RF circuit power-off control port of the radar sensor chip; wherein, the enable control is implemented by ANDing the PWM_EN control signal with the pulse width modulation signal generated inside the chip through an AND gate to generate a fine-tuning pulse width modulation signal (FINEPWM), when PWM_EN is at a low level, the fine-tuning pulse width modulation signal FINE_PWM becomes a constant low level, and when PWM_EN is at a high level, the fine-tuning pulse width modulation signal FINE_PWM is a pulse width modulation signal with adjustable duty cycle generated inside the chip; Step 4: The voltage-controlled oscillator generates a radio frequency signal and a local oscillator signal. The radio frequency signal is amplified by the power amplifier and then transmitted through the transceiver integrated PCB antenna. The voltage-controlled oscillator and the power amplifier both have power-off control ports. Changing the level of the power-off port can allow them to start working or stop working quickly. Step 5, the transceiver integrated PCB antenna receives the echo signal, and after amplification by the low-noise RF amplifier, the echo signal and the local oscillator signal are mixed by a mixer to obtain a Doppler frequency signal; wherein, the low-noise RF amplifier and the mixer both have a power-off control port, and changing the level of the power-off port can make them start working quickly or stop working quickly; Step 6, the Doppler frequency signal output by the mixer passes through an impedance conversion switch (SW) to the sampling and holding capacitors Csp and Csn and the differential amplifier; wherein the output amplitude of the mixer is determined by the working current of the mixer and the load resistances Rsp and Rsn on the drain, and the larger the load resistance, the larger the output amplitude; wherein the impedance conversion switch (SW) is closed during the operation of the RF circuit and is disconnected during the non-operation of the RF circuit; if there is no impedance control switch, during the period when the mixer stops working, its DC voltage will be pulled up to the power supply voltage VDD of the RF circuit because the load resistance is not disconnected, thereby generating a large interference with the same PWM frequency on the final intermediate frequency signal, and because the load resistances Rsp and Rsn are relatively small, the charge on the sampling and holding capacitor is discharged too quickly, and the voltage on the sampling and holding capacitor cannot be maintained until the next RF working period, so the final signal amplitude is very small; comparatively speaking, if an analog switch (SW) made of PMOS and NMOS is connected in series in the load resistance branch, it can also play a role in increasing the impedance, but this requires that the MOS switch can work at the RF frequency; Step 7, the signal voltage on the sampling and holding capacitor is connected to the input end of the differential amplifier through the DC blocking capacitor, and the gain resistors Rgp and Rgn use large resistors to increase the input impedance of the differential amplifier. At the same time, the feedback resistors Rfp and Rfn are increased in proportion to maintain the required amplification factor, that is, to maintain the original gain, and the common-mode suppression capability of the differential amplifier is used to suppress common-mode interference and common-mode noise as much as possible for further amplification by the subsequent amplifier; Step 8: After the output voltage of the differential amplifier passes through the DC blocking capacitor Cdc, it is sent to the single op amp for further amplification. At the same time, a feedback capacitor of appropriate size can be connected in parallel to the feedback resistor Rf for low-pass filtering to reduce PWM ripple and various noises. Step 9: The analog-to-digital converter inside the microprocessor digitizes the analog intermediate frequency signal, performs algorithm processing, and determines whether to output a trigger signal for radar sensing.

8. The method of reducing duty cycle and increasing impedance according to claim 1, characterized in that: In step 3, the method of narrowing the pulse width of the pulse width modulation signal is to delay the coarse pulse width modulation signal (COARSE_PWM) for an adjustable time length, and then AND the delayed coarse pulse width modulation signal with the inverted signal of the original coarse pulse width modulation signal, and then invert it to obtain a new pulse width modulation signal with a narrowed low-level pulse width, and its low-level pulse width is equal to the delay time; the comparative method is to use digital delay, which requires a very high-frequency clock source, and this high-frequency clock oscillator consumes a lot of power; Among them, the adjustment method of different duty cycles is achieved by setting different analog delay durations, and the setting of different analog durations is achieved by charging the capacitor with different currents. The specific method is to set different charging currents and charged capacitors of different capacities in the register. When the coarse-adjusted pulse width signal is used to charge the capacitor through different driving currents, the voltage of the capacitor is transmitted to the next stage only when it is charged to the flip level of the next-stage digital circuit, thereby achieving different delay durations from the low level to the high level rising edge; similarly, controlling the discharge current of the capacitor can achieve different delay durations from the high level to the low level falling edge.

9. The method of reducing duty cycle and increasing impedance according to claim 1, characterized in that: In step 2, the method of implementing analog delay in the analog delay circuit is to make a current source with a very small current, invert the original PWM signal with an inverter, and use a current mirror method to control the charging speed of the PMOS tube to the capacitor, and the NMOS performs normal discharge; thus, the rising edge time of the subsequent circuit becomes slower, and the drop voltage remains basically unchanged; The delayed signal is ANDed with the inverted signal of the original PWM signal, and then inverted to obtain a narrow low-level pulse whose pulse width is equal to the delay duration. In order to control the delay duration and compensate for the error caused by process deviation, MOS tubes can be used to switch different current sources, and MOS can be used to switch different capacitors, so that a variety of delay combinations can be obtained. Among them, the delay time of some combinations is basically the same, and the actual number of combinations is slightly smaller; because the low-level pulse width is different under different delay durations, the duty cycle of the new PWM signal is also different. If the PWM control signal is working in the RF circuit during the high level period, PMOS can be changed to NMOS, or one more inversion can be performed, or the PMOS and NMOS of the delay circuit can be controlled by current mirrors at the same time, that is, the charging speed and discharge speed of the capacitor are controlled at the same time, and the rising edge and falling edge are delayed at the same time; the power consumption of this analog delay circuit is extremely low, generally only 1uA.

10. The method of reducing duty cycle and increasing impedance according to claim 1, characterized in that: In step 9, the microprocessor works in an ultra-low power consumption mode, and after setting the chip PWM working mode to allow the radar chip to work in PWM mode, the core is stopped to save power consumption; The sampling method is to set the wake-up timer to wake up the core at a frequency of hundreds of Hz. Each time it wakes up, the number of wake-up times is recorded and sampled once, and then the core continues to stop running. If the wake-up count reaches the required number of sampling points, the MCU sets the chip to stop working and sets the core clock to a high-frequency clock to calculate this set of data at the fastest speed. After the calculation is completed, it is reset to ultra-low power mode, and can sleep for a period of time, or the PWM signal of the chip can be turned on again, and the sampling process of the wake-up method is performed. Because after the RF circuit is turned on, even if the intermediate frequency circuit is always working, an interference signal will be generated due to the change of the DC level, and a certain amount of time is required; After each wake-up, the count is accumulated and the count value is judged. If the value is too small, no sampling is performed, thus avoiding the collection of interference signals during the period when the intermediate frequency is stable.

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