Preparation method of cantilever beam type coupler, photon chip and optical computing equipment

Abstract

The embodiment of the invention provides a preparation method of a cantilever beam type coupler, a photon chip and optical computing equipment. The method comprises the following steps: providing a substrate; forming a waveguide layer on the substrate; patterning the waveguide layer to form a waveguide and anchoring parts which are positioned on two sides of the waveguide and are connected with the waveguide; an opening is formed between the waveguide and the anchoring part; an inverted conical waveguide structure is arranged in the waveguide; etching the substrate through the opening by using an anisotropic etching process, and forming a groove on the substrate; and etching the substrate through the opening and the groove by using an isotropic etching process so as to form a cavity below the waveguide. According to the technical scheme provided by the embodiment of the invention, the width and depth of the cavity can be flexibly and accurately regulated and controlled in the preparation process, and the device performance and the structural mechanical stability of the cantilever beam type edge coupler can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a cantilever beam coupler, a photonic chip and an optical computing device. Background Art

[0002] At present, there is a large difference between the mode spot size of the waveguide on the photonic chip and the mode spot size of the external optical element (such as optical fiber). Generally, the mode spot size of the waveguide is much smaller than that of the optical fiber, and the matching degree between the two is poor. In order to improve the optical coupling efficiency between the waveguide on the photonic chip and the external optical element, an edge coupler (or end coupler) can be used to increase the mode spot size of the waveguide and thus improve the matching degree of the mode spot sizes of the two.

[0003] In order to avoid light loss to the substrate when increasing the waveguide mode spot size, a cantilever edge coupler was proposed. The main idea is to etch away the substrate under the waveguide used for light coupling through an etching process to form a cavity. In this way, the light field in the waveguide will no longer leak to the substrate, thereby reducing light loss.

[0004] However, cantilever beam edge couplers prepared using existing preparation processes either have poor performance or poor mechanical stability. Summary of the invention

[0005] In view of the above problems, the present application is proposed to provide a method for preparing a cantilever beam type coupler, a photonic chip and an optical computing device that solve the above problems or at least partially solve the above problems.

[0006] Therefore, in one embodiment of the present application, a method for preparing a cantilever beam type coupler is provided, comprising:

[0007] providing a substrate;

[0008] forming a waveguide layer on the substrate;

[0009] The waveguide layer is patterned to form a waveguide and anchoring parts located on both sides of the waveguide and connected to the waveguide; an opening is provided between the waveguide and the anchoring parts; and an inverted tapered waveguide structure is built into the waveguide;

[0010] Using an anisotropic etching process, etching the substrate through the opening to form a groove on the substrate;

[0011] The substrate is etched through the opening and the trench using an isotropic etching process to form a cavity below the waveguide.

[0012] In another embodiment of the present application, a photonic chip is provided, comprising a cantilever beam coupler prepared by the above-mentioned preparation method.

[0013] In another embodiment of the present application, an optical computing device is provided, including: the above-mentioned photonic chip.

[0014] Through research, it is found that the cavity width and cavity depth of the cantilever beam edge coupler are important factors affecting its performance and structural mechanical stability. In the preparation process, whether the width and depth of the cavity can be flexibly and accurately controlled is crucial to improving the performance and structural mechanical stability of the cantilever beam edge coupler sub-device. In the technical solution provided in the embodiment of the present application, when preparing the cavity below the waveguide, the substrate is first anisotropically etched through the opening (or etching hole) in the waveguide layer to form a groove, and then the substrate is isotropically etched through the opening and groove in the waveguide layer to form a cavity. The width of the cavity can be accurately controlled by the process duration of the isotropic etching process, and the depth of the cavity can be understood as the sum of the depth of the groove and the depth of the isotropic etching process. Although the depth of the isotropic etching process is linked to the width of the cavity, the depth of the groove can be accurately controlled by the process duration of the anisotropic etching process, that is, the depth of the cavity can also be accurately controlled. It can be seen that the technical solution provided in the embodiment of the present application can flexibly and accurately control the width and depth of the cavity during the preparation process, which helps to improve the device performance and structural mechanical stability of the cantilever beam edge coupler. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic diagram of the structure of a cantilever beam coupler provided in one embodiment of the present application;

[0017] Figure 2 A schematic diagram of a preparation method according to an embodiment of the present application;

[0018] Figure 3 A cross-sectional view of a first semiconductor structure prepared according to an embodiment of the present application;

[0019] Figure 4 A top view of a second semiconductor structure prepared according to an embodiment of the present application;

[0020] Figure 5A cross-sectional view of a third semiconductor structure prepared according to an embodiment of the present application;

[0021] Figure 6 A cross-sectional view of a fourth semiconductor structure prepared according to an embodiment of the present application;

[0022] Figure 7 A cross-sectional view of a fifth semiconductor structure prepared according to an embodiment of the present application;

[0023] Figure 8 A cross-sectional view of a sixth semiconductor structure prepared according to an embodiment of the present application;

[0024] Fig. 9 A cross-sectional view of a seventh semiconductor structure prepared according to an embodiment of the present application;

[0025] Fig.10 A cross-sectional view of an eighth semiconductor structure prepared according to an embodiment of the present application;

[0026] Fig.11 A cross-sectional view of a ninth semiconductor structure prepared according to an embodiment of the present application;

[0027] Fig.12 A cross-sectional view of a tenth semiconductor structure prepared according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below according to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0029] In addition, some of the processes described in the specification, claims and the above-mentioned figures of the present application include multiple operations that appear in a specific order, and these operations may not be executed in the order in which they appear in this article or may be executed in parallel. The serial numbers of the operations, such as 201, 202, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0030] First, the vocabulary involved in the embodiments of the present application is explained. It can be understood that this explanation is for a clearer understanding of the embodiments of the present application, and does not necessarily constitute a limitation on the embodiments of the present application.

[0031] A silicon-on-insulator (SOI) substrate includes a top silicon layer, a silicon substrate (or bottom silicon layer), and a silicon dioxide buried oxide layer between the top silicon layer and the silicon substrate.

[0032] Single-mode fiber refers to an optical fiber that has only one transmission mode. The transmission loss and dispersion of single-mode fiber are relatively small. Small transmission loss can make the signal transmit farther in the optical fiber, and small transmission dispersion is conducive to the transmission of high-speed and large-capacity data. Therefore, in communication systems, especially large-capacity communication systems, single-mode fiber is mostly used.

[0033] Single-mode waveguide usually refers to a dielectric device in a photonic chip that is used to guide light waves to propagate therein.

[0034] Mode Field Diameter (MFD), also known as mode spot size, refers to the cross-sectional size of the transmission light beam in an optical fiber or waveguide. Mode spot size is a key parameter in the field of optics and fiber-optic communications, which directly affects the transmission efficiency and quality of light.

[0035] Edge coupler refers to a coupler located at the edge of a photonic chip. The advantages of an end-face coupler are high coupling efficiency and large operating bandwidth.

[0036] Before introducing the preparation method of the cantilever beam type coupler provided in the embodiment of the present application, the structure and working principle of the cantilever beam type coupler are introduced:

[0037] The cantilever beam type coupler in the embodiment of the present application is a type of edge coupler, which can be called a cantilever beam type edge coupler. The cantilever beam type edge coupler is located at the edge of the photonic chip. Figure 1 As shown, the cantilever beam type edge coupler 1 comprises: a substrate 11 and a waveguide layer 12 arranged above the substrate 11; a cavity 110 is provided in the substrate 11, and the waveguide layer 12 comprises: a cantilever waveguide 121 suspended above the cavity 110, anchoring portions 122 fixed on the substrate 11 and located on both sides of the cantilever waveguide 121, and a support beam 123 connected between the cantilever waveguide 121 and the anchoring portions 122, the support beam 123 is used to support the cantilever waveguide 121 to be suspended above the cavity 110, and an opening 124 is opened in the waveguide layer 12 between the cantilever waveguide 121 and the anchoring portions 122.

[0038] In order to provide a good supporting effect, there may be multiple support beams. The multiple support beams are distributed on both sides of the cantilever waveguide. Exemplarily, multiple support beams are arranged on both sides of the cantilever waveguide, and the multiple support beams on the same side of the cantilever waveguide are arranged at intervals, and the above-mentioned opening 124 is opened between any two adjacent support beams on the same side of the cantilever waveguide.

[0039] It should be noted that the waveguide 121 is suspended above the cavity 110 by the support force provided by the support beam 123. Figure 1 The larger the support beam 123 is, the longer the support beam 123 is; the longer the support beam 123 is, the smaller the rigidity of the support beam 123 is, and the easier it is for the support beam 123 to bend or even break, which will inevitably affect the cantilever waveguide in the subsequent packaging process (for example, in some reverse molding processes, it is necessary to Figure 1 The top surface film shown needs to be pressed above the cantilever waveguide to ensure a tight fit for mechanical stability.

[0040] Illustratively, an opening 124 formed in the waveguide layer between the cantilever waveguide and the anchor portion communicates with the cavity 110 in the substrate.

[0041] For example, Figure 1 As shown, part of the space surrounded by the cavity 110 is located directly below the waveguide 121 and part of it is located directly below the anchor 122. It should be noted that if the depth of the cavity is too small, the lower surface of the inverted tapered waveguide structure will be too close to the substrate 11, and the light field in the waveguide (or in the inverted tapered waveguide structure) may leak into the substrate, causing light loss. If the width of the cavity is too large, more of the space surrounded by the cavity will be located directly below the anchor, which will affect the mechanical stability of the anchor, and then affect the mechanical stability of the waveguide.

[0042] Exemplarily, the waveguide layer may be a dielectric layer, such as a SiO2 layer.

[0043] Exemplarily, the cantilever waveguide may be: a SiO2 waveguide.

[0044] Exemplarily, the substrate may be a semiconductor substrate, such as a silicon substrate.

[0045] Exemplarily, the cantilever waveguide has an optical coupling end face, which is used for optical coupling with an external optical element. Usually, the cantilever beam type coupler is arranged on a photonic chip, the photonic chip has a facet, and the optical coupling end face of the cantilever waveguide is located on the chip facet. The facet of the photonic chip is generated by cutting the photonic chip, that is, the facet of the photonic chip refers to the cutting surface of the photonic chip. Exemplarily, the photonic chip can be a part of a wafer, and the photonic chip can be cut from the wafer, and the cutting surface is the facet of the photonic chip.

[0046] Exemplarily, an inverted tapered waveguide structure (or inverted tapered waveguide core layer) is built into the cantilever waveguide. In order to increase the size of the waveguide mode field and match it with the size of the optical fiber mode field, the width of the inverted tapered waveguide structure can be reduced. When the width of the inverted tapered waveguide structure is reduced, its ability to confine the light field is weakened, and part of the light field is distributed in the coated cantilever waveguide, and its mode spot size is increased.

[0047] Exemplarily, the inverted tapered waveguide structure has a variable width along its length direction. Exemplarily, the width of the inverted tapered waveguide structure gradually increases in a direction away from the light coupling end face.

[0048] In one embodiment, the photonic chip may further include a rectangular waveguide structure (or rectangular waveguide core layer) connected to the inverted tapered waveguide structure. Exemplarily, the rectangular waveguide structure has a constant width along its length.

[0049] Exemplarily, the width of the inverted tapered waveguide structure gradually increases to the width of the rectangular waveguide structure in the direction away from the optical coupling end face. For example, the width of the rectangular waveguide structure is 500 nm, the width of the tip of the inverted tapered waveguide structure is 150 nm, and the height of the inverted tapered waveguide structure and the rectangular waveguide structure is 250 nm.

[0050] Exemplarily, the rectangular waveguide structure may be a single-mode waveguide.

[0051] Exemplarily, the rectangular waveguide structure may be a silicon waveguide.

[0052] Exemplarily, the inverted tapered waveguide structure may specifically be an inverted tapered silicon waveguide.

[0053] Exemplarily, the rectangular waveguide structure and the inverted tapered waveguide structure may be integrally formed.

[0054] Exemplarily, the inverted tapered waveguide structure is built into the cantilever waveguide and is not exposed. In other words, the light field is first coupled into the cantilever waveguide and then coupled into the inverted tapered waveguide structure.

[0055] Exemplarily, the tip (or the narrowest end) of the inverted tapered waveguide structure is spaced apart from the optical coupling end face of the cantilever waveguide, for example, the spacing distance is between 0 and 6 microns.

[0056] Taking the cantilever beam edge coupler on the photonic chip for optical coupling between the single-mode waveguide on the photonic chip and the external single-mode optical fiber as an example, the working principle of the cantilever beam edge coupler is briefly introduced:

[0057] In the scenario where the light field enters the photonic chip from the outside, the external single-mode optical fiber is connected to the optical coupling end face of the cantilever waveguide of the cantilever beam edge coupler (for example: fusion splicing), and the light field enters the cantilever waveguide from the external single-mode optical fiber, then enters the inverted tapered waveguide structure, and finally enters the rectangular waveguide structure. Since the width of the end of the inverted tapered waveguide structure close to the optical coupling end face of the cantilever waveguide is smaller, its ability to confine the light field becomes weaker, and part of the light field is distributed in the coated cantilever waveguide, and its mode spot size becomes larger, matching the mode spot size of the single-mode optical fiber, which helps to improve the light coupling efficiency.

[0058] In the scenario where the light field is output from the photonic chip to the outside, the external single-mode optical fiber is connected to the optical coupling end face of the cantilever waveguide of the cantilever beam edge coupler (for example, fusion splicing), and the light field enters the inverted tapered waveguide structure from the rectangular waveguide structure of the photonic chip, then enters the cantilever waveguide from the inverted tapered waveguide structure, and then enters the external optical fiber from the cantilever waveguide. Since the width of the end of the inverted tapered waveguide structure close to the optical coupling end face of the cantilever waveguide is smaller, its ability to confine the light field becomes weaker, and part of the light field is distributed in the coated cantilever waveguide, and its mode spot size becomes larger, matching the mode spot size of the single-mode optical fiber, which helps to improve the light coupling efficiency.

[0059] The cantilever beam edge coupler provided in the embodiment of the present application is used for coupling optical signals across chips. Sometimes a chip is coupled to an optical fiber via a cantilever beam edge coupler. Sometimes a chip is coupled to another chip via a cantilever beam edge coupler. The cantilever beam edge coupler is used as a mode spot size converter in some devices to convert between an optical mode outside the chip and an optical mode supported by a waveguide on the chip.

[0060] The following will be combined Figure 2 A method for preparing a cantilever beam type coupler provided in an embodiment of the present application is introduced. Figure 2 As shown, the method may include the following steps:

[0061] 201. Provide a substrate.

[0062] The substrate may be a semiconductor substrate. The material of the semiconductor substrate may be any semiconductor material, such as silicon, germanium, etc., which is not specifically limited in the embodiments of the present application.

[0063] Exemplarily, the substrate may be a silicon substrate, for example, a silicon wafer.

[0064] Exemplarily, the substrate may be an SOI substrate, for example, an SOI wafer.

[0065] 202. Form a waveguide layer on the substrate.

[0066] like Figure 3 As shown, the waveguide layer 51 is located on the substrate 50, and the waveguide layer 51 may include: a cladding 511 and an inverted tapered waveguide structure 512 covered by the cladding 511. Exemplarily, the cladding 51 may include a lower layer 511a located below the inverted tapered waveguide structure 512 and an upper layer 511b covering the inverted tapered waveguide structure 512.

[0067] Exemplarily, the material of the inverted tapered waveguide structure may be silicon or silicon nitride.

[0068] Exemplarily, the material of the cladding layer may be silicon dioxide.

[0069] The material of the inverted tapered waveguide structure and the material of the cladding can be selected according to actual needs. The embodiment of the present application does not make any specific limitations on this. It only needs to ensure that the refractive index difference between the material of the inverted tapered waveguide structure and the material of the cladding is greater than a preset refractive index threshold.

[0070] Taking the substrate as a silicon substrate as an example, a silicon dioxide layer (that is, the lower layer below the inverted tapered waveguide structure) can be first deposited on the silicon substrate, and then a silicon layer or a silicon nitride layer can be deposited on the silicon dioxide layer. The silicon layer or the silicon nitride layer is etched to form an inverted tapered waveguide structure, and then an upper layer for covering the inverted tapered waveguide structure is deposited to obtain the above-mentioned waveguide layer.

[0071] Taking the substrate as an SOI substrate as an example, the top silicon layer in the SOI substrate can be etched to form an inverted tapered waveguide structure, and then an upper layer (i.e., a covering layer) for covering the inverted tapered waveguide structure can be deposited to obtain the above-mentioned waveguide layer. The lower layer in the waveguide layer located below the inverted tapered waveguide structure is a silicon dioxide buried oxide layer (i.e., a buried oxide layer) in the SOI substrate.

[0072] Optionally, the waveguide layer may further include: a rectangular waveguide structure connected to the inverted tapered waveguide structure. The rectangular waveguide structure and the inverted tapered waveguide structure may be integrally formed, and both are located on the same layer. Exemplarily, the inverted tapered waveguide structure and the rectangular waveguide structure may be formed by etching the silicon layer, the silicon nitride layer, or the top silicon in the SOI substrate. Figure 4 FIG. 4 is a top view of an inverted tapered waveguide structure 41 and a rectangular waveguide structure 42. Figure 4 As shown, the rectangular waveguide structure and the inverted tapered waveguide structure can be integrally formed and both are located in the same layer, and the width of the inverted tapered waveguide structure gradually increases in a direction away from the optical coupling end face to the width value of the rectangular waveguide structure.

[0073] 203. Pattern the waveguide layer to form a waveguide and anchoring portions located on both sides of the waveguide and connected to the waveguide.

[0074] An opening is provided between the waveguide and the anchoring portion, and an inverted tapered waveguide structure is built in the waveguide.

[0075] Exemplarily, the waveguide and the anchoring portion are connected via a support beam, which is a part of the patterned waveguide layer.

[0076] In practical applications, the waveguide layer can be patterned by photolithography, etching and other steps to form the above-mentioned opening, which can be called an etching hole.

[0077] Optionally, after the patterned waveguide layer is obtained through steps such as photolithography and etching, the patterned photoresist layer is removed and the entire substrate is cleaned to remove impurities.

[0078] 204. Using an anisotropic etching process, etch the substrate through the opening to form a groove on the substrate.

[0079] In the present invention, the anisotropic etching process used is an etching process based on physical bombardment, and the isotropic etching process used is an etching process based on chemical reaction.

[0080] In practical applications, the main feature of wet etching is isotropy, that is, etching at the same etching rate in all directions (lateral and longitudinal). This etching method is essentially isotropic because it has the same etching rate in all directions, resulting in undercutting of the etched material under the mask.

[0081] Dry etching uses plasma to etch, and its characteristic is anisotropy, that is, the longitudinal and lateral etching can be strictly controlled. Dry etching does not use solutions, but uses gas to impact the surface of the material for scraping, and its characteristic is high processing precision. The anisotropy of dry etching means that the etching rate in different directions is different, which enables dry etching to preferentially etch in specific directions, leaving other directions, thereby achieving precise control of the material.

[0082] The anisotropic etching process in step 204 may be a dry etching process, such as a plasma etching process. Thus, by utilizing the anisotropy of the dry etching process, it is ensured that the area of ​​the substrate directly below the opening is preferentially etched to form a groove, while the area of ​​the substrate below the patterned waveguide layer is less etched or not etched.

[0083] In this way, it can be ensured that the width of the groove is determined by the opening width rather than the etching time of the dry etching process, and the depth of the groove is determined by the etching time of the dry etching process.

[0084] 205. Etch the substrate through the opening and the groove using an isotropic etching process to form a cavity below the waveguide.

[0085] The anisotropic etching process in step 205 may be a wet etching process. Thus, by utilizing the isotropy of the wet etching process, the area of ​​the substrate below the groove and the area of ​​the substrate below the patterned waveguide layer may be etched at the same etching rate through the opening and the groove, thereby forming a cavity below the waveguide.

[0086] The space enclosed by the cavity is partially located directly below the waveguide and partially located directly below the anchoring portion. Figure 1 shown.

[0087] The width of the cavity is determined by the etching time of the wet etching process, that is, the width of the cavity can be precisely controlled by controlling the etching time of the wet etching process, and the depth of the cavity is the sum of the first depth and the second depth. Among them, the first depth is the depth obtained by the dry etching process in step 204, and the second depth is the depth obtained by the wet etching process in step 205. The longitudinal and lateral etching rates of the wet etching process are close to 1:1, that is, it is impossible to independently control the size of the second depth and the size of the width of the cavity. However, since the first depth can be determined by the etching time of the dry etching process, the depth of the cavity can be precisely controlled by controlling the etching time of the dry etching process.

[0088] Optionally, in the above step 203 , a hard mask layer may be used to transfer the fine pattern of the photoresist to a sufficient depth on the substrate to avoid pattern collapse.

[0089] That is, the above step 203 can be implemented by the following steps:

[0090] 2031. Form a hard mask layer on the waveguide layer.

[0091] 2032. Pattern the hard mask layer to obtain the patterned hard mask layer.

[0092] 2033. Transfer the pattern of the patterned hard mask layer to the waveguide layer through an etching process to form a waveguide and anchoring parts located on both sides of the waveguide and connected to the waveguide.

[0093] In one feasible solution, Figure 5As shown, a waveguide layer 51 is formed on a substrate 50, a hard mask layer 52 is formed on the waveguide layer 51, and then a photoresist layer 53 is formed on the hard mask layer 52. The photoresist layer 53 is photoetched to obtain a patterned photoresist layer; the hard mask layer 52 is etched to transfer the pattern of the photoresist layer to the hard mask layer to obtain a patterned hard mask layer; the waveguide layer 51 is further etched to transfer the pattern of the hard mask layer to the waveguide layer, thereby obtaining a patterned waveguide layer. After step 203, the following is obtained: Figure 6 The semiconductor structure shown includes an opening 60 formed by etching.

[0094] Exemplarily, the waveguide layer may be etched by an anisotropic etching process. In practical applications, generally, dry etching has anisotropic characteristics, and wet etching has isotropic characteristics. The anisotropic etching process may be a dry etching process, such as reactive ion etching, ion beam etching, plasma etching, etc.

[0095] In order to facilitate the removal of the excess hard mask layer by wet etching in the subsequent process, when selecting a material for the hard mask layer 52, a material whose etching selectivity ratio with the material of the cladding in the waveguide layer 51 under the same etching conditions is greater than a preset threshold can be selected. The etching selectivity ratio of two materials is the ratio of the larger etching rate to the smaller etching rate of the etching rates of the two materials under the same etching conditions. The preset threshold can be set according to actual needs, and the present application does not make specific restrictions on this. For example, when the material of the cladding in the waveguide layer 51 is silicon dioxide, the material of the hard mask layer 52 can be silicon nitride.

[0096] In practical applications, we can obtain Figure 6 After the semiconductor structure shown in FIG. 1 is formed, the redundant photoresist layer 53 can be removed and the impurities can be removed by cleaning to obtain the semiconductor structure shown in FIG. Figure 7 The semiconductor structure shown.

[0097] Optionally, in order to prevent the etching process in the subsequent steps 204 and 205 from affecting the sidewalls of the opening, a sidewall protection film may be formed on the sidewalls of the opening. The sidewall protection film may prevent the subsequent etching process from etching the sidewalls of the opening, thereby ensuring that the subsequent etching process does not change the width of the opening. Figure 7 As shown, the width d1 of the opening is determined by the patterning process in step 203 and is not affected by the subsequent etching process. In this way, the subsequent etching process will not widen the opening width d1, thereby ensuring the mechanical stability of the waveguide.

[0098] In an optional embodiment, after transferring the pattern of the patterned hard mask layer to the waveguide layer by an etching process (i.e., step 203) and before etching the substrate through the opening by an anisotropic etching process (i.e., step 204), the method further includes:

[0099] 206. Deposit a sidewall mask layer on the patterned hard mask layer.

[0100] For example, a sidewall mask layer can be deposited on the imaged hard mask layer by an atomic layer deposition (ALD) process. The good step coverage capability of the atomic layer deposition process is utilized to form a sidewall mask layer of uniform thickness on the surface. It should be noted that the step coverage capability is one of the process characteristics of the atomic layer deposition process.

[0101] Exemplarily, the thickness of the sidewall mask layer is between 40 nm and 75 nm.

[0102] Exemplarily, the thickness of the sidewall mask layer is 60 nm.

[0103] like Figure 8 As shown, the sidewall mask layer 54 includes a first portion covering the upper surface of the patterned hard mask layer 52 and the upper surface of the substrate 50 and a second portion covering the sidewall in the opening 60 .

[0104] The material of the sidewall mask layer can be selected according to actual needs, and the material can be an insulating material or a dielectric material.

[0105] Optionally, the material of the sidewall mask layer is the same as that of the hard mask layer. In this way, after the cavity is subsequently formed, the redundant sidewall mask layer and the hard mask layer can be removed at one time.

[0106] 207. Using an anisotropic etching process, remove the first portion of the sidewall mask layer and retain the second portion of the sidewall mask layer.

[0107] After step 207, the following is obtained: Fig. 9 The second portion of the sidewall mask layer covering the sidewall in the opening 60 forms a sidewall protection film for protecting the sidewall in the opening 60 .

[0108] It should be noted that Fig. 9 In the process, the patterned hard mask layer 52 can protect the patterned waveguide layer in the subsequent steps 204 and 205.

[0109] The etching time of the anisotropic etching process in step 207 can be selected according to the thickness of the sidewall mask layer, and it only needs to ensure that the substrate 50 can be exposed.

[0110] In the embodiment of the present application, the process of preparing the cavity is divided into two steps, namely step 204 and step 205 .

[0111] against Fig. 9 The semiconductor structure shown in FIG. 1 is subjected to step 204, that is, the substrate 50 is etched through the opening 60 by an anisotropic etching process to form a groove 501 on the substrate 50. Fig.10 The depth of the groove 501 is d2. The size of d2 is proportional to the etching time of step 204.

[0112] The anisotropic etching process is mainly an etching process based on physical bombardment. By adjusting the etching time of step 204, the size of d2 can be adjusted, and then the final cavity depth can be adjusted.

[0113] against Fig.10 The semiconductor structure shown in FIG. 1 is subjected to step 205, that is, the substrate 50 is etched through the opening 60 and the groove 501 by an isotropic etching process to form a cavity 502 below the waveguide 511, as shown in FIG. Fig.11 shown.

[0114] like Fig.11 As shown, the depth obtained by the isotropic etching process in step 205 is d3, and the size of d3 is proportional to the etching time of step 205. The depth of cavity 502 is the sum of d2 and d3.

[0115] like Fig.11 As shown, the isotropic etching process in step 205 etches a width of d4, where d4 is also the width of the cavity, and the size of d4 is proportional to the etching time of step 205.

[0116] Based on this, according to the specific values ​​of the final required depth and width of the cavity, the specific values ​​of d2 and d3 can be determined, and then according to the specific values ​​of d2 and d3, the etching time of step 204 and step 205 can be arranged to obtain the required depth and width of the cavity.

[0117] Illustratively, in the above step 205, "the step of etching the substrate through the opening and the groove using an isotropic etching process to form a cavity below the waveguide" may include: etching the substrate through the opening and the groove using an isotropic etching process according to a preset first etching time to form a cavity below the waveguide; the first etching time is related to the desired cavity width.

[0118] Illustratively, in the above step 204, "using an anisotropic etching process to etch the substrate through the opening to form a groove on the substrate" may include: according to a preset second etching time, using an anisotropic etching process to etch the substrate through the opening to form a groove on the substrate; the second etching time is related to the required cavity depth and the first etching time.

[0119] The specific calculation method of the first etching time and the second etching time can be designed according to actual needs, and the embodiment of the present application does not make any specific limitation on this.

[0120] Optionally, after step 205, the method may further include:

[0121] 208. Use an isotropic etching process to remove the imaged hard mask layer and a second portion of the sidewall mask layer covering the sidewall in the opening.

[0122] For example, the imaged hard mask layer and the second portion of the sidewall mask layer covering the sidewall in the opening can be removed by a wet etching process, thereby obtaining Fig.12 The semiconductor structure shown.

[0123] For example, when the materials of the hard mask layer and the sidewall mask layer are both silicon dioxide, the excess silicon nitride layer may be removed by hot phosphoric acid wet etching.

[0124] Subsequently, the cantilever waveguide can be obtained by cutting the waveguide, and the cut end face formed by the cutting on the cantilever waveguide is used for optical coupling with an external optical element, that is, the optical coupling end face.

[0125] In summary, the cavity depth and width of the cantilever beam edge coupler are regulated separately by introducing the sidewall protection process (i.e., forming a sidewall protection layer). The width d1 of the opening is precisely regulated by chip design (groove design dimensions) and process step 203; the cavity width d4 is precisely regulated by adjusting the etching time of step 205; and the cavity depth is precisely regulated by adjusting the etching time of step 204 based on the determined etching time of step 205.

[0126] The embodiment of the present application also provides a photonic chip. The photonic chip may include the cantilever beam coupler involved in the above embodiments. Exemplarily, the photonic chip may be a photonic computing chip, and exemplary, the photonic computing chip is a photonic computing chip based on a neural network.

[0127] Exemplarily, the photonic chip may also include the above-mentioned rectangular waveguide.

[0128] The present application also provides an optical computing device, which may include the photonic chip mentioned in the above embodiment.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application is described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents; and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application. In addition, if two or more features, systems, products, materials and / or methods described herein do not contradict each other, any combination of these features, systems, products, materials and / or methods is included within the scope of the present disclosure.

Claims

1. A method for preparing a cantilever beam coupler, characterized in that: include: providing a substrate; forming a waveguide layer on the substrate; Patterning the waveguide layer to form a waveguide and anchoring portions located on both sides of the waveguide and connected to the waveguide; An opening is provided between the waveguide and the anchoring portion; an inverted tapered waveguide structure is built into the waveguide; Using an anisotropic etching process, etching the substrate through the opening to form a groove on the substrate; The substrate is etched through the opening and the trench using an isotropic etching process to form a cavity below the waveguide.

2. The method according to claim 1, characterized in that The waveguide layer is patterned to form a waveguide and anchoring portions located on both sides of the waveguide and connected to the waveguide, comprising: forming a hard mask layer on the waveguide layer; Patterning the hard mask layer to obtain the patterned hard mask layer; The pattern of the patterned hard mask layer is transferred to the waveguide layer through an etching process to form a waveguide and anchoring parts located on both sides of the waveguide and connected to the waveguide, and the waveguide and the anchoring parts are connected through a supporting beam.

3. The method according to claim 2, characterized in that After transferring the pattern of the patterned hard mask layer to the waveguide layer by an etching process and before etching the substrate through the opening by an anisotropic etching process, the method further includes: Depositing a sidewall mask layer on the patterned hard mask layer; the sidewall mask layer includes a first portion covering an upper surface of the patterned hard mask layer and an upper surface of the substrate and a second portion covering a sidewall in the opening; The first portion of the sidewall mask layer is removed by an anisotropic etching process, and the second portion of the sidewall mask layer is retained.

4. The method according to claim 3, characterized in that: Depositing a sidewall mask layer on the patterned mask layer comprises: A sidewall mask layer is deposited on the patterned hard mask layer using an atomic deposition process.

5. The method according to claim 3, characterized in that: After etching the substrate through the opening and the groove using an isotropic etching process to form a cavity below the waveguide, the method further includes: The patterned hard mask layer and a second portion of the sidewall mask layer covering the sidewall in the opening are removed by an isotropic etching process.

6. The method according to any one of claims 1 to 5, characterized in that The substrate comprises a silicon-on-insulator substrate; the silicon-on-insulator substrate comprises a back substrate, a top silicon layer, and a buried oxide layer located between the back substrate and the top silicon layer; forming a waveguide layer on the substrate, comprising: patterning the top silicon layer to form the inverted tapered waveguide structure; forming a covering layer for covering the inverted tapered waveguide structure to obtain the waveguide layer; The waveguide layer includes the buried oxide layer, the inverted tapered waveguide structure and the cover layer; The inverted tapered waveguide structure is located in the waveguide.

7. The method according to any one of claims 1 to 5, characterized in that The cantilever beam type coupler comprises a cantilever waveguide, which is obtained by cutting the waveguide. The cut end face formed by the cutting on the cantilever waveguide is used for optical coupling with an external optical element. The width of the inverted tapered waveguide structure gradually increases in a direction away from the cut end face.

8. The method according to any one of claims 1 to 5, characterized in that The step of etching the substrate through the opening and the groove by an isotropic etching process to form a cavity below the waveguide comprises: According to a preset first etching time, the substrate is etched through the opening and the groove by using an isotropic etching process to form a cavity below the waveguide; The first etching time is related to the required cavity width.

9. The method according to claim 8, characterized in that The substrate is etched through the opening by an anisotropic etching process to form a groove on the substrate, comprising: According to a preset second etching time, the substrate is etched through the opening using an anisotropic etching process to form a groove on the substrate; The second etching time is related to the required cavity depth and the first etching time.

10. A photonic chip, characterized in that: The invention comprises a cantilever beam type coupler prepared by the preparation method according to any one of claims 1 to 9.

11. An optical computing device, characterized in that include: The photonic chip as described in claim 10 above.

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