First In First Out control system, chip

Abstract

The present invention discloses a first-in first-out control system and a chip, relating to the technical field of first-in first-out. Among them, the system includes: a plurality of first-in first-out buffers; a control circuit, the input end of the control circuit is connected to the output end of an external data generation device, the first output end of the control circuit is connected to the write ends of the plurality of first-in first-out buffers, the read end of the control circuit is connected to the readout ends of the plurality of first-in first-out buffers, and the second output end of the control circuit is connected to the input end of an external data receiving device. The control circuit is used for determining at least one first target buffer from the plurality of first-in first-out buffers, and writing the data to be written generated by the external data generation device into the first target buffer; determining at least one second target buffer from the plurality of first-in first-out buffers, reading data from the second target buffer, and sending the read data to the external data receiving device, wherein the number of the first target buffers is the same as that of the second target buffers.

Description

Technical Field

[0001] The present invention relates to the technical field of first-in first-out, and particularly to a first-in first-out control system and a chip. Background Art

[0002] FIFO (First Input First Output) is a commonly used data buffer and memory in chip design, which has the characteristic of first-in first-out. Asynchronous FIFO is usually used to store some data across clock domains. It is of great significance to read and write data based on first-in first-out. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, the first object of the present invention is to propose a first-in first-out control system to realize data reading and writing based on first-in first-out.

[0004] The second object of the present invention is to propose a chip.

[0005] To achieve the above object, a first-in first-out control system according to an embodiment of the first aspect of the present invention includes: a plurality of first-in first-out buffers; a control circuit, an input end of the control circuit is connected to an output end of an external data generating device, a first output end of the control circuit is connected to a writing end of the plurality of first-in first-out buffers, a reading end of the control circuit is connected to a reading out end of the plurality of first-in first-out buffers, a second output end of the control circuit is connected to an input end of an external data receiving device, and the control circuit is configured to determine at least one first target buffer from the plurality of first-in first-out buffers, and write the data to be written generated by the external data generating device into the first target buffer; determine at least one second target buffer from the plurality of first-in first-out buffers, read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffers is the same as that of the second target buffers.

[0006] In addition, the first-in first-out control system according to an embodiment of the present invention may further have the following additional technical features:

[0007] In an embodiment of the present invention, the control circuit includes a mode control device and a write controller. The output end of the mode control device is connected to the control end of the write controller. The input end of the write controller is designed as the input end of the control circuit, and the output end of the write controller is designed as the first output end of the control circuit. Wherein, when the mode control device controls the working mode of the write controller to be the combined mode, the write controller is used to determine that the first target buffer is all the first-in-first-out buffers, and write the data to be written into the first target buffer; when the mode control device controls the working mode of the write controller to be the split mode, the write controller is used to determine one of the first-in-first-out buffers as the first target buffer according to the data type of the data to be written, and write the data to be written into the first target buffer.

[0008] In an embodiment of the present invention, the write controller includes: a plurality of first selection devices, and the output ends of the plurality of first selection devices are respectively connected to the write ends of the plurality of first-in-first-out buffers in one-to-one correspondence; a write control circuit includes a plurality of output ends, and the plurality of output ends of the write control circuit are respectively connected to the first input ends of the plurality of first selection devices in one-to-one correspondence. The write control circuit is used to determine the first target buffer and output a first write enable signal to the first selection device corresponding to the first target buffer; a selector includes a plurality of output ends, and the plurality of output ends of the selector are respectively connected to the second input ends of the plurality of first selection devices in one-to-one correspondence. The selector is used to determine the first target buffer and output a second write enable signal to the first selection device corresponding to the first target buffer. Wherein, when the working mode is the combined mode, the first selection device is used to send the first write enable signal to the first-in-first-out buffer, and when the working mode is the split mode, the first selection device is used to send the second write enable signal to the first-in-first-out buffer.

[0009] In an embodiment of the present invention, the control circuit further includes a write counter. The write counter is used to generate a first counting result according to the data to be written. The write control circuit includes: a plurality of first enable devices, and the output ends of the plurality of first enable devices are respectively connected to the first input ends of the plurality of first selection devices in one-to-one correspondence. The control ends of the plurality of first enable devices are all connected to the output end of the write counter. Each first enable device stores a first trigger data, and the first trigger data stored in any two first enable devices are different. For any one of the first enable devices, when the first counting result is consistent with the first trigger data stored in the first enable device, the first enable device outputs the first write enable signal.

[0010] In an embodiment of the present invention, the control circuit further includes a read controller. The control end of the read controller is connected to the output end of the mode control device. The reading end of the read controller is designed as the reading end of the control circuit. The output end of the read controller is designed as the second output end of the control circuit. The read controller is used to read data from the second target buffer. Wherein, when the mode control device controls the working mode of the read controller to be the combined mode, the read controller determines that the second target buffer is all the first-in-first-out buffers. When the mode control device controls the working mode of the read controller to be the split mode, the read controller determines one of the second target buffers from multiple first-in-first-out buffers.

[0011] In an embodiment of the present invention, the control circuit further includes a read counter. The read counter is used to generate a second counting result. The read controller includes: a plurality of second enabling devices. The output ends of the plurality of second enabling devices are respectively connected to the reading ends of the plurality of first-in-first-out buffers in one-to-one correspondence. The control ends of the plurality of second enabling devices are all connected to the output end of the read counter. Each of the second enabling devices stores a second trigger data, and the second trigger data stored in any two of the second enabling devices are different. For any one of the second enabling devices, when the second counting result is consistent with the second trigger data stored in the second enabling device, the second enabling device outputs a first read enabling signal to the corresponding first-in-first-out buffer.

[0012] In an embodiment of the present invention, the read controller further includes: a plurality of second selection devices. The output ends of the plurality of second selection devices are respectively connected to the writing ends of the plurality of first-in-first-out buffers in one-to-one correspondence. The first input ends of the plurality of second selection devices are respectively connected to the output ends of the plurality of second enabling devices in one-to-one correspondence. The second input ends of the plurality of second selection devices are respectively connected to the plurality of output ends of the reader. The reader is used to determine the second target buffer and output a second read enabling signal to the corresponding first selection device. Wherein, when the working mode is the combined mode, the second selection device is used to send the first read enabling signal to the first-in-first-out buffer. When the working mode is the split mode, the second selection device is used to send the second read enabling signal to the first-in-first-out buffer.

[0013] In an embodiment of the present invention, the read controller further includes: a third selection device, wherein a plurality of input ends of the third selection device are respectively and correspondingly connected to the read-out ends of a plurality of the first-in first-out (FIFO) buffers, a control end of the third selection device is connected to the read counter, an output end of the third selection device is designed as an output end of the read controller, and the third selection device is configured to determine a second target buffer according to the second counting result, read data from the second target buffer, and send the read data to the external data receiving device.

[0014] In an embodiment of the present invention, the read controller further includes: a fourth selection device, wherein a first input end of the fourth selection device is connected to an output end of the third selection device, a second input end of the fourth selection device is connected to a read-out end of a preset first-in first-out buffer, an output end of the fourth selection device is designed as an output end of the read controller, a control end of the fourth selection device is connected to an output end of the mode control device, and the fourth selection device is configured to, when the working mode is a combined mode, send the data read by the third selection device to the external data receiving device, and, when the working mode is a split mode, read data from the preset first-in first-out buffer and send the read data to the external data receiving device.

[0015] To achieve the above object, an embodiment of the second aspect of the present invention provides a chip, including the above-mentioned first-in first-out control system.

[0016] According to the first-in first-out control system and the chip of the embodiments of the present invention, a plurality of first-in first-out buffers are provided; a control circuit, an input end of the control circuit is connected to an output end of an external data generating device, a first output end of the control circuit is connected to write-in ends of a plurality of first-in first-out buffers, a read end of the control circuit is connected to read-out ends of a plurality of first-in first-out buffers, a second output end of the control circuit is connected to an input end of an external data receiving device, and the control circuit is configured to determine at least one first target buffer from a plurality of first-in first-out buffers, write data to be written generated by the external data generating device into the first target buffer, and determine at least one second target buffer from a plurality of first-in first-out buffers, read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffers is the same as that of the second target buffers. Through the first-in first-out control system, it is possible to meet the requirements of depth or read speed by adjusting the number of the first target buffers and the second target buffers, so as to achieve high-performance first-in first-out control.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0018] Figure 1 is the structural block diagram of the FIFO control system according to an embodiment of the present invention;

[0019] Figure 2 is the structural schematic diagram of the write controller according to an example of the present invention;

[0020] Figure 3 is the structural schematic diagram of the read controller according to an example of the present invention;

[0021] Figure 4 is the structural schematic diagram of the read controller according to another example of the present invention;

[0022] Figure 5 is the structural schematic diagram of the FIFO control system according to an example of the present invention;

[0023] Figure 6 is the structural block diagram of the chip according to an embodiment of the present invention. Detailed implementation manners

[0024] The following describes the FIFO control system and the chip according to the embodiments of the present invention with reference to the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described with reference to the accompanying drawings are exemplary and should not be construed as limiting the present invention.

[0025] A FIFO usually has a write port and a read port. Data is read according to the principle of first in first out. It is not possible to directly read the data at a specific position. Only by reading out all the previous data can the data at a specific position be obtained. In order to utilize the FIFO for data reading and writing, the following three methods can be adopted:

[0026] First, the FIFO depth is greater than the maximum amount of data that can be stored at one time, that is, a FIFO with a large depth, which can prevent data loss caused by the FIFO being full due to the write speed being greater than the read speed. However, since the data is first in first out and cannot be read according to certain application rules, in some practical applications, various types of data are stored in this FIFO, but the software only needs a certain type of data at a certain time. This results in the software having to read out all the data, screen out the data it needs and take it away, and store the unnecessary data in a section of memory for other sub-applications to read. This will consume the time for reading and transfer, the screening time, and also consume the storage space of the memory.

[0027] Second, there are multiple FIFOs. Data is written into different FIFOs according to the rules of the application based on the configuration. The hardware performs data screening and processing before writing. In this way, the data read by the software from different FIFOs can be processed immediately, without the need for the software to perform screening and processing again, nor the need for data transfer and storage. However, the disadvantage is that due to area and cost limitations, the depth of each FIFO is limited. When the data is of the same type and needs to be stored in the same FIFO, and the data volume is greater than the FIFO depth, data loss will occur, unable to meet the requirements.

[0028] Third, a combination of multiple small FIFOs and a large FIFO can take into account the advantages of the first two solutions and overcome their disadvantages. However, this will increase the chip area and cost. In two different application scenarios, there is always a part of the FIFO idle and wasted.

[0029] Therefore, the present invention proposes a first-in-first-out control system.

[0030] Figure 1 It is a schematic structural diagram of the first-in-first-out control system according to an embodiment of the present invention.

[0031] As Figure 1 shown, the first-in-first-out control system 100 includes: a plurality of first-in-first-out buffers 200; a control circuit 300, the input end of the control circuit 300 is connected to the output end of an external data generation device, the first output end of the control circuit 300 is connected to the write end of the plurality of first-in-first-out buffers 200, the read end of the control circuit 300 is connected to the read end of the plurality of first-in-first-out buffers 200, the second output end of the control circuit 300 is connected to the input end of an external data receiving device, the control circuit 300 is configured to determine at least one first target buffer from the plurality of first-in-first-out buffers 200, and write the data to be written generated by the external data generation device into the first target buffer, the control circuit 300 is further configured to determine at least one second target buffer from the plurality of first-in-first-out buffers 200, read the data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffer and the second target buffer is the same.

[0032] It should be noted that Figure 1 only shows the connection relationship between the first-in-first-out buffer 200 and the control circuit 300, does not show that the control circuit 300 includes an input end, a first output end, a second output end and a read end, nor does it show that the first-in-first-out buffer 200 includes a write end and a read end.

[0033] Specifically, in order to achieve the use of a large-depth first-in-first-out buffer 200, and be able to quickly read data, and without increasing the chip area and cost, the first-in-first-out control system 100 as described above is designed.

[0034] In the FIFO control system 100, a control circuit 300 and a plurality of FIFO buffers 200 are included. The control circuit 300 can determine at least one first target buffer from the plurality of FIFO buffers 200, and write the data to be written generated by an external data generation device into the first target buffer. The control circuit 300 can also determine at least one second target buffer from the plurality of FIFO buffers 200, and read data from the second target buffer.

[0035] Through this system, the depth of the FIFO buffer 200 and the data reading speed can be freely adjusted according to actual needs.

[0036] Specifically, when there is a requirement for the data reading speed of the buffer, the number of the first target buffer and the second target buffer can be determined to be one. At this time, for each received data to be written, the corresponding first target buffer is determined, and the data to be written is written into the first target buffer. In this way, when data needs to be read, it can be determined in which FIFO buffer 200 the data to be read is stored. After determining the FIFO buffer 200 storing the data to be read, the FIFO buffer 200 storing the data to be read is used as the second target buffer, and data is read from the second target buffer.

[0037] When there is a requirement for the depth of the buffer, the number of the first target buffer and the second target buffer can be determined to be multiple according to the actual depth requirement. At this time, the buffers that can accommodate the data to be written are the multiple first target buffers. Since there are multiple first target buffers, data to be written with a larger data volume can be accommodated, thereby realizing a buffer with a high depth.

[0038] Taking the number of the first target buffers as three as an example, obviously, the data volume that can be stored in three buffers is greater than that in one buffer. That is to say, when the number of the first target buffers is three, the control circuit 300 can write at most the data to be written with a data volume equal to the storage capacity of the three buffers into the first target buffer, thereby realizing a buffer with a high depth. Moreover, the buffer with a high depth still follows the first-in, first-out rule.

[0039] Therefore, a first-in-first-out control system 100 is provided, including: a plurality of first-in-first-out buffers 200; a control circuit 300, the input end of the control circuit 300 is connected to the output end of an external data generation device, the first output end of the control circuit 300 is connected to the write ends of the plurality of first-in-first-out buffers 200, the read end of the control circuit 300 is connected to the read ends of the plurality of first-in-first-out buffers 200, and the second output end of the control circuit 300 is connected to the input end of an external data receiving device. The control circuit 300 is configured to determine at least one first target buffer from the plurality of first-in-first-out buffers 200, write the data to be written generated by the external data generation device into the first target buffer, and determine at least one second target buffer from the plurality of first-in-first-out buffers 200, read data from the second target buffer, and send the read data to the external data receiving device, where the number of the first target buffers is the same as that of the second target buffers. Through the first-in-first-out control system 100, it is possible to meet the requirements of depth or read speed by adjusting the number of the first target buffers and the second target buffers, thereby achieving high-performance first-in-first-out control.

[0040] In some embodiments of the present invention, the control circuit 300 includes a mode control device and a write controller. The output end of the mode control device is connected to the control end of the write controller. The input end of the write controller is designed as the input end of the control circuit 300, and the output end of the write controller is designed as the first output end of the control circuit 300. Wherein, when the mode control device controls the working mode of the write controller to be the combined mode, the write controller is configured to determine that the first target buffer is all the first-in-first-out buffers 200 and write the data to be written into the first target buffer; when the mode control device controls the working mode of the write controller to be the split mode, the write controller is configured to determine a first target buffer from the plurality of first-in-first-out buffers 200 according to the data type of the data to be written and write the data to be written into the first target buffer.

[0041] Specifically, in order to better meet the two requirements of depth and read speed, the working modes are set to include the combined mode and the split mode. When there is a requirement for depth, the mode control device controls the working mode of the write controller to be the combined mode. When there is a requirement for speed, the mode control device controls the working mode of the write controller to be the split mode.

[0042] In the combined mode, the write controller determines that the first target buffer is all the first-in-first-out buffers 200 and writes the data to be written into the first target buffer.

[0043] Moreover, in order to write the data to be written into the first target buffer, for each data to be written, a buffer corresponding to the data to be written can be selected from the first target buffer, and the data to be written can be written into the corresponding buffer.

[0044] That is to say, in the combined mode, the first target buffer is the entire first-in-first-out buffer 200. Since there are multiple first-in-first-out buffers 200, they can accommodate a large amount of data to be written. Therefore, when the data generation circuit generates the data to be written, the write controller splits the data to be written into at least two pieces of data to be written, and writes the data to be written into the first-in-first-out buffer 200. As an example, assume that there are three pieces of data to be written, namely data to be written 1, data to be written 2, and data to be written 3. The first target buffer corresponding to data to be written 1 is the first buffer, the first target buffer corresponding to data to be written 2 is the second buffer, and the first target buffer corresponding to data to be written 3 is the third buffer. Then, data to be written 1 is written into the first buffer, data to be written 2 is written into the second buffer, and data to be written 3 is written into the third buffer.

[0045] It can be seen that at this time, the above-mentioned multiple first-in-first-out buffers 200 can be regarded as a whole, so as to achieve high depth.

[0046] In the split mode, the write controller determines the first target buffer from the multiple first-in-first-out buffers 200 according to the data type of the data to be written, and writes the data to be written into the first target buffer.

[0047] That is to say, in the split mode, after the data generation circuit generates the data to be written, the write controller will determine a first target buffer from the multiple first-in-first-out buffers 200 according to the type of the data to be written, and write the data to be written into the first target buffer. At this time, when it is necessary to read the data to be written, the first target buffer corresponding to the data to be written can be determined according to the type of the data to be read, and the data can be read from the first target buffer, so as to achieve high-speed reading.

[0048] In some embodiments of the present invention, the write controller includes: a plurality of first selection devices, the output ends of the plurality of first selection devices are respectively connected to the writing ends of the plurality of first-in-first-out buffers 200 in one-to-one correspondence; a writing control circuit includes a plurality of output ends, the plurality of output ends of the writing control circuit are respectively connected to the first input ends of the plurality of first selection devices in one-to-one correspondence, and the writing control circuit is used to determine the first target buffer and output a first write enable signal to the first selection device corresponding to the first target buffer; a selector includes a plurality of output ends, the plurality of output ends of the selector are respectively connected to the second input ends of the plurality of first selection devices in one-to-one correspondence, and the selector is used to determine the first target buffer and output a second write enable signal to the first selection device corresponding to the first target buffer; wherein, when the working mode is the combined mode, the first selection device is used to send the first write enable signal to the first-in-first-out buffer 200, and when the working mode is the split mode, the first selection device is used to send the second write enable signal to the first-in-first-out buffer 200.

[0049] Thus, by providing a write control circuit and a selector, the write control circuit is used to output a first write enable signal required in the combined mode, and the selector is used to output a second write enable signal required in the split mode. The first selection device can determine whether the write enable signal sent to the first-in-first-out buffer 200 is the first write enable signal or the second write enable signal. With this arrangement, it is possible to achieve switching between the combined mode and the split mode by only controlling the first selection device, thereby realizing high-speed and efficient mode switching.

[0050] In some embodiments of the present invention, the control circuit 300 further includes a write counter, which is used to generate a first counting result according to the data to be written. The write control circuit includes: a plurality of first enable devices, the output terminals of the plurality of first enable devices are respectively and correspondingly connected to the first input terminals of the plurality of first selection devices, the control terminals of the plurality of first enable devices are all connected to the output terminal of the write counter, and each first enable device stores a first trigger data, and the first trigger data stored in any two first enable devices are different. For any one of the first enable devices, when the first counting result is consistent with the first trigger data stored in the first enable device, the first enable device outputs a first write enable signal.

[0051] Specifically, the control circuit 300 is further provided with a write counter, and the write control circuit is provided with a plurality of first enable devices. The write counter is used to generate a first counting result, and the first comparison result is used to compare the first counting result with the first trigger data stored therein, and confirm whether to output a first write enable signal according to the comparison result.

[0052] To generate the first counting result, the write counter can be set to increase the first counting result by a preset value when generating a data to be written. For example, the control circuit 300 can be set to generate a write signal every time it receives a data to be written, and the write counter adds one to the first counting result every time it receives a write signal.

[0053] After a certain first-in-first-out buffer 200 receives the first write enable signal, the write controller can write the current data to be written into the first-in-first-out buffer 200.

[0054] Thus, it is possible to control which of the plurality of first enable devices outputs the first write enable signal according to the first counting result generated by the write counter, so as to determine which first-in-first-out buffer 200 the current data to be written is specifically written into according to the first counting result generated by the write counter. With this arrangement, it is possible to simply and accurately write the data to be written into the first-in-first-out buffer 200.

[0055] The above-mentioned write controller will be described below with a specific example.

[0056] Specifically, referring to Figure 2 , in Figure 2 , 1 is a mode control device, 2 is a write controller, 3 is a first selection device, 4 is a write control circuit, 5 is a selector, 6 is a write counter, 7 is a first enabling device, 8 is a first AND gate, and 9 is a second AND gate.

[0057] The number of first-in-first-out buffers 200 is M. Figure 2 Among the write FIFOs 0, 1, 2, …, M - 1 in

[0058] Figure 2 , write FIFO0 means it is connected to the first first-in-first-out buffer 200, write FIFO1 means it is connected to the second first-in-first-out buffer 200, write FIFO2 means it is connected to the third first-in-first-out buffer 200, and write FIFOM - 1 means it is connected to the Mth first-in-first-out buffer 200. Figure 2 The 0, 1, 2, …, M - 1 in

[0059] are the ports of the selector 5 connected to the first-in-first-out buffer 200.

[0060] Among them, the first control signal indicating the working mode as the combined mode output by the mode control device 1 is a high-level signal, and the write signal is a high-level signal.

[0061] When the mode control device 1 controls the working mode to be the combined mode, the mode control device 1 outputs a combined mode enabling signal of a high-level signal, and this high-level signal is output to the first AND gate 8 and also output to the first selection device 3. When the mode control device 1 controls the working mode to be the split mode, the mode control device 1 outputs a split mode enabling signal to the first selection device 3.

[0062] It can be seen that in the combined mode, when generating the first data to be written, the control circuit 300 generates a write signal, the first AND gate 8 outputs a high level, the write counter 6 adds 1 to the first counting result from -1 to get 0. At this time, the first enabling device 7 with the first trigger data being 0 outputs a first write enabling signal with a high level. Since the write signal is a high-level signal, the corresponding second AND gate 9 will output the first write enabling signal output by the first enabling device 7 with the first trigger data being 0 to the corresponding first selection device 3, and then output the first write enabling signal to the writing end of the first first-in-first-out buffer 200.

[0063] After the first write enabling signal is output to the first first-in-first-out buffer 200, the write controller 2 can write the above-mentioned first data to be written into the first first-in-first-out buffer 200.

[0064] When generating the second data to be written, the control circuit 300 generates a write signal, the first AND gate 8 outputs a high level, the write counter 6 adds 1 to the first counting result from 0 to get 1. At this time, the first enabling device 7 with the first trigger data being 1 outputs a first write enabling signal with a high level. Since the write signal is a high-level signal, the corresponding second AND gate 9 will output the first write enabling signal output by the first enabling device 7 with the first trigger data being 1 to the corresponding first selection device 3, and then output it to the writing end of the second first-in-first-out buffer 200.

[0065] After the first write enabling signal is output to the second first-in-first-out buffer 200, the write controller 2 can write the above-mentioned second data to be written into the second first-in-first-out buffer 200.

[0066] Continuously performing the above operations, in the combined mode, the write counter 6 will add 1 when the write signal comes. When the count reaches M, it will automatically return to 0. The write controller 2 decides which first-in-first-out buffer 200 to write the data into according to the comparison of the value of the write counter 6.

[0067] In the split mode, the selector 5 in the write controller 2 writes the data into the corresponding first-in-first-out buffer 200 according to the user configuration and the characteristics of the data to be written itself.

[0068] For example, assuming that according to the characteristics of the first data to be written, it is determined that the first data to be written needs to be written into the first first-in-first-out buffer 200, then it can be controlled by the selector 5 itself, or according to the user configuration, a second write enabling signal is sent through port 0 on the selector 5. Since the current working mode is the split mode, the first selection device 3 will send the second write enabling signal to the first first-in-first-out buffer 200. After the first first-in-first-out buffer 200 receives the write enabling signal, the write controller 2 can write the above-mentioned first data to be written into the first first-in-first-out buffer 200.

[0069] For another example, assuming that according to the characteristics of the second data to be written, it is determined that the second data to be written needs to be written into the third first-in-first-out buffer 200, it can be controlled by the selector 5 itself, or according to user configuration, a second write enable signal is sent through port 2 on the selector 5. Since the current working mode is the split mode, the first selection device 3 will send the second write enable signal to the third first-in-first-out buffer 200. After the third first-in-first-out buffer 200 receives the write enable signal, the write controller 2 can write the above-mentioned second data to be written into the third first-in-first-out buffer 200.

[0070] In some embodiments of the present invention, the control circuit 300 further includes a read controller. The control end of the read controller is connected to the output end of the mode control device. The reading end of the read controller is designed as the reading end of the control circuit 300, and the output end of the read controller is designed as the second output end of the control circuit 300. The read controller is used to read data from the second target buffer; wherein, when the mode control device controls the working mode of the read controller to be the combined mode, the read controller determines that the second target buffer is all the first-in-first-out buffers 200; when the mode control device controls the working mode of the read controller to be the split mode, the read controller determines a second target buffer from multiple first-in-first-out buffers 200.

[0071] That is to say, when the read controller reads data from the first-in-first-out buffer 200, it also needs to determine the second target buffer according to the working mode.

[0072] When the current working mode is the combined mode, the second target buffer is all the first-in-first-out buffers 200. At this time, the write controller polls and writes the data to be written into all the first-in-first-out buffers 200, and the read controller polls and reads out the data from all the first-in-first-out buffers 200 when it needs to read data.

[0073] When the current working mode is the split mode, the read controller needs to determine the first-in-first-out buffer 200 where the data to be read is located, and use this first-in-first-out buffer 200 as the second target buffer, and read data from this second target buffer.

[0074] In some embodiments of the present invention, the control circuit 300 further includes a read counter for generating a second counting result, and a read controller, including: a plurality of second enabling devices, the output ends of the plurality of second enabling devices are respectively and correspondingly connected to the reading ends of the plurality of first-in-first-out buffers 200, the control ends of the plurality of second enabling devices are all connected to the output end of the read counter, each second enabling device stores a second trigger data, and the second trigger data stored in any two second enabling devices are different. For any one of the second enabling devices, when the second counting result is consistent with the second trigger data stored in the second enabling device, the second enabling device outputs a first read enabling signal to the corresponding first-in-first-out buffer 200.

[0075] Specifically, it is set that the control circuit 300 further includes a read counter. In order to generate a second counting result, it can be set that when the read counter receives a signal indicating data reading each time, the second counting result is increased by a preset value, or it can be set that the second counting result is increased by a preset value at intervals of a preset time.

[0076] Thus, it is judged which second enabling device outputs the first read enabling signal according to the second counting result generated by the read counter, so as to realize quickly and accurately sending the read enabling signal to the first-in-first-out buffer 200.

[0077] In some embodiments of the present invention, the read controller further includes: a plurality of second selection devices, the output ends of the plurality of second selection devices are respectively and correspondingly connected to the writing ends of the plurality of first-in-first-out buffers 200, the first input ends of the plurality of second selection devices are respectively and correspondingly connected to the output ends of the plurality of second enabling devices, and the second input ends of the plurality of second selection devices are respectively and correspondingly connected to the plurality of output ends of the reader; the reader is used for determining a second target buffer and outputting a second read enabling signal to the first selection device corresponding to the second target buffer; wherein, when the working mode is the combination mode, the second selection device is used for sending the first read enabling signal to the first-in-first-out buffer 200, and when the working mode is the split mode, the second selection device is used for sending the second read enabling signal to the first-in-first-out buffer 200.

[0078] Thus, it is set that the read controller further includes a second selection device and a reader, and the reader is used for outputting a second read enabling signal. That is to say, the second enabling device outputs the first read enabling signal required in the combination mode, and the reader outputs the second read enabling signal required in the split mode. At this time, only the second selection device needs to select the enabling signal output to the first-in-first-out buffer 200 to realize different working modes, so as to realize a fast and efficient working mode switching.

[0079] In some embodiments of the present invention, the read controller further includes: a third selection device, multiple input ends of the third selection device are respectively and correspondingly connected to the reading ends of multiple first-in-first-out buffers 200, a control end of the third selection device is connected to the read counter, an output end of the third selection device is designed as the output end of the read controller, and the third selection device is configured to determine a second target buffer according to a second counting result and read data from the second target buffer.

[0080] Therefore, it is provided that the read controller further includes a third selection device, and a control end of the third selection device is connected to an output end of the read counter. At this time, according to the second counting result output by the read counter, a second enabling device outputs a first read enabling signal, and the third selection device determines the second target buffer, so as to realize outputting a read enabling signal to the first-in-first-out buffer 200 according to the second counting result generated by the read counter and reading data therefrom.

[0081] In some embodiments of the present invention, the read controller further includes: a fourth selection device, a first input end of the fourth selection device is connected to an output end of the third selection device, a second input end of the fourth selection device is connected to a read-out end of a preset first-in-first-out buffer 200, an output end of the fourth selection device is designed as the output end of the read controller, a control end of the fourth selection device is connected to an output end of a mode control device, and the fourth selection device is configured to, when the working mode is a combined mode, send the data read by the third selection device to an external data receiving device, and, when the working mode is a split mode, read data from the preset first-in-first-out buffer 200 and send the read data to the external data receiving device.

[0082] The above read controller will be described below with a specific example.

[0083] Specifically, refer to Figure 3 and Figure 4 . In this example, 10 is the read controller, 11 is the read counter, 12 is the second enabling device, 13 is the second selection device, 14 is the third selection device, 15 is the fourth selection device, 16 is the third AND gate, 17 is the fourth AND gate, 18 is the fifth AND gate. 1 is the mode control device.

[0084] Among them, Figure 3 is the part for sending the read enabling signal in this example, Figure 4 is the part for reading data in this example.

[0085] The number of the first-in-first-out buffers 200 is M, Figure 3Among the read FIFOs 0, 1, 2, …, M-1, read FIFO 0 means being connected to the first first-in-first-out buffer 200, read FIFO 1 means being connected to the second first-in-first-out buffer 200, read FIFO 2 means being connected to the third first-in-first-out buffer 200, and read FIFO M-1 means being connected to the Mth first-in-first-out buffer 200.

[0086] Similarly, Figure 4 Among the FIFO 0 data, FIFO 1 data, FIFO 2 data, …, FIFO M-1 data, FIFO 0 data means being connected to the first first-in-first-out buffer 200, FIFO 1 data means being connected to the second first-in-first-out buffer 200, FIFO 2 data means being connected to the third first-in-first-out buffer 200, and FIFO M-1 data means being connected to the Mth first-in-first-out buffer 200.

[0087] Figure 3 In [a certain context], read counter = 0 means that the second trigger data stored inside the second enabling device 12 is 0, read counter = 1 means that the second trigger data stored inside the second enabling device 12 is 1, read counter = 2 means that the second trigger data stored inside the second enabling device 12 is 2, and read counter = M means that the second trigger data stored inside the second enabling device 12 is M. In this example, the initial first counting result of the read counter 11 is -1.

[0088] Figure 3 In [a certain context], read signals 0, 1, 2, …, M-1 are all second read enabling signals output by the reader.

[0089] Among them, the first control signal output by the mode control device 1 indicating the working mode is the combined mode is a high-level signal, and read signal 0 is a signal indicating data reading and is also a high-level signal.

[0090] When the mode control device 1 controls the working mode to be the combined mode, the mode control device 1 outputs a combined mode enabling signal of a high-level signal, and this high-level signal is output to the fourth AND gate 17 and is also output to the first selection device 3. When the mode control device 1 controls the working mode to be the split mode, the mode control device 2 outputs a split mode enabling signal to the first selection device 3.

[0091] It can be seen that in the combined mode, when data reading is required, the control circuit 300 generates a read signal 0. The fourth AND gate 17 outputs a high level. The read counter 11 adds 1 to the second counting result from -1, obtaining 0. At this time, the second enabling device 12 with the second trigger data being 0 outputs a first read enabling signal with a high level. Since the read signal 0 is a high-level signal, the corresponding second AND gate 9 will output the first read enabling signal output by the second enabling device 12 with the second trigger data being 0 to the corresponding second selection device 13, and then output the first read enabling signal to the readout end of the first first-in-first-out buffer 200.

[0092] After the first read enabling signal is output to the first first-in-first-out buffer 200, the read controller 10 can read data from this first first-in-first-out buffer 200.

[0093] Furthermore, the control circuit 300 generates a read signal 0. The fourth AND gate 17 outputs a high level. The read counter 11 adds 1 to the second counting result from 0, obtaining 1. At this time, the second enabling device 12 with the second trigger data being 1 outputs a first read enabling signal with a high level. Since the read signal 0 is a high-level signal, the corresponding second AND gate 9 will output the first read enabling signal output by the second enabling device 12 with the second trigger data being 1 to the corresponding second selection device 13, and then output it to the readout end of the second first-in-first-out buffer 200.

[0094] After the first read enabling signal is output to the second first-in-first-out buffer 200, the read controller 10 can read out data from this second first-in-first-out buffer 200.

[0095] Keep performing the above operations until all the data that needs to be read out is read out. Through this setting, in the combined mode, when the read signal 0 acts, the read counter 11 will add 1. When the count reaches M, it automatically returns to 0. The read controller 10 compares the read counter 11 and reads data from the corresponding first-in-first-out buffer 200, and the corresponding read pointer adds 1. The data is output to the bus through the interface, enabling all the first-in-first-out buffers 200 to be read out through one interface in the first-in-first-out order. In the view of the user, it is a large-depth buffer.

[0096] In the split mode, taking the second and third first-in-first-out buffers 200 as an example, the read interface 1 will access the second first-in-first-out buffer 200 through the read signal 1, and the data is sent to the bus by the interface 1. The read interface 2 will access the third first-in-first-out buffer 200 through the read signal 2, and the data is sent to the bus through the interface 2.

[0097] For example, assume that the data to be read is stored in the first FIFO buffer 200, then a second read enable signal, read signal 0, can be issued. Since the current working mode is the split mode, the second selection device 13 will send this second read enable signal to the first FIFO buffer 200. After the first FIFO buffer 200 receives the read enable signal, the read controller 10 can read the data from the first FIFO buffer 200.

[0098] For another example, assume that the data to be read is stored in the third FIFO buffer 200, then a second read enable signal, read signal 2, can be issued. Since the current working mode is the split mode, the second selection device 13 will send this second read enable signal to the third FIFO buffer 200. After the third FIFO buffer 200 receives the read enable signal, the read controller 10 can read the data from the third FIFO buffer 200.

[0099] Continue to refer to Figure 4 to illustrate how to read data.

[0100] When the working mode is the combined mode, the mode control device 1 outputs a high-level combined mode enable signal, and this high-level signal is output to the fifth AND gate 18 and also output to the fourth selection device 15. When the mode control device 1 controls the working mode to be the split mode, the mode control device 2 outputs a split mode enable signal to the fourth selection device 15.

[0101] It can be seen that in the combined mode, when data needs to be read, the control circuit 300 generates a read signal 0, the fifth AND gate 18 outputs a high level, the read counter 11 adds 1 to the second count result from -1 to get 0. At this time, the third selection device 14 reads the data from the first FIFO buffer 200. Since the working mode is the combined mode, the fourth selection device 15 outputs the data read by the third selection device 14 through the read interface 0.

[0102] Furthermore, the control circuit 300 generates a read signal 0, the fifth AND gate 18 outputs a high level, the read counter 11 adds 1 to the second count result from -1 to get 1. At this time, the third selection device 14 reads the data from the second FIFO buffer 200. Since the working mode is the combined mode, the fourth selection device 15 outputs the data read by the third selection device 14 through the read interface 0.

[0103] By continuously performing the above operations, data output in the combined mode can be achieved.

[0104] In the split mode, when the data to be read is in the first first-in-first-out buffer 200, the read controller 10 reads the data from the first first-in-first-out buffer 200, and the read data passes through the fourth selection device 15 and is output from the read interface 0 to the external data receiving device.

[0105] When the data to be read is in the second first-in-first-out buffer 200, the read controller 10 reads the data from the second first-in-first-out buffer 200, and the read data is output from the read interface 1 to the external data receiving device.

[0106] When the data to be read is in the third first-in-first-out buffer 200, the read controller 10 reads the data from the third first-in-first-out buffer 200, and the read data is output from the read interface 2 to the external data receiving device.

[0107] When the data to be read is in the Mth first-in-first-out buffer 200, the read controller 10 reads the data from the Mth first-in-first-out buffer 200, and the read data is output from the read interface M - 1 to the external data receiving device.

[0108] The following is an explanation with reference to Figure 5 the example shown below.

[0109] In Figure 5 , FIFO0 is the first first-in-first-out buffer 200 mentioned above, FIFO1 is the second first-in-first-out buffer 200, FIFO2 is the third first-in-first-out buffer 200, and FIFO(M - 1) is the Mth first-in-first-out buffer 200. Figure 5 The "write" in Figure 5 means the write end of the first-in-first-out buffer 200,

[0110] Figure 5 In the data storage example in the combined mode in Figure 5 , it can be seen that the data to be written is written into each first-in-first-out buffer 200 in the order of data 0, data 1, data 2,..., data M - 1, data M, data M + 1, data M + 2,..., data 2M + 1,..., data (N - 1)×M, data (N - 1)×M + 1, data (N - 1)×M + 2,..., data N×M + 1.

[0111] Specifically, the write controller 2 reorganizes the data and stores the data 0 into FIFO0, the data 1 into FIFO1... After FIFO(M - 1) is stored, each first-in-first-out buffer 200 stores one data, and the new data is then stored into FIFO0. The data storage is organized in such a cyclic order. And the write pointer inside each first-in-first-out buffer 200 does not need to increase according to the number of stored data. At this time, the read controller 10 also reads the data 0 from FIFO0, the data 1 from FIFO1..., and the data M from FIFO0... The data will be output to the bus through the same output interface.

[0112] Of course, in the split mode, the write controller 2 will write the to-be-written data with different characteristics into different first-in-first-out buffers 200 according to the configurable data classification method. The relationships between the first-in-first-out buffers 200 are independent. At this time, the read controller 10 will read data from the corresponding first-in-first-out buffers 200 according to different read interfaces. The data will be output to the bus through multiple output interfaces.

[0113] In summary, the first-in-first-out control system according to the embodiment of the present invention sets multiple first-in-first-out buffers; a control circuit, the input end of the control circuit is connected to the output end of an external data generation device, the first output end of the control circuit is connected to the write ends of the multiple first-in-first-out buffers, the read end of the control circuit is connected to the read ends of the multiple first-in-first-out buffers, the second output end of the control circuit is connected to the input end of an external data receiving device, and the control circuit is used to determine at least one first target buffer from the multiple first-in-first-out buffers, and write the to-be-written data generated by the external data generation device into the first target buffer, and determine at least one second target buffer from the multiple first-in-first-out buffers, and read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffers is the same as that of the second target buffers. Through this first-in-first-out control system, it is possible to meet the requirements of depth or read speed by adjusting the number of the first target buffers and the second target buffers, thereby achieving high-performance first-in-first-out control.

[0114] Furthermore, the present invention proposes a chip.

[0115] Figure 6 It is the structural block diagram of the chip according to the embodiment of the present invention.

[0116] As Figure 6 shown, the chip 1000 includes the above-mentioned first-in-first-out control system 100.

[0117] A chip according to an embodiment of the present invention, through the above-mentioned first-in-first-out control system, sets a plurality of first-in-first-out buffers; a control circuit, the input end of the control circuit is connected to the output end of an external data generating device, the first output end of the control circuit is connected to the writing ends of the plurality of first-in-first-out buffers, the reading end of the control circuit is connected to the reading-out ends of the plurality of first-in-first-out buffers, and the second output end of the control circuit is connected to the input end of an external data receiving device. The control circuit is used to determine at least one first target buffer from the plurality of first-in-first-out buffers, and write the data to be written generated by the external data generating device into the first target buffer, and determine at least one second target buffer from the plurality of first-in-first-out buffers, and read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffers is the same as that of the second target buffers. Through this first-in-first-out control system, it is possible to meet the requirements of depth or reading speed by adjusting the number of the first target buffers and the second target buffers, so as to achieve high-performance first-in-first-out control.

[0118] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein can be considered as a definite sequence list of executable instructions for implementing logical functions, which can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus or device), or in combination with these instruction execution systems, apparatus or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0119] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0120] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0121] In the description of this specification, the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as a limitation on the present invention.

[0122] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0123] In the description of this specification, unless otherwise specified, the terms "installed", "connected", "joined", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral one; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal connection of two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0124] In the present invention, unless otherwise clearly specified and defined, a first feature being "on" or "under" a second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, a first feature being "above", "over" and "on top of" a second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. A first feature being "under", "below" and "beneath" a second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0125] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A first-in, first-out control system, characterized in that: The system comprises: Multiple first-in, first-out buffers; A control circuit, wherein an input end of the control circuit is connected to an output end of an external data generating device, a first output end of the control circuit is connected to a write end of a plurality of the first-in-first-out buffers, a read end of the control circuit is connected to a read end of the plurality of the first-in-first-out buffers, and a second output end of the control circuit is connected to an input end of an external data receiving device, the control circuit is used to determine at least one first target buffer from the plurality of the first-in-first-out buffers, and write the to-be-written data generated by the external data generating device into the first target buffer; determine at least one second target buffer from the plurality of the first-in-first-out buffers, and read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffers is the same as the number of the second target buffers; The control circuit includes a mode control device and a write controller, the output end of the mode control device is connected to the control end of the write controller, the input end of the write controller is designed as the input end of the control circuit, and the output end of the write controller is designed as the first output end of the control circuit; wherein, When the mode control device controls the operation mode of the write controller to be the combined mode, the write controller is used to determine that the first target buffer is all the first-in-first-out buffers, and write the data to be written into the first target buffer; When the mode control device controls the working mode of the write controller to be the split mode, the write controller is used to determine a first target buffer from the plurality of first-in first-out buffers according to the data type of the data to be written, and write the data to be written into the first target buffer; The write controller comprises: A plurality of first selection devices, wherein the output ends of the plurality of first selection devices are connected to the write ends of the plurality of first-in-first-out buffers in a one-to-one correspondence; A write control circuit, comprising a plurality of output terminals, wherein the plurality of output terminals of the write control circuit are connected one-to-one with the first input terminals of the plurality of first selection devices, and the write control circuit is used to determine the first target buffer and output a first write enable signal to the first selection device corresponding to the first target buffer; A selector, comprising a plurality of output terminals, wherein the plurality of output terminals of the selector are connected one-to-one with the second input terminals of the plurality of first selection devices, and the selector is used to determine the first target buffer and output a second write enable signal to the first selection device corresponding to the first target buffer; Wherein, when the working mode is the combined mode, the first selection device is used to send the first write enable signal to the first-in first-out buffer, and when the working mode is the split mode, the first selection device is used to send the second write enable signal to the first-in first-out buffer; The control circuit further includes a write counter, wherein the write counter is used to generate a first counting result according to the data to be written, and the write control circuit includes: a plurality of first enabling devices, wherein output ends of the plurality of first enabling devices are connected to first input ends of the plurality of first selecting devices in a one-to-one correspondence, control ends of the plurality of first enabling devices are all connected to the output end of the write counter, a first trigger data is stored in each of the first enabling devices, and the first trigger data stored in any two of the first enabling devices are different, and for any one of the first enabling devices, when the first counting result is consistent with the first trigger data stored in the first enabling device, the first enabling device outputs the first write enable signal; The control circuit further includes a read controller, a control end of the read controller is connected to an output end of the mode control device, a read end of the read controller is designed as a read end of the control circuit, an output end of the read controller is designed as a second output end of the control circuit, and the read controller is used to read data from the second target buffer; wherein, When the mode control device controls the working mode of the read controller to be the combined mode, the read controller determines that the second target buffer is all the first-in-first-out buffers; When the mode control device controls the working mode of the read controller to be a split mode, the read controller determines a second target buffer from the plurality of first-in first-out buffers; The control circuit further includes a read counter, the read counter is used to generate a second counting result, and the read controller includes: A plurality of second enabling devices, the output ends of the plurality of second enabling devices are connected to the read ends of the plurality of first-in-first-out buffers in a one-to-one correspondence, the control ends of the plurality of second enabling devices are all connected to the output end of the read counter, each of the second enabling devices stores a second trigger data, and the second trigger data stored in any two of the second enabling devices are different, and for any one of the second enabling devices, when the second counting result is consistent with the second trigger data stored in the second enabling device, the second enabling device outputs a first read enable signal to the corresponding first-in-first-out buffer; The read controller further includes: A plurality of second selection devices, wherein the output ends of the plurality of second selection devices are connected to the write ends of the plurality of first-in-first-out buffers in a one-to-one correspondence, the first input ends of the plurality of second selection devices are connected to the output ends of the plurality of second enabling devices in a one-to-one correspondence, and the second input ends of the plurality of second selection devices are connected to the plurality of output ends of the reader in a one-to-one correspondence; The reader is used to determine the second target buffer and output a second read enable signal to a first selection device corresponding to the second target buffer; Wherein, when the working mode is the combined mode, the second selection device is used to send the first read enable signal to the first-in first-out buffer, and when the working mode is the split mode, the second selection device is used to send the second read enable signal to the first-in first-out buffer; The read controller further includes: a third selection device, wherein a plurality of input terminals of the third selection device are connected one-to-one with read terminals of the plurality of first-in-first-out buffers, a control terminal of the third selection device is connected to the read counter, an output terminal of the third selection device is designed as an output terminal of the read controller, and the third selection device is used to determine a second target buffer according to the second counting result, and read data from the second target buffer, and send the read data to the external data receiving device; The read controller further includes: a fourth selection device, wherein a first input terminal of the fourth selection device is connected to an output terminal of the third selection device, a second input terminal of the fourth selection device is connected to a read terminal of a preset first-in-first-out buffer, an output terminal of the fourth selection device is designed to be an output terminal of the read controller, a control terminal of the fourth selection device is connected to an output terminal of the mode control device, and the fourth selection device is used to send the data read by the third selection device to the external data receiving device when the working mode is the combined mode, and to read data from the preset first-in-first-out buffer and send the read data to the external data receiving device when the working mode is the split mode; Wherein, when the working mode is the combined mode, the write controller polls and writes the data to be written into all the first-in-first-out buffers, and the read controller polls and reads the data from all the first-in-first-out buffers.

2. A chip, characterized in that: Comprising a first-in, first-out control system according to claim 1.

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