Computing chip and instruction processing method

Abstract

The embodiment of the invention provides a computing chip and an instruction processing method, and relates to the technical field of integrated circuits, the computing chip adopts a superscalar processor architecture, and comprises an instruction processing unit and a plurality of registers coupled with the instruction processing unit, the plurality of registers comprise a general register and a plurality of private registers respectively coupled with the general register; the general register is used for storing an execution result of a microinstruction which is executed before the jump instruction and is referenced by the microinstruction executed after the jump instruction in a plurality of microinstructions of the calculation task; each private register in the plurality of private registers is used for storing an execution result of any microinstruction in the plurality of microinstructions; the instruction processing unit is used for analyzing each microinstruction in the plurality of microinstructions; and obtaining data in the register according to the analysis result to execute the microinstruction and storing an execution result to the register. According to the embodiment of the invention, the processing efficiency of the processor on the microinstruction can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular, to a computing chip and an instruction processing method. Background Art

[0002] Generally, computing chips such as single-core central processing units (CPUs) can improve CPU performance by increasing the parallelism between instructions at the architectural level of instruction processing. For example, a processor using a superscalar processor architecture executes instructions out of order to improve the parallelism between instructions. Specifically, the processor predicts at least one instruction to be executed after the currently executed instruction to execute the predicted instruction in advance. In this way, there is no need to wait for all previous instructions to be executed before executing the subsequent instructions according to the instruction order in the computing task, thereby greatly improving the parallelism between instructions.

[0003] In the related art, different instructions in the same computing task may use the same register, so that out-of-order execution of instructions easily leads to read / write conflicts on the same register. The processor can resolve the read / write conflict by renaming the register. For example, register renaming may include selecting one of multiple instructions involving read / write conflicts of the register to still use the register, naming at least one register without read / write conflicts and corresponding to at least one instruction in one-to-one correspondence with at least one instruction for at least one instruction among the multiple instructions except the one instruction, and establishing a mapping relationship between a new register name and the corresponding instruction.

[0004] However, when register renaming is used, it is time-consuming to establish the mapping relationship between the new register name and the corresponding instruction. In addition, physical registers need to be added to the processor to cooperate with the renaming, which can easily reduce the processor performance. In other words, register renaming can easily reduce the processor's processing efficiency for instructions. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a computing chip and an instruction processing method. In the instruction processing method, based on the relative distance between microinstructions and the private register reference source operand to avoid register renaming, on this basis, combined with general registers to ensure accurate reference of data when the relative distance between instructions changes due to jump instructions, thereby improving the processor's processing efficiency of instructions.

[0006] In a first aspect, an embodiment of the present application provides a computing chip, which adopts a superscalar processor architecture, including: multiple registers and an instruction processing unit, the multiple registers are respectively coupled to the instruction processing unit, the multiple registers include: a general register and a plurality of private registers respectively coupled to the general registers; the general register is used to store an execution result of a first instruction referenced by a second instruction, wherein the first instruction includes a microinstruction executed before a jump instruction among multiple microinstructions for implementing a computing task; the second instruction includes a microinstruction executed after the jump instruction; each of the multiple private registers is used to store a microinstruction other than a save instruction among the multiple microinstructions The execution result of the instruction; an instruction processing unit is used to parse any microinstruction among multiple microinstructions, obtain a source operand of a first register among multiple registers to determine the execution result of any microinstruction according to the parsing result, and store the execution result of any microinstruction in a second register among multiple registers different from the first register, and perform parsing on any microinstruction among the multiple microinstructions until the computing task is completed; wherein the source operand includes the execution result of another microinstruction referenced by any microinstruction; in the case where the source operand includes the execution result in a private register, the parsing result includes a relative distance index for indicating the relative distance between any microinstruction and another microinstruction.

[0007] In the embodiment of the present application, by storing the execution results of microinstructions other than write instructions in private registers, in the case where no jump instruction is encountered, it can be ensured that the microinstruction directly references the source operand, that is, the execution result of another microinstruction, based on the relative distance between the microinstruction and another microinstruction, thereby avoiding the register renaming caused by the special naming register for referencing the source operand through the relative distance difference between different microinstructions. For the case of encountering a jump instruction, by saving the execution result of another microinstruction to a general register and obtaining the source operand in the general register, the microinstruction references the source operand before the jump instruction, avoiding the source operation data reference error caused by the change in the relative distance between instructions caused by the jump instruction when directly referencing the source operand based on the relative distance between microinstructions. In this way, the register renaming operation in the out-of-order execution of instructions and the degradation caused by the mapping between the search instruction and the register under the register renaming operation can be avoided, and the additional addition of physical registers can be avoided, thereby improving the processing efficiency of the processor for instructions.

[0008] According to the first aspect, the instruction processing unit is specifically used to: obtain one microinstruction from multiple microinstructions, and parse one microinstruction to obtain a parsing result; wherein the parsing result includes obtaining a position identifier, or a relative distance index and a second register identifier; obtaining a position identifier including a first register identifier or a relative distance index; obtaining a source operand from a first private register indicated by the relative distance index, or a first general register indicated by the first register identifier; based on the source operand obtained from the first private register, executing any microinstruction to obtain an execution result of any microinstruction, and storing the execution result of any microinstruction in a second private register allocated to any microinstruction in multiple private registers; in the case where the parsing result includes a second register identifier, storing the source operand obtained from the first private register in a second general register indicated by the second register identifier; storing the source operand obtained from the first general register in an idle private register among multiple private registers; executing and obtaining one microinstruction from multiple microinstructions until the computing task is completed.

[0009] In an embodiment of the present application, a relative distance index or a first register identifier for indicating the storage location of a source operand is obtained by parsing a microinstruction through an instruction processing unit. In one case, a second register identifier for indicating the storage location of an execution result can also be obtained, thereby enabling execution of the microinstruction without register renaming based on the parsing result, thereby ensuring improved instruction processing efficiency.

[0010] According to the first aspect, or any implementation method of the first aspect above, the instruction processing unit is also used to: after determining the execution result of any microinstruction, submit any microinstruction for the computing chip to perform a computing task based on the execution result of any microinstruction; before storing the execution result of any microinstruction in a register: if a preset number of microinstructions before any microinstruction are submitted, then the private register occupied by the microinstruction with the farthest relative distance from any microinstruction among the preset number of microinstructions is updated to an idle state; or, if any microinstruction is a jump instruction, then the private register occupied by each microinstruction among the preset number of microinstructions before the jump instruction is updated to an idle state; wherein the preset number includes an integer ≥1; the instruction processing unit is specifically used to: store the execution result of any microinstruction to an idle register according to the analysis result.

[0011] The embodiment of the present application can release the register based on the submission of microinstructions, that is, update the idle state, to achieve the effect of unlimited private registers, thereby further improving the instruction processing efficiency and reducing the hardware cost of the computing chip.

[0012] According to the first aspect, or any implementation of the first aspect above, the preset number is equal to the number of the plurality of private registers.

[0013] In the embodiment of the present application, the instruction window can be adaptively expanded according to the number of registers, which is beneficial to improving the utilization rate of registers and expanding the instruction-level parallel capability.

[0014] According to the first aspect, or any implementation of the first aspect above, the instruction processing unit is specifically used to: create at least one thread for executing a computing task, and allocate at least two private registers from a plurality of private registers to each thread in the at least one thread; wherein each thread is used to process at least one microinstruction from a plurality of microinstructions; and parse any microinstruction from the plurality of microinstructions through each thread respectively.

[0015] In the embodiment of the present application, the instruction processing unit can realize instruction processing of multiple threads by allocating private registers of the lock brother, thereby further improving the instruction processing efficiency.

[0016] According to the first aspect, or any implementation method of the first aspect above, the instruction processing unit is specifically used to: predict any microinstruction among multiple microinstructions according to the out-of-order processing rules of the superscalar processor architecture, and perform parsing on any microinstruction among the multiple microinstructions to obtain a parsing result; in the case of a prediction error, update the register occupied by any microinstruction with a prediction error to an idle state, and re-execute the prediction to obtain any microinstruction among the multiple microinstructions.

[0017] In the embodiment of the present application, if an instruction prediction error occurs, it is only necessary to refresh the private register, without looking up the mapping relationship to restore the register to the state before the predicted instruction is used. A simpler out-of-order execution pipeline is implemented with less complex hardware, and the recovery speed of predicted missed instruction processing is accelerated.

[0018] According to the first aspect, or any implementation of the first aspect above, the instruction processing unit includes an instruction cache module, an instruction fetch module coupled to the instruction cache module, a decoding module coupled to the instruction fetch module, and an execution module coupled to multiple private registers respectively; the decoding module is coupled to the multiple private registers respectively; the instruction cache module is used to store multiple microinstructions; the instruction fetch module is used to obtain a microinstruction in the instruction cache module, obtain any microinstruction among the multiple microinstructions, and pass any microinstruction among the multiple microinstructions to the decoding module until the computing task is completed; the decoding module is used to parse any microinstruction among the multiple microinstructions, and according to the parsing result, obtain the source operand of the first register among the multiple registers, and send the source operand and the parsing result to the execution module; the execution module is used to determine the execution result of any microinstruction based on the operand and the parsing result, and store the execution result of any microinstruction to a second register among the multiple registers that is different from the first register.

[0019] In the embodiment of the present application, instruction processing based on relative distance index, private register and general register is implemented through the instruction cache module, instruction fetch module, decoding module and execution module in the instruction processing unit, without the need for register renaming, thereby improving instruction processing efficiency.

[0020] In a second aspect, an embodiment of the present application provides an instruction processing method, which is applied to a computing chip using a superscalar processor architecture, wherein the computing chip includes multiple registers, and the multiple registers include: general registers and multiple private registers; the method includes: obtaining multiple microinstructions for implementing computing tasks; parsing any microinstruction among the multiple microinstructions to obtain a parsing result; according to the parsing result, obtaining a source operand in a first register among the multiple registers; wherein the source operand includes an execution result of another microinstruction referenced by any microinstruction; when the first register includes a private register, the parsing result includes a relative distance index for indicating the relative distance between any microinstruction and another microinstruction; based on the parsing result The method comprises the steps of: determining an execution result of any microinstruction and storing the execution result of any microinstruction in a second register different from the first register among the multiple registers, and parsing any microinstruction among the multiple microinstructions to obtain the parsing result until the computing task is completed; wherein: when any microinstruction includes a first instruction, the second register includes a general register, the first instruction includes a microinstruction among the multiple microinstructions that is executed before the jump instruction and the execution result is referenced by the second instruction, and the second instruction includes a microinstruction that is executed after the jump instruction; when any microinstruction includes a microinstruction other than a save instruction among the multiple microinstructions, the second register includes any private register among the multiple private registers.

[0021] According to a second aspect, any microinstruction among a plurality of microinstructions is parsed to obtain a parsing result, including: obtaining a microinstruction among the plurality of microinstructions, parsing the microinstruction, and obtaining a parsing result; wherein the parsing result includes obtaining a position identifier, or a relative distance index and a second register identifier; obtaining a position identifier including a first register identifier or a relative distance index; obtaining a source operand in a first register among a plurality of registers according to the parsing result, including: obtaining a source operand from a first private register indicated by the relative distance index, or a first general register indicated by the first register identifier; determining an execution result of any microinstruction based on the parsing result and the source operand, and storing the execution result of any microinstruction in a plurality of registers corresponding to the first register identifier; A second register different from the first private register is used, and any microinstruction among the multiple microinstructions is parsed to obtain a parsing result until the computing task is completed, including: based on the source operand obtained from the first private register, any microinstruction is executed to obtain an execution result of any microinstruction, and the execution result of any microinstruction is stored in a second private register allocated to any microinstruction among the multiple private registers; when the parsing result includes a second register identifier, the source operand obtained from the first private register is stored in a second general register indicated by the second register identifier; the source operand obtained from the first general register is stored in an idle private register among the multiple private registers; and one microinstruction among the multiple microinstructions is obtained by execution until the computing task is completed.

[0022] According to the second aspect, or any implementation of the second aspect above, after determining the execution result of any microinstruction, the method also includes: submitting any microinstruction for the method to perform a computing task based on the execution result of any microinstruction; before storing the execution result of any microinstruction in a register, the method also includes: if a preset number of microinstructions before any microinstruction are submitted, then the private register occupied by the microinstruction with the farthest relative distance from any microinstruction among the preset number of microinstructions is updated to an idle state; or, if any microinstruction is a jump instruction, then the private register occupied by each microinstruction in the preset number of microinstructions before the jump instruction is updated to an idle state; wherein the preset number includes an integer ≥1; storing the execution result of any microinstruction to a second register different from the first register among multiple registers includes: storing the execution result of any microinstruction to an idle register according to the analysis result.

[0023] According to the second aspect, or any implementation of the second aspect, the preset number is equal to the number of the plurality of private registers.

[0024] According to the second aspect, or any implementation method of the second aspect above, any microinstruction among multiple microinstructions is parsed to obtain a parsing result, including: creating at least one thread for executing a computing task, and allocating at least two private registers among multiple private registers to each thread in at least one thread; wherein each thread is used to process at least one microinstruction among multiple microinstructions; and parsing any microinstruction among at least one microinstruction through each thread.

[0025] According to the second aspect, or any implementation method of the second aspect above, any microinstruction among multiple microinstructions is parsed to obtain a parsing result, including: according to the out-of-order processing rules of the superscalar processor architecture, any microinstruction among multiple microinstructions is predicted, and any microinstruction among multiple microinstructions is parsed to obtain a parsing result; in the case of a prediction error, the register occupied by any microinstruction with a prediction error is updated to an idle state, and the prediction is re-executed to obtain any microinstruction among the multiple microinstructions.

[0026] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0027] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor and a transceiver; a memory for storing one or more programs; when the one or more programs are executed by one or more processors, the one or more processors implement a method such as the second aspect and any one of the implementation methods of the second aspect.

[0028] In a fourth aspect, an embodiment of the present application provides a computer-readable medium for storing a computer program, wherein the computer program includes instructions for executing the method in the second aspect or any possible implementation of the second aspect.

[0029] In a fifth aspect, an embodiment of the present application provides a computer program comprising instructions for executing the method in the second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0031] Figure 1 is a schematic diagram showing an exemplary register read / write conflict;

[0032] Figure 2 It is one of the structural block diagrams of a computing chip 200 provided in an embodiment of the present application;

[0033] Figure 3 It is a flowchart of an instruction processing method provided in an embodiment of the present application;

[0034] Figure 4 is an example diagram of the relationship between the instruction dependency distance and the number of dependencies provided in an embodiment of the present application;

[0035] Figure 5 It is one of the schematic diagrams of the instruction processing process in an instruction processing method provided in an embodiment of the present application;

[0036] Figure 6 It is one of the schematic diagrams of the instruction processing process in an instruction processing method provided in an embodiment of the present application;

[0037] Figure 7 It is one of the schematic diagrams of the instruction processing process in an instruction processing method provided in an embodiment of the present application;

[0038] Figure 8 It is one of the structural block diagrams of a computing chip 800 provided in an embodiment of the present application;

[0039] Fig. 9 This is one of the schematic diagrams of the instruction processing process in an instruction processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0042] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0043] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0044] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0045] In order to facilitate understanding of this embodiment, some technical terms and background technologies involved in this embodiment are first introduced:

[0046] Superscalar CPU (central processing unit): A processor that uses a superscalar processor architecture, that is, a CPU that runs multiple instructions at the same time to improve operating efficiency and utilization of computing resources in the CPU, that is, a superscalar processor. For example, the CPU decomposes the computing task into multiple instructions to be executed on different threads, and each thread independently uses different computing resources in the CPU, thereby improving the utilization of computing resources in the CPU. For each thread, the next thread to be executed can be predicted before the thread completes execution. In other words, the instructions in the superscalar CPU are no longer executed in the order of instructions in the computing task, but are executed out of order: the subsequent execution instructions can be predicted and scheduled and put into execution before the current instruction is executed. In this way, if the prediction is correct, the subsequent execution instructions do not need to wait for a long time to be executed, and the execution results can be used directly, thereby improving the operating efficiency of the instructions. If the prediction is wrong, the execution result of the predicted subsequent execution instruction can only be abandoned, and the correct subsequent execution instruction can be re-predicted from the instruction with the wrong prediction.

[0047] Microinstructions: In a CPU cycle of a computer, a group of microinstructions that implement certain operating functions constitute a microinstruction. Among them, microinstructions are various control commands issued by the control component to the execution component through the control line, and are the smallest unit of instructions.

[0048] Register: Some small storage areas inside the CPU used to store data. They are used to temporarily store the data involved in the operation and the results of the operation. In fact, registers are a commonly used sequential logic circuit, but this sequential logic circuit only contains storage circuits.

[0049] Register file: Also known as register file, it is an array of multiple registers in the CPU, used to temporarily store data between the memory and the CPU computing unit. The register file is usually implemented by a fast static random read / write memory (SRAM), with dedicated read and write ports, which can access different registers in multiple ways concurrently.

[0050] General purpose register (GPR): A register contained in the fixed register set of the processor architecture, also known as an architectural register. The fixed register set may include general purpose registers, special purpose registers, and a program counter.

[0051] Program counter (PC): used to store the address of the instruction, also known as the program counter. The PC value is the address of the instruction.

[0052] Commit: In the instruction processing of superscalar processors, a final stage is usually added, called the commit stage, to ensure that the processor correctly executes the program in the serial order of the program. When an instruction reaches the commit stage, it may include: marking the instruction as completed, and when the execution of the instruction before the instruction in the serial order of the program is completed, using the execution result of the instruction to update the internal state of the processor (for example, write back: using the execution result of the instruction to update the content corresponding to the instruction in the processor main memory), at this time, the instruction is called retired, that is, the instruction can be removed from the instruction processing pipeline. Among them, the internal state of the processor may include speculative state and architectural state. The speculative state refers to the state of the components in the superscalar processor corresponding to the execution result of the predicted instruction during operation, such as the values ​​of the reorder cache, the emission queue and the store buffer. The architectural state refers to the values ​​of the general registers, PC and memory components defined in the instruction set of the superscalar processor. Due to out-of-order execution, the speculative state is ahead of the state defined by the instruction set, that is, the architectural state.

[0053] Thread: It is the smallest unit that the operating system can schedule operations. It is contained in the process and is the actual operation unit in the process. A thread refers to a single sequential control flow in the process. A process can have multiple threads running concurrently, and each thread executes different tasks in parallel.

[0054] Program counter (PC): Also called instruction counter, it is used to store the address of the instruction. The value in the program counter PC is used to indicate the location of the current instruction in the main memory. When an instruction is fetched, the value in PC will automatically increase according to the length of the instruction word. For example, the address of a single-word instruction is (PC)+1àPC; the address of a double-word instruction is (PC)+2àPC, and so on.

[0055] Instruction Fetch (IF): Instruction fetch, generally refers to the process of the CPU reading an instruction from the main memory (CPU's memory) and storing it in the instruction register. The value in the Program Counter (PC) is used to indicate the storage address in the main memory of the instruction to be executed in the current instruction execution cycle. At the end of the instruction fetch operation, the PC points to the instruction to be read in the next cycle.

[0056] The out-of-order execution of superscalar processors can fully exploit the potential parallel benefits of instructions in a thread and improve the expected performance. However, the use of the same register by different instructions in out-of-order execution introduces problems about write after write (WAW) and write after read (WAR). For example, Figure 1 FIG. 1 is a schematic diagram showing an exemplary register read / write conflict. Figure 1 As shown:

[0057] The write-before-write problem refers to the problem that different instructions write to the same register, and the different operation orders lead to different data in the register, causing the execution results of different instructions to be wrong. For example, instruction 1 "R1 = R2 + R3" and instruction 2 "R1 = R4 * R5" both write to register R1, resulting in R1 may be the execution result of R2 + R3, or the execution result of R4 * R5, causing the execution result of instruction 1 or instruction 2 to be wrong.

[0058] The problem of read-before-write refers to the problem that when the execution result of an instruction and the source operand of another instruction use the same register, the different read and write orders lead to different data in the register, causing the execution result of the other instruction to be wrong. Among them, the source operand refers to the operand in the instruction whose content does not change with the execution of the instruction. For example, instruction 3 "R1=R2*R3" performs a read operation on register R2, and instruction 4 "R2=R4+R5" performs a write operation on register R2, resulting in register R2 may contain the execution result of R4+R5. In this way, instruction 3 may reference the execution result of R4+R5, or it may be data different from the execution result, causing the execution result of instruction 3 to be wrong.

[0059] In one example, the WAW and WAR problems can be eliminated by register renaming. Figure 1 , register R1 used by instruction 2 can be updated to register R6 through register renaming, thereby avoiding data anomalies caused by instruction 1 and instruction 2 writing to the same register. Register R2 used by instruction 4 can be updated to register R6 through register renaming, thereby avoiding data anomalies caused by instruction 4 and instruction 3 operating on the same register. However, register renaming requires establishing a mapping relationship between new register names and corresponding instructions, which is time-consuming; and it requires adding physical registers to the processor to achieve this, which increases hardware complexity. This can easily reduce the processor's processing efficiency for instructions.

[0060] Therefore, the embodiment of the present application provides a computing chip and an instruction processing method to solve the above problems. Exemplarily, in the instruction processing method provided by the embodiment of the present application, by storing the execution results of microinstructions other than write instructions in private registers, for the case where no jump instruction is encountered, it can be ensured that the microinstruction directly references the source operand, that is, the execution result of another microinstruction, based on the relative distance between the microinstruction and another microinstruction, thereby avoiding the register renaming caused by the special naming register for referencing the source operand through the relative distance difference between different microinstructions. For the case of encountering a jump instruction, by saving the execution result of another microinstruction to a general register and obtaining the source operand in the general register, the microinstruction references the source operand before the jump instruction, avoiding the source operation data reference error caused by the change in the relative distance between instructions caused by the jump instruction when directly referencing the source operand based on the relative distance between microinstructions. In this way, the register renaming operation in the out-of-order execution of instructions and the degradation caused by the mapping between the search instruction and the register under the register renaming operation can be avoided, and the additional addition of physical registers can also be avoided, thereby improving the processing efficiency of the processor for instructions.

[0061] That is to say, the embodiment of the present application is equivalent to indicating the source operand by the relative distance index between microinstructions. The microinstructions can refer to the execution results of the previous microinstructions. Accordingly, a new instruction set and compiler are designed so that there is no register renaming in the instruction processing pipeline. In this way, there is no need to record mapping, and the scalability of the reorder buffer (ROB) is also improved. Among them, the reorder buffer is a cache used to record the order of instructions in the program during the out-of-order execution of instructions to ensure the order of instruction submission.

[0062] The embodiments of the present application can be applied to computing chips and electronic devices running computing chips. The computing chip can be, for example, a superscalar CPU, and the electronic device can be, for example, a mobile terminal, a computer, a tablet computer, a wearable device, a server, an Internet TV, and other devices running the computing chip. The embodiments of the present application are not limited to this.

[0063] For example, Figure 2 This is one of the structural block diagrams of a computing chip 200 provided in an embodiment of the present application. Figure 2 As shown, the computing chip 200 adopts a superscalar processor architecture and may include multiple registers and an instruction processing unit. Among them, the multiple registers are respectively coupled to the instruction processing unit, and the multiple registers may specifically include: a general register 201 and multiple private registers respectively coupled to the general registers. The multiple private registers may be, for example, a private register stack 202. The processing unit may include an instruction cache 2031, an instruction fetch module 2032 coupled to the instruction cache module 2031, a decoding module 2033 coupled to the instruction fetch module 2032, and an execution module 2034 coupled to the private register stack 202. The decoding module 2033 is respectively coupled to the private register pair 202 and the general register 201. The above coupling may be, for example, through circuit connection, electrical connection through silicon vias (TSV), or through software interaction.

[0064] The general register 201 is used to store the execution result of the first instruction referenced by the second instruction, wherein the first instruction includes a microinstruction executed before the jump instruction among multiple microinstructions for implementing the computing task; and the second instruction includes a microinstruction executed after the jump instruction.

[0065] Each private register in the private register file 202 is used to store the execution result of a microinstruction other than a write instruction among the multiple microinstructions.

[0066] An instruction processing unit, configured to parse any microinstruction from among the plurality of microinstructions, obtain a source operand of a first register from among the plurality of registers (such as the private register file 202 and the general register 201) according to the parsing result to determine an execution result of any microinstruction, store the execution result of any microinstruction in a second register from among the plurality of registers (such as the private register file 202) that is different from the first register, and parse any microinstruction from among the plurality of microinstructions until the computing task is completed;

[0067] The source operand includes the execution result of another microinstruction referenced by any microinstruction; when the source operand includes the execution result in a private register, the parsing result includes a relative distance index for indicating the relative distance between any microinstruction and another microinstruction.

[0068] Exemplarily, the instruction processing unit implements the above instruction processing process through the modules included:

[0069] An instruction cache module 2031, used for storing a plurality of microinstructions;

[0070] The instruction fetch module 2032 is used to fetch a microinstruction in the instruction cache module 2031, obtain any microinstruction from a plurality of microinstructions, and transmit any microinstruction from the plurality of microinstructions to the decoding module 2033 until the computing task is completed;

[0071] The decoding module 2033 is used to parse any microinstruction among the multiple microinstructions, and obtain the source operand stored in the first register (such as the private register file 202 and the general register 201) according to the parsing result, and send the source operand and the parsing result to the execution module 2034;

[0072] The execution module 2034 is used to determine the execution result of any microinstruction based on the operands and the parsing result and store the execution result of any microinstruction in a second register different from the first register in multiple registers (such as the private register file 202 and the general register 201).

[0073] It is understandable that both the first register and the second register may include private registers or general registers, and the difference is that the first register and the second register are different registers. For example, the first register is a private register T1, and the second register is a private register T2 or R1, the first register is a general register R1, and the second register is a private register T1 or a general register R2.

[0074] In one example, see Figure 2, the computing chip 200 may also include a storage unit 205. The storage unit 205 may specifically include a load / store unit (LSU) and a cache unit. The load / store unit is used to store data in a storage space such as a private register in a private register stack 202 in response to an instruction accessing / writing back (read / write, rd / wt) data (e.g., accessing a source operand in the form of an immediate number / writing back the execution result of an instruction). The cache unit may include an L1 cache (L1 Cache): an instruction cache for storing instructions and a data cache for storing data. An immediate number generally refers to an operand given in an immediate addressing mode instruction. The operand provided by the immediate addressing mode follows the opcode immediately and is placed in the instruction code segment together with the opcode.

[0075] For ease of understanding, the following Figures 2 to 7 ,right Figure 2 The processor shown and the process of the processor performing instruction processing are specifically described.

[0076] Figure 3 is a flow chart of an instruction processing method provided in an embodiment of the present application. Figure 3 As shown, the instruction processing method can be applied to Figure 2 The computing chip shown may include Figure 2 The electronic device of the computing chip shown may specifically include the following steps:

[0077] S301, obtaining a plurality of microinstructions for implementing a computing task.

[0078] like Figure 2 As shown, in the process of computing chip 200 performing computing tasks, multiple microinstructions for implementing computing tasks can be stored in instruction cache module 2031 (i.e., ICACHE) in response to the execution instruction of the computing task to improve instruction processing efficiency. On this basis, instruction fetch module 2032 can be, for example, an instruction fetch unit (IFU) that obtains a microinstruction (such as Inst) in instruction cache module 2031 according to the address of the instruction in the program counter, obtains any microinstruction (such as Inst) among multiple microinstructions, i.e., the currently processed microinstruction, and passes any microinstruction (such as Inst) among multiple microinstructions to decoding module 2033 until the computing task is completed. For ease of description, the current instruction is used to represent any of the above microinstructions in the following.

[0079] Exemplarily, the computing task may be, for example, an image processing task, a file storage task, a video encoding task, etc. The embodiment of the present application is not limited to this and may be specifically set according to application requirements.

[0080] S302, parse any microinstruction among the multiple microinstructions to obtain a parsing result.

[0081] When the decoding module 2033 receives any of the above-mentioned microinstructions sent by the instruction fetch module 2032, it can parse any of the microinstructions, and based on the parsing result, obtain the source operand stored in the first register of multiple registers (such as the private register file 202 and the general register 201), and send the source operand and the parsing result to the execution module 2034.

[0082] Exemplarily, the above parsing results may include an opcode (such as "ADD" representing an addition operation) and decoded data (operands, operand acquisition locations, etc.), instruction types, etc., which are used to obtain operands and execute operations indicated by microinstructions. Among them, instruction types can be divided according to the acquisition locations of operands, or according to the functions of instructions, which are not limited in the embodiments of the present application.

[0083] In one example, the data decoded in the parsing result may specifically include three types:

[0084] The first type is the relative distance index. The relative distance index includes the relative distance between the current microinstruction and another microinstruction referenced by the current microinstruction. The relative distance can be, for example, the difference between the PC values ​​of the instructions. For example, the relative distance indexes in the parsing result of the microinstruction "ADD t#4, t#1" are t#4 and t#1, which represent the fourth instruction and the first instruction before the current instruction, that is, the PC values ​​whose differences with the PC value of the current instruction are 4 and 1 respectively; the relative distance index in the parsing result of the microinstruction "LW[t#1,0]" is t#1. The relative distance index can be used to indicate the register where another microinstruction referenced by the current microinstruction stores the execution result, that is, the storage location of the source operand.

[0085] The second type is the first register identifier. The first register identifier is used to indicate a general register storing a source operand. For example, the first register identifier in the parsed result of the microinstruction "GET R3" is "R3".

[0086] The third type is a relative distance index and a second register identifier. The second register identifier is used to indicate a general register storing the execution result. For example, in the parsing result of the microinstruction "SET R2, t#1", the second register identifier is "R2".

[0087] The embodiment of the present application can avoid naming registers specifically for the execution results of microinstructions, i.e., outputs, through the relative distances between the above instructions and the private registers assigned to the instructions. Not only can the problem of register renaming be avoided by the difference in relative distances between different instructions, but the number of bits of the code can also be reduced, further improving instruction processing efficiency and processor performance. Exemplarily, the instruction encoding format is shown in Table 1-1 below:

[0088]

[0089] It can be seen that the naming of the register storing the output of the instruction is omitted in the encoding format of the embodiment of the present application. For example, the microinstruction in the embodiment of the present application is "ADD t#1t#2", and the microinstruction in the traditional encoding format is "ADD R2 R0 R1", that is, the embodiment of the present application can describe the microinstruction by combining the PC value of the microinstruction with two relative distance indexes t#1 and t#2. The traditional microinstruction is "ADD R2 R0 R1", and the microinstruction must be described by naming three registers "R2, R0 and R1" representing two inputs and one output respectively. In addition, the embodiment of the present application can ensure that the number of encoding bits occupied by the instruction in the instruction encoding format provided by the embodiment of the present application can be reduced to 16bit compared with the number of encoding bits occupied by the instruction in the traditional instruction encoding format, and there is no 16bit and 32bit mixing, so as to ensure that the instruction length is consistent, the hardware decoding complexity can be greatly reduced, and the efficiency of out-of-order execution is improved. Exemplary, the number of encoding bits corresponding to the above-mentioned instruction encoding format is shown in Table 1-2 below:

[0090]

[0091] In one example, Figure 4 : is an example diagram of the relationship between the instruction dependency distance and the number of dependencies provided in the embodiment of the present application. Figure 4 As shown, after topologically sorting the dependency distance and the number of dependencies between instructions in the computing task by SPEC2017 (a CPU subsystem testing tool), the test result can be obtained: instruction dependency distance ≤ 8. In other words, any microinstruction in the computing task usually references the execution result of the eighth instruction before the microinstruction. Based on this, when any microinstruction references the previous 8 microinstructions, the instruction encoding space advantage is the greatest, which can avoid unnecessary longer distance indexing and is more efficient and accurate. Therefore, in one example, the range of the relative distance index can be set to 8. For example, the 10th microinstruction can reference the execution results of microinstructions 1 to microinstruction 8, but cannot reference the execution result of microinstruction 0.

[0092] Exemplarily, the relative distance index may include:

[0093] t#1: The difference between the PC value of the current instruction and the instruction is 1, that is, the relative distance between the first instruction before the current instruction and the current instruction;

[0094] t#2: The difference between the PC value of the current instruction and the current instruction is 2, that is, the relative distance between the two instructions before the current instruction and the current instruction;

[0095] t#3: The difference between the PC value of the current instruction and the instruction is 3, that is, the relative distance between the third instruction before the current instruction and the current instruction;

[0096] t#4: The difference between the PC value of the current instruction and the current instruction is 4, that is, the relative distance between the fourth instruction before the current instruction and the current instruction;

[0097] t#5: The difference between the PC value of the current instruction and the instruction is 5, that is, the relative distance between the fifth instruction before the current instruction and the current instruction;

[0098] t#6: The difference between the PC value of the current instruction and the instruction is 6, that is, the relative distance between the sixth instruction before the current instruction and the current instruction;

[0099] t#7: The difference between the PC value of the current instruction and the instruction is 7, that is, the relative distance between the seventh instruction before the current instruction and the current instruction;

[0100] t#8: The difference between the PC value of the current instruction and the current instruction is 8, that is, the relative distance between the eighth instruction before the current instruction and the current instruction.

[0101] S303, according to the parsing result, obtain the source operand in the first register of the multiple registers; wherein the source operand includes the execution result of another microinstruction referenced by any microinstruction; when the first register includes a private register, the parsing result includes a relative distance index for indicating the relative distance between any microinstruction and another microinstruction.

[0102] After obtaining the parsing result, the decoding module 2033 may obtain the source operand in the first register of the plurality of registers according to the parsing result. The first register may include a private register in the private register file 202 or a general register 201 .

[0103] For example, when the parsing result includes a relative distance index, the first register may include a private register. For example, the relative distance indexes in the parsing result of the microinstruction "ADD t#4, t#1" are t#4 and t#1, representing PC values ​​whose differences from the PC value of the current instruction are 4 and 1, respectively. Accordingly, the first register may include two private registers storing execution results of microinstructions whose PC values ​​differ from the PC value of the current instruction by 4 and 1, respectively, for example, private register TR4 and private register TR1. The relative distance index in the parsing result of the microinstruction "LW[t#1,0]" is t#1. When the parsing result includes a first register identifier, the first register may include a general register indicated by the first register identifier, such as general register R3.

[0104] It can be understood that there may be multiple general registers 201 , and the general register R3 is one of the multiple general registers 201 .

[0105] After obtaining the source operand, the decoding module 2033 can send the source operand and the parsing result to the execution module 2034 respectively. Figure 2 The operation code / operand (opc / data) is shown to be sent separately. In one example, the operation code and the operand can be sent together. The embodiment of the present application is not limited to this and can be set according to application requirements.

[0106] S304, based on the parsing result and the source operand, determine the execution result of any microinstruction and store the execution result of any microinstruction in a second register different from the first register among the multiple registers, and perform parsing on any microinstruction among the multiple microinstructions to obtain the parsing result until the computing task is completed; wherein, in the case where any microinstruction includes a first instruction, the second register includes a general register, the first instruction includes a microinstruction among the multiple microinstructions that is executed before the jump instruction and the execution result is referenced by the second instruction, and the second instruction includes a microinstruction executed after the jump instruction; in the case where any microinstruction includes a microinstruction other than a write instruction among the multiple microinstructions, the second register includes any private register among the multiple private registers.

[0107] After receiving the parsing result and source operand sent by the decoding module 2033, the execution module 2034 can determine the execution result of any microinstruction based on the parsing result and the source operand, and store the execution result of any microinstruction in a second register different from the first register (such as the private register file 202 and the general register 201).

[0108] In an optional implementation, the execution module 2034 may perform the following operations:

[0109] Obtain a source operand from a first private register indicated by a relative distance index or a first general register indicated by a first register identifier;

[0110] Execute a microinstruction based on the source operand obtained from the first private register, obtain an execution result of any microinstruction, and store the execution result of any microinstruction in a second private register allocated to any microinstruction among the plurality of private registers;

[0111] When the parsing result includes the second register identifier, the source operand is obtained from the first private register and stored in the second general register indicated by the second register identifier;

[0112] storing the source operand obtained from the first general register into an unused private register among the plurality of private registers;

[0113] Execution fetches one of the multiple microinstructions until the computation task is completed.

[0114] For example, Figure 5 FIG. 1 is a schematic diagram of an instruction processing process in an instruction processing method provided in an embodiment of the present application. Figure 5 As shown, the instruction fetch module 2032 fetches one microinstruction each time, namely the currently executed microinstruction pointed to by the PC: microinstruction 10. Take the range of the relative distance index ≤ 8 as an example: the index distance of microinstruction 10, namely the relative distance index, is "1" and "6", then microinstruction 10 references the temporary result 7 of the first instruction microinstruction 9 before microinstruction 10, and the temporary result 2 of the sixth instruction microinstruction 4 before microinstruction 10, that is, the source operands of microinstruction 10 are the temporary result 7 and the temporary result 2.

[0115] When the execution module 2034 obtains the execution result of the microinstruction 10, the execution result can be stored in the second private register, that is, the private register allocated to the microinstruction 10. In other words, each microinstruction can be allocated a private register for storing the execution result of the microinstruction. Figure 6 is one of the schematic diagrams of the instruction processing process in an instruction processing method provided in an embodiment of the present application. In one example, the execution module 2034 can allocate a private register according to the PC value of the current instruction. For example, Figure 6As shown, the PC values ​​of microinstructions 2 to 9 increase in sequence, and the execution module 2034 allocates different private registers to each microinstruction according to the PC value of each microinstruction, for example, physical registers 0 to 7. It is understandable that the computing chip can manage these eight physical registers by marking TR1, TR2, TR3, TR4, TR5, TR6, TR7 and TR8. For example, the execution module 2034 allocates private register TR1, i.e., physical register 0, to microinstruction 2. Accordingly, Figure 5 As shown, the temporary result 2 can be stored in the private register TR3, and the temporary result 7 can be stored in the private register TR8.

[0116] For example, Figure 7 FIG. 1 is a schematic diagram of an instruction processing process in an instruction processing method provided in an embodiment of the present application. Figure 7 As shown, the above relative distance index is an index based on continuous PC values, for example, Figure 7 The microinstructions processed continuously in the computation task correspond to continuous PC values: PC=0B, PC=2B, PC=4B, PC=6B. However, the jump instruction causes the execution module 2034 to switch the instruction processing flow to a new instruction position in the computation task. Accordingly, the PC value of the instruction starts to accumulate from the PC value of the instruction at the new position after the jump, resulting in the PC values ​​before and after the jump instruction being no longer continuous. In this way, the content accessed by the execution module 2034 according to the relative distance index is determined based on the PC value of the instruction at the new position after the jump, and the obtained content may not exist or be inaccurate because the PC value is no longer continuous.

[0117] In this regard, the execution module 2034 of the embodiment of the present application no longer directly accesses the source operand in the private register according to the relative distance index when encountering a jump instruction, but stores the referenced execution result of the jump instruction from the private register to the general register, and then imports the source operand from the general register to the private register when referencing the source operand, thereby avoiding the problem of abnormal reference of the source operand under the relative distance index caused by the discontinuity of the PC value caused by the jump instruction. In addition, the execution module 2034 imports the source operand from the general register to the private register to ensure that at least one microinstruction can normally perform reference based on the relative distance index, thereby achieving accurate and efficient instruction processing.

[0118] For details, see Figure 7 , general register 201 (such as Figure 7A general purpose register GPR in the first instruction is used to store the execution result of the first instruction referenced by the second instruction, wherein the first instruction includes a microinstruction executed before the jump instruction among multiple microinstructions for implementing the computing task, that is, the microinstruction involving the jump instruction. For example, the first instruction may be Figure 7 In the microinstruction before the jump instruction "BR" (conditional jump instruction) shown, the execution result is referenced by the microinstruction executed after the jump instruction "BR", that is, the second instruction.

[0119] For example, the jump instructions may be the five jump instructions shown in Table 2 below:

[0120]

[0121] Still see Figure 7 , when the parsing result includes the second register identifier, the execution module 2034 stores the source operand obtained from the first private register to the second general register indicated by the second register identifier; when the parsing result includes the first register identifier, the source operand obtained from the first general register is stored to an idle private register among the multiple private registers. For example, the computing tasks are shown in Table 3 below:

[0122]

[0123]

[0124] In combination with the above Table 3, it can be seen that the embodiment of the present application can directly reference the source operand based on the relative distance index between instructions. In this way, there is no need to specifically name the register for the output, which not only reduces the coding difficulty and the number of bits occupied by the instruction encoding, but also avoids the decrease in processing efficiency caused by register renaming. In addition, in the case of encountering a jump instruction, the execution module 2034 of the embodiment of the present application can, for example, save the data in the private register (such as the private register TR2 in Table 3) to the general register GPR (such as the general register R2 in Table 3) through the save instruction SET. To the new PC value, that is, in the case of executing a jump instruction, such as Figure 7 After the BR instruction, the execution module 2034, for example, imports the value of the general register GPR into an idle private register (such as the private register TR3 in Table 3) through a GET instruction, so that the instruction after the jump instruction can use the content before the jump instruction again. For example, the microinstruction "ADD t#4, t#1" in Table 3 references the data in the private register TR3 through the relative distance index t#1, and the data flow involved can be, for example, Figure 2 The data set_data, the identifier gpr_id of the general register and the instruction get / set. In this way, the relative distance change caused by the jump instruction can be dealt with, thereby ensuring the accurate instruction processing.

[0125] In an optional implementation, the instruction processing unit may also submit any microinstruction after determining the execution result of any microinstruction for the computing chip to perform a computing task based on the execution result of any microinstruction;

[0126] Before storing the result of any microinstruction in a register:

[0127] If a preset number of microinstructions before any microinstruction are all submitted, the private registers occupied by the microinstruction with the farthest relative distance from any microinstruction among the preset number of microinstructions are updated to an idle state; or, if any microinstruction is a jump instruction, the private registers occupied by each microinstruction among the preset number of microinstructions before the jump instruction are updated to an idle state; wherein the preset number includes an integer ≥1;

[0128] The instruction processing unit is specifically used to store the execution result of any microinstruction into an idle register according to the analysis result.

[0129] Exemplarily, in a computing chip with a superscalar architecture, the execution module 2034 in the instruction processing unit can submit the microinstruction for the computing chip to perform a computing task based on the execution result of any microinstruction after executing the current microinstruction and obtaining the execution result. For example, this instruction is marked as completed, and when the execution of the instruction before the instruction in the serial order of the program is completed, the execution result of the instruction is used to update the state inside the processor (for example, write back: use the execution result of the instruction to update the content corresponding to the instruction in the processor main memory). At this time, this instruction is called retired, that is, the instruction can be removed from the instruction processing pipeline.

[0130] On this basis, the number of registers, i.e., physical registers, of a computing chip is usually limited. Figure 6 As shown, the computing chip has 8 physical registers, and the preset number can be 8. The current instruction processed by the execution module 2034 is microinstruction 10. When the 8 microinstructions before microinstruction 10, i.e., microinstructions 2 to 9, are all submitted, the private register occupied by microinstruction 2, i.e., the oldest microinstruction among the 8 microinstructions, i.e., physical register 0, is updated to an idle state, that is, the private register is released. For example, Figure 2 As shown, at this time, the processing of the microinstruction 10 by the execution module 2034 can be suspended, that is, stalled.

[0131] It can be understood that the reference distance of the microinstructions in the embodiment of the present application is ≤8. In this way, microinstructions 2 to 9 are all submitted, indicating that no subsequent microinstructions will reference the execution results of microinstruction 2. Releasing the private register corresponding to microinstruction 2 can take into account both abnormal instruction processing and effective use of private registers.

[0132] Alternatively, if the current microinstruction is a jump instruction, the private registers occupied by each microinstruction in the preset number of microinstructions before the jump instruction are updated to an idle state. When the jump instruction is executed, the execution result of the microinstruction before the jump instruction is stored in the general register without being obtained from the private register. Based on this, the private registers occupied by each microinstruction in the preset number of microinstructions before the jump instruction can be released.

[0133] In one example, the way to release the private register may be to mark the private register to be released as an idle state, and the execution module 2034 may allocate the private register in the idle state to the microinstruction that needs to use the private register, for example, to the microinstruction 10, and write the execution result of the microinstruction 10 into the private register. The preset number includes an integer ≥1.

[0134] Still see Figure 6 , the above-mentioned release of private registers is equivalent to determining the private registers that can be released during the instruction processing by moving the execution window (such as 8 instruction windows) that can contain a preset number of microinstructions, thereby ensuring that the current instruction always has a corresponding private register that can be used during the instruction processing. For example, when the execution module 2034 obtains the execution result of microinstruction 10, before storing the execution result in the register, if the private register corresponding to microinstruction 2 is released, the execution window can be moved: the execution window is moved to microinstruction 10, so that the new execution window contains microinstructions 3 to microinstructions 10, and the execution result of microinstruction 10 is stored in physical register 0. In this way, the embodiment of the present application can achieve the effect of unlimited private registers based on the release of the submission management register of the microinstruction, thereby further improving the instruction processing efficiency and reducing the hardware cost of the computing chip. Similarly, such as Figure 5 As shown, the execution module 2034 releases the private register in a manner of moving the execution window. For the released private register, the temporarily stored result therein is overwritten by the currently written execution result.

[0135] In addition, the computing chip can write the execution result into the general register when the general register is in an idle state.

[0136] In an optional example, the preset number may be equal to the number of the plurality of private registers.

[0137] For example, see Figure 6, if a computing chip such as a processor has 16 physical registers (such as physical register 0 to physical register 15), then an execution window containing 16 microinstructions can be constructed: a 16-instruction window.

[0138] In addition, the main hot spots and key paths (such as the output of instructions and the storage location of source data referenced by instructions) of the embodiment of the present application are eliminated from the front-end pipeline, which is conducive to expanding instruction-level parallel processing. The instruction window can be adaptively expanded according to the number of registers, thereby facilitating the expansion of instruction-level parallel capabilities.

[0139] In an optional embodiment, the instruction processing unit can predict any one of the multiple microinstructions based on the out-of-order processing rules of the superscalar processor architecture, and execute parsing of any one of the multiple microinstructions; then, in the event of a prediction error, the register occupied by any of the mispredicted microinstructions is updated to an idle state, and the predicted any one of the multiple microinstructions is re-executed.

[0140] For example, in a computing chip with a superscalar architecture, if an instruction is predicted incorrectly, the registers occupied by the instruction that is predicted incorrectly are cleared, that is, refreshed (e.g. Figure 2 The conventional superscalar processor needs to spend several beats to restore the mapping relationship between registers and instructions to the state before the prediction error and restore the release list recording the register state, while the embodiment of the present application only needs to re-predict the microinstructions and update the registers occupied by any microinstruction with the prediction error to the idle state, that is, clear the registers, thereby greatly simplifying the implementation logic of out-of-order execution of instructions and further improving processing efficiency.

[0141] In the embodiment of the present application, if an instruction prediction error occurs, it is only necessary to refresh the private register, without looking up the mapping relationship to restore the register to the state before the predicted instruction is used. A simpler out-of-order execution pipeline is implemented with less complex hardware, and the recovery speed of predicted missed instruction processing is accelerated.

[0142] In an optional implementation, the instruction processing unit may specifically create at least one thread for executing a computing task, and allocate at least two private registers of the plurality of private registers to each thread in the at least one thread; wherein each thread is used to process at least one microinstruction of the plurality of microinstructions;

[0143] Each thread performs parsing on any microinstruction in at least one microinstruction and any microinstruction in the plurality of microinstructions.

[0144] For example, Figure 8 This is one of the structural block diagrams of a computing chip 800 provided in an embodiment of the present application. Figure 8 As shown, the computing chip 800 and Figure 2 The computing chip 200 shown is similar, and the same parts are not repeated here. For details, see the above Figure 2 Description of the embodiment. The difference is that there are multiple private register stacks in the computing chip 800. Based on this, the instruction processing unit can specifically create at least one thread for executing the computing task, and allocate at least two private registers of the multiple private registers to each thread in the at least one thread, so that the computing chip 800 can perform multi-threaded processing on the instruction. Among them, the components used by each thread need to be added additionally, such as private registers; the common parts can be shared, such as computing units, decoding modules, etc.

[0145] For example, Fig. 9 FIG. 1 is a schematic diagram of an instruction processing process in an instruction processing method provided in an embodiment of the present application. Fig. 9 As shown, Figure 8 The computing chip in can create multiple threads to process computing tasks, and each thread processes a microinstruction sequence of the computing task. For example, thread TH1 processes the instruction sequence starting with microinstruction 1-0. Each thread can process microinstructions in the same way, and each thread is allocated multiple private registers. For example, the instruction processing unit allocates a total of 32 private registers to threads TH1 to TH4. In one example, each thread can be allocated 8 private registers, for example, thread TH1 is allocated private registers 1-0 to private registers 1-7, and thread TH2 is allocated private registers 2-0 to private registers 2-7. The embodiment of the present application does not specifically limit the allocation of private registers in the case of multi-threading, and can be set according to application requirements.

[0146] In an embodiment of the present application, a computing chip can create at least one thread and allocate multiple private registers to each thread to implement multi-threaded instruction processing and further improve instruction processing efficiency.

[0147] It should be understood that Figure 2 and Figure 8 The processor shown is only one example of a processor, and the processor may have more or fewer components than shown in the figure, may combine two or more components, or may have a different configuration of components. Figure 2 and Figure 8 The various components shown in the EMBODIMENTS 2000 may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application specific integrated circuits.

[0148] In addition, this application Figure 2 and Figure 8The processor shown includes hardware and / or software modules that perform the corresponding functions in order to implement the functions of the processor in the above-mentioned embodiment of the present application. In combination with the steps of each example described in the embodiment disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.

[0149] This embodiment also provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the data processing method in the above-mentioned embodiment.

[0150] This embodiment also provides a computer program product. When the computer program product runs on a computer, it enables the computer to execute the above-mentioned related steps to implement the data processing method in the above-mentioned embodiment.

[0151] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here.

[0152] Any content of each embodiment of the present application, as well as any content of the same embodiment, can be freely combined. Any combination of the above content is within the scope of the present application.

[0153] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0154] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A computing chip, characterized in that: The computing chip adopts a superscalar processor architecture, including: a plurality of registers and an instruction processing unit, the plurality of registers are respectively coupled to the instruction processing unit, the plurality of registers include: a general register and a plurality of private registers respectively coupled to the general register; The general register is used to store an execution result of a first instruction referenced by a second instruction, wherein the first instruction includes a microinstruction executed before a jump instruction among a plurality of microinstructions for implementing a computing task; and the second instruction includes a microinstruction executed after the jump instruction; Each private register of the plurality of private registers is used to store the execution result of the microinstructions other than the save instruction in the plurality of microinstructions; The instruction processing unit is used to parse any microinstruction among the multiple microinstructions, obtain a source operand of a first register among the multiple registers to determine an execution result of the any microinstruction according to the parsing result, store the execution result of the any microinstruction in a second register among the multiple registers that is different from the first register, and perform the parsing of any microinstruction among the multiple microinstructions until the computing task is completed; Wherein, the source operand includes the execution result of another microinstruction referenced by any microinstruction; when the source operand includes the execution result in the private register, the parsing result includes a relative distance index for indicating the relative distance between any microinstruction and the other microinstruction.

2. The computing chip according to claim 1, characterized in that: The instruction processing unit is specifically used for: Obtain one microinstruction from the plurality of microinstructions, and parse the one microinstruction to obtain a parsing result; wherein the parsing result includes an acquisition position identifier, or a relative distance index and a second register identifier; the acquisition position identifier includes a first register identifier or the relative distance index; Obtain the source operand from a first private register indicated by the relative distance index or a first general register indicated by the first register identifier; Execute the any microinstruction based on the source operand obtained from the first private register, obtain an execution result of the any microinstruction, and store the execution result of the any microinstruction in a second private register allocated to the any microinstruction among the plurality of private registers; When the parsing result includes a second register identifier, storing the source operand obtained from the first private register into a second general register indicated by the second register identifier; storing the source operand obtained from the first general register into an idle private register among the plurality of private registers; The obtaining of one of the plurality of microinstructions is executed until the computing task is completed.

3. The computing chip according to claim 1 or 2, characterized in that: The instruction processing unit is further used for: After determining the execution result of any one of the microinstructions, submitting any one of the microinstructions for the computing chip to perform the computing task based on the execution result of any one of the microinstructions; Before storing the execution result of any microinstruction in a register: If a preset number of microinstructions before any microinstruction are all submitted, then the private register occupied by the microinstruction with the farthest relative distance from any microinstruction among the preset number of microinstructions is updated to an idle state; Alternatively, if any of the microinstructions is a jump instruction, the private registers occupied by each microinstruction in a preset number of microinstructions before the jump instruction are updated to an idle state; wherein the preset number includes an integer ≥1; The instruction processing unit is specifically used for: According to the analysis result, the execution result of any microinstruction is stored in an idle register.

4. The computing chip according to claim 3, characterized in that: The preset number is equal to the number of the plurality of private registers.

5. The computing chip according to any one of claims 1 to 4, characterized in that: The instruction processing unit is specifically used for: Creating at least one thread for executing the computing task, and respectively allocating at least two private registers of the plurality of private registers to each thread of the at least one thread; wherein each thread is used to process at least one microinstruction of the plurality of microinstructions; The parsing of any microinstruction among the multiple microinstructions is performed by each thread on any microinstruction among the at least one microinstruction.

6. The computing chip according to any one of claims 1 to 5, characterized in that: The instruction processing unit is specifically used for: According to the out-of-order processing rule of the superscalar processor architecture, predict and obtain any microinstruction among the multiple microinstructions, and perform the parsing of any microinstruction among the multiple microinstructions to obtain a parsing result; In the case of a prediction error, the register occupied by any microinstruction with the prediction error is updated to an idle state, and the prediction is re-executed to obtain any microinstruction among the multiple microinstructions.

7. The computing chip according to any one of claims 1 to 6, characterized in that: The instruction processing unit includes an instruction cache module, an instruction fetch module coupled to the instruction cache module, a decoding module coupled to the instruction fetch module, and an execution module coupled to the plurality of private registers respectively; the decoding module is coupled to the plurality of private registers respectively; The instruction cache module is used to store the multiple microinstructions; The instruction fetch module is used to obtain a microinstruction in the instruction cache module, obtain any microinstruction among the multiple microinstructions, and transfer any microinstruction among the multiple microinstructions to the decoding module until the computing task is completed; The decoding module is used to parse any microinstruction among the multiple microinstructions, and obtain a source operand of a first register among the multiple registers according to the parsing result, and send the source operand and the parsing result to the execution module; The execution module is used to determine the execution result of any microinstruction based on the operand and the parsing result, and store the execution result of any microinstruction in a second register of the plurality of registers that is different from the first register.

8. A command processing method, characterized in that: The method is applied to a computing chip using a superscalar processor architecture, wherein the computing chip includes a plurality of registers, wherein the plurality of registers include: a general register and a plurality of private registers; and the method includes: Retrieving a plurality of microinstructions for implementing a computing task; Parsing any microinstruction among the plurality of microinstructions to obtain a parsing result; According to the parsing result, a source operand in a first register of the plurality of registers is obtained; wherein the source operand includes an execution result of another microinstruction referenced by any one of the microinstructions; in the case where the first register includes the private register, the parsing result includes a relative distance index for indicating a relative distance between any one of the microinstructions and the another microinstruction; Based on the parsing result and the source operand, determining the execution result of any microinstruction and storing the execution result of any microinstruction in a second register different from the first register among the multiple registers, and performing the parsing of any microinstruction among the multiple microinstructions to obtain the parsing result until the computing task is completed; wherein: In the case where any of the microinstructions includes a first instruction, the second register includes the general register, the first instruction includes a microinstruction among the plurality of microinstructions that is executed before a jump instruction and whose execution result is referenced by the second instruction, and the second instruction includes a microinstruction that is executed after the jump instruction; In a case where the any microinstruction includes a microinstruction other than a save instruction among the plurality of microinstructions, the second register includes any private register among the plurality of private registers.

9. The method according to claim 8, characterized in that The step of parsing any microinstruction among the plurality of microinstructions to obtain a parsing result includes: Obtain one microinstruction from the plurality of microinstructions, and parse the one microinstruction to obtain a parsing result; wherein the parsing result includes an acquisition position identifier, or a relative distance index and a second register identifier; the acquisition position identifier includes a first register identifier or the relative distance index; The step of obtaining a source operand in a first register among the plurality of registers according to the parsing result includes: Obtain the source operand from a first private register indicated by the relative distance index or a first general register indicated by the first register identifier; The step of determining the execution result of any microinstruction based on the parsing result and the source operand and storing the execution result of any microinstruction in a second register different from the first register among the plurality of registers, and parsing any microinstruction among the plurality of microinstructions to obtain the parsing result until the computing task is completed includes: Execute the any microinstruction based on the source operand obtained from the first private register, obtain an execution result of the any microinstruction, and store the execution result of the any microinstruction in a second private register allocated to the any microinstruction among the plurality of private registers; When the parsing result includes a second register identifier, storing the source operand obtained from the first private register into a second general register indicated by the second register identifier; storing the source operand obtained from the first general register into an idle private register among the plurality of private registers; The obtaining of one of the plurality of microinstructions is executed until the computing task is completed.

10. The method according to claim 8 or 9, characterized in that: After determining the execution result of any one of the microinstructions, the method further includes: Submitting any of the microinstructions for the method to perform the computing task based on the execution result of any of the microinstructions; Before storing the execution result of any microinstruction in a register, the method further includes: If the preset number of microinstructions before any microinstruction are all submitted, the private register occupied by the microinstruction with the farthest relative distance from any microinstruction among the preset number of microinstructions is updated to an idle state; or, if any microinstruction is a jump instruction, the private register occupied by each microinstruction among the preset number of microinstructions before the jump instruction is updated to an idle state; wherein the preset number includes an integer ≥1; The storing the execution result of any microinstruction into a second register different from the first register among the plurality of registers comprises: According to the analysis result, the execution result of any microinstruction is stored in an idle register.

11. The method according to claim 10, characterized in that The preset number is equal to the number of the plurality of private registers.

12. The method according to any one of claims 8 to 11, characterized in that The step of parsing any microinstruction among the plurality of microinstructions to obtain a parsing result includes: Creating at least one thread for executing the computing task, and respectively allocating at least two private registers of the plurality of private registers to each thread of the at least one thread; wherein each thread is used to process at least one microinstruction of the plurality of microinstructions; The parsing of any microinstruction among the multiple microinstructions is performed by each thread on any microinstruction among the at least one microinstruction.

13. The method according to any one of claims 8 to 12, characterized in that The step of parsing any microinstruction among the plurality of microinstructions to obtain a parsing result includes: According to the out-of-order processing rule of the superscalar processor architecture, predict and obtain any microinstruction among the multiple microinstructions, and perform the parsing of any microinstruction among the multiple microinstructions to obtain a parsing result; In the case of a prediction error, the register occupied by any microinstruction with the prediction error is updated to an idle state, and the prediction is re-executed to obtain any microinstruction among the multiple microinstructions.

14. An electronic device, characterized in that: include: processor; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 8 to 13.

15. A computer-readable storage medium, characterized in that: The method comprises a computer program, wherein when the computer program is run on an electronic device, the electronic device executes the method according to any one of claims 8 to 13.

16. A computer program product, characterized in that The invention comprises a computer program, which, when executed by an electronic device, enables the electronic device to execute the method according to any one of claims 8 to 13.

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