RISC-V Vector Register Release Method and Device

Abstract

This specification relates to the field of computer technologies, and specifically discloses a RISC-V vector register release method and apparatus. The method includes: in response to a vector instruction, storing multiple vector target register mapping information of the vector instruction in a preset circular buffer list in a reorder buffer; assisting the reorder buffer through the circular buffer list to release the vector target registers corresponding to the vector target register mapping information in units of the registers identified by the register retirement items in the circular buffer list. In this way, it is not necessary to significantly increase the hardware resources required for each ROB item, and the vector registers can be released into the FRL as soon as possible to improve the utilization efficiency of vector physical registers. Based on the original ROB, the following modifications for vector instructions are proposed in this solution.

Description

Technical Field

[0001] This specification relates to the field of computer technologies, and particularly to a method and apparatus for releasing RISC-V vector registers. Background Art

[0002] Many CPU cores implement register renaming, that is, mapping an architectural register to a physical register in the core to avoid false register dependencies such as write-after-read and write-after-write, so as to improve the instruction level parallelism (ILP) and performance of the CPU. For such CPU cores that implement register renaming, masked instructions need to copy the unmasked fields from the old target physical register A to the new target physical register B mapped by the same architectural register to ensure that the values of these fields remain unchanged. At this time, a masked instruction needs to read the values of four different physical registers: 2 sources, 1 mask, and one currently mapped target physical register. Register renaming is usually completed through the following several hardware buffers: Speculative rename table (SRT): Stores the mapping relationship between the latest (but possibly incorrect and subject to flushing) architectural register and the physical register. Architectural rename table (ART): Stores the mapping relationship between the architectural register and the physical register in the architectural state. Free register list (FRL): Generally implemented as a bit list, with each physical register corresponding to a bit, and the bit value of 1 indicating that the physical register is not currently in use. Reorder buffer (ROB): The ROB is a first-in-first-out (FIFO) circular buffer used to maintain the order relationship between instructions in an out-of-order execution CPU core.

[0003] When an instruction undergoes register renaming, the renaming unit performs the following operations: Query the SRT and find the physical register currently mapped to each source architectural register. When the instruction is subsequently inserted into the ROB at the Dispatch pipeline stage, the renaming information of its destination register is also saved in the corresponding ROB entry. For each destination architectural register, select a physical register with its corresponding FRL bit set to 1 and write this mapping into the SRT entry corresponding to the destination architectural register. At the same time, set this FRL bit to 0. In subsequent execution, the instruction (or one or more corresponding microinstructions) reads and writes these physical registers.

[0004] At the Retire pipeline stage, the oldest instruction (i.e., at the head of the ROB) can Retire if it has been executed successfully and there are no exceptions, which means releasing the hardware resources used by these instructions, including the physical registers they are mapped to. At this time, the mapping relationship from the destination architectural register to the physical register is written into the Architecture Renaming Table ART. The physical register replaced in the ART will set its FRL bit to 1 and can be reused in a new register mapping in the next clock cycle. Another function of the ART is to restore the SRT when a pipeline flush occurs due to a branch prediction error. When a pipeline flush occurs due to a branch prediction error, the branch prediction instruction that triggers the flush is not necessarily the oldest instruction in the pipeline. At this time, the following operations are required to restore the SRT content up to this instruction: Clear and temporarily suspend the CPU pipeline. Clear all instruction entries in the ROB that are younger than this branch instruction. Write each entry of the ART into the corresponding entry of the SRT. Starting from the first entry of the ROB, write the destination register mapping content into the SRT. The CPU pipeline resumes operation and fetches and executes instructions starting from the correct instruction address after the corrected branch instruction.

[0005] Both scalar and vector instructions may encounter exceptions. Exception handling is performed when the instruction is the oldest instruction in the pipeline. When RISC-V handles vector instruction exceptions, it first saves the position of the field where the exception occurs in the destination register (group) in the vstart CSR register, writes the data of all fields with an index smaller than the exception index of this instruction into the destination register, and then performs exception handling. After the exception handling is completed, the vector instruction is re-executed. The instruction will read the vstart value and set the mask of all fields with an index smaller than the vstart value to 0, that is, the result will not be written into the corresponding position in the destination register.

[0006] A scheme for simply extending the existing scalar ROB to support RISC-V vector instructions. The release of physical registers is still at the instruction granularity. However, when this scheme is extended to RISC-V vector instructions, the following problems will be faced: Each ROB entry needs to store all the mapping information from the target architecture to physical registers. And a RISC-V vector instruction can have up to 8 target registers, and the mapping information of these registers needs to be stored in the ROB entry, thus greatly increasing the hardware resources required for each ROB entry. While a RISC-V scalar instruction has only 0 or 1 target register, most of the register mapping fields in the ROB entries of these instructions are not used, resulting in overly large ROB entries and wasting hardware resources. A RISC-V vector instruction can have up to 8 target registers. If these target registers can be released only after the instruction is ready, it may delay the release time of these physical registers, thus reducing the frequency of reuse of these physical registers, decreasing the utilization efficiency of the vector physical register file, affecting performance or increasing the area of the vector physical register file.

[0007] In the above scheme, all register mapping information is stored in the ROB, and the release of physical registers is at the instruction granularity. This scheme will cause many unused fields in the ROB entry and a too long usage cycle of physical vector registers. These two problems will increase the hardware resources required for the ROB and cause performance losses due to insufficient number of vector physical registers. To avoid the above performance losses, the number of registers in the vector register file must be increased, further increasing the hardware resources required for the ROB.

[0008] For the above problems, no effective solution has been proposed yet. Summary of the Invention

[0009] The embodiments of this specification provide a method and device for releasing RISC-V vector registers, an optimized RISC-V vector instruction ROB extension scheme, which releases at the physical register granularity and can release physical vector registers as soon as possible, improving the utilization efficiency of the vector register file. Therefore, the same performance as the simple extension scheme can be achieved with fewer hardware resources and a register file with fewer entries.

[0010] The embodiments of this specification provide a method for releasing RISC-V vector registers, including:

[0011] In response to a vector instruction, store the mapping information of multiple vector target registers of the vector instruction in a preset circular cache list in the reorder buffer; assist the reorder buffer through the circular cache list to release the vector target registers corresponding to the vector target register mapping information with the registers identified by the register retirement items in the circular cache list as the granularity.

[0012] In one embodiment, the method further comprises:

[0013] Set a circular cache entry identifier field in the reorder buffer entry, wherein the circular cache entry identifier field is used to configure different values according to the vector destination register situation corresponding to the vector instruction.

[0014] In one embodiment, the method further comprises:

[0015] In response to a vector instruction, store scalar register mapping information of the vector instruction in the architecture register and physical register fields in the reorder buffer.

[0016] In one embodiment, the method further comprises:

[0017] The circular cache list allocates a register retirement entry for each vector destination register corresponding to the vector instruction; wherein the register retirement entry includes a circular cache list index, a vector instruction index field corresponding to the reorder buffer, a destination architecture register field, a corresponding destination physical register field, a vector instruction processing exception record identifier field, and a number field of register write microinstructions.

[0018] In one embodiment, releasing the vector destination register corresponding to the vector target register mapping information in terms of the registers identified by the register retirement entries in the circular cache list includes: sequentially releasing registers starting from the item pointed to by a preset circular cache pointer head every clock cycle; sequentially allocating vector register mapping starting from the item pointed to by a preset circular cache pointer tail every clock cycle; wherein the circular cache pointer head points to the longest-lived valid item in the circular cache list, and the circular cache pointer tail points to the first invalid item in the circular cache list.

[0019] In one embodiment, the number field of the register write microinstructions is used to initialize and generate corresponding values according to the number of vector microinstructions to be written to the vector destination register corresponding to the register retirement entry; and perform corresponding value adjustment according to the execution status of the vector microinstructions; wherein the vector microinstructions are generated by decoding the vector instruction.

[0020] In one embodiment, the number field of the register write microinstructions is used to initialize and generate corresponding field numbers or byte numbers according to the number of vector microinstructions to be written to the vector destination register corresponding to the register retirement entry; and perform corresponding field number or byte number adjustment according to the execution status of the vector microinstructions; wherein the vector microinstructions are generated by decoding the vector instruction.

[0021] In one embodiment, starting from the item pointed to by a preset circular buffer pointer head in each clock cycle, the sequential release register includes: identifying, starting from the item pointed to by the preset circular buffer pointer head, the number field of the register write microinstructions in all consecutive register retirement items that are filled with microinstructions and have no vector instruction processing exceptions; releasing the corresponding registers through the identified register retirement items, mapping the registers corresponding to the register retirement items to the architecture rename table, and releasing the physical registers in the replaced items in the architecture rename table to the free register table for subsequent calls.

[0022] The embodiments of this specification also provide a RISC-V vector register release device, which includes: an allocation module and a release module; the allocation module is used to store, in response to a vector instruction, mapping information of multiple vector target registers of the vector instruction in a preset circular buffer list in the reorder buffer; the release module is used to assist the reorder buffer through the circular buffer list, and release the vector target registers corresponding to the mapping information of the vector target registers in granularity of the registers identified by the register retirement items in the circular buffer list.

[0023] The embodiments of this specification also provide a central processing device, which includes a central processing core with a reorder buffer based on instructions, microinstructions, and macroinstructions, and the central processing device applies the above-mentioned RISC-V vector register release method.

[0024] For a RISC-V CPU core that implements RISC-V vector extension, the RISC-V vector register release method and device provided by this application, compared with the traditional solution, do not need to significantly increase the hardware resources required for each ROB item, and release the vector registers into the FRL as soon as possible to improve the utilization efficiency of vector physical registers. Based on the original ROB, the following changes for vector instructions are proposed in this solution.

[0025] Referring to the following description and drawings, specific embodiments of the present invention are disclosed in detail, indicating the ways in which the principles of the present invention can be adopted. It should be understood that the embodiments of the present invention are not limited in scope thereby. Features described and / or illustrated for one embodiment can be used in the same or similar way in one or more other embodiments, combined with the features in other embodiments, or replace the features in other embodiments.

[0026] It should be emphasized that the term "comprising / including" when used in this text refers to the presence of features, components, steps, or assemblies, but does not exclude the presence or addition of one or more other features, components, steps, or assemblies. Description of the Drawings

[0027] The accompanying drawings described herein are used to provide a further understanding of the present specification, form a part of the present specification, and do not limit the present specification. In the drawings:

[0028] Figure 1 It is a schematic flowchart of the RISC-V vector register release method provided by an embodiment of the present application;

[0029] Figure 2 It is a schematic diagram of the application effect of the RISC-V vector register release method provided by an embodiment of the present application;

[0030] Figure 3 It is a diagram showing multiple pipeline stages of a CPU architecture in the prior art;

[0031] Figure 4 It is a schematic flowchart of the release stage provided by another embodiment of the present application;

[0032] Figure 5 It is a schematic structural diagram of the RISC-V vector register release device provided by an embodiment of the present application. Detailed implementation manners

[0033] Hereinafter, the principles and spirit of the present specification will be described with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and then implement the present specification, and do not limit the scope of the present specification in any way. On the contrary, these embodiments are provided to make the disclosure of the present specification more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] Those skilled in the art know that the embodiments of the present specification can be implemented as a system, a device, a method, or a computer program product. Therefore, the disclosure of the present specification can be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0035] Combined with the accompanying drawings and the description of the specific embodiments of the present invention, the details of the present invention can be more clearly understood. However, the specific embodiments of the present invention described herein are only for the purpose of explaining the present invention and cannot be construed in any way as a limitation of the present invention. Under the teaching of the present invention, those skilled in the art can conceive any possible variations based on the present invention, and these should be regarded as belonging to the scope of the present invention. It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the communication inside two elements. It can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific situations. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are only for the purpose of illustration and do not represent the only embodiments.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art belonging to the technical field of this specification. The terms used herein in this specification are only for the purpose of describing specific embodiments and are not intended to limit this specification. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0037] The embodiments of this specification provide a method for releasing RISC-V vector store hardware resources. <tmp Figure 1 The flowchart of the RISC-V vector register release method in an embodiment of this specification is shown. Although this specification provides method operation steps or device structures as shown in the following embodiments or drawings, more or fewer operation steps or module units may be included in the method or device based on routine or non-creative labor. In steps or structures where there is no necessary causal relationship logically, the execution order of these steps or the module structure of the device is not limited to the execution order or module structure described in the embodiments of this specification and shown in the drawings. When the method or module structure is applied to an actual device or terminal product, it can be executed sequentially or in parallel according to the method or module structure shown in the embodiments or drawings (for example, in an environment of parallel processors or multi-threaded processing, or even a distributed processing environment).

[0038] Please refer to Figure 1 As shown, the RISC-V vector register release method provided by the embodiments of this specification may specifically include:

[0039] S101 stores, in a preset circular buffer list in the reorder buffer, mapping information of multiple vector destination registers of the vector instruction in response to the vector instruction;

[0040] S102 assists the reorder buffer through the circular buffer list to release the vector destination registers corresponding to the mapping information of the vector destination registers in a register retirement item identified by the circular buffer list as a granularity.

[0041] In this embodiment, it mainly aims at the defect of the utilization efficiency of the vector register file caused by the existing register release with instruction as the granularity; specifically, the RISC-V vector instruction set is one of the many standard instruction set extensions of RISC-V, which is used to support the single instruction multiple data (SIMD) computing mode to improve the computing power and efficiency of the corresponding CPU. The register width used by SIMD instructions is generally 128 bits or wider, and each vector register contains multiple integer fields with a width of 8 / 16 / 32 / 64 bits or floating-point fields with a width of 16 / 32 / 64 bits. In common SIMD instruction sets (such as AVX512 in X64), the registers and data widths corresponding to each instruction are fixed. However, a RISC-V vector instruction can be used for different register widths and data widths. The advantage of this is that an application program using RISC-V vector instructions can run on CPUs with different register and vector pipeline widths without any modification. In RISC-V, the width of the field is represented by SEW (selected element width). However, in this method, since there are multiple micro-instructions in the vector instruction and each micro-instruction has a corresponding vector destination register, and these vector destination registers are only released after the entire vector instruction is completed, the vector destination registers occupied by the executed micro-instructions cannot be effectively released, thus reducing the utilization efficiency of the vector destination registers. In the above embodiment provided by this application, by setting a circular buffer list to monitor the execution status of each micro-instruction and assisting the reorder buffer to release the vector destination registers in a register granularity, the same performance as the simple extension scheme can be achieved with fewer hardware resources and a register file with fewer items. The specific implementation methods of each step will be described in detail in the subsequent embodiments and will not be elaborated here one by one.

[0042] In one embodiment, the method further includes: setting a circular buffer item identification field in the reorder buffer item, where the circular buffer item identification field is used to configure different values according to the situation of the vector destination registers corresponding to the vector instruction.

[0043] Specifically, in this embodiment, a 1-bit circular buffer entry identification field (use_VRRB field) is mainly added to the Reorder Buffer (ROB). If a vector instruction has one or more vector destination registers, this bit is set to 1 when the ROB entry is allocated; otherwise, this bit is set to 0. In this way, the relevant situation of the corresponding vector destination register can be determined through the use_VRRB field subsequently.

[0044] In one embodiment, the method further includes: in response to a vector instruction, storing scalar register mapping information of the vector instruction in an architecture register and a physical register field in a reorder buffer.

[0045] Specifically, in actual work, the existing architecture registers and physical register fields in the ROB are only used to save scalar register mappings, rather than vector register mappings. Some RISC-V vector instructions have scalar destination registers, and the corresponding scalar register mapping information is saved in the ROB entries corresponding to these instructions.

[0046] In one embodiment, the method further includes: the circular buffer list allocates a register retirement entry for each vector destination register corresponding to the vector instruction;

[0047] Wherein, the register retirement entry includes a circular buffer list index, a vector instruction index field corresponding to the reorder buffer, a destination architecture register field, a corresponding destination physical register field, a vector instruction processing exception record identification field, and a number field of register write microinstructions.

[0048] Specifically, a new hardware table is added in this application: the vector register retire buffer (VRRB), which is the same as the reorder buffer (ROB). The VRRB is also a First In First Out (FIFO) circular buffer. A VRRB entry, that is, a circular buffer entry, is allocated for each vector destination register. The VRRB entry includes the following fields: [[ID=!7]]

[0049] Circular buffer list index IDX: provides the VRRB index, which is used for sequential allocation and release of VRRB entries;

[0050] Vector instruction index field IID corresponding to the reorder buffer: provides the instruction index, corresponding to the IID field in the ROB, which is used to identify the ROB entry / instruction to which this VRRB entry belongs;

[0051] Destination architecture register field Arch_Reg: provides destination architecture register information;

[0052] Corresponding to the target physical register domain Phy_Reg: Provide information about the corresponding target physical register;

[0053] The number field Cnt_Down of the register write micro-instruction: Provide a register change counter, initialized to the number of micro-instructions generated by this instruction and written to this register. When a micro-instruction writes to this physical register, the corresponding Cnt_Down value is decremented by one. When the Cnt_Down value of a field is 0, all fields in this register have been written.

[0054] The vector instruction processing exception record identification field Exception: The initial value is -1. If an exception occurs when an instruction / micro-instruction processes a certain field, the index corresponding to this field will be written into this field.

[0055] Furthermore, in one embodiment, releasing the vector target register corresponding to the vector target register mapping information in terms of the registers identified by the register retirement items in the circular cache list includes: Sequentially releasing registers starting from the item pointed to by a preset circular cache pointer head every clock cycle; Sequentially allocating vector register mappings starting from the item pointed to by a preset circular cache pointer tail every clock cycle; wherein, the circular cache pointer head points to the oldest valid item in the circular cache list, and the circular cache pointer tail points to the first invalid item in the circular cache list.

[0056] Specifically, in actual work, this application also provides two pointers:

[0057] The circular cache pointer head VRRB head: Points to the oldest valid item in the VRRB, and attempts to sequentially release registers starting from the item pointed to by the VRRB head every clock cycle.

[0058] The circular cache pointer tail VRRB tail: Points to the first invalid item in the VRRB, and sequentially allocates new vector register mappings starting from the item pointed to by the VRRB tail every clock cycle.

[0059] Please refer to Figure 2 as shown in Figure 2 For the RISC-V vector register release method provided by this application, the ROB+VRRB with vector instruction support added; Figure 2The code in the example is a segment of SAXPY (Scalar Alpha X Plus Y), which is a common computational operation in vector processors. It is a combination of scalar multiplication and vector addition: v8 = fa0 * v0 + v8, where fa0 is a scalar, and v8 and v0 are vectors. In the example, the instruction with IID = 0 sets LMUL to 4 (m4) and SEW to 32 (e32). Assuming VLEN = 128, each register has 4 32-bit fields, and each vector instruction processes the contents of 4 target registers. The 6th and 7th (IID = 5 and 6) instructions in the ROB are vector ALU instructions, each with 4 target registers. Therefore, 4 VRRB entries are allocated for each instruction, as shown in the figure. The IID value in the VRRB entry is the IID value of its corresponding instruction in the ROB.

[0060] In an embodiment of the present application, starting from the item pointed to by the preset circular buffer pointer head in each clock cycle, sequentially releasing registers includes: identifying, starting from the item pointed to by the preset circular buffer pointer head, all consecutive register retirement items that are filled with microinstructions by microinstructions and have no vector instruction processing exceptions in the quantity field of the registers written by the microinstructions; releasing the corresponding registers through the identified register retirement items, mapping the registers corresponding to the register retirement items to the architecture rename table, and releasing the physical registers in the replaced items in the architecture rename table to the free register table for subsequent calls.

[0061] Specifically, as Figure 2 shown, in actual work, when a vector instruction becomes the oldest unreleased instruction in the ROB (that is, the ROB head points to its ROB entry), if the bit in its use_VRRB field is 1, it has one or more corresponding VRRB entries. At this time, the VRRB head pointer should point to the first VRRB entry of this vector instruction. Starting from this VRRB head entry, all consecutive VRRB entries with Cnt_Down = 0 and Exception = -1 can be released, and their register mappings will be written into the ART. The VRRB head will move to the first item that does not meet the above conditions in this instruction; after all VRRB entries of this instruction are released, the VRRB head will move to the first VRRB entry of the next vector instruction. In the latter case, the VRRB will notify the ROB that this instruction has been fully executed and can be released from the ROB. As shown in the figure, for the first two target registers of the instruction with IID = 5, they have been fully written and there is no exception, while there is still one field in the third target register that has not been written (Cnt_Down = 1). Therefore, the first two registers can be released, and the VRRB head moves from the IDX = 0 entry to the IDX = 2 entry.

[0062] In one embodiment of the present application, the quantity field of the register write micro-instruction is used to initialize and generate corresponding numerical values, field numbers, or byte numbers according to the number of vector micro-instructions of the vector target register corresponding to the register retirement item to be written; and, adjust the corresponding numerical values, field numbers, or byte numbers according to the execution status of the vector micro-instructions; wherein, the vector micro-instructions are generated by decoding the vector instructions.

[0063] Specifically, in the present application, the VRRB Cnt_Down field is initialized to the number of micro-instructions written to this register. A possible solution is to set this field to the number of fields (VLEN / SEW), or always initialize it to the number of bytes (VLEN / 8). In these two alternative solutions, the rewrite time of Cnt_Down is the same as that of this solution, except that the number of Cnt_Down decreases is the number of written fields and the number of written bytes respectively.

[0064] For a clearer understanding of the application position of the RISC-V vector register release method provided by the present application in actual work, please refer specifically to Figure 3 As shown, in order to improve performance, modern CPU architectures generally include multiple pipeline stages, including branch prediction, instruction cache, instruction decoding, register renaming, distribution, execution, and retirement.

[0065] The present application mainly makes adjustments to Dispatch, Execution, and Retire, specifically as follows:

[0066] Dispatch: Information related to an instruction is written into the ROB. If the instruction is a vector instruction with a vector target register, then VRRB items equal to the number of target registers are allocated for this instruction, and the contents of these items are initialized. This stage also saves the number of current idle VRRB items. If there are not enough VRRB items at this time, the vector micro-instructions that have not been allocated VRRB items will stall in the Dispatch stage and wait for idle VRRB items to be released in the next clock cycle.

[0067] Execution: When a vector micro-instruction finishes execution and writes the result into the register file, the Cnt_Down field of its VRRB item is decremented by one. If an exception occurs, the index of the exception field is written into the Exception field of the corresponding VRRB item.

[0068] Retire: The following Figure 4 operations are performed on the oldest item in the ROB:

[0069] 1. First, check the value of Use_VRRB in the ROB head item. If it is 1, which means there is at least one VRRB item in this item, jump to step 4; otherwise, execute the next step.

[0070] 2. Check if the instruction without VRRB item is abnormal. If it is abnormal, trigger the exception handling and end; otherwise, execute the next step.

[0071] 3. Determine if the instruction has been executed completely. If it has, jump to step 11; otherwise, the instruction has not been executed completely and cannot retire, then end.

[0072] 4. Read the VRRB item pointed to by the VRRB head pointer.

[0073] 5. If the Cnt_Down of this item is not 0, it means the corresponding vector uop of this item has not been executed completely, then end; otherwise, execute the next step.

[0074] 6. If the Exception of this item is not zero, it indicates that the execution of the corresponding vector uop of this item is abnormal, then execute the next step; otherwise, jump to step 8.

[0075] 7. Send the exception index to the ROB. After receiving it, the ROB saves the exception index in the vstart CSR, and then triggers the exception handling and end.

[0076] 8. At this time, the uop corresponding to the VRRB head item has been executed completely and there is no exception. Write the register mapping of this item into the vector ART, and release the physical registers in the replaced item in the vector ART to the vector FRL.

[0077] 9. Release this VRRB head item, that is, move the VRRB head pointer to the next position (VRRB_head + 1) % VRRB_size, and at the same time notify the Dispatch stage that this VRRB item has been released.

[0078] 10. Determine if the new VRRB head item has the same IID as the old VRRB head item. If it does, jump to step 4; otherwise, execute the next step.

[0079] 11. At this time, the instruction corresponding to the ROB head item has been executed completely and there is no exception, and it can retire. If there is a scalar register mapping in this item, write this mapping into the scalar ART, and release the physical registers in the replaced item in the vector ART to the vector FRL.

[0080] 12. Release this ROB head item, that is, move the ROB head pointer to the next position (ROB_head + 1) % ROB_size, and end.

[0081] Please refer to Figure 5 As shown, the embodiment of this specification also provides a RISC-V vector register release device, which includes an allocation module 501 and a release module 502; the allocation module 501 is used to store multiple vector target register mapping information of the vector instruction in a preset circular cache list in the reorder buffer in response to the vector instruction; the release module 502 is used to assist the reorder buffer through the circular cache list, and release the vector target register corresponding to the vector target register mapping information in units of the registers identified by the register retirement items in the circular cache list. Since the principle of this device for solving problems is similar to that of the RISC-V vector register release method, the implementation of this device can refer to the implementation of the RISC-V vector register release method, and the repeated parts will not be elaborated.

[0082] The embodiment of this specification also provides a central processing device, which includes a central processing core based on a reorder buffer of instructions, microinstructions and macroinstructions, and the central processing device applies the above-mentioned RISC-V vector register release method.

[0083] In the above embodiment, in many CPU cores, the ROB does not store instructions, but stores microinstructions (microuop) or macroinstructions (macro op), which are both specific conversion formats of instructions in a CPU core: one instruction may be converted into one or more microinstructions / macroinstructions, or two instructions may be combined into one microinstruction / macroinstruction, etc. The ROB based on instructions / microinstructions / macroinstructions is designed for scalar instructions and faces the same problems for vector instructions. Therefore, this application is also applicable to CPU cores using a ROB based on microinstructions / macroinstructions. Similarly, for high-performance, superscalar CPU cores that can rename, execute, and retire multiple instructions within one clock cycle, this application is also applicable.

[0084] For a RISC-V CPU core implementing RISC-V vector extensions, the RISC-V vector register release method and device provided by this application, compared with the traditional solution, do not need to significantly increase the hardware resources required for each ROB item, and release the vector registers into the FRL as soon as possible to improve the utilization efficiency of vector physical registers. Based on the original ROB, the following changes for vector instructions are proposed.

[0085] Obviously, those skilled in the art should understand that the various modules or steps of the embodiments of the present specification described above can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Optionally, they can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order than here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the embodiments of the present specification are not limited to any specific combination of hardware and software.

[0086] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and many applications other than the examples provided will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this specification should not be determined by reference to the above description, but rather by reference to the full scope of the foregoing claims and the equivalents thereof.

[0087] The above are only the preferred embodiments of this specification and are not used to limit this specification. For those skilled in the art, various changes and modifications can be made to the embodiments of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included within the protection scope of this specification.

Claims

1. A RISC-V vector register release method, characterized in that: The method comprises: In response to a vector instruction, storing a plurality of vector target register mapping information of the vector instruction in a circular cache list preset in a reorder cache; Assisting the reorder cache by using the circular cache list, releasing the vector target register corresponding to the vector target register mapping information at a granularity of registers identified by register retirement entries in the circular cache list; Releasing the vector target registers corresponding to the vector target register mapping information at a granularity of registers identified by register retirement entries in the circular buffer list includes: sequentially releasing registers starting from an entry pointed to by a preset circular buffer head pointer in each clock cycle; sequentially allocating vector register mappings starting from an entry pointed to by a preset circular buffer tail pointer in each clock cycle; wherein the circular buffer head pointer points to the longest valid entry in the circular buffer, and the circular buffer tail pointer points to the first invalid entry in the circular buffer; The register write microinstruction quantity field is used to initialize and generate a corresponding value according to the number of vector microinstructions that need to be written into the vector target register corresponding to the register retirement item; and to adjust the corresponding value according to the execution state of the vector microinstruction; wherein the vector microinstruction is generated by decoding the vector instruction; The circular cache list is a first-in-first-out circular buffer.

2. The RISC-V vector register release method according to claim 1, wherein: The method further comprises: A circular cache entry identification field is set in the reorder cache entry, wherein the circular cache entry identification field is used to configure different values according to the vector target register corresponding to the vector instruction.

3. The RISC-V vector register release method according to claim 1, wherein: The method further comprises: In response to a vector instruction, scalar register mapping information of the vector instruction is stored in the architectural register and physical register fields of the re-order cache.

4. The RISC-V vector register release method according to claim 1, wherein: The method further comprises: The circular cache list allocates a register retirement entry for each vector target register corresponding to the vector instruction; The register retirement item includes a circular cache list index, a vector instruction index field corresponding to the reorder cache, a target architecture register field, a corresponding target physical register field, a vector instruction processing exception record identification field, and a register write microinstruction quantity field.

5. The RISC-V vector register release method according to claim 1, wherein: The register write microinstruction quantity field is used to initialize and generate a corresponding number of fields or bytes according to the number of vector microinstructions that need to be written into the vector target register corresponding to the register retirement item; and to adjust the corresponding number of fields or bytes according to the execution state of the vector microinstruction; The vector microinstruction is generated by decoding the vector instruction.

6. The RISC-V vector register release method according to claim 1 or 5, characterized in that: Each clock cycle starts by presetting the circular buffer pointer to the entry pointed to by the registers, including: identifying, according to the entry pointed to by the preset circular cache pointer, the number fields of all consecutive register write microinstructions that are filled with microinstructions, and determining the register retirement entry of the register that needs to release the register based on the number fields of the register write microinstructions and the register retirement entry of the vector instruction-free processing exception; The corresponding register is released by the determined register retirement item, the register mapping corresponding to the register retirement item is stored in the architecture rename table, and the physical register in the replaced item in the architecture rename table is released to the free register table for subsequent call.

7. A RISC-V vector register release device, characterized in that: The device comprises: an allocation module and a release module; The allocation module is configured to store, in response to a vector instruction, a plurality of vector target register mapping information of the vector instruction in a circular cache list preset in the reorder cache; The release module is used to assist in reordering the cache through the circular cache list, and release the vector target register corresponding to the vector target register mapping information with the register identified by the register retirement item in the circular cache list as the granularity; releasing the vector target register corresponding to the vector target register mapping information with the register identified by the register retirement item in the circular cache list as the granularity includes: sequentially releasing registers starting from the item pointed to by the preset circular cache pointer head in each clock cycle; sequentially allocating vector register mappings starting from the item pointed to by the preset circular cache pointer tail in each clock cycle; wherein the circular cache pointer head points to the longest valid item in the circular buffer, and the circular cache pointer tail points to the first invalid item in the circular buffer; the number field of the register write microinstruction is used to initialize and generate a corresponding value according to the number of vector microinstructions written to the vector target register corresponding to the register retirement item as needed; and performing corresponding value adjustment according to the execution status of the vector microinstruction; wherein the vector microinstruction is generated by decoding the vector instruction; The circular cache list is a first-in-first-out circular buffer.

8. A central processing unit comprising a central processing core based on an instruction reorder cache, characterized in that: The central processing unit applies the RISC-V vector register release method according to any one of claims 1 to 6.

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