Method and device for resetting multi-core DSP (Digital Signal Processor) master control system
By configuring independent watchdogs for each DSP core with FPGA software and employing combined software and hardware resets, the system addresses freezing issues, ensuring synchronized recovery and stable operation in multi-core DSP systems.
Patent Information
- Application Number
- CN202411172424.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2024-12-17
AI Technical Summary
Existing multi-core DSP main control systems face issues where DSP software frequently freezes or runs abnormally, leading to system instability and potential harm, with existing reset methods failing to restore the system to a normal state effectively.
Implementing an independent watchdog for each DSP core using FPGA software, which initializes and configures the watchdog during startup, performs regular feeding operations, and triggers a reset when abnormal conditions occur, combining software and hardware resets to ensure synchronous recovery.
The solution effectively resets the multi-core DSP system upon abnormality, ensuring synchronous startup and data sharing among cores, thereby restoring normal operation and preventing system crashes.
Smart Images
Figure CN119149298A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of DSP control, and in particular relates to a reset method and a device for a multi-core DSP main control system. Background Art
[0002] At present, the aiming device system has been widely used. The aiming device system is generally composed of a main control board, an inertial data collector, a transfer mechanism, a CCD light tube and other components. The hardware structure diagram is as follows: Figure 2 As shown in the figure. The main control board needs to interface with other components and undertakes the control and algorithm calculation of the aiming system. Generally, FPGA+multi-core DSP is used as the main processing chip, and FPGA and DSP software are designed at the same time. DSP software often runs abnormally or freezes when the system is accidentally disturbed, which may cause greater impact or harm.
[0003] In order to enable the aiming system to quickly recover to a normal state when it freezes, the present invention provides a method and device for resetting a multi-core DSP main control system. Summary of the invention
[0004] In order to solve the above problems existing in the prior art, the present invention provides a reset method and device for a multi-core DSP main control system.
[0005] In order to achieve the above object, the present invention adopts the following technical solutions.
[0006] In a first aspect, the present invention provides a reset method for a multi-core DSP master control system, comprising the following steps:
[0007] Configure an independent watchdog implemented by FPGA software for each DSP core;
[0008] When powered on, each DSP core initializes and configures its own watchdog. After normal operation, the watchdog is fed regularly in the main loop program.
[0009] When a DSP core program runs abnormally or crashes, the dog barking function is triggered because the dog feeding operation cannot be performed. By resetting each DSP core, the multi-core DSP main control system returns to normal.
[0010] Furthermore, after power-on, the FPGA defaults to each watchdog being in the barking enable off state; when the DSP software is loaded into the memory and started running, each DSP core performs the following initialization configuration on its own watchdog: setting the barking time and turning on the barking enable.
[0011] Furthermore, by writing 0x07D0 to the barking time parameter register, the barking time is set to 2000ms; by writing 0xAA to the watchdog enable register, the barking enable is turned on, and by writing 0xFF, the barking enable is turned off; and by writing 0xAA to the dog feeding register, the dog feeding operation is implemented.
[0012] Furthermore, after the barking function is triggered, the FPGA puts each watchdog in a barking enable off state, and then resets each DSP core.
[0013] Further, performing a reset operation on each DSP core includes: performing a software reset on each DSP core.
[0014] Furthermore, performing a reset operation on each DSP core includes: first performing a software reset on each DSP core, and if the reset of each DSP core is successful, the reset is completed; otherwise, performing a hardware reset on each DSP core.
[0015] Furthermore, the method for performing hardware reset on each DSP core includes: outputting a high level pulse signal or a low level pulse signal to the reset pin of each DSP core chip.
[0016] Furthermore, the method for performing hardware reset on each DSP core includes: disconnecting the DC power supply of the multi-core DSP main control system for a period of time, and then powering it on to restart.
[0017] Furthermore, the multi-core DSP is TMS320C6674, which has 4 DSP cores in total.
[0018] In a second aspect, the present invention provides a reset device for a multi-core DSP master control system, comprising:
[0019] Watchdog deployment module, used to configure an independent watchdog implemented by FPGA software for each DSP core;
[0020] The watchdog configuration module is used for each DSP core to initialize and configure its own watchdog when powered on; after normal operation, the watchdog is fed regularly in the main loop program;
[0021] The reset execution module is used to trigger the dog barking function when a DSP core program runs abnormally or crashes because the dog feeding operation cannot be performed. The multi-core DSP main control system returns to normal by resetting each DSP core.
[0022] Compared with the prior art, the present invention has the following beneficial effects.
[0023] The present invention configures an independent watchdog implemented by FPGA software for each DSP core. When starting, each DSP core initializes and configures its own watchdog. After normal operation, the dog feeding operation is performed in the main loop program. When a DSP core program runs abnormally or crashes, the dog barking function is triggered because the dog feeding operation cannot be performed. The multi-core DSP main control system is restored to normal by resetting each DSP core, thereby realizing the automatic reset of the multi-core DSP main control system. The present invention can effectively solve the problem that the multi-core DSP cannot be restored to normal once a core program of the multi-core DSP runs abnormally or crashes. By setting multiple watchdogs with independent functions, the multi-core DSP can be reset as a whole, ensuring the synchronous startup loading, operation and data sharing between cores of each core. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 The present invention is a flowchart of a method for resetting a multi-core DSP main control system.
[0025] Figure 2 Schematic diagram of the hardware structure of the aiming device system.
[0026] Figure 3 This is a schematic diagram of a hardware reset circuit.
[0027] Figure 4 This is the reset workflow diagram of the aiming device system using a 4-core DSP.
[0028] Figure 5 The present invention is a block diagram of a reset device for a multi-core DSP main control system according to an embodiment of the present invention. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical solution and advantages of the present invention clearer and more understandable, the present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0030] Figure 1 This is a flowchart of a reset method of a multi-core DSP master control system according to an embodiment of the present invention, comprising the following steps:
[0031] Step 101, configuring an independent watchdog implemented by FPGA software for each DSP core;
[0032] Step 102, when powered on, each DSP core initializes and configures its own watchdog; after normal operation, the watchdog is fed regularly in the main loop program;
[0033] Step 103, when a DSP core program runs abnormally or crashes, the dog barking function is triggered because the dog feeding operation cannot be performed, and the multi-core DSP main control system is restored to normal by resetting each DSP core.
[0034] This embodiment provides a reset method for a multi-core DSP master control system based on a watchdog. The multi-core DSP master control system generally uses FPGA + multi-core DSP as the main processing chip, and designs FPGA and DSP software at the same time. Watchdog is the common name for the program operation monitoring system WATCHDOG, which is used to monitor and protect the normal operation of computer systems, networks or specific devices. The watchdog is equivalent to a counter (timer). When the computer is working normally, it will continuously send a count reset pulse signal (commonly known as a dog feeding signal) to the counter, so that the counter cannot output an overflow signal; if the computer falls into an infinite loop, the counter cannot receive the reset signal, and the counter outputs an overflow signal when it is full, so that the computer is reset (commonly known as a dog barking). The watchdog can be implemented by software or hardware. The counter of the software watchdog is implemented by the timing / timer inside the CPU. The hardware watchdog can use a special watchdog chip or be built by a first-level monostable circuit.
[0035] In this embodiment, step 101 is mainly used to configure an independent watchdog for each DSP core. In order to facilitate monitoring of the work of each DSP core, this embodiment configures an independent watchdog for each DSP core, and the watchdog is implemented by FPGA software. Each DSP core can control the corresponding watchdog independently.
[0036] In this embodiment, step 102 is mainly used to control the watchdog. The control of the watchdog includes: when the system is powered on, each DSP core initializes and configures its own watchdog, that is, sets the value of the relevant register; after the system works normally, a timed dog feeding operation is performed in the main loop program, that is, a reset pulse signal (i.e., a dog feeding signal) is output at regular intervals, so that the counter in the watchdog is reset before the counter overflows, and the counter starts counting from zero again. As long as the program of the DSP core runs normally, the dog feeding signal can be continuously output to avoid the counter overflowing.
[0037] In the present embodiment, step 103 is mainly used to restore to normal by executing reset when the program runs abnormally or crashes. As mentioned above, when the computer crashes, it will not be able to output the dog feeding signal, thereby triggering the dog barking function. Crash is a phenomenon in which the computer program is trapped in an unexpected dead loop due to interference or other reasons. The root cause of the crash is that the program has an abnormal jump. Since the position of the abnormal jump is random, when the program jumps to the non-first byte of a certain instruction, the second half of this instruction and the first half of the next instruction may be executed as one instruction. The string of instructions executed in this way is a completely unrecognizable section of the program, which is likely to form an endless loop. Once the crash occurs, special means must be taken to intervene (such as reset) to make it jump out of the endless loop and resume normal operation. In the present embodiment, when a certain DSP core program runs abnormally or crashes, the multi-core DSP main control system is restored to normal by resetting each DSP core at the same time. This embodiment sets multiple watchdogs with independent functions and performs a reset operation on each DSP core at the same time, so that the multi-core DSP can be reset as a whole, ensuring that each core starts loading and running synchronously and that data is shared between cores.
[0038] As an optional embodiment, after power-on, the FPGA defaults to each watchdog being in a barking enable OFF state; when the DSP software is loaded into the memory and started running, each DSP core performs the following initialization configuration on its own watchdog: setting the barking time and turning on the barking enable.
[0039] This embodiment provides a method for setting the watchdog when the system is powered on. As mentioned above, the watchdog is implemented by FPGA. When the system is just powered on, FPGA sets all watchdogs to the default barking enable off state, the purpose of which is to prohibit all watchdogs from outputting barking signals to avoid affecting the normal startup of the system. When the DSP software is loaded into the memory and started running, each DSP core initializes and configures its own watchdog, first sets the barking time, and then turns on the barking enable. The barking time refers to the time required for the watchdog counter to overflow, which is greater than the dog feeding signal cycle.
[0040] As an optional embodiment, the barking time is set to 2000ms by writing 0x07D0 to the barking time parameter register; the barking enable is turned on by writing 0xAA to the watchdog enable register, and the barking enable is turned off by writing 0xFF; the dog feeding operation is implemented by writing 0xAA to the dog feeding register.
[0041] This embodiment provides a specific scheme for watchdog configuration. This embodiment sets the barking time through the barking time parameter register. The unit of the barking time is ms. For example, by writing the hexadecimal number 0x07D0 (converted to decimal number 2000) to the barking time parameter register, the barking time is set to 2s. The barking enable is turned on and off by setting the watchdog enable register. When 0xAA is written to the register, the barking enable is turned on; when 0xFF is written, the barking enable is turned off. The dog feeding operation is implemented by setting the dog feeding register. For example, writing 0xAA to the dog feeding register can implement the dog feeding operation. It is worth noting that this embodiment only provides a preferred implementation method, and does not deny or exclude other feasible implementation methods, such as setting a barking time different from 2s, turning on and off the barking enable by writing a specific value different from that of this embodiment, etc.
[0042] As an optional embodiment, after the barking function is triggered, the FPGA puts each watchdog in a barking enable off state, and then performs a reset operation on each DSP core.
[0043] This embodiment provides a technical solution for resetting each DSP core after the barking function is triggered. In order to prevent the watchdog from affecting the reset operation, this embodiment first turns off the barking enable of all watchdogs by FPGA before performing the reset operation, that is, all watchdogs are in the default state when powered on.
[0044] As an optional embodiment, performing a reset operation on each DSP core includes: performing a software reset on each DSP core.
[0045] This embodiment defines the reset operation. Computer reset can be divided into software reset and hardware reset. Soft reset is a reset mechanism implemented by software. When the system needs to be reset, it can be implemented by running a specific reset code or sending a reset instruction. The advantage of software reset is that it can avoid the waste of hardware resources because no additional hardware circuit is required. In addition, software reset can also provide more flexible reset control, such as selectively resetting part of the system or module as needed, so the reset execution speed is also faster. Software reset is usually implemented through a program counter. When the system needs to be reset, the program counter will be reset to a specific value, so that the program starts to execute from the specified position. In order to ensure the correctness of the software reset, the reset code usually checks some hardware states, such as power supply voltage, to confirm that the system is stable and the reset operation can be performed safely. Hardware reset is different from software reset. Hardware reset is a reset mechanism implemented by hardware. In hardware reset, when the system needs to be reset, the entire hardware system will be forcibly reset to return to the initial state. Hardware reset usually requires additional hardware circuits to implement, such as reset gates, reset pins, etc. A reset signal is generated by the hardware, which is transmitted to the entire system to reset all hardware states to the initial state. Although hardware reset requires additional hardware circuits, it has the advantages of more thorough reset, better reliability and stability because it is performed by hardware. The main purpose of using software reset in this embodiment is to save hardware resources and achieve fast reset.
[0046] As an optional embodiment, performing a reset operation on each DSP core includes: first performing a software reset on each DSP core. If the reset of each DSP core is successful, the reset is completed; otherwise, performing a hardware reset on each DSP core.
[0047] This embodiment provides an improved solution for resetting each DSP core. As mentioned above, software reset and hardware reset each have their own advantages and disadvantages. This embodiment adopts a solution combining software reset and hardware reset, which can make up for each other's shortcomings and achieve a better reset effect. This embodiment first performs a software reset on each DSP core. If the reset of each DSP core is successful, then a quick reset of the system can be achieved. Since the reliability of software reset is not as high as that of hardware reset, it is easy to fail to reset successfully, and the computer cannot jump out of the dead loop state. In this embodiment, once it is found that the software reset of a DSP core fails, the reset mode can be switched to hardware reset until the reset of each DSP core is successful.
[0048] As an optional embodiment, the method for performing hardware reset on each DSP core includes: outputting a high level pulse signal or a low level pulse signal to the reset pin of each DSP core chip.
[0049] This embodiment provides a technical solution for implementing hardware reset. DSP core chips are generally provided with reset pins, such as RST, RESET, etc., and hardware reset can be implemented by adding a high-level pulse signal or a low-level pulse signal with a certain width (not less than a set threshold) to the reset pin. Figure 3 It is a schematic diagram of a specific low-level reset circuit. Resistor R and capacitor C can realize automatic reset when power is turned on: when power is just turned on, since the voltage on capacitor C is 0, the power supply VCC slowly charges capacitor C through resistor R, which is equivalent to generating a low-level pulse signal on the reset pin Reset to reset the CPU. A button switch is connected in parallel with capacitor C, and manual reset can be achieved by pressing the button switch. In this embodiment, a low-level signal is output to Reset from the IO port of the DSP core to achieve reset. In order to improve the reliability of reset, an electronic switch can be connected in parallel at both ends of capacitor C, and the IO port outputs a high-level signal to the control end of the electronic switch. The electronic switch is turned on to discharge capacitor C quickly, and a reliable low-level reset signal is generated on Reset.
[0050] As an optional embodiment, the method for performing a hardware reset on each DSP core includes: disconnecting the DC power supply of the multi-core DSP main control system for a period of time, and then powering it on to restart.
[0051] This embodiment provides another technical solution for hardware reset. The hardware reset solution of this embodiment is similar to the power-off restart of a computer, which first turns off the power of the system for a period of time, and then powers it on to restart. This is the most reliable reset solution, but the disadvantage is that the reset execution time is long. When the general hardware reset solution (such as the previous embodiment) cannot make the system jump out of the dead state, the power-off and then power-on restart solution of this embodiment can be used.
[0052] As an optional embodiment, the multi-core DSP is TMS320C6674, which has 4 DSP cores in total.
[0053] This embodiment provides a technical solution for multi-core DSP. The multi-core DSP of this embodiment adopts a quad-core TMS320C6674. TMS320C6674 is a high-performance digital signal processor that supports 64-bit DDR3 interface, provides 8GB addressable memory space, and 16-bit EMIF interface, and supports asynchronous SRAM, NAND and NOR flash memory. Other interfaces include two telecommunication serial ports (TSIP), UART interface, I 2 C interface, SPI interface, sixteen 64-bit timers and three on-chip PLLs to meet various application requirements.
[0054] Figure 5 The present invention is a schematic diagram of a reset device for a multi-core DSP master control system according to an embodiment of the present invention, wherein the device comprises:
[0055] A watchdog arrangement module 11 is used to configure an independent watchdog implemented by FPGA software for each DSP core;
[0056] The watchdog configuration module 12 is used for each DSP core to initialize and configure its own watchdog when powered on; after normal operation, the watchdog is fed regularly in the main loop program;
[0057] The reset execution module 13 is used to trigger the dog barking function when a DSP core program runs abnormally or crashes because the dog feeding operation cannot be performed. The multi-core DSP main control system is restored to normal by resetting each DSP core.
[0058] The device of this embodiment can be used to perform Figure 1 The technical solution of the method embodiment shown has similar implementation principles and technical effects, which will not be repeated here.
[0059] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A reset method for a multi-core DSP master control system, It is characterized in that The following steps are involved: Configure an independent watchdog implemented by FPGA software for each DSP core; When powered on, each DSP core initializes and configures its own watchdog. After normal operation, the watchdog is fed regularly in the main loop program. When a DSP core program runs abnormally or crashes, the dog barking function is triggered because the dog feeding operation cannot be performed. By resetting each DSP core, the multi-core DSP main control system returns to normal.
2. The reset method of the multi-core DSP master control system according to claim 1, It is characterized in that After power-on, the FPGA defaults to each watchdog being in the barking enable off state; when the DSP software is loaded into the memory and started running, each DSP core performs the following initialization configuration on its own watchdog: setting the barking time and turning on the barking enable.
3. The reset method of the multi-core DSP master control system according to claim 2, It is characterized in that By writing 0x07D0 to the barking time parameter register, the barking time is set to 2000ms; by writing 0xAA to the watchdog enable register, the barking function is turned on, and by writing 0xFF, the barking function is turned off; by writing 0xAA to the dog feeding register, the dog feeding operation is implemented.
4. The reset method of the multi-core DSP master control system according to claim 1, It is characterized in that After the barking function is triggered, the FPGA puts each watchdog in the barking enable off state, and then resets each DSP core.
5. The reset method of the multi-core DSP master control system according to claim 1, It is characterized in that The resetting operation for each DSP core includes: performing a software reset for each DSP core.
6. The reset method of the multi-core DSP master control system according to claim 1, It is characterized in that The reset operation for each DSP core includes: firstly performing a software reset on each DSP core. If the reset of each DSP core is successful, the reset is completed; otherwise, performing a hardware reset on each DSP core.
7. The reset method of the multi-core DSP master control system according to claim 6, It is characterized in that The method for hardware resetting each DSP core includes: outputting a high level pulse signal or a low level pulse signal to the reset pin of each DSP core chip.
8. The reset method of the multi-core DSP master control system according to claim 6, It is characterized in that The method for performing hardware reset on each DSP core includes: disconnecting the DC power supply of the multi-core DSP main control system for a period of time, and then powering on and restarting.
9. The reset method of the multi-core DSP master control system according to claim 1, It is characterized in that The multi-core DSP is TMS320C6674, which has 4 DSP cores in total.
10. A reset device for a multi-core DSP master control system, It is characterized in that include: Watchdog deployment module, used to configure an independent watchdog implemented by FPGA software for each DSP core; The watchdog configuration module is used for each DSP core to initialize and configure its own watchdog when powered on; after normal operation, the watchdog is fed regularly in the main loop program; The reset execution module is used to trigger the dog barking function when a DSP core program runs abnormally or crashes because the dog feeding operation cannot be performed. The multi-core DSP main control system returns to normal by resetting each DSP core.