Multi-core processing FTL physical address allocation method and storage device

Abstract

The invention relates to a multi-core processing FTL physical address allocation method and storage equipment, and belongs to the technical field of storage. The method comprises the following steps: in response to a write command, determining the number of sub-blocks occupied by to-be-written data corresponding to the write command; wherein each physical block in the memory is divided into a plurality of sub-blocks according to a preset unit data volume, and the sub-blocks have physical address numbers; obtaining a target physical address number currently stored in the public memory area as a start through an atomic operation mode, and updating the target physical address number based on the number of the sub-blocks; and distributing a corresponding physical address to the to-be-written data according to the obtained target physical address number. By adopting the method, the problem of starvation of a certain core can be avoided.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a multi-core processing FTL physical address allocation method and storage device. Background Art

[0002] SSD (Solid State Disk) controllers usually contain multiple cores. When processing a large number of I / O (Input / Output) commands, the SSD controller can use multiple cores for concurrent processing, thereby achieving high processing power for the SSD as a whole. When the SSD controller processes write commands concurrently through multiple cores, the data streams of multiple cores are aggregated and written into the SSD block, so the SSD controller needs to allocate FTL (Flash Translation Layer) physical addresses for write commands.

[0003] The existing physical address allocation method is that multiple cores compete for a lock. The core that grabs the lock occupies the physical address by itself and releases the lock after completing the write command, while the core that fails to grab the lock needs to wait. The disadvantage of this allocation method is that there is a possibility that a core cannot grab the lock for a long time, which causes the write command executed by the core to take a long time to complete, affecting the QoS (Quality of Service) of the write command. Therefore, a method for allocating physical addresses in a block is urgently needed. Summary of the invention

[0004] Based on this, it is necessary to provide a multi-core processing FTL physical address allocation method and storage device to address the above technical problems.

[0005] In a first aspect, a multi-core processing FTL physical address allocation method is provided, the method comprising:

[0006] In response to a write command, determining the number of sub-blocks occupied by the to-be-written data corresponding to the write command; wherein each physical block in the memory is divided into a plurality of sub-blocks according to a preset unit data amount, and the sub-blocks have physical address numbers;

[0007] Obtaining, by atomic operation, a target physical address number currently stored in the public memory area as a start, and updating the target physical address number based on the number of sub-blocks;

[0008] According to the acquired target physical address number, a corresponding physical address is allocated to the data to be written.

[0009] As an optional implementation, the method further includes:

[0010] For each physical block in the memory, dividing the physical block into a plurality of sub-blocks according to the preset unit data amount;

[0011] The sub-blocks are traversed in the order of addresses of the sub-blocks in the physical block, and a physical address number is assigned to each sub-block.

[0012] As an optional implementation manner, allocating a physical address number to each of the sub-blocks includes:

[0013] Determining whether the sub-block is a bad sub-block;

[0014] If the sub-block is a non-bad sub-block, the maximum allocated physical address number in the physical block to which the sub-block belongs is increased by 1 to obtain the physical address number of the sub-block;

[0015] If the sub-block is a bad sub-block, the sub-block is skipped, and the non-bad sub-blocks before and after the bad sub-block are numbered consecutively.

[0016] As an optional implementation manner, allocating a corresponding physical address for the data to be written according to the acquired target physical address number includes:

[0017] Obtaining bad sub-block distribution information and configuration information of a physical block to be written, wherein the physical block to be written is a physical block in the memory where data is currently to be written;

[0018] Based on the bad sub-block distribution information, the configuration information, the acquired target physical address number and the unit data amount, a corresponding starting physical address is allocated to the data to be written.

[0019] As an optional implementation, the configuration information includes one or more of a plane size, a page size, and a number of planes.

[0020] As an optional implementation, the starting physical address number in the physical address number range corresponding to the write command executed by any core is the acquired target physical address number, and the ending physical address number is the sum of the acquired target physical address number and the number of sub-blocks.

[0021] As an optional implementation, when two cores execute a write command, the steps include:

[0022] If, in response to the first write command, the first core in the multi-core obtains a start physical address number N1 allocated for the first write command, and an end physical address number N2=N1+D1-1, where D1 is the number of sub-blocks occupied by the first write command;

[0023] If in response to the second write command, the second core in the multi-core obtains a start physical address number M1 allocated for the second write command, and an end physical address number M2=M1+D2-1, where D2 is the number of sub-blocks occupied by the second write command;

[0024] The relationship between the starting physical address number and the ending physical address number obtained by the first core and the second core is:

[0025] M1≥N2+1; or N1≥M2+1.

[0026] As an optional implementation manner, the determining the number of sub-blocks occupied by the to-be-written data corresponding to the write command includes:

[0027] Determine a target data amount of data to be written corresponding to the write command;

[0028] The number of sub-blocks occupied by the data to be written is determined according to the target data amount and the preset unit data amount.

[0029] As an optional implementation manner, updating the target physical address number based on the number of sub-blocks includes:

[0030] Determine the sum of the target physical address number and the number of sub-blocks;

[0031] The target physical address number currently stored in the public memory area is updated to the sum value.

[0032] In a second aspect, a storage device is provided, comprising: a memory and a processor, wherein the processor comprises multiple cores, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the multi-core processing FTL physical address allocation method described in any one of the first aspects is implemented.

[0033] The present application provides a multi-core processing FTL physical address allocation method and storage device. The technical solution provided by the embodiment of the present application brings at least the following beneficial effects: any core in the SSD master control, in response to a write command, determines the number of sub-blocks occupied by the data to be written corresponding to the write command. Wherein, each physical block in the memory is divided into multiple sub-blocks according to a preset unit data volume, and the sub-block has a physical address number. Then, the core obtains the target physical address number currently stored in the public memory area as the start through an atomic operation, updates the target physical address number based on the number of sub-blocks, and allocates the corresponding physical address for the data to be written according to the obtained target physical address number. In this way, (1) in the scenario where the SSD master control includes multiple cores, each core is guaranteed at the bottom layer through the atomicity of the atomic operation mode, even if each core operates the physical address number stored in the public memory area at the same time, it is still executed in a serial order, ensuring that there will be no conflict with the physical address allocation being performed by other cores. Therefore, in a multi-core scenario, each core does not need to seize a lock or wait for a token, avoiding the starvation problem of a certain core. (2) The atomic operation mode is only a synchronization behavior, that is, there is no process that needs to be tried again after the operation fails, and the atomic operation mode takes a very short time. This ensures that a core will not wait for a long time due to a lock grabbing failure, greatly reducing the time consumption caused by multi-core competition and breaking through the performance bottleneck.

[0034] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A schematic diagram of physical address allocation provided in an embodiment of the present application;

[0037] Figure 2 A flowchart of a multi-core processing FTL physical address allocation method provided in an embodiment of the present application;

[0038] Figure 3A A schematic diagram of sub-block division provided in an embodiment of the present application;

[0039] Figure 3B A schematic diagram of sub-block division provided in an embodiment of the present application;

[0040] Figure 3C A schematic diagram of physical address number allocation provided in an embodiment of the present application;

[0041] Figure 4 A schematic diagram of the structure of a multi-core processing FTL physical address allocation device provided in an embodiment of the present application;

[0042] Figure 5 A schematic diagram of the structure of a storage device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] The multi-core processing FTL physical address allocation method provided in the relevant embodiments of the present application can be applied to the SSD master control, and specifically can be applied to the cores in the SSD master control. The SSD master control usually includes multiple cores. When processing a large number of I / O commands, the SSD master control can use multiple cores for concurrent processing, thereby achieving high processing capabilities of the SSD as a whole. Figure 1 As shown in the figure, when the SSD master controls write commands through multiple cores concurrently, the data streams of multiple cores are written to the blocks of the SSD at the same time. Therefore, the SSD master controls need to allocate physical addresses to the blocks. Currently, the commonly used physical address allocation methods for multiple cores include the following three allocation methods:

[0045] Allocation method 1: A core uniformly allocates physical addresses for write commands of all cores, and then distributes the write commands with allocated physical addresses to other cores. The disadvantage of this allocation method is that all write commands flow to the core that allocates the physical address, and the core that allocates the physical address can easily become a performance bottleneck due to insufficient processing power.

[0046] Allocation method 2: When allocating physical addresses, multiple cores compete for a lock. The core that grabs the lock occupies the physical address by itself and releases the lock after completing the write command, while the core that cannot grab the lock needs to wait. The disadvantage of this allocation method is that there is a possibility that a core cannot grab the lock for a long time, which causes the write command executed by the core to take a long time to complete, affecting the QoS of the write command. At the same time, frequent lock grabbing will also occupy a lot of core overhead, affecting overall performance.

[0047] Allocation method three: A variable is maintained in the shared memory as a token. The token indicates the core that has ownership of the physical address allocation. Only the corresponding core has the right to use the shared memory. If the corresponding core has no use requirements, the token can be updated according to certain rules to point to other cores. The disadvantage of this allocation method is that although it solves the problem of long-term starvation due to failure to grab the lock, the core still has to wait for the token for a long time, and the token update will also occupy a lot of core overhead, resulting in poor overall performance.

[0048] In the current development of high-performance SSDs, it is necessary to ensure both the I / O command processing bandwidth and the QoS of I / O commands. High processing bandwidth depends on efficient command processing capabilities, and the current core performance has become one of the bottlenecks for achieving high processing bandwidth. Therefore, the above allocation methods 1, 2, and 3 will all lead to additional core overhead, affecting the I / O command processing bandwidth. At the same time, both allocation methods 2 and 3 have different degrees of starvation problems for individual cores, affecting the QoS of I / O commands.

[0049] The following will be combined with specific implementation methods to describe in detail a multi-core processing FTL physical address allocation method provided in an embodiment of the present application. The method can be applied to the control component (i.e., the main control) of the SSD. Figure 2 A flowchart of a multi-core processing FTL physical address allocation method provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the specific steps are as follows:

[0050] Step 201, in response to a write command, determine the number of sub-blocks occupied by the to-be-written data corresponding to the write command. Each physical block in the memory is divided into a plurality of sub-blocks according to a preset unit data volume, and the sub-blocks have physical address numbers.

[0051] In implementation, each physical block in the memory of the SSD is divided into multiple sub-blocks according to the unit data volume, and each sub-block has a unique physical address number. The embodiment of the present application will later introduce the process of dividing the physical block into multiple sub-blocks and assigning physical address numbers to each sub-block in detail, which will not be repeated here. After receiving the write command, the core in the SSD master control can respond to the write command and determine the number of sub-blocks occupied by the data to be written corresponding to the write command.

[0052] As an optional implementation manner, the process of the core in the SSD master controller determining the number of sub-blocks occupied by the to-be-written data corresponding to the write command is as follows:

[0053] Step 1: determine the target data volume of the data to be written corresponding to the write command.

[0054] In implementation, after receiving a write command, the core in the SSD master control can respond to the write command and determine the target data volume of the data to be written corresponding to the write command. For example, in a multi-core scenario, the target data volume of the data to be written in the write command 0 executed by core 0 is 16K, and the target data volume of the data to be written in the write command 1 executed by core 1 is 32K.

[0055] Step 2: Determine the number of sub-blocks occupied by the data to be written according to the target data volume and the preset unit data volume.

[0056] In implementation, after the core in the SSD master determines the target data volume of the data to be written corresponding to the write command, the quotient of the target data volume and the preset unit data volume of the sub-block can be further determined as the number of sub-blocks occupied by the data to be written. For example, in a multi-core scenario, the unit data volume is 4K, and the target data volume of the data to be written in the write command 0 executed by core 0 is 16K, then the number of sub-blocks occupied by the data to be written is 16K / 4K=4; the target data volume of the data to be written in the write command 1 executed by core 1 is 32K, then the number of sub-blocks occupied by the data to be written is 32K / 4K=8.

[0057] As an optional implementation, the SSD master controller divides the physical block into multiple sub-blocks and allocates a physical address number to each sub-block as follows:

[0058] Step 1: for each physical block in the memory, divide the physical block into a plurality of sub-blocks according to a preset unit data amount.

[0059] In practice, each Die (chip) is an independent storage unit. A Die is composed of multiple Planes (planes), and multiple Planes share a set of operation buses. Multiple Planes can form a unit to operate concurrently, forming a Multi-plane. A Plane is composed of several Blocks (blocks). Figure 3A and 3B As shown in FIG. 1 , a Plane is composed of 4 Blocks. For each physical block in the memory, the SSD master controller can divide the physical block into multiple sub-blocks according to the preset unit data volume. Figure 3A As shown, the SSD master controller divides the physical block into several sub-blocks, and the data amount corresponding to each sub-block is the unit data amount, such as 4K.

[0060] Step 2: traverse each sub-block in the order of its address in the physical block and assign a physical address number to each sub-block.

[0061] In practice, after the SSD master controller divides the physical block into multiple sub-blocks, it can traverse each sub-block according to the address order of the sub-blocks in the physical block (address order from small to large), and assign a physical address number to each sub-block. Figure 3A As shown, each sub-block is assigned a physical address number starting from sub-block 0 and the physical address numbers are assigned in sequence according to the address order.

[0062] As an optional implementation, in order to avoid a sub-block being a bad sub-block and causing subsequent failure of writing data to be written, the SSD master controller allocates a physical address number to each sub-block as follows:

[0063] Step 1: determine whether the sub-block is a bad sub-block.

[0064] In implementation, when the SSD master controller allocates a physical address number to a sub-block, it may first determine whether the sub-block is a bad sub-block.

[0065] Step 2: If the sub-block is not a bad sub-block, add 1 to the maximum allocated physical address number in the physical block to which the sub-block belongs, to obtain the physical address number of the sub-block.

[0066] In implementation, if the sub-block is not a bad sub-block, the SSD master controller can add 1 to the maximum physical address number that has been allocated in the physical block to which the sub-block belongs, to obtain the physical address number of the sub-block, thereby preventing the physical address number allocated to the bad sub-block from affecting the subsequent writing of data to be written. At the same time, the continuity of the physical address number is guaranteed. For example, Figure 3A and Figure 3B It is known that in Figure 3A In the example, the physical address number of the third sub-block in the first row is sub-block 2, and in Figure 3B In , since a bad sub-block is skipped, the physical address number of the third sub-block in the first row is sub-block 1, and the physical address numbers starting from sub-block 0 remain continuous; similarly, in Figure 3A In the example, the physical address number of the third sub-block in the second row is sub-block 66, and in Figure 3B In the example, since two bad sub-blocks (the second sub-block in the first row and the second row) are skipped, the physical address number of the third sub-block in the second row is sub-block 64, and the physical address numbers starting from sub-block 0 remain continuous.

[0067] Step 3: If the sub-block is a bad sub-block, the sub-block is skipped, and the non-bad sub-blocks before and after the bad sub-block are numbered consecutively.

[0068] In implementation, if the sub-block is a bad sub-block, the sub-block is skipped and no physical address number is assigned, and the non-bad sub-blocks before and after the bad sub-block are numbered consecutively. Figure 3B As shown, the second sub-block in the first row and the second sub-block in the second row are both bad sub-blocks, and no physical address number is assigned to either of them.

[0069] Step 202, through an atomic operation, obtain the target physical address number currently stored in the public memory area as a start, and update the target physical address number based on the number of sub-blocks.

[0070] In implementation, the count of physical address numbers is stored in the public memory area within the SSD master chip, and each core can access the public memory area in a multi-core scenario. The specific storage location will be slightly different in different chip architectures. Usually the public memory area refers to SRAM (Static Random-Access Memory). SRAM is a high-speed, low-power memory used to store temporary data and program code. It has fast read and write speeds and high stability, but relatively small capacity. The count of physical address numbers stored in the public memory area is used to represent the minimum physical address number of the sub-block that can be occupied.

[0071] When multiple cores operate on the count of the physical address numbers stored in the common memory area, the atomic operation function sync_fetch_and_add can be used. For example, the atomic operation function provided in gcc 4.1.2 is type_sync_fetch_and_add(type*ptr, type value). Among them, type*ptr represents the operation address pointer, type value represents the increment value, and the return value is the old value before the increment. In the present application, the return value is the target physical address number currently stored in the common memory area, the increment value is the number of sub-blocks, the return value ~ (return value + increment value - 1) is the range of the physical address numbers assigned by the write command, and the return value + increment value is the updated target physical address number stored in the common memory area. The atomic operation method of the embodiment of the present application is introduced by taking the atomic operation function sync_fetch_and_add as an example. The atomic operation method can also adopt other types of atomic operation functions (in the C11 standard library<stdatomic.h> , or the built-in functions __sync_ series and __atomic_ series provided by the GCC compiler) are implemented, and the embodiments of the present application are not limited.

[0072] For example, taking a single core executing a write command as an example, the target data size of the data to be written in the write command 0 executed by core 0 is 16K, and the number of sub-blocks occupied by the data to be written is 4. At this time, core 0 calls the atomic operation function sync_fetch_and_add(&pbaValue, 4) to implement the allocation of physical address numbers. If the return value of the atomic operation function is m, it means that the 4 consecutive physical address numbers m to m+3 are the physical address numbers allocated by core 0 for write command 0. Among them, the variable pba Value represents the address pointer of the physical address number stored in the public memory area.

[0073] As an optional implementation, the starting physical address number in the physical address number range corresponding to the write command executed by any core is the obtained target physical address number, and the ending physical address number is the sum of the obtained target physical address number and the number of sub-blocks.

[0074] As an optional implementation, when two cores execute a write command, the steps include:

[0075] If in response to the first write command, the first core in the multi-core obtains a starting physical address number assigned to the first write command of N1, and an ending physical address number of N2=N1+D1-1, where D1 is the number of sub-blocks occupied by the first write command; if in response to the second write command, the second core in the multi-core obtains a starting physical address number assigned to the second write command of M1, and an ending physical address number of M2=M1+D2-1, where D2 is the number of sub-blocks occupied by the second write command;

[0076] The relationship between the start physical address number and the end physical address number obtained for the first core and the second core is: M1≥N2+1; or N1≥M2+1.

[0077] In implementation, for the case where multiple cores execute write commands, the first core in the multiple cores responds to the first write command, and the starting physical address number assigned to the first write command is obtained as N1, and the ending physical address number N2=N1+D1-1, where D1 is the number of sub-blocks occupied by the first write command. The second core in the multiple cores responds to the second write command, and the starting physical address number assigned to the second write command is obtained as M1, and the ending physical address number M2=M1+D2-1, where D2 is the number of sub-blocks occupied by the second write command. The relationship between the starting physical address number and the ending physical address number obtained for the first core and the second core is: M1≥N2+1; or N1≥M2+1. If the first core and the second core execute write commands adjacently, then M1=N2+1, or N1=M2+1. If the first core and the second core execute write commands non-adjacently, then M1>N2+1, or N1>M2+1. Among them, N2+1=N1+D1 is the target physical address number after the first check is performed to update the target physical address number stored in the public memory area; M2+1=M1+D2 is the target physical address number after the second check is performed to update the target physical address number stored in the public memory area.

[0078] For example, taking the execution of a write command by multiple cores as an example, the target data volume of the data to be written in the write command 0 executed by core 0 is 16K, and the number of sub-blocks occupied by the data to be written is 4. At this time, core 0 calls the atomic operation function sync_fetch_and_add(&pbaValue, 4) to implement the allocation of physical address numbers. The target data volume of the data to be written in the write command 1 executed by core 1 is 32K, and the number of sub-blocks occupied by the data to be written is 8. At this time, core 1 calls the atomic operation function sync_fetch_and_add(&pbaValue, 8) to implement the allocation of physical address numbers. Since the atomic operation function is atomic, the return values ​​obtained by the two cores will not overlap. The return value obtained by core 0 is m, indicating that the 4 consecutive physical address numbers from m to m+3 are the physical address numbers allocated by core 0 for write command 0; the return value obtained by core 1 is n, indicating that the 8 consecutive physical address numbers from n to n+7 are the physical address numbers allocated by core 1 for write command 1. If only these two cores are currently executing write commands, for example, at this time n = m + 4 (core 0 executes the atomic operation function before core 1) or m = n + 8 (core 1 executes the atomic operation function before core 0), the physical address numbers assigned to the two cores will not overlap. Among them, the variable pba Value represents the address pointer of the physical address number stored in the public memory area. The scenario of more cores is similar to the scenario of the above two cores, and will not be repeated here.

[0079] In the scenario where the SSD master controller contains multiple cores, each core does not know (nor does it need to know) whether other cores have operations to process. Each core uses the atomicity of the atomic operation function to ensure at the bottom layer that even if each core operates the physical address number stored in the public memory area at the same time, it is still executed in a serial order to ensure that there will be no conflict with the physical address allocation being performed by other cores. Therefore, in the multi-core scenario, each core does not need to worry about the timing issue when calling the atomic operation function, and the processing is more efficient.

[0080] As an optional implementation, the core in the SSD master controller updates the target physical address number based on the number of sub-blocks by: determining the sum of the target physical address number and the number of sub-blocks; and updating the target physical address number currently stored in the public memory area to the sum.

[0081] In implementation, the core in the SSD master updates the target physical address number currently stored in the public memory area through the atomic operation function sync_fetch_and_add. Specifically, after the atomic operation function obtains the target physical address number currently stored in the public memory area, it can further determine the sum of the target physical address number and the number of sub-blocks, and then update the target physical address number currently stored in the public memory area to the sum. For example, if the target physical address number currently stored in the public memory area is 2 and the number of sub-blocks is 4, then the updated target physical address number stored in the public memory area is 2+4=6.

[0082] Step 203: assign a corresponding physical address to the data to be written according to the acquired target physical address number.

[0083] In implementation, after the core in the SSD master controller obtains the target physical address number through the atomic operation function, it can further convert the target physical address number into a real physical address based on the target physical address number, and can assign a corresponding real physical address to the write data, thereby executing a write command based on the real physical address.

[0084] As an optional implementation, the core in the SSD master controller allocates the corresponding physical address to the data to be written based on the acquired target physical address number as follows:

[0085] Step 1: Obtain bad sub-block distribution information and configuration information of a physical block to be written, wherein the physical block to be written is a physical block in the memory where data is currently to be written.

[0086] In implementation, when the core in the SSD master determines the real physical address corresponding to the write command, it needs to obtain the bad sub-block distribution information and configuration information of the physical block to be written. The physical block to be written is the physical block corresponding to the current data to be written in the memory, and the configuration information includes one or more of the plane size, page size, and number of planes.

[0087] Step 2: Based on the bad sub-block distribution information, configuration information, the acquired target physical address number and unit data volume, a corresponding starting physical address is allocated to the data to be written.

[0088] In implementation, the core in the SSD master controller allocates the corresponding starting physical address for the data to be written based on the bad sub-block distribution information, configuration information, the obtained target physical address number and the unit data volume. For example, the target data volume of the data to be written in the write command 0 executed by core 0 is 16K. The return value of the atomic operation function is 2, indicating that the allocated starting physical address number is 2 and the number of sub-blocks occupied by the data to be written is 4. Figure 3CAs shown, sub-blocks 2 to 5 are the allocated physical addresses. Since there are multiple bad sub-blocks between sub-block 3 and sub-block 4, the core in the SSD master control can determine the starting physical address corresponding to the data to be written based on the bad sub-block distribution information, configuration information, the obtained target physical address number and the unit data amount.

[0089] For example, for a write command (write cmd) with a data volume of 16K, the core obtains a return value of 2 through the atomic operation function sync_fetch_and_add(&pbaValue, 4), indicating that the allocated starting physical address number is 2 and the number of occupied sub-blocks is 4. Wherein, &pbaValue represents the pointer address of the physical address number count stored in the public memory area. Figure 3C As shown in the figure, the physical address numbers corresponding to the four 4K sub-blocks of sub-block 2, sub-block 3, sub-block 4 and sub-block 5 in the physical block are the assigned physical address numbers. At this time, the core needs to convert the assigned physical address number into the actual physical address. We use logicPos to represent the assigned physical address number ( Figure 3C The sub-block 0, sub-block 1, sub-block 2, etc. marked in the table are only physical address numbers and are used as placeholders, not actual physical addresses). The actual physical address (that is, the physical address actually used to store the data to be written in the chip) is represented by phyPos. At the same time, the core pre-stores the distribution of bad planes in the current block, as well as basic block configuration information such as the plane page size and the number of planes in the current block. Based on the above configuration information, the core can calculate that the physical address corresponding to logicPos=2 is the third 4K unit in plane 0 of page 0, and use this as the starting point to load the data to be written. In the process of loading the data to be written later, if a bad plane is encountered, it is necessary to jump and skip the bad sub-block, that is, Figure 3C The physical address jump process of logicPos3→logicPos4.

[0090] The embodiment of the present application provides a multi-core processing FTL physical address allocation method, in which the core in the SSD master responds to a write command and determines the number of sub-blocks occupied by the data to be written corresponding to the write command. Each block in the memory is divided into multiple sub-blocks according to a preset unit data volume, and the sub-block has a physical address number. Then, the core in the SSD master obtains the target physical address number currently stored in the public memory area through an atomic operation, and updates the target physical address number based on the number of sub-blocks. After that, the core in the SSD master determines the physical address corresponding to the data to be written based on the obtained target physical address number. In this way, (1) in the scenario where the SSD master contains multiple cores, each core is guaranteed at the bottom layer through the atomicity of the atomic operation method, even if each core operates the physical address number stored in the public memory area at the same time, it is still executed in a serial order, ensuring that there will be no conflict with the physical address allocation being performed by other cores. Therefore, in the multi-core scenario, each core does not need to seize the lock or wait for the token, avoiding the starvation problem of a certain core. (2) The atomic operation mode is only a synchronous behavior, that is, there is no process that needs to be tried again after the operation fails, and the atomic operation mode takes a very short time, which ensures that a core will not wait for a long time due to a lock grabbing failure, greatly reducing the time consumption caused by multi-core competition, and can break through the performance bottleneck of multi-core. The more cores there are, the more obvious this advantage is. Because in the prior art, the more cores there are for lock grabbing or token operations, the longer the waiting time. From the perspective of a single core, it often takes many attempts to succeed. If it fails and is ready to exit, and then try to inquire again after a while, the processing is not only inefficient, but also causes individual cores to be unable to allocate physical addresses.

[0091] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0092] It can be understood that the same / similar parts between the various embodiments of the above method in this specification can refer to each other, and each embodiment focuses on the differences from other embodiments. For related points, please refer to the description of other method embodiments.

[0093] The present application also provides a multi-core processing FTL physical address allocation device, such as Figure 4 As shown, the device comprises:

[0094] A first determination module 410 is used to determine, in response to a write command, the number of sub-blocks occupied by the to-be-written data corresponding to the write command; wherein each physical block in the memory is divided into a plurality of sub-blocks according to a preset unit data amount, and the sub-blocks have physical address numbers;

[0095] The operation module 420 is used to obtain the target physical address number currently stored in the public memory area as a start through an atomic operation, and update the target physical address number based on the number of sub-blocks;

[0096] The second determining module 430 is used to allocate a corresponding physical address to the data to be written according to the acquired target physical address number.

[0097] As an optional implementation, the device further includes:

[0098] A partitioning module, for partitioning each physical block in the memory into a plurality of sub-blocks according to a preset unit data amount;

[0099] The allocation module is used to traverse each sub-block according to the address sequence of the sub-block in the physical block and allocate a physical address number to each sub-block.

[0100] As an optional implementation, the allocation module is specifically used to:

[0101] Determine whether the sub-block is a bad sub-block;

[0102] If the sub-block is not a bad sub-block, then the maximum allocated physical address number in the physical block to which the sub-block belongs is increased by 1 to obtain the physical address number of the sub-block;

[0103] If the sub-block is a bad sub-block, the sub-block is skipped, and the non-bad sub-blocks before and after the bad sub-block are numbered consecutively.

[0104] As an optional implementation, the starting physical address number in the physical address number range corresponding to the write command executed by any core is the obtained target physical address number, and the ending physical address number is the sum of the obtained target physical address number and the number of sub-blocks.

[0105] As an optional implementation, when two cores execute a write command, the steps include:

[0106] If, in response to the first write command, the first core in the multi-core obtains a start physical address number N1 allocated for the first write command, and an end physical address number N2=N1+D1-1, where D1 is the number of sub-blocks occupied by the first write command;

[0107] If in response to the second write command, the second core in the multi-core obtains a start physical address number M1 allocated for the second write command, and an end physical address number M2=M1+D2-1, where D2 is the number of sub-blocks occupied by the second write command;

[0108] The relationship between the starting physical address number and the ending physical address number obtained for the first core and the second core is:

[0109] M1≥N2+1; or N1≥M2+1.

[0110] As an optional implementation manner, the second determining module 430 is specifically configured to:

[0111] Obtaining bad sub-block distribution information and configuration information of a physical block to be written, where the physical block to be written is a physical block in the memory where data is currently to be written;

[0112] Based on the bad sub-block distribution information, configuration information, the acquired target physical address number and the unit data amount, a corresponding starting physical address is allocated to the data to be written.

[0113] As an optional implementation, the configuration information includes one or more of a plane size, a page size, and a number of planes.

[0114] As an optional implementation manner, the first determining module 410 is specifically configured to:

[0115] Determine a target data amount of data to be written corresponding to a write command;

[0116] The number of sub-blocks occupied by the data to be written is determined according to the target data volume and the preset unit data volume.

[0117] As an optional implementation, the operation module is specifically used to:

[0118] Determine the sum of the target physical address number and the number of sub-blocks;

[0119] Update the target physical address number currently stored in the common memory area to the sum value.

[0120] For the specific definition of the multi-core processing FTL physical address allocation device, please refer to the definition of the multi-core processing FTL physical address allocation method above, which will not be repeated here. Each module in the above-mentioned multi-core processing FTL physical address allocation device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0121] The present disclosure also provides a storage device, which includes a processor and a memory, wherein the processor includes multiple cores, wherein the memory stores a computer program, and when the computer program is executed by the processor, the method of any of the above embodiments can be implemented, and the execution method and beneficial effects are similar, which will not be repeated here.

[0122] Figure 5 is a schematic diagram of a storage device provided by an embodiment of the present disclosure, such as Figure 5 As shown, the storage device may include a processor 510 and a memory 520, wherein the memory 520 stores a computer program, and when the computer program is executed by the processor 510, the method provided by any of the above embodiments can be implemented, and its execution method and beneficial effects are similar and will not be repeated here.

[0123] Of course, to simplify, Figure 5 Only some of the components of the storage device related to the present invention are shown, and components such as a bus, an input / output interface, an input device, and an output device are omitted. In addition, the storage device may also include any other appropriate components according to specific application conditions.

[0124] An embodiment of the present disclosure provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method of any of the above embodiments can be implemented. The execution method and beneficial effects are similar and will not be repeated here.

[0125] The above-mentioned computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0126] The computer program may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer device, partially on the user's device, as a separate software package, partially on the user's computer device and partially on a remote computer device, or entirely on a remote computer device or server.

[0127] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0128] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-core processing FTL physical address allocation method, characterized in that: The method comprises: In response to a write command, determining the number of sub-blocks occupied by the to-be-written data corresponding to the write command; wherein each physical block in the memory is divided into a plurality of sub-blocks according to a preset unit data amount, and the sub-blocks have physical address numbers; Obtaining, by atomic operation, a target physical address number currently stored in the public memory area as a start, and updating the target physical address number based on the number of sub-blocks; According to the acquired target physical address number, a corresponding physical address is allocated to the data to be written.

2. The method according to claim 1, characterized in that The method further comprises: For each physical block in the memory, dividing the physical block into a plurality of sub-blocks according to the preset unit data amount; The sub-blocks are traversed in the order of addresses of the sub-blocks in the physical block, and a physical address number is assigned to each sub-block.

3. The method according to claim 2, characterized in that The allocating a physical address number to each of the sub-blocks comprises: Determining whether the sub-block is a bad sub-block; If the sub-block is a non-bad sub-block, the maximum allocated physical address number in the physical block to which the sub-block belongs is increased by 1 to obtain the physical address number of the sub-block; If the sub-block is a bad sub-block, the sub-block is skipped, and the non-bad sub-blocks before and after the bad sub-block are numbered consecutively.

4. The method according to claim 1, characterized in that The step of allocating a corresponding physical address to the data to be written according to the acquired target physical address number includes: Obtaining bad sub-block distribution information and configuration information of a physical block to be written, wherein the physical block to be written is a physical block in the memory where data is currently to be written; Based on the bad sub-block distribution information, the configuration information, the acquired target physical address number and the unit data amount, a corresponding starting physical address is allocated to the data to be written.

5. The method according to claim 4, characterized in that The configuration information includes one or more of a plane size, a page size, and the number of planes.

6. The method according to claim 1, characterized in that The starting physical address number in the physical address number range corresponding to the write command executed by any core is the acquired target physical address number, and the ending physical address number is the sum of the acquired target physical address number and the number of sub-blocks.

7. The method according to claim 6, characterized in that When two cores execute write commands, they include: If, in response to the first write command, the first core in the multi-core obtains a start physical address number N1 allocated for the first write command, and an end physical address number N2=N1+D1-1, where D1 is the number of sub-blocks occupied by the first write command; If in response to the second write command, the second core in the multi-core obtains a start physical address number M1 allocated for the second write command, and an end physical address number M2=M1+D2-1, where D2 is the number of sub-blocks occupied by the second write command; The relationship between the starting physical address number and the ending physical address number obtained by the first core and the second core is: M1≥N2+1; or N1≥M2+1.

8. The method according to claim 1, characterized in that The determining the number of sub-blocks occupied by the to-be-written data corresponding to the write command includes: Determine a target data amount of data to be written corresponding to the write command; The number of sub-blocks occupied by the data to be written is determined according to the target data amount and the preset unit data amount.

9. The method according to claim 1, characterized in that: The updating of the target physical address number based on the number of sub-blocks includes: Determine the sum of the target physical address number and the number of sub-blocks; The target physical address number currently stored in the public memory area is updated to the sum value.

10. A storage device, characterized in that: include: A memory and a processor, wherein the processor includes multiple cores, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the multi-core processing FTL physical address allocation method as described in any one of claims 1-9 is implemented.

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